drm/i915: Fix pipe gamma enable/disable vs. CxSR on gmch platforms

Like most other plane control register bits, the pipe gamma
enable bit is also blocked by CxSR. So make sure we kick the
machine out of CxSR before trying to change that bit.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220622155452.32587-8-ville.syrjala@linux.intel.com
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>

diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index fc23d5d..123c57c 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -1287,6 +1287,10 @@ intel_color_add_affected_planes(struct intel_crtc_state *new_crtc_state)
                        return PTR_ERR(plane_state);
 
                new_crtc_state->update_planes |= BIT(plane->id);
+
+               /* plane control register changes blocked by CxSR */
+               if (HAS_GMCH(dev_priv))
+                       new_crtc_state->disable_cxsr = true;
        }
 
        return 0;