*/
#include "xe_bb.h"
-#include "xe_sa.h"
+
#include "xe_device.h"
#include "xe_engine_types.h"
#include "xe_hw_fence.h"
+#include "xe_sa.h"
#include "xe_sched_job.h"
#include "xe_vm_types.h"
* Copyright © 2021 Intel Corporation
*/
-
#include "xe_bo.h"
#include <linux/dma-buf.h>
* Copyright © 2022 Intel Corporation
*/
-#include "xe_bo.h"
#include "xe_bo_evict.h"
+
+#include "xe_bo.h"
#include "xe_device.h"
#include "xe_ggtt.h"
#include "xe_gt.h"
* Copyright © 2022 Intel Corporation
*/
+#include "xe_debugfs.h"
+
#include <linux/string_helpers.h>
#include <drm/drm_debugfs.h>
#include "xe_bo.h"
#include "xe_device.h"
-#include "xe_debugfs.h"
#include "xe_gt_debugfs.h"
#include "xe_step.h"
#include "xe_device.h"
-#include <drm/drm_gem_ttm_helper.h>
#include <drm/drm_aperture.h>
+#include <drm/drm_atomic_helper.h>
+#include <drm/drm_gem_ttm_helper.h>
#include <drm/drm_ioctl.h>
-#include <drm/xe_drm.h>
#include <drm/drm_managed.h>
-#include <drm/drm_atomic_helper.h>
+#include <drm/xe_drm.h>
#include "xe_bo.h"
#include "xe_debugfs.h"
#include "xe_exec.h"
#include "xe_gt.h"
#include "xe_irq.h"
-#include "xe_module.h"
#include "xe_mmio.h"
+#include "xe_module.h"
#include "xe_pcode.h"
#include "xe_pm.h"
#include "xe_query.h"
#include <drm/drm_util.h>
#include "xe_device_types.h"
-#include "xe_macros.h"
#include "xe_force_wake.h"
+#include "xe_macros.h"
#include "gt/intel_gpu_commands.h"
* Copyright © 2022 Intel Corporation
*/
+#include "xe_dma_buf.h"
+
+#include <kunit/test.h>
#include <linux/dma-buf.h>
+#include <linux/pci-p2pdma.h>
#include <drm/drm_device.h>
#include <drm/drm_prime.h>
-
#include <drm/ttm/ttm_tt.h>
-#include <kunit/test.h>
-#include <linux/pci-p2pdma.h>
-
#include "tests/xe_test.h"
#include "xe_bo.h"
#include "xe_device.h"
-#include "xe_dma_buf.h"
#include "xe_ttm_vram_mgr.h"
#include "xe_vm.h"
#include "xe_engine.h"
+#include <linux/nospec.h>
+
#include <drm/drm_device.h>
#include <drm/drm_file.h>
#include <drm/xe_drm.h>
-#include <linux/nospec.h>
#include "xe_device.h"
#include "xe_gt.h"
* Copyright © 2022 Intel Corporation
*/
+#include "xe_exec.h"
+
#include <drm/drm_device.h>
#include <drm/drm_file.h>
#include <drm/xe_drm.h>
#include "xe_bo.h"
#include "xe_device.h"
#include "xe_engine.h"
-#include "xe_exec.h"
#include "xe_macros.h"
#include "xe_sched_job.h"
#include "xe_sync.h"
* Copyright © 2021 Intel Corporation
*/
-#include <drm/drm_managed.h>
-
#include "xe_execlist.h"
+#include <drm/drm_managed.h>
+
#include "xe_bo.h"
#include "xe_device.h"
#include "xe_engine.h"
-#include "xe_hw_fence.h"
#include "xe_gt.h"
+#include "xe_hw_fence.h"
#include "xe_lrc.h"
#include "xe_macros.h"
#include "xe_mmio.h"
#include "xe_ring_ops_types.h"
#include "xe_sched_job.h"
-#include "i915_reg.h"
+#include "gt/intel_engine_regs.h"
#include "gt/intel_gpu_commands.h"
#include "gt/intel_gt_regs.h"
#include "gt/intel_lrc_reg.h"
-#include "gt/intel_engine_regs.h"
+#include "i915_reg.h"
#define XE_EXECLIST_HANG_LIMIT 1
* Copyright © 2022 Intel Corporation
*/
+#include "xe_force_wake.h"
+
#include <drm/drm_util.h>
-#include "xe_force_wake.h"
#include "xe_gt.h"
#include "xe_mmio.h"
-#include "gt/intel_gt_regs.h"
+#include "gt/intel_gt_regs.h"
#define XE_FORCE_WAKE_ACK_TIMEOUT_MS 50
#include "xe_ggtt.h"
#include <linux/sizes.h>
-#include <drm/i915_drm.h>
#include <drm/drm_managed.h>
+#include <drm/i915_drm.h>
-#include "xe_device.h"
#include "xe_bo.h"
+#include "xe_device.h"
#include "xe_gt.h"
#include "xe_gt_tlb_invalidation.h"
#include "xe_map.h"
#include "xe_mmio.h"
#include "xe_wopcm.h"
-#include "i915_reg.h"
#include "gt/intel_gt_regs.h"
+#include "i915_reg.h"
/* FIXME: Common file, preferably auto-gen */
#define MTL_GGTT_PTE_PAT0 BIT_ULL(52)
* Copyright © 2022 Intel Corporation
*/
+#include "xe_gt.h"
+
#include <linux/minmax.h>
#include <drm/drm_managed.h>
#include "xe_execlist.h"
#include "xe_force_wake.h"
#include "xe_ggtt.h"
-#include "xe_gt.h"
#include "xe_gt_clock.h"
#include "xe_gt_mcr.h"
#include "xe_gt_pagefault.h"
* Copyright © 2022 Intel Corporation
*/
-#include "i915_reg.h"
-#include "gt/intel_gt_regs.h"
+#include "xe_gt_clock.h"
#include "xe_device.h"
#include "xe_gt.h"
-#include "xe_gt_clock.h"
#include "xe_macros.h"
#include "xe_mmio.h"
+#include "gt/intel_gt_regs.h"
+#include "i915_reg.h"
+
static u32 read_reference_ts_freq(struct xe_gt *gt)
{
u32 ts_override = xe_mmio_read32(gt, GEN9_TIMESTAMP_OVERRIDE.reg);
* Copyright © 2022 Intel Corporation
*/
+#include "xe_gt_debugfs.h"
+
#include <drm/drm_debugfs.h>
#include <drm/drm_managed.h>
#include "xe_force_wake.h"
#include "xe_ggtt.h"
#include "xe_gt.h"
-#include "xe_gt_debugfs.h"
#include "xe_gt_mcr.h"
#include "xe_gt_topology.h"
#include "xe_hw_engine.h"
* Copyright © 2022 Intel Corporation
*/
-#include "xe_gt.h"
#include "xe_gt_mcr.h"
+
+#include "xe_gt.h"
#include "xe_gt_topology.h"
#include "xe_gt_types.h"
#include "xe_mmio.h"
* Copyright © 2022 Intel Corporation
*/
+#include "xe_gt_pagefault.h"
+
#include <linux/circ_buf.h>
#include <drm/drm_managed.h>
#include "xe_bo.h"
#include "xe_gt.h"
-#include "xe_gt_pagefault.h"
#include "xe_gt_tlb_invalidation.h"
#include "xe_guc.h"
#include "xe_guc_ct.h"
* Copyright © 2022 Intel Corporation
*/
+#include "xe_gt_sysfs.h"
+
#include <linux/kobject.h>
#include <linux/sysfs.h>
+
#include <drm/drm_managed.h>
+
#include "xe_gt.h"
-#include "xe_gt_sysfs.h"
static void xe_gt_sysfs_kobj_release(struct kobject *kobj)
{
* Copyright © 2023 Intel Corporation
*/
-#include "xe_gt.h"
#include "xe_gt_tlb_invalidation.h"
+
+#include "xe_gt.h"
#include "xe_guc.h"
#include "xe_guc_ct.h"
#include "xe_trace.h"
* Copyright © 2022 Intel Corporation
*/
+#include "xe_gt_topology.h"
+
#include <linux/bitmap.h>
#include "xe_gt.h"
-#include "xe_gt_topology.h"
#include "xe_mmio.h"
#define XE_MAX_DSS_FUSE_BITS (32 * XE_MAX_DSS_FUSE_REGS)
* Copyright © 2022 Intel Corporation
*/
+#include "xe_guc.h"
+
#include "xe_bo.h"
#include "xe_device.h"
-#include "xe_guc.h"
+#include "xe_force_wake.h"
+#include "xe_gt.h"
#include "xe_guc_ads.h"
#include "xe_guc_ct.h"
#include "xe_guc_hwconfig.h"
#include "xe_guc_log.h"
-#include "xe_guc_reg.h"
#include "xe_guc_pc.h"
+#include "xe_guc_reg.h"
#include "xe_guc_submit.h"
-#include "xe_gt.h"
+#include "xe_mmio.h"
#include "xe_platform_types.h"
#include "xe_uc_fw.h"
#include "xe_wopcm.h"
-#include "xe_mmio.h"
-#include "xe_force_wake.h"
-#include "i915_reg_defs.h"
+
#include "gt/intel_gt_regs.h"
+#include "i915_reg_defs.h"
/* TODO: move to common file */
#define GUC_PVC_MOCS_INDEX_MASK REG_GENMASK(25, 24)
#ifndef _XE_GUC_H_
#define _XE_GUC_H_
-#include "xe_hw_engine_types.h"
#include "xe_guc_types.h"
+#include "xe_hw_engine_types.h"
#include "xe_macros.h"
struct drm_printer;
* Copyright © 2022 Intel Corporation
*/
+#include "xe_guc_ads.h"
+
#include <drm/drm_managed.h>
#include "xe_bo.h"
#include "xe_gt.h"
#include "xe_guc.h"
-#include "xe_guc_ads.h"
#include "xe_guc_reg.h"
#include "xe_hw_engine.h"
#include "xe_lrc.h"
#include "xe_map.h"
#include "xe_mmio.h"
#include "xe_platform_types.h"
-#include "gt/intel_gt_regs.h"
+
#include "gt/intel_engine_regs.h"
+#include "gt/intel_gt_regs.h"
/* Slack of a few additional entries per engine */
#define ADS_REGSET_EXTRA_MAX 8
* Copyright © 2022 Intel Corporation
*/
+#include "xe_guc_ct.h"
+
#include <linux/bitfield.h>
#include <linux/circ_buf.h>
#include <linux/delay.h>
#include "xe_bo.h"
#include "xe_device.h"
#include "xe_gt.h"
-#include "xe_guc.h"
-#include "xe_guc_ct.h"
#include "xe_gt_pagefault.h"
#include "xe_gt_tlb_invalidation.h"
+#include "xe_guc.h"
#include "xe_guc_submit.h"
#include "xe_map.h"
#include "xe_trace.h"
#ifndef _XE_GUC_CT_TYPES_H_
#define _XE_GUC_CT_TYPES_H_
-#include <linux/iosys-map.h>
#include <linux/interrupt.h>
+#include <linux/iosys-map.h>
#include <linux/spinlock_types.h>
#include <linux/wait.h>
#include <linux/xarray.h>
* Copyright © 2022 Intel Corporation
*/
+#include "xe_guc_debugfs.h"
+
#include <drm/drm_debugfs.h>
#include <drm/drm_managed.h>
#include "xe_gt.h"
#include "xe_guc.h"
#include "xe_guc_ct.h"
-#include "xe_guc_debugfs.h"
#include "xe_guc_log.h"
#include "xe_macros.h"
#include "abi/guc_actions_abi.h"
#include "abi/guc_actions_slpc_abi.h"
-#include "abi/guc_errors_abi.h"
-#include "abi/guc_communication_mmio_abi.h"
#include "abi/guc_communication_ctb_abi.h"
+#include "abi/guc_communication_mmio_abi.h"
+#include "abi/guc_errors_abi.h"
#include "abi/guc_klvs_abi.h"
#include "abi/guc_messages_abi.h"
* Copyright © 2022 Intel Corporation
*/
+#include "xe_guc_hwconfig.h"
+
#include <drm/drm_managed.h>
#include "xe_bo.h"
#include "xe_device.h"
#include "xe_gt.h"
#include "xe_guc.h"
-#include "xe_guc_hwconfig.h"
#include "xe_map.h"
static struct xe_gt *
* Copyright © 2022 Intel Corporation
*/
+#include "xe_guc_log.h"
+
#include <drm/drm_managed.h>
#include "xe_bo.h"
#include "xe_gt.h"
-#include "xe_guc_log.h"
#include "xe_map.h"
#include "xe_module.h"
* Copyright © 2022 Intel Corporation
*/
+#include "xe_guc_pc.h"
+
+#include <linux/delay.h>
+
#include <drm/drm_managed.h>
+
#include "xe_bo.h"
#include "xe_device.h"
#include "xe_gt.h"
-#include "xe_gt_types.h"
#include "xe_gt_sysfs.h"
+#include "xe_gt_types.h"
#include "xe_guc_ct.h"
#include "xe_map.h"
#include "xe_mmio.h"
#include "xe_pcode.h"
-#include "i915_reg_defs.h"
-#include "i915_reg.h"
-
-#include <linux/delay.h>
+#include "i915_reg.h"
+#include "i915_reg_defs.h"
#include "intel_mchbar_regs.h"
/* For GEN6_RP_STATE_CAP.reg to be merged when the definition moves to Xe */
#ifndef _XE_GUC_PC_TYPES_H_
#define _XE_GUC_PC_TYPES_H_
-#include <linux/types.h>
#include <linux/mutex.h>
+#include <linux/types.h>
/**
* struct xe_guc_pc - GuC Power Conservation (PC)
* Copyright © 2022 Intel Corporation
*/
+#include "xe_guc_submit.h"
+
#include <linux/bitfield.h>
#include <linux/bitmap.h>
#include <linux/circ_buf.h>
#include "xe_device.h"
#include "xe_engine.h"
+#include "xe_force_wake.h"
+#include "xe_gpu_scheduler.h"
+#include "xe_gt.h"
#include "xe_guc.h"
#include "xe_guc_ct.h"
#include "xe_guc_engine_types.h"
-#include "xe_guc_submit.h"
-#include "xe_gt.h"
-#include "xe_force_wake.h"
-#include "xe_gpu_scheduler.h"
#include "xe_hw_engine.h"
#include "xe_hw_fence.h"
#include "xe_lrc.h"
* Copyright © 2022 Intel Corporation
*/
+#include "xe_huc.h"
+
#include "xe_bo.h"
#include "xe_device.h"
#include "xe_force_wake.h"
#include "xe_gt.h"
#include "xe_guc.h"
#include "xe_guc_reg.h"
-#include "xe_huc.h"
#include "xe_mmio.h"
#include "xe_uc_fw.h"
* Copyright © 2022 Intel Corporation
*/
+#include "xe_huc_debugfs.h"
+
#include <drm/drm_debugfs.h>
#include <drm/drm_managed.h>
#include "xe_device.h"
#include "xe_gt.h"
#include "xe_huc.h"
-#include "xe_huc_debugfs.h"
#include "xe_macros.h"
static struct xe_gt *
#include "xe_wa.h"
#include "gt/intel_engine_regs.h"
-#include "i915_reg.h"
#include "gt/intel_gt_regs.h"
+#include "i915_reg.h"
#define MAX_MMIO_BASES 3
struct engine_info {
#ifndef _XE_HW_FENCE_TYPES_H_
#define _XE_HW_FENCE_TYPES_H_
-#include <linux/iosys-map.h>
#include <linux/dma-fence.h>
+#include <linux/iosys-map.h>
#include <linux/irq_work.h>
#include <linux/list.h>
#include <linux/spinlock.h>
* Copyright © 2021 Intel Corporation
*/
+#include "xe_irq.h"
+
#include <linux/sched/clock.h>
#include <drm/drm_managed.h>
#include "xe_device.h"
#include "xe_drv.h"
-#include "xe_guc.h"
#include "xe_gt.h"
+#include "xe_guc.h"
#include "xe_hw_engine.h"
#include "xe_mmio.h"
-#include "i915_reg.h"
#include "gt/intel_gt_regs.h"
+#include "i915_reg.h"
static void gen3_assert_iir_is_zero(struct xe_gt *gt, i915_reg_t reg)
{
#include "xe_device.h"
#include "xe_engine_types.h"
#include "xe_gt.h"
-#include "xe_map.h"
#include "xe_hw_fence.h"
+#include "xe_map.h"
#include "xe_vm.h"
-#include "i915_reg.h"
+#include "gt/intel_engine_regs.h"
#include "gt/intel_gpu_commands.h"
#include "gt/intel_gt_regs.h"
#include "gt/intel_lrc_reg.h"
-#include "gt/intel_engine_regs.h"
+#include "i915_reg.h"
#define GEN8_CTX_VALID (1 << 0)
#define GEN8_CTX_L3LLC_COHERENT (1 << 5)
/*
* Copyright © 2020 Intel Corporation
*/
+
#include "xe_migrate.h"
+#include <linux/sizes.h>
+
+#include <drm/drm_managed.h>
+#include <drm/ttm/ttm_tt.h>
+#include <drm/xe_drm.h>
+
#include "xe_bb.h"
#include "xe_bo.h"
#include "xe_engine.h"
#include "xe_trace.h"
#include "xe_vm.h"
-#include <linux/sizes.h>
-#include <drm/drm_managed.h>
-#include <drm/ttm/ttm_tt.h>
-#include <drm/xe_drm.h>
-
#include "gt/intel_gpu_commands.h"
/**
#include "xe_macros.h"
#include "xe_module.h"
-#include "i915_reg.h"
#include "gt/intel_engine_regs.h"
#include "gt/intel_gt_regs.h"
+#include "i915_reg.h"
#define XEHP_MTCFG_ADDR _MMIO(0x101800)
#define TILE_COUNT REG_GENMASK(15, 8)
* Copyright © 2022 Intel Corporation
*/
+#include "xe_mocs.h"
+
#include "xe_bo.h"
#include "xe_device.h"
#include "xe_engine.h"
#include "xe_gt.h"
-#include "xe_platform_types.h"
#include "xe_mmio.h"
-#include "xe_mocs.h"
+#include "xe_platform_types.h"
#include "xe_step_types.h"
#include "gt/intel_gt_regs.h"
* Copyright © 2021 Intel Corporation
*/
+#include "xe_module.h"
+
#include <linux/init.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/pm_runtime.h>
-#include <drm/drm_drv.h>
#include <drm/drm_color_mgmt.h>
+#include <drm/drm_drv.h>
#include <drm/xe_pciids.h>
-#include "xe_drv.h"
#include "xe_device.h"
+#include "xe_drv.h"
#include "xe_macros.h"
#include "xe_module.h"
#include "xe_pm.h"
* Copyright © 2022 Intel Corporation
*/
-#include "xe_pcode_api.h"
#include "xe_pcode.h"
-#include "xe_gt.h"
-#include "xe_mmio.h"
-
+#include <linux/delay.h>
#include <linux/errno.h>
-#include <linux/delay.h>
+#include "xe_gt.h"
+#include "xe_mmio.h"
+#include "xe_pcode_api.h"
/**
* DOC: PCODE
* Copyright © 2022 Intel Corporation
*/
+#include "xe_pm.h"
+
#include <linux/pm_runtime.h>
#include <drm/ttm/ttm_placement.h>
#include "xe_bo.h"
#include "xe_bo_evict.h"
#include "xe_device.h"
-#include "xe_pm.h"
-#include "xe_gt.h"
#include "xe_ggtt.h"
+#include "xe_gt.h"
#include "xe_irq.h"
#include "xe_pcode.h"
* Copyright © 2022 Intel Corporation
*/
+#include "xe_preempt_fence.h"
+
#include <linux/slab.h>
#include "xe_engine.h"
-#include "xe_preempt_fence.h"
#include "xe_vm.h"
static void preempt_fence_work_func(struct work_struct *w)
* Copyright © 2022 Intel Corporation
*/
+#include "xe_pt.h"
+
#include "xe_bo.h"
#include "xe_device.h"
#include "xe_gt.h"
#include "xe_gt_tlb_invalidation.h"
#include "xe_migrate.h"
-#include "xe_pt.h"
#include "xe_pt_types.h"
#include "xe_pt_walk.h"
-#include "xe_vm.h"
#include "xe_res_cursor.h"
#include "xe_trace.h"
#include "xe_ttm_stolen_mgr.h"
+#include "xe_vm.h"
struct xe_pt_dir {
struct xe_pt pt;
* Copyright © 2022 Intel Corporation
*/
-#include <drm/xe_drm.h>
-#include <drm/ttm/ttm_placement.h>
+#include "xe_query.h"
+
#include <linux/nospec.h>
+#include <drm/ttm/ttm_placement.h>
+#include <drm/xe_drm.h>
+
#include "xe_bo.h"
#include "xe_device.h"
-#include "xe_gt.h"
-#include "xe_macros.h"
-#include "xe_query.h"
#include "xe_ggtt.h"
+#include "xe_gt.h"
#include "xe_guc_hwconfig.h"
+#include "xe_macros.h"
static const enum xe_engine_class xe_to_user_engine_class[] = {
[XE_ENGINE_CLASS_RENDER] = DRM_XE_ENGINE_CLASS_RENDER,
#include <linux/string_helpers.h>
#include <linux/xarray.h>
-#include <drm/drm_print.h>
#include <drm/drm_managed.h>
+#include <drm/drm_print.h>
-#include "xe_rtp_types.h"
#include "xe_device_types.h"
#include "xe_force_wake.h"
#include "xe_gt.h"
#include "xe_gt_mcr.h"
#include "xe_macros.h"
#include "xe_mmio.h"
+#include "xe_rtp_types.h"
#include "gt/intel_engine_regs.h"
#include "gt/intel_gt_regs.h"
#ifndef _XE_REG_SR_TYPES_
#define _XE_REG_SR_TYPES_
-#include <linux/xarray.h>
#include <linux/types.h>
+#include <linux/xarray.h>
#include "i915_reg_defs.h"
#include "xe_reg_whitelist.h"
-#include "xe_platform_types.h"
#include "xe_gt_types.h"
+#include "xe_platform_types.h"
#include "xe_rtp.h"
-#include "../i915/gt/intel_engine_regs.h"
-#include "../i915/gt/intel_gt_regs.h"
+#include "gt/intel_engine_regs.h"
+#include "gt/intel_gt_regs.h"
#undef _MMIO
#undef MCR_REG
* Copyright © 2022 Intel Corporation
*/
+#include "xe_ring_ops.h"
+
#include "xe_engine_types.h"
#include "xe_gt.h"
#include "xe_lrc.h"
#include "xe_macros.h"
-#include "xe_ring_ops.h"
#include "xe_sched_job.h"
#include "xe_vm_types.h"
-#include "i915_reg.h"
#include "gt/intel_gpu_commands.h"
#include "gt/intel_gt_regs.h"
#include "gt/intel_lrc_reg.h"
+#include "i915_reg.h"
static u32 preparser_disable(bool state)
{
#ifndef _XE_RTP_
#define _XE_RTP_
-#include <linux/xarray.h>
#include <linux/types.h>
+#include <linux/xarray.h>
#include "xe_rtp_types.h"
* Copyright © 2022 Intel Corporation
*/
+#include "xe_sa.h"
+
#include <linux/kernel.h>
+
#include <drm/drm_managed.h>
#include "xe_bo.h"
#include "xe_device.h"
#include "xe_gt.h"
#include "xe_map.h"
-#include "xe_sa.h"
static void xe_sa_bo_manager_fini(struct drm_device *drm, void *arg)
{
#include <linux/kthread.h>
#include <linux/sched/mm.h>
#include <linux/uaccess.h>
-#include <drm/xe_drm.h>
+
#include <drm/drm_print.h>
#include <drm/drm_syncobj.h>
+#include <drm/xe_drm.h>
#include "xe_device_types.h"
-#include "xe_sched_job_types.h"
#include "xe_macros.h"
+#include "xe_sched_job_types.h"
#define SYNC_FLAGS_TYPE_MASK 0x3
#define SYNC_FLAGS_FENCE_INSTALLED 0x10000
#if !defined(_XE_TRACE_H_) || defined(TRACE_HEADER_MULTI_READ)
#define _XE_TRACE_H_
-#include <linux/types.h>
#include <linux/tracepoint.h>
+#include <linux/types.h>
#include "xe_bo_types.h"
#include "xe_engine_types.h"
#include "xe_gpu_scheduler_types.h"
-#include "xe_gt_types.h"
#include "xe_gt_tlb_invalidation_types.h"
+#include "xe_gt_types.h"
#include "xe_guc_engine_types.h"
#include "xe_sched_job.h"
#include "xe_vm_types.h"
#include <drm/drm_managed.h>
-#include <drm/ttm/ttm_range_manager.h>
#include <drm/ttm/ttm_placement.h>
+#include <drm/ttm/ttm_range_manager.h>
#include <drm/ttm/ttm_tt.h>
#include "xe_bo.h"
#include <drm/drm_mm.h>
#include <drm/ttm/ttm_device.h>
-#include <drm/ttm/ttm_range_manager.h>
#include <drm/ttm/ttm_placement.h>
+#include <drm/ttm/ttm_range_manager.h>
#include "../i915/i915_reg.h"
#include <drm/drm_managed.h>
-#include <drm/ttm/ttm_range_manager.h>
#include <drm/ttm/ttm_placement.h>
+#include <drm/ttm/ttm_range_manager.h>
#include "xe_bo.h"
#include "xe_device.h"
#include "xe_tuning.h"
-#include "xe_platform_types.h"
#include "xe_gt_types.h"
+#include "xe_platform_types.h"
#include "xe_rtp.h"
#include "gt/intel_gt_regs.h"
* Copyright © 2022 Intel Corporation
*/
+#include "xe_uc.h"
+
#include "xe_device.h"
-#include "xe_huc.h"
#include "xe_gt.h"
#include "xe_guc.h"
#include "xe_guc_pc.h"
#include "xe_guc_submit.h"
-#include "xe_uc.h"
+#include "xe_huc.h"
#include "xe_uc_fw.h"
#include "xe_wopcm.h"
#include <linux/errno.h>
-#include "xe_uc_fw_types.h"
-#include "xe_uc_fw_abi.h"
#include "xe_macros.h"
+#include "xe_uc_fw_abi.h"
+#include "xe_uc_fw_types.h"
struct drm_printer;
#ifndef _XE_UC_FW_ABI_H
#define _XE_UC_FW_ABI_H
-#include <linux/types.h>
#include <linux/build_bug.h>
+#include <linux/types.h>
/**
* DOC: Firmware Layout
#include "xe_preempt_fence.h"
#include "xe_pt.h"
#include "xe_res_cursor.h"
-#include "xe_trace.h"
#include "xe_sync.h"
+#include "xe_trace.h"
#define TEST_VM_ASYNC_OPS_ERROR
* Copyright © 2021 Intel Corporation
*/
-#include <drm/xe_drm.h>
-#include <drm/ttm/ttm_tt.h>
+#include "xe_vm_madvise.h"
+
#include <linux/nospec.h>
+#include <drm/ttm/ttm_tt.h>
+#include <drm/xe_drm.h>
+
#include "xe_bo.h"
#include "xe_vm.h"
-#include "xe_vm_madvise.h"
static int madvise_preferred_mem_class(struct xe_device *xe, struct xe_vm *vm,
struct xe_vma **vmas, int num_vmas,
* Copyright © 2022 Intel Corporation
*/
+#include "xe_wopcm.h"
+
#include "xe_device.h"
#include "xe_force_wake.h"
#include "xe_gt.h"
#include "xe_guc_reg.h"
#include "xe_mmio.h"
#include "xe_uc_fw.h"
-#include "xe_wopcm.h"
/**
* DOC: Write Once Protected Content Memory (WOPCM) Layout