drm/msm/a6xx: Correct the highestbank configuration

Highest bank bit configuration is different for a618 gpu. Update
it with the correct configuration which is the reset value incidentally.

Signed-off-by: Akhil P Oommen <akhilpo@codeaurora.org>
Signed-off-by: Sharat Masetty <smasetty@codeaurora.org>
Fixes: e812744c5f95 ("drm: msm: a6xx: Add support for A618")
Reviewed-by: Rob Clark <robdclark@gmail.com>
Signed-off-by: Rob Clark <robdclark@chromium.org>

diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index daf0780..536d196 100644 (file)
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
@@ -470,10 +470,12 @@ static int a6xx_hw_init(struct msm_gpu *gpu)
        /* Select CP0 to always count cycles */
        gpu_write(gpu, REG_A6XX_CP_PERFCTR_CP_SEL_0, PERF_CP_ALWAYS_COUNT);
 
-       gpu_write(gpu, REG_A6XX_RB_NC_MODE_CNTL, 2 << 1);
-       gpu_write(gpu, REG_A6XX_TPL1_NC_MODE_CNTL, 2 << 1);
-       gpu_write(gpu, REG_A6XX_SP_NC_MODE_CNTL, 2 << 1);
-       gpu_write(gpu, REG_A6XX_UCHE_MODE_CNTL, 2 << 21);
+       if (adreno_is_a630(adreno_gpu)) {
+               gpu_write(gpu, REG_A6XX_RB_NC_MODE_CNTL, 2 << 1);
+               gpu_write(gpu, REG_A6XX_TPL1_NC_MODE_CNTL, 2 << 1);
+               gpu_write(gpu, REG_A6XX_SP_NC_MODE_CNTL, 2 << 1);
+               gpu_write(gpu, REG_A6XX_UCHE_MODE_CNTL, 2 << 21);
+       }
 
        /* Enable fault detection */
        gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL,