Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

Pull ARM Device-tree updates from Olof Johansson:
 "Besides new bindings and additional descriptions of hardware blocks
  for various SoCs and boards, the main new contents here is:

  SoCs:
   - Intel Agilex (SoCFPGA)
   - NXP i.MX8MM (Quad Cortex-A53 with media/graphics focus)

  New boards:
   - Allwinner:
      + RerVision H3-DVK (H3)
      + Oceanic 5205 5inMFD (H6)
      + Beelink GS2 (H6)
      + Orange Pi 3 (H6)
   - Rockchip:
      + Orange Pi RK3399
      + Nanopi NEO4
      + Veyron-Mighty Chromebook variant
   - Amlogic:
      + SEI Robotics SEI510
   - ST Micro:
      + stm32mp157a discovery1
      + stm32mp157c discovery2
   - NXP:
      + Eckelmann ci4x10 (i.MX6DL)
      + i.MX8MM EVK (i.MX8MM)
      + ZII i.MX7 RPU2 (i.MX7)
      + ZII SPB4 (VF610)
      + Zii Ultra (i.MX8M)
      + TQ TQMa7S (i.MX7Solo)
      + TQ TQMa7D (i.MX7Dual)
      + Kobo Aura (i.MX50)
      + Menlosystems M53 (i.MX53)j
   - Nvidia:
      + Jetson Nano (Tegra T210)"

* tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (593 commits)
  arm64: dts: bitmain: Add UART pinctrl support for Sophon Edge
  arm64: dts: bitmain: Add pinctrl support for BM1880 SoC
  arm64: dts: bitmain: Add GPIO Line names for Sophon Edge board
  arm64: dts: bitmain: Add GPIO support for BM1880 SoC
  ARM: dts: gemini: Indent DIR-685 partition table
  dt-bindings: hwmon (pwm-fan) Remove dead "cooling-*-state" properties
  ARM: dts: qcom-apq8064: Set 'cxo_board' as ref clock of the DSI PHY
  arm64: dts: msm8998: thermal: Restrict thermal zone name length to under 20
  arm64: dts: msm8998: thermal: Fix number of supported sensors
  arm64: dts: msm8998-mtp: thermal: Remove skin and battery thermal zones
  arm64: dts: exynos: Move fixed-clocks out of soc
  arm64: dts: exynos: Move pmu and timer nodes out of soc
  ARM: dts: s5pv210: Fix camera clock provider on Goni board
  ARM: dts: exynos: Properly override node to use MDMA0 on Universal C210
  ARM: dts: exynos: Move fixed-clocks out of soc on Exynos3250
  ARM: dts: exynos: Remove unneeded address/size cells from fixed-clock on Exynos3250
  ARM: dts: exynos: Move pmu and timer nodes out of soc
  arm64: dts: rockchip: fix IO domain voltage setting of APIO5 on rockpro64
  arm64: dts: db820c: Add sound card support
  arm64: dts: apq8096-db820c: Add HDMI display support
  ...

diff --git a/Documentation/devicetree/bindings/arm/amlogic.txt b/Documentation/devicetree/bindings/arm/amlogic.txt
index 7f40cb5..061f7b9 100644 (file)
--- a/Documentation/devicetree/bindings/arm/amlogic.txt
+++ b/Documentation/devicetree/bindings/arm/amlogic.txt
@@ -110,6 +110,7 @@ Board compatible values (alphabetically, grouped by SoC):
 
   - "amlogic,u200" (Meson g12a s905d2)
   - "amediatech,x96-max" (Meson g12a s905x2)
+  - "seirobotics,sei510" (Meson g12a s905x2)
 
 Amlogic Meson Firmware registers Interface
 ------------------------------------------

diff --git a/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt b/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt
index 72d481c..5d7dbab 100644 (file)
--- a/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt
+++ b/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt
@@ -22,9 +22,11 @@ Required properties:
 -------------------
 - compatible:  should be "fsl,imx-scu".
 - mbox-names:  should include "tx0", "tx1", "tx2", "tx3",
-                              "rx0", "rx1", "rx2", "rx3".
-- mboxes:      List of phandle of 4 MU channels for tx and 4 MU channels
-               for rx. All 8 MU channels must be in the same MU instance.
+                              "rx0", "rx1", "rx2", "rx3";
+               include "gip3" if want to support general MU interrupt.
+- mboxes:      List of phandle of 4 MU channels for tx, 4 MU channels for
+               rx, and 1 optional MU channel for general interrupt.
+               All MU channels must be in the same MU instance.
                Cross instances are not allowed. The MU instance can only
                be one of LSIO MU0~M4 for imx8qxp and imx8qm. Users need
                to make sure use the one which is not conflict with other
@@ -34,6 +36,7 @@ Required properties:
                Channel 1 must be "tx1" or "rx1".
                Channel 2 must be "tx2" or "rx2".
                Channel 3 must be "tx3" or "rx3".
+               General interrupt rx channel must be "gip3".
                e.g.
                mboxes = <&lsio_mu1 0 0
                          &lsio_mu1 0 1
@@ -42,10 +45,18 @@ Required properties:
                          &lsio_mu1 1 0
                          &lsio_mu1 1 1
                          &lsio_mu1 1 2
-                         &lsio_mu1 1 3>;
+                         &lsio_mu1 1 3
+                         &lsio_mu1 3 3>;
                See Documentation/devicetree/bindings/mailbox/fsl,mu.txt
                for detailed mailbox binding.
 
+Note: Each mu which supports general interrupt should have an alias correctly
+numbered in "aliases" node.
+e.g.
+aliases {
+       mu1 = &lsio_mu1;
+};
+
 i.MX SCU Client Device Node:
 ============================================================
 
@@ -124,6 +135,10 @@ Required properties:
 
 Example (imx8qxp):
 -------------
+aliases {
+       mu1 = &lsio_mu1;
+};
+
 lsio_mu1: mailbox@5d1c0000 {
        ...
        #mbox-cells = <2>;
@@ -133,7 +148,8 @@ firmware {
        scu {
                compatible = "fsl,imx-scu";
                mbox-names = "tx0", "tx1", "tx2", "tx3",
-                            "rx0", "rx1", "rx2", "rx3";
+                            "rx0", "rx1", "rx2", "rx3",
+                            "gip3";
                mboxes = <&lsio_mu1 0 0
                          &lsio_mu1 0 1
                          &lsio_mu1 0 2
@@ -141,7 +157,8 @@ firmware {
                          &lsio_mu1 1 0
                          &lsio_mu1 1 1
                          &lsio_mu1 1 2
-                         &lsio_mu1 1 3>;
+                         &lsio_mu1 1 3
+                         &lsio_mu1 3 3>;
 
                clk: clk {
                        compatible = "fsl,imx8qxp-clk", "fsl,scu-clk";

diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml
index 7e2cd6a..407138e 100644 (file)
--- a/Documentation/devicetree/bindings/arm/fsl.yaml
+++ b/Documentation/devicetree/bindings/arm/fsl.yaml
@@ -51,6 +51,13 @@ properties:
           - const: i2se,duckbill-2
           - const: fsl,imx28
 
+      - description: i.MX50 based Boards
+        items:
+          - enum:
+              - fsl,imx50-evk
+              - kobo,aura
+          - const: fsl,imx50
+
       - description: i.MX51 Babbage Board
         items:
           - enum:
@@ -67,6 +74,7 @@ properties:
               - fsl,imx53-evk
               - fsl,imx53-qsb
               - fsl,imx53-smd
+              - menlo,m53menlo
           - const: fsl,imx53
 
       - description: i.MX6Q based Boards
@@ -90,6 +98,7 @@ properties:
       - description: i.MX6DL based Boards
         items:
           - enum:
+              - eckelmann,imx6dl-ci4x10
               - fsl,imx6dl-sabreauto      # i.MX6 DualLite/Solo SABRE Automotive Board
               - fsl,imx6dl-sabresd        # i.MX6 DualLite SABRE Smart Device Board
               - technologic,imx6dl-ts4900
@@ -137,10 +146,18 @@ properties:
           - const: fsl,imx6ull # This seems odd. Should be last?
           - const: fsl,imx6ulz
 
+      - description: i.MX7S based Boards
+        items:
+          - enum:
+              - tq,imx7s-mba7             # i.MX7S TQ MBa7 with TQMa7S SoM
+          - const: fsl,imx7s
+
       - description: i.MX7D based Boards
         items:
           - enum:
               - fsl,imx7d-sdb             # i.MX7 SabreSD Board
+              - tq,imx7d-mba7             # i.MX7D TQ MBa7 with TQMa7D SoM
+              - zii,imx7d-rpu2            # ZII RPU2 Board
           - const: fsl,imx7d
 
       - description:
@@ -154,6 +171,12 @@ properties:
           - const: compulab,cl-som-imx7
           - const: fsl,imx7d
 
+      - description: i.MX8MM based Boards
+        items:
+          - enum:
+              - fsl,imx8mm-evk            # i.MX8MM EVK Board
+          - const: fsl,imx8mm
+
       - description: i.MX8QXP based Boards
         items:
           - enum:
@@ -176,6 +199,19 @@ properties:
               - fsl,vf610
               - fsl,vf610m4
 
+      - description: ZII's VF610 based Boards
+        items:
+          - enum:
+              - zii,vf610cfu1      # ZII VF610 CFU1 Board
+              - zii,vf610dev-c     # ZII VF610 Development Board, Rev C
+              - zii,vf610dev-b     # ZII VF610 Development Board, Rev B
+              - zii,vf610scu4-aib  # ZII VF610 SCU4 AIB
+              - zii,vf610dtu       # ZII VF610 SSMB DTU Board
+              - zii,vf610spu3      # ZII VF610 SSMB SPU3 Board
+              - zii,vf610spb4      # ZII VF610 SPB4 Board
+          - const: zii,vf610dev
+          - const: fsl,vf610
+
       - description: LS1012A based Boards
         items:
           - enum:

diff --git a/Documentation/devicetree/bindings/arm/omap/omap.txt b/Documentation/devicetree/bindings/arm/omap/omap.txt
index 2ecc712..1c1e48f 100644 (file)
--- a/Documentation/devicetree/bindings/arm/omap/omap.txt
+++ b/Documentation/devicetree/bindings/arm/omap/omap.txt
@@ -92,6 +92,9 @@ SoCs:
 - DRA718
   compatible = "ti,dra718", "ti,dra722", "ti,dra72", "ti,dra7"
 
+- AM5748
+  compatible = "ti,am5748", "ti,dra762", "ti,dra7"
+
 - AM5728
   compatible = "ti,am5728", "ti,dra742", "ti,dra74", "ti,dra7"
 
@@ -184,6 +187,9 @@ Boards:
 - AM57XX SBC-AM57x
   compatible = "compulab,sbc-am57x", "compulab,cl-som-am57x", "ti,am5728", "ti,dra742", "ti,dra74", "ti,dra7"
 
+- AM5748 IDK
+  compatible = "ti,am5748-idk", "ti,am5748", "ti,dra762", "ti,dra7";
+
 - AM5728 IDK
   compatible = "ti,am5728-idk", "ti,am5728", "ti,dra742", "ti,dra74", "ti,dra7"
 

diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml
index 061a03e..5c6bbf1 100644 (file)
--- a/Documentation/devicetree/bindings/arm/rockchip.yaml
+++ b/Documentation/devicetree/bindings/arm/rockchip.yaml
@@ -97,6 +97,7 @@ properties:
           - enum:
               - friendlyarm,nanopc-t4
               - friendlyarm,nanopi-m4
+              - friendlyarm,nanopi-neo4
           - const: rockchip,rk3399
 
       - description: GeekBuying GeekBox
@@ -146,7 +147,7 @@ properties:
           - const: google,gru
           - const: rockchip,rk3399
 
-      - description: Google Jaq (Haier Chromebook 11 and more)
+      - description: Google Jaq (Haier Chromebook 11 and more w/ uSD)
         items:
           - const: google,veyron-jaq-rev5
           - const: google,veyron-jaq-rev4
@@ -159,6 +160,12 @@ properties:
 
       - description: Google Jerry (Hisense Chromebook C11 and more)
         items:
+          - const: google,veyron-jerry-rev15
+          - const: google,veyron-jerry-rev14
+          - const: google,veyron-jerry-rev13
+          - const: google,veyron-jerry-rev12
+          - const: google,veyron-jerry-rev11
+          - const: google,veyron-jerry-rev10
           - const: google,veyron-jerry-rev7
           - const: google,veyron-jerry-rev6
           - const: google,veyron-jerry-rev5
@@ -199,6 +206,17 @@ properties:
           - const: google,veyron
           - const: rockchip,rk3288
 
+      - description: Google Mighty (Haier Chromebook 11 and more w/ SD)
+        items:
+          - const: google,veyron-mighty-rev5
+          - const: google,veyron-mighty-rev4
+          - const: google,veyron-mighty-rev3
+          - const: google,veyron-mighty-rev2
+          - const: google,veyron-mighty-rev1
+          - const: google,veyron-mighty
+          - const: google,veyron
+          - const: rockchip,rk3288
+
       - description: Google Minnie (Asus Chromebook Flip C100P)
         items:
           - const: google,veyron-minnie-rev4
@@ -308,6 +326,11 @@ properties:
           - const: netxeon,r89
           - const: rockchip,rk3288
 
+      - description: Orange Pi RK3399 board
+        items:
+          - const: rockchip,rk3399-orangepi
+          - const: rockchip,rk3399
+
       - description: Phytec phyCORE-RK3288 Rapid Development Kit
         items:
           - const: phytec,rk3288-pcm-947

diff --git a/Documentation/devicetree/bindings/arm/sunxi.txt b/Documentation/devicetree/bindings/arm/sunxi.txt
deleted file mode 100644 (file)
index 9254cbe..0000000
--- a/Documentation/devicetree/bindings/arm/sunxi.txt
+++ /dev/null
@@ -1,23 +0,0 @@
-Allwinner sunXi Platforms Device Tree Bindings
-
-Each device tree must specify which Allwinner SoC it uses,
-using one of the following compatible strings:
-
-  allwinner,sun4i-a10
-  allwinner,sun5i-a10s
-  allwinner,sun5i-a13
-  allwinner,sun5i-r8
-  allwinner,sun6i-a31
-  allwinner,sun7i-a20
-  allwinner,sun8i-a23
-  allwinner,sun8i-a33
-  allwinner,sun8i-a83t
-  allwinner,sun8i-h2-plus
-  allwinner,sun8i-h3
-  allwinner,sun8i-r40
-  allwinner,sun8i-t3
-  allwinner,sun8i-v3s
-  allwinner,sun9i-a80
-  allwinner,sun50i-a64
-  allwinner,suniv-f1c100s
-  nextthing,gr8

diff --git a/Documentation/devicetree/bindings/arm/sunxi.yaml b/Documentation/devicetree/bindings/arm/sunxi.yaml
new file mode 100644 (file)
index 0000000..285f4fc
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/sunxi.yaml
@@ -0,0 +1,807 @@
+# SPDX-License-Identifier: (GPL-2.0+ OR X11)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/sunxi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Allwinner platforms device tree bindings
+
+maintainers:
+  - Chen-Yu Tsai <wens@csie.org>
+  - Maxime Ripard <maxime.ripard@bootlin.com>
+
+properties:
+  $nodename:
+    const: '/'
+  compatible:
+    oneOf:
+
+      - description: Allwinner A23 Evaluation Board
+        items:
+          - const: allwinner,sun8i-a23-evb
+          - const: allwinner,sun8i-a23
+
+      - description: Allwinner A31 APP4 Evaluation Board
+        items:
+          - const: allwinner,app4-evb1
+          - const: allwinner,sun6i-a31
+
+      - description: Allwinner A83t Homlet Evaluation Board v2
+        items:
+          - const: allwinner,h8homlet-v2
+          - const: allwinner,sun8i-a83t
+
+      - description: Allwinner GA10H Quad Core Tablet v1.1
+        items:
+          - const: allwinner,ga10h-v1.1
+          - const: allwinner,sun8i-a33
+
+      - description: Allwinner GT90H Tablet v4
+        items:
+          - const: allwinner,gt90h-v4
+          - const: allwinner,sun8i-a23
+
+      - description: Allwinner R16 EVB (Parrot)
+        items:
+          - const: allwinner,parrot
+          - const: allwinner,sun8i-a33
+
+      - description: Amarula A64 Relic
+        items:
+          - const: amarula,a64-relic
+          - const: allwinner,sun50i-a64
+
+      - description: Auxtek T003 A10s HDMI TV Stick
+        items:
+          - const: allwinner,auxtek-t003
+          - const: allwinner,sun5i-a10s
+
+      - description: Auxtek T004 A10s HDMI TV Stick
+        items:
+          - const: allwinner,auxtek-t004
+          - const: allwinner,sun5i-a10s
+
+      - description: BA10 TV Box
+        items:
+          - const: allwinner,ba10-tvbox
+          - const: allwinner,sun4i-a10
+
+      - description: BananaPi
+        items:
+          - const: lemaker,bananapi
+          - const: allwinner,sun7i-a20
+
+      - description: BananaPi M1 Plus
+        items:
+          - const: sinovoip,bpi-m1-plus
+          - const: allwinner,sun7i-a20
+
+      - description: BananaPi M2
+        items:
+          - const: sinovoip,bpi-m2
+          - const: allwinner,sun6i-a31s
+
+      - description: BananaPi M2 Berry
+        items:
+          - const: sinovoip,bpi-m2-berry
+          - const: allwinner,sun8i-r40
+
+      - description: BananaPi M2 Plus
+        items:
+          - const: sinovoip,bpi-m2-plus
+          - const: allwinner,sun8i-h3
+
+      - description: BananaPi M2 Plus
+        items:
+          - const: sinovoip,bpi-m2-plus
+          - const: allwinner,sun50i-h5
+
+      - description: BananaPi M2 Plus v1.2
+        items:
+          - const: bananapi,bpi-m2-plus-v1.2
+          - const: allwinner,sun8i-h3
+
+      - description: BananaPi M2 Plus v1.2
+        items:
+          - const: bananapi,bpi-m2-plus-v1.2
+          - const: allwinner,sun50i-h5
+
+      - description: BananaPi M2 Magic
+        items:
+          - const: sinovoip,bananapi-m2m
+          - const: allwinner,sun8i-a33
+
+      - description: BananaPi M2 Ultra
+        items:
+          - const: sinovoip,bpi-m2-ultra
+          - const: allwinner,sun8i-r40
+
+      - description: BananaPi M2 Zero
+        items:
+          - const: sinovoip,bpi-m2-zero
+          - const: allwinner,sun8i-h2-plus
+
+      - description: BananaPi M3
+        items:
+          - const: sinovoip,bpi-m3
+          - const: allwinner,sun8i-a83t
+
+      - description: BananaPi M64
+        items:
+          - const: sinovoip,bananapi-m64
+          - const: allwinner,sun50i-a64
+
+      - description: BananaPro
+        items:
+          - const: lemaker,bananapro
+          - const: allwinner,sun7i-a20
+
+      - description: Beelink GS1
+        items:
+          - const: azw,beelink-gs1
+          - const: allwinner,sun50i-h6
+
+      - description: Beelink X2
+        items:
+          - const: roofull,beelink-x2
+          - const: allwinner,sun8i-h3
+
+      - description: Chuwi V7 CW0825
+        items:
+          - const: chuwi,v7-cw0825
+          - const: allwinner,sun4i-a10
+
+      - description: Colorfly E708 Q1 Tablet
+        items:
+          - const: colorfly,e708-q1
+          - const: allwinner,sun6i-a31s
+
+      - description: CSQ CS908 Set Top Box
+        items:
+          - const: csq,cs908
+          - const: allwinner,sun6i-a31s
+
+      - description: Cubietech Cubieboard
+        items:
+          - const: cubietech,a10-cubieboard
+          - const: allwinner,sun4i-a10
+
+      - description: Cubietech Cubieboard2
+        items:
+          - const: cubietech,cubieboard2
+          - const: allwinner,sun7i-a20
+
+      - description: Cubietech Cubieboard4
+        items:
+          - const: cubietech,a80-cubieboard4
+          - const: allwinner,sun9i-a80
+
+      - description: Cubietech Cubietruck
+        items:
+          - const: cubietech,cubietruck
+          - const: allwinner,sun7i-a20
+
+      - description: Cubietech Cubietruck Plus
+        items:
+          - const: cubietech,cubietruck-plus
+          - const: allwinner,sun8i-a83t
+
+      - description: Difrnce DIT4350
+        items:
+          - const: difrnce,dit4350
+          - const: allwinner,sun5i-a13
+
+      - description: Dserve DSRV9703C
+        items:
+          - const: dserve,dsrv9703c
+          - const: allwinner,sun4i-a10
+
+      - description: Empire Electronix D709 Tablet
+        items:
+          - const: empire-electronix,d709
+          - const: allwinner,sun5i-a13
+
+      - description: Empire Electronix M712 Tablet
+        items:
+          - const: empire-electronix,m712
+          - const: allwinner,sun5i-a13
+
+      - description: FriendlyARM NanoPi A64
+        items:
+          - const: friendlyarm,nanopi-a64
+          - const: allwinner,sun50i-a64
+
+      - description: FriendlyARM NanoPi M1
+        items:
+          - const: friendlyarm,nanopi-m1
+          - const: allwinner,sun8i-h3
+
+      - description: FriendlyARM NanoPi M1 Plus
+        items:
+          - const: friendlyarm,nanopi-m1-plus
+          - const: allwinner,sun8i-h3
+
+      - description: FriendlyARM NanoPi Neo
+        items:
+          - const: friendlyarm,nanopi-neo
+          - const: allwinner,sun8i-h3
+
+      - description: FriendlyARM NanoPi Neo 2
+        items:
+          - const: friendlyarm,nanopi-neo2
+          - const: allwinner,sun50i-h5
+
+      - description: FriendlyARM NanoPi Neo Air
+        items:
+          - const: friendlyarm,nanopi-neo-air
+          - const: allwinner,sun8i-h3
+
+      - description: FriendlyARM NanoPi Neo Plus2
+        items:
+          - const: friendlyarm,nanopi-neo-plus2
+          - const: allwinner,sun50i-h5
+
+      - description: Gemei G9 Tablet
+        items:
+          - const: gemei,g9
+          - const: allwinner,sun4i-a10
+
+      - description: Hyundai A7HD
+        items:
+          - const: hyundai,a7hd
+          - const: allwinner,sun4i-a10
+
+      - description: HSG H702
+        items:
+          - const: hsg,h702
+          - const: allwinner,sun5i-a13
+
+      - description: I12 TV Box
+        items:
+          - const: allwinner,i12-tvbox
+          - const: allwinner,sun7i-a20
+
+      - description: ICNova A20 SWAC
+        items:
+          - const: swac,icnova-a20-swac
+          - const: incircuit,icnova-a20
+          - const: allwinner,sun7i-a20
+
+      - description: INet-1
+        items:
+          - const: inet-tek,inet1
+          - const: allwinner,sun4i-a10
+
+      - description: iNet-86DZ Rev 01
+        items:
+          - const: primux,inet86dz
+          - const: allwinner,sun8i-a23
+
+      - description: iNet-9F Rev 03
+        items:
+          - const: inet-tek,inet9f-rev03
+          - const: allwinner,sun4i-a10
+
+      - description: iNet-97F Rev 02
+        items:
+          - const: primux,inet97fv2
+          - const: allwinner,sun4i-a10
+
+      - description: iNet-98V Rev 02
+        items:
+          - const: primux,inet98v-rev2
+          - const: allwinner,sun5i-a13
+
+      - description: iNet D978 Rev 02 Tablet
+        items:
+          - const: primux,inet-d978-rev2
+          - const: allwinner,sun8i-a33
+
+      - description: iNet Q972 Tablet
+        items:
+          - const: inet-tek,inet-q972
+          - const: allwinner,sun6i-a31s
+
+      - description: Itead Ibox A20
+        items:
+          - const: itead,itead-ibox-a20
+          - const: allwinner,sun7i-a20
+
+      - description: Itead Iteaduino Plus A10
+        items:
+          - const: itead,iteaduino-plus-a10
+          - const: allwinner,sun4i-a10
+
+      - description: Jesurun Q5
+        items:
+          - const: jesurun,q5
+          - const: allwinner,sun4i-a10
+
+      - description: Lamobo R1
+        items:
+          - const: lamobo,lamobo-r1
+          - const: allwinner,sun7i-a20
+
+      - description: Libre Computer Board ALL-H3-CC H2+
+        items:
+          - const: libretech,all-h3-cc-h2-plus
+          - const: allwinner,sun8i-h2-plus
+
+      - description: Libre Computer Board ALL-H3-CC H3
+        items:
+          - const: libretech,all-h3-cc-h3
+          - const: allwinner,sun8i-h3
+
+      - description: Libre Computer Board ALL-H3-CC H5
+        items:
+          - const: libretech,all-h3-cc-h5
+          - const: allwinner,sun50i-h5
+
+      - description: Lichee Pi One
+        items:
+          - const: licheepi,licheepi-one
+          - const: allwinner,sun5i-a13
+
+      - description: Lichee Pi Zero
+        items:
+          - const: licheepi,licheepi-zero
+          - const: allwinner,sun8i-v3s
+
+      - description: Lichee Pi Zero (with Dock)
+        items:
+          - const: licheepi,licheepi-zero-dock
+          - const: licheepi,licheepi-zero
+          - const: allwinner,sun8i-v3s
+
+      - description: Linksprite PCDuino
+        items:
+          - const: linksprite,a10-pcduino
+          - const: allwinner,sun4i-a10
+
+      - description: Linksprite PCDuino2
+        items:
+          - const: linksprite,a10-pcduino2
+          - const: allwinner,sun4i-a10
+
+      - description: Linksprite PCDuino3
+        items:
+          - const: linksprite,pcduino3
+          - const: allwinner,sun7i-a20
+
+      - description: Linksprite PCDuino3 Nano
+        items:
+          - const: linksprite,pcduino3-nano
+          - const: allwinner,sun7i-a20
+
+      - description: HAOYU Electronics Marsboard A10
+        items:
+          - const: haoyu,a10-marsboard
+          - const: allwinner,sun4i-a10
+
+      - description: MapleBoard MP130
+        items:
+          - const: mapleboard,mp130
+          - const: allwinner,sun8i-h3
+
+      - description: Mele A1000
+        items:
+          - const: mele,a1000
+          - const: allwinner,sun4i-a10
+
+      - description: Mele A1000G Quad Set Top Box
+        items:
+          - const: mele,a1000g-quad
+          - const: allwinner,sun6i-a31
+
+      - description: Mele I7 Quad Set Top Box
+        items:
+          - const: mele,i7
+          - const: allwinner,sun6i-a31
+
+      - description: Mele M3
+        items:
+          - const: mele,m3
+          - const: allwinner,sun7i-a20
+
+      - description: Mele M9 Set Top Box
+        items:
+          - const: mele,m9
+          - const: allwinner,sun6i-a31
+
+      - description: Merrii A20 Hummingboard
+        items:
+          - const: merrii,a20-hummingbird
+          - const: allwinner,sun7i-a20
+
+      - description: Merrii A31 Hummingboard
+        items:
+          - const: merrii,a31-hummingbird
+          - const: allwinner,sun6i-a31
+
+      - description: Merrii A80 Optimus
+        items:
+          - const: merrii,a80-optimus
+          - const: allwinner,sun9i-a80
+
+      - description: Miniand Hackberry
+        items:
+          - const: miniand,hackberry
+          - const: allwinner,sun4i-a10
+
+      - description: MK802
+        items:
+          - const: allwinner,mk802
+          - const: allwinner,sun4i-a10
+
+      - description: MK802-A10s
+        items:
+          - const: allwinner,a10s-mk802
+          - const: allwinner,sun5i-a10s
+
+      - description: MK802-II
+        items:
+          - const: allwinner,mk802ii
+          - const: allwinner,sun4i-a10
+
+      - description: MK808c
+        items:
+          - const: allwinner,mk808c
+          - const: allwinner,sun7i-a20
+
+      - description: MSI Primo81 Tablet
+        items:
+          - const: msi,primo81
+          - const: allwinner,sun6i-a31s
+
+      - description: Emlid Neutis N5 Developper Board
+        items:
+          - const: emlid,neutis-n5-devboard
+          - const: emlid,neutis-n5
+          - const: allwinner,sun50i-h5
+
+      - description: NextThing Co. CHIP
+        items:
+          - const: nextthing,chip
+          - const: allwinner,sun5i-r8
+          - const: allwinner,sun5i-a13
+
+      - description: NextThing Co. CHIP Pro
+        items:
+          - const: nextthing,chip-pro
+          - const: nextthing,gr8
+
+      - description: NextThing Co. GR8 Evaluation Board
+        items:
+          - const: nextthing,gr8-evb
+          - const: nextthing,gr8
+
+      - description: Nintendo NES Classic
+        items:
+          - const: nintendo,nes-classic
+          - const: allwinner,sun8i-r16
+          - const: allwinner,sun8i-a33
+
+      - description: Nintendo Super NES Classic
+        items:
+          - const: nintendo,super-nes-classic
+          - const: nintendo,nes-classic
+          - const: allwinner,sun8i-r16
+          - const: allwinner,sun8i-a33
+
+      - description: Oceanic 5inMFD (5205)
+        items:
+          - const: oceanic,5205-5inmfd
+          - const: allwinner,sun50i-a64
+
+      - description: Olimex A10-OlinuXino LIME
+        items:
+          - const: olimex,a10-olinuxino-lime
+          - const: allwinner,sun4i-a10
+
+      - description: Olimex A10s-OlinuXino Micro
+        items:
+          - const: olimex,a10s-olinuxino-micro
+          - const: allwinner,sun5i-a10s
+
+      - description: Olimex A13-OlinuXino
+        items:
+          - const: olimex,a13-olinuxino
+          - const: allwinner,sun5i-a13
+
+      - description: Olimex A13-OlinuXino Micro
+        items:
+          - const: olimex,a13-olinuxino-micro
+          - const: allwinner,sun5i-a13
+
+      - description: Olimex A20-Olimex SOM Evaluation Board
+        items:
+          - const: olimex,a20-olimex-som-evb
+          - const: allwinner,sun7i-a20
+
+      - description: Olimex A20-Olimex SOM Evaluation Board (with eMMC)
+        items:
+          - const: olimex,a20-olimex-som-evb-emmc
+          - const: allwinner,sun7i-a20
+
+      - description: Olimex A20-OlinuXino LIME
+        items:
+          - const: olimex,a20-olinuxino-lime
+          - const: allwinner,sun7i-a20
+
+      - description: Olimex A20-OlinuXino LIME2
+        items:
+          - const: olimex,a20-olinuxino-lime2
+          - const: allwinner,sun7i-a20
+
+      - description: Olimex A20-OlinuXino LIME2 (with eMMC)
+        items:
+          - const: olimex,a20-olinuxino-lime2-emmc
+          - const: allwinner,sun7i-a20
+
+      - description: Olimex A20-OlinuXino Micro
+        items:
+          - const: olimex,a20-olinuxino-micro
+          - const: allwinner,sun7i-a20
+
+      - description: Olimex A20-OlinuXino Micro (with eMMC)
+        items:
+          - const: olimex,a20-olinuxino-micro-emmc
+          - const: allwinner,sun7i-a20
+
+      - description: Olimex A20-SOM204 Evaluation Board
+        items:
+          - const: olimex,a20-olimex-som204-evb
+          - const: allwinner,sun7i-a20
+
+      - description: Olimex A20-SOM204 Evaluation Board (with eMMC)
+        items:
+          - const: olimex,a20-olimex-som204-evb-emmc
+          - const: allwinner,sun7i-a20
+
+      - description: Olimex A33-OlinuXino
+        items:
+          - const: olimex,a33-olinuxino
+          - const: allwinner,sun8i-a33
+
+      - description: Olimex A64-OlinuXino
+        items:
+          - const: olimex,a64-olinuxino
+          - const: allwinner,sun50i-a64
+
+      - description: Olimex A64 Teres-I
+        items:
+          - const: olimex,a64-teres-i
+          - const: allwinner,sun50i-a64
+
+      - description: Pine64
+        items:
+          - const: pine64,pine64
+          - const: allwinner,sun50i-a64
+
+      - description: Pine64+
+        items:
+          - const: pine64,pine64-plus
+          - const: allwinner,sun50i-a64
+
+      - description: Pine64 PineH64
+        items:
+          - const: pine64,pine-h64
+          - const: allwinner,sun50i-h6
+
+      - description: Pine64 LTS
+        items:
+          - const: pine64,pine64-lts
+          - const: allwinner,sun50i-r18
+          - const: allwinner,sun50i-a64
+
+      - description: Pine64 Pinebook
+        items:
+          - const: pine64,pinebook
+          - const: allwinner,sun50i-a64
+
+      - description: Pine64 SoPine Baseboard
+        items:
+          - const: pine64,sopine-baseboard
+          - const: pine64,sopine
+          - const: allwinner,sun50i-a64
+
+      - description: PineRiver Mini X-Plus
+        items:
+          - const: pineriver,mini-xplus
+          - const: allwinner,sun4i-a10
+
+      - description: Point of View Protab2-IPS9
+        items:
+          - const: pov,protab2-ips9
+          - const: allwinner,sun4i-a10
+
+      - description: Polaroid MID2407PXE03 Tablet
+        items:
+          - const: polaroid,mid2407pxe03
+          - const: allwinner,sun8i-a23
+
+      - description: Polaroid MID2809PXE04 Tablet
+        items:
+          - const: polaroid,mid2809pxe04
+          - const: allwinner,sun8i-a23
+
+      - description: Q8 A13 Tablet
+        items:
+          - const: allwinner,q8-a13
+          - const: allwinner,sun5i-a13
+
+      - description: Q8 A23 Tablet
+        items:
+          - const: allwinner,q8-a23
+          - const: allwinner,sun8i-a23
+
+      - description: Q8 A33 Tablet
+        items:
+          - const: allwinner,q8-a33
+          - const: allwinner,sun8i-a33
+
+      - description: Qihua CQA3T BV3
+        items:
+          - const: qihua,t3-cqa3t-bv3
+          - const: allwinner,sun8i-t3
+          - const: allwinner,sun8i-r40
+
+      - description: R7 A10s HDMI TV Stick
+        items:
+          - const: allwinner,r7-tv-dongle
+          - const: allwinner,sun5i-a10s
+
+      - description: RerVision H3-DVK
+        items:
+          - const: rervision,h3-dvk
+          - const: allwinner,sun8i-h3
+
+      - description: Sinlinx SinA31s Core Board
+        items:
+          - const: sinlinx,sina31s
+          - const: allwinner,sun6i-a31s
+
+      - description: Sinlinx SinA31s Development Board
+        items:
+          - const: sinlinx,sina31s-sdk
+          - const: allwinner,sun6i-a31s
+
+      - description: Sinlinx SinA33
+        items:
+          - const: sinlinx,sina33
+          - const: allwinner,sun8i-a33
+
+      - description: TBS A711 Tablet
+        items:
+          - const: tbs-biometrics,a711
+          - const: allwinner,sun8i-a83t
+
+      - description: Utoo P66
+        items:
+          - const: utoo,p66
+          - const: allwinner,sun5i-a13
+
+      - description: Wexler TAB7200
+        items:
+          - const: wexler,tab7200
+          - const: allwinner,sun7i-a20
+
+      - description: WITS A31 Colombus Evaluation Board
+        items:
+          - const: wits,colombus
+          - const: allwinner,sun6i-a31
+
+      - description: WITS Pro A20 DKT
+        items:
+          - const: wits,pro-a20-dkt
+          - const: allwinner,sun7i-a20
+
+      - description: Wobo i5
+        items:
+          - const: wobo,a10s-wobo-i5
+          - const: allwinner,sun5i-a10s
+
+      - description: Yones TopTech BS1078 v2 Tablet
+        items:
+          - const: yones-toptech,bs1078-v2
+          - const: allwinner,sun6i-a31s
+
+      - description: Xunlong OrangePi
+        items:
+          - const: xunlong,orangepi
+          - const: allwinner,sun7i-a20
+
+      - description: Xunlong OrangePi 2
+        items:
+          - const: xunlong,orangepi-2
+          - const: allwinner,sun8i-h3
+
+      - description: Xunlong OrangePi 3
+        items:
+          - const: xunlong,orangepi-3
+          - const: allwinner,sun50i-h6
+
+      - description: Xunlong OrangePi Lite
+        items:
+          - const: xunlong,orangepi-lite
+          - const: allwinner,sun8i-h3
+
+      - description: Xunlong OrangePi Lite2
+        items:
+          - const: xunlong,orangepi-lite2
+          - const: allwinner,sun50i-h6
+
+      - description: Xunlong OrangePi Mini
+        items:
+          - const: xunlong,orangepi-mini
+          - const: allwinner,sun7i-a20
+
+      - description: Xunlong OrangePi One
+        items:
+          - const: xunlong,orangepi-one
+          - const: allwinner,sun8i-h3
+
+      - description: Xunlong OrangePi One Plus
+        items:
+          - const: xunlong,orangepi-one-plus
+          - const: allwinner,sun50i-h6
+
+      - description: Xunlong OrangePi PC
+        items:
+          - const: xunlong,orangepi-pc
+          - const: allwinner,sun8i-h3
+
+      - description: Xunlong OrangePi PC 2
+        items:
+          - const: xunlong,orangepi-pc2
+          - const: allwinner,sun50i-h5
+
+      - description: Xunlong OrangePi PC Plus
+        items:
+          - const: xunlong,orangepi-pc-plus
+          - const: allwinner,sun8i-h3
+
+      - description: Xunlong OrangePi Plus
+        items:
+          - const: xunlong,orangepi-plus
+          - const: allwinner,sun8i-h3
+
+      - description: Xunlong OrangePi Plus 2E
+        items:
+          - const: xunlong,orangepi-plus2e
+          - const: allwinner,sun8i-h3
+
+      - description: Xunlong OrangePi Prime
+        items:
+          - const: xunlong,orangepi-prime
+          - const: allwinner,sun50i-h5
+
+      - description: Xunlong OrangePi R1
+        items:
+          - const: xunlong,orangepi-r1
+          - const: allwinner,sun8i-h2-plus
+
+      - description: Xunlong OrangePi Win
+        items:
+          - const: xunlong,orangepi-win
+          - const: allwinner,sun50i-a64
+
+      - description: Xunlong OrangePi Zero
+        items:
+          - const: xunlong,orangepi-zero
+          - const: allwinner,sun8i-h2-plus
+
+      - description: Xunlong OrangePi Zero Plus
+        items:
+          - const: xunlong,orangepi-zero-plus
+          - const: allwinner,sun50i-h5
+
+      - description: Xunlong OrangePi Zero Plus2
+        items:
+          - const: xunlong,orangepi-zero-plus2
+          - const: allwinner,sun50i-h5
+
+      - description: Xunlong OrangePi Zero Plus2
+        items:
+          - const: xunlong,orangepi-zero-plus2-h3
+          - const: allwinner,sun8i-h3

diff --git a/Documentation/devicetree/bindings/clock/xlnx,zynqmp-clk.txt b/Documentation/devicetree/bindings/clock/xlnx,zynqmp-clk.txt
new file mode 100644 (file)
index 0000000..391ee1a
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/xlnx,zynqmp-clk.txt
@@ -0,0 +1,63 @@
+--------------------------------------------------------------------------
+Device Tree Clock bindings for the Zynq Ultrascale+ MPSoC controlled using
+Zynq MPSoC firmware interface
+--------------------------------------------------------------------------
+The clock controller is a h/w block of Zynq Ultrascale+ MPSoC clock
+tree. It reads required input clock frequencies from the devicetree and acts
+as clock provider for all clock consumers of PS clocks.
+
+See clock_bindings.txt for more information on the generic clock bindings.
+
+Required properties:
+ - #clock-cells:       Must be 1
+ - compatible:         Must contain:   "xlnx,zynqmp-clk"
+ - clocks:             List of clock specifiers which are external input
+                       clocks to the given clock controller. Please refer
+                       the next section to find the input clocks for a
+                       given controller.
+ - clock-names:                List of clock names which are exteral input clocks
+                       to the given clock controller. Please refer to the
+                       clock bindings for more details.
+
+Input clocks for zynqmp Ultrascale+ clock controller:
+
+The Zynq UltraScale+ MPSoC has one primary and four alternative reference clock
+inputs. These required clock inputs are:
+ - pss_ref_clk (PS reference clock)
+ - video_clk (reference clock for video system )
+ - pss_alt_ref_clk (alternative PS reference clock)
+ - aux_ref_clk
+ - gt_crx_ref_clk (transceiver reference clock)
+
+The following strings are optional parameters to the 'clock-names' property in
+order to provide an optional (E)MIO clock source:
+ - swdt0_ext_clk
+ - swdt1_ext_clk
+ - gem0_emio_clk
+ - gem1_emio_clk
+ - gem2_emio_clk
+ - gem3_emio_clk
+ - mio_clk_XX          # with XX = 00..77
+ - mio_clk_50_or_51    #for the mux clock to gem tsu from 50 or 51
+
+
+Output clocks are registered based on clock information received
+from firmware. Output clocks indexes are mentioned in
+include/dt-bindings/clock/xlnx-zynqmp-clk.h.
+
+-------
+Example
+-------
+
+firmware {
+       zynqmp_firmware: zynqmp-firmware {
+               compatible = "xlnx,zynqmp-firmware";
+               method = "smc";
+               zynqmp_clk: clock-controller {
+                       #clock-cells = <1>;
+                       compatible = "xlnx,zynqmp-clk";
+                       clocks = <&pss_ref_clk>, <&video_clk>, <&pss_alt_ref_clk>, <&aux_ref_clk>, <&gt_crx_ref_clk>;
+                       clock-names = "pss_ref_clk", "video_clk", "pss_alt_ref_clk","aux_ref_clk", "gt_crx_ref_clk";
+               };
+       };
+};

diff --git a/Documentation/devicetree/bindings/dma/fsl-imx-sdma.txt b/Documentation/devicetree/bindings/dma/fsl-imx-sdma.txt
index 3c9a57a..9d8bbac 100644 (file)
--- a/Documentation/devicetree/bindings/dma/fsl-imx-sdma.txt
+++ b/Documentation/devicetree/bindings/dma/fsl-imx-sdma.txt
@@ -9,6 +9,7 @@ Required properties:
       "fsl,imx53-sdma"
       "fsl,imx6q-sdma"
       "fsl,imx7d-sdma"
+      "fsl,imx8mq-sdma"
   The -to variants should be preferred since they allow to determine the
   correct ROM script addresses needed for the driver to work without additional
   firmware.

diff --git a/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.txt b/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.txt
index 614bac5..a4fe136 100644 (file)
--- a/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.txt
+++ b/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.txt
@@ -17,53 +17,6 @@ Required properties:
                  - "smc" : SMC #0, following the SMCCC
                  - "hvc" : HVC #0, following the SMCCC
 
---------------------------------------------------------------------------
-Device Tree Clock bindings for the Zynq Ultrascale+ MPSoC controlled using
-Zynq MPSoC firmware interface
---------------------------------------------------------------------------
-The clock controller is a h/w block of Zynq Ultrascale+ MPSoC clock
-tree. It reads required input clock frequencies from the devicetree and acts
-as clock provider for all clock consumers of PS clocks.
-
-See clock_bindings.txt for more information on the generic clock bindings.
-
-Required properties:
- - #clock-cells:       Must be 1
- - compatible:         Must contain:   "xlnx,zynqmp-clk"
- - clocks:             List of clock specifiers which are external input
-                       clocks to the given clock controller. Please refer
-                       the next section to find the input clocks for a
-                       given controller.
- - clock-names:                List of clock names which are exteral input clocks
-                       to the given clock controller. Please refer to the
-                       clock bindings for more details.
-
-Input clocks for zynqmp Ultrascale+ clock controller:
-
-The Zynq UltraScale+ MPSoC has one primary and four alternative reference clock
-inputs. These required clock inputs are:
- - pss_ref_clk (PS reference clock)
- - video_clk (reference clock for video system )
- - pss_alt_ref_clk (alternative PS reference clock)
- - aux_ref_clk
- - gt_crx_ref_clk (transceiver reference clock)
-
-The following strings are optional parameters to the 'clock-names' property in
-order to provide an optional (E)MIO clock source:
- - swdt0_ext_clk
- - swdt1_ext_clk
- - gem0_emio_clk
- - gem1_emio_clk
- - gem2_emio_clk
- - gem3_emio_clk
- - mio_clk_XX          # with XX = 00..77
- - mio_clk_50_or_51    #for the mux clock to gem tsu from 50 or 51
-
-
-Output clocks are registered based on clock information received
-from firmware. Output clocks indexes are mentioned in
-include/dt-bindings/clock/xlnx,zynqmp-clk.h.
-
 -------
 Example
 -------
@@ -72,11 +25,6 @@ firmware {
        zynqmp_firmware: zynqmp-firmware {
                compatible = "xlnx,zynqmp-firmware";
                method = "smc";
-               zynqmp_clk: clock-controller {
-                       #clock-cells = <1>;
-                       compatible = "xlnx,zynqmp-clk";
-                       clocks = <&pss_ref_clk>, <&video_clk>, <&pss_alt_ref_clk>, <&aux_ref_clk>, <&gt_crx_ref_clk>;
-                       clock-names = "pss_ref_clk", "video_clk", "pss_alt_ref_clk","aux_ref_clk", "gt_crx_ref_clk";
-               };
+               ...
        };
 };

diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt b/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt
index 18a2cde..1b1a741 100644 (file)
--- a/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt
+++ b/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt
@@ -37,6 +37,20 @@ Optional properties:
 - operating-points-v2 : Refer to Documentation/devicetree/bindings/opp/opp.txt
   for details.
 
+- resets : Phandle of the GPU reset line.
+
+Vendor-specific bindings
+------------------------
+
+The Mali GPU is integrated very differently from one SoC to
+another. In order to accomodate those differences, you have the option
+to specify one more vendor-specific compatible, among:
+
+- "amlogic,meson-gxm-mali"
+  Required properties:
+  - resets : Should contain phandles of :
+    + GPU reset line
+    + GPU APB glue reset line
 
 Example for a Mali-T760:
 

diff --git a/Documentation/devicetree/bindings/hwmon/pwm-fan.txt b/Documentation/devicetree/bindings/hwmon/pwm-fan.txt
index 6ced829..41b7676 100644 (file)
--- a/Documentation/devicetree/bindings/hwmon/pwm-fan.txt
+++ b/Documentation/devicetree/bindings/hwmon/pwm-fan.txt
@@ -21,8 +21,6 @@ Optional properties:
 Example:
        fan0: pwm-fan {
                compatible = "pwm-fan";
-               cooling-min-state = <0>;
-               cooling-max-state = <3>;
                #cooling-cells = <2>;
                pwms = <&pwm 0 10000 0>;
                cooling-levels = <0 102 170 230>;

diff --git a/Documentation/devicetree/bindings/iio/adc/imx7d-adc.txt b/Documentation/devicetree/bindings/iio/adc/imx7d-adc.txt
index 5c184b9..f1f3a55 100644 (file)
--- a/Documentation/devicetree/bindings/iio/adc/imx7d-adc.txt
+++ b/Documentation/devicetree/bindings/iio/adc/imx7d-adc.txt
@@ -10,6 +10,7 @@ Required properties:
 - clocks: The root clock of the ADC controller
 - clock-names: Must contain "adc", matching entry in the clocks property
 - vref-supply: The regulator supply ADC reference voltage
+- #io-channel-cells: Must be 1 as per ../iio-bindings.txt
 
 Example:
 adc1: adc@30610000 {
@@ -19,4 +20,5 @@ adc1: adc@30610000 {
        clocks = <&clks IMX7D_ADC_ROOT_CLK>;
        clock-names = "adc";
        vref-supply = <&reg_vcc_3v3_mcu>;
+       #io-channel-cells = <1>;
 };

diff --git a/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.txt b/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.txt
index c81993f..c878768 100644 (file)
--- a/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.txt
+++ b/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.txt
@@ -13,6 +13,7 @@ VADC node:
     Definition: Should contain "qcom,spmi-vadc".
                 Should contain "qcom,spmi-adc5" for PMIC5 ADC driver.
                 Should contain "qcom,spmi-adc-rev2" for PMIC rev2 ADC driver.
+                Should contain "qcom,pms405-adc" for PMS405 PMIC
 
 - reg:
     Usage: required

diff --git a/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt b/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt
index c5d5891..0e312fe 100644 (file)
--- a/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt
+++ b/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt
@@ -1,15 +1,18 @@
-+Mediatek MT65xx/MT67xx/MT81xx sysirq
+MediaTek sysirq
 
-Mediatek SOCs sysirq support controllable irq inverter for each GIC SPI
+MediaTek SOCs sysirq support controllable irq inverter for each GIC SPI
 interrupt.
 
 Required properties:
 - compatible: should be
+       "mediatek,mt8516-sysirq", "mediatek,mt6577-sysirq": for MT8516
+       "mediatek,mt8183-sysirq", "mediatek,mt6577-sysirq": for MT8183
        "mediatek,mt8173-sysirq", "mediatek,mt6577-sysirq": for MT8173
        "mediatek,mt8135-sysirq", "mediatek,mt6577-sysirq": for MT8135
        "mediatek,mt8127-sysirq", "mediatek,mt6577-sysirq": for MT8127
        "mediatek,mt7622-sysirq", "mediatek,mt6577-sysirq": for MT7622
        "mediatek,mt7623-sysirq", "mediatek,mt6577-sysirq": for MT7623
+       "mediatek,mt7629-sysirq", "mediatek,mt6577-sysirq": for MT7629
        "mediatek,mt6795-sysirq", "mediatek,mt6577-sysirq": for MT6795
        "mediatek,mt6797-sysirq", "mediatek,mt6577-sysirq": for MT6797
        "mediatek,mt6765-sysirq", "mediatek,mt6577-sysirq": for MT6765

diff --git a/Documentation/devicetree/bindings/memory-controllers/fsl/mmdc.txt b/Documentation/devicetree/bindings/memory-controllers/fsl/mmdc.txt
new file mode 100644 (file)
index 0000000..bcc36c5
--- /dev/null
+++ b/Documentation/devicetree/bindings/memory-controllers/fsl/mmdc.txt
@@ -0,0 +1,35 @@
+Freescale Multi Mode DDR controller (MMDC)
+
+Required properties :
+- compatible : should be one of following:
+       for i.MX6Q/i.MX6DL:
+       - "fsl,imx6q-mmdc";
+       for i.MX6QP:
+       - "fsl,imx6qp-mmdc", "fsl,imx6q-mmdc";
+       for i.MX6SL:
+       - "fsl,imx6sl-mmdc", "fsl,imx6q-mmdc";
+       for i.MX6SLL:
+       - "fsl,imx6sll-mmdc", "fsl,imx6q-mmdc";
+       for i.MX6SX:
+       - "fsl,imx6sx-mmdc", "fsl,imx6q-mmdc";
+       for i.MX6UL/i.MX6ULL/i.MX6ULZ:
+       - "fsl,imx6ul-mmdc", "fsl,imx6q-mmdc";
+       for i.MX7ULP:
+       - "fsl,imx7ulp-mmdc", "fsl,imx6q-mmdc";
+- reg : address and size of MMDC DDR controller registers
+
+Optional properties :
+- clocks : the clock provided by the SoC to access the MMDC registers
+
+Example :
+       mmdc0: memory-controller@21b0000 { /* MMDC0 */
+               compatible = "fsl,imx6q-mmdc";
+               reg = <0x021b0000 0x4000>;
+               clocks = <&clks IMX6QDL_CLK_MMDC_P0_IPG>;
+       };
+
+       mmdc1: memory-controller@21b4000 { /* MMDC1 */
+               compatible = "fsl,imx6q-mmdc";
+               reg = <0x021b4000 0x4000>;
+               status = "disabled";
+       };

diff --git a/Documentation/devicetree/bindings/mmc/k3-dw-mshc.txt b/Documentation/devicetree/bindings/mmc/k3-dw-mshc.txt
index 07242d1..36c4bea 100644 (file)
--- a/Documentation/devicetree/bindings/mmc/k3-dw-mshc.txt
+++ b/Documentation/devicetree/bindings/mmc/k3-dw-mshc.txt
@@ -13,6 +13,8 @@ Required Properties:
 
 * compatible: should be one of the following.
   - "hisilicon,hi3660-dw-mshc": for controllers with hi3660 specific extensions.
+  - "hisilicon,hi3670-dw-mshc", "hisilicon,hi3660-dw-mshc": for controllers
+     with hi3670 specific extensions.
   - "hisilicon,hi4511-dw-mshc": for controllers with hi4511 specific extensions.
   - "hisilicon,hi6220-dw-mshc": for controllers with hi6220 specific extensions.
 

diff --git a/Documentation/devicetree/bindings/power/amlogic,meson-gx-pwrc.txt b/Documentation/devicetree/bindings/power/amlogic,meson-gx-pwrc.txt
index 1cd050b..0fdc3dd 100644 (file)
--- a/Documentation/devicetree/bindings/power/amlogic,meson-gx-pwrc.txt
+++ b/Documentation/devicetree/bindings/power/amlogic,meson-gx-pwrc.txt
@@ -16,7 +16,9 @@ Device Tree Bindings:
 ---------------------
 
 Required properties:
-- compatible: should be "amlogic,meson-gx-pwrc-vpu" for the Meson GX SoCs
+- compatible: should be one of the following :
+       - "amlogic,meson-gx-pwrc-vpu" for the Meson GX SoCs
+       - "amlogic,meson-g12a-pwrc-vpu" for the Meson G12A SoCs
 - #power-domain-cells: should be 0
 - amlogic,hhi-sysctrl: phandle to the HHI sysctrl node
 - resets: phandles to the reset lines needed for this power demain sequence

diff --git a/Documentation/devicetree/bindings/reset/hisilicon,hi3660-reset.txt b/Documentation/devicetree/bindings/reset/hisilicon,hi3660-reset.txt
index 2bf3344..2df4bdd 100644 (file)
--- a/Documentation/devicetree/bindings/reset/hisilicon,hi3660-reset.txt
+++ b/Documentation/devicetree/bindings/reset/hisilicon,hi3660-reset.txt
@@ -5,11 +5,12 @@ Please also refer to reset.txt in this directory for common reset
 controller binding usage.
 
 The reset controller registers are part of the system-ctl block on
-hi3660 SoC.
+hi3660 and hi3670 SoCs.
 
 Required properties:
-- compatible: should be
-                "hisilicon,hi3660-reset"
+- compatible: should be one of the following:
+                "hisilicon,hi3660-reset" for HI3660
+                "hisilicon,hi3670-reset", "hisilicon,hi3660-reset" for HI3670
 - hisi,rst-syscon: phandle of the reset's syscon.
 - #reset-cells : Specifies the number of cells needed to encode a
   reset source.  The type shall be a <u32> and the value shall be 2.

diff --git a/Documentation/devicetree/bindings/serial/mtk-uart.txt b/Documentation/devicetree/bindings/serial/mtk-uart.txt
index bcfb131..c6b5262 100644 (file)
--- a/Documentation/devicetree/bindings/serial/mtk-uart.txt
+++ b/Documentation/devicetree/bindings/serial/mtk-uart.txt
@@ -1,4 +1,4 @@
-* Mediatek Universal Asynchronous Receiver/Transmitter (UART)
+* MediaTek Universal Asynchronous Receiver/Transmitter (UART)
 
 Required properties:
 - compatible should contain:
@@ -13,10 +13,12 @@ Required properties:
   * "mediatek,mt6797-uart" for MT6797 compatible UARTS
   * "mediatek,mt7622-uart" for MT7622 compatible UARTS
   * "mediatek,mt7623-uart" for MT7623 compatible UARTS
+  * "mediatek,mt7629-uart" for MT7629 compatible UARTS
   * "mediatek,mt8127-uart" for MT8127 compatible UARTS
   * "mediatek,mt8135-uart" for MT8135 compatible UARTS
   * "mediatek,mt8173-uart" for MT8173 compatible UARTS
   * "mediatek,mt8183-uart", "mediatek,mt6577-uart" for MT8183 compatible UARTS
+  * "mediatek,mt8516-uart" for MT8516 compatible UARTS
   * "mediatek,mt6577-uart" for MT6577 and all of the above
 
 - reg: The base address of the UART register bank.

diff --git a/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt b/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt
index d6fe16f..876693a 100644 (file)
--- a/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt
+++ b/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt
@@ -23,6 +23,7 @@ Required properties:
        - "mediatek,mt7622-scpsys"
        - "mediatek,mt7623-scpsys", "mediatek,mt2701-scpsys": For MT7623 SoC
        - "mediatek,mt7623a-scpsys": For MT7623A SoC
+       - "mediatek,mt7629-scpsys", "mediatek,mt7622-scpsys": For MT7629 SoC
        - "mediatek,mt8173-scpsys"
 - #power-domain-cells: Must be 1
 - reg: Address range of the SCPSYS unit
@@ -33,8 +34,8 @@ Required properties:
        Required clocks for MT2701 or MT7623: "mm", "mfg", "ethif"
        Required clocks for MT2712: "mm", "mfg", "venc", "jpgdec", "audio", "vdec"
        Required clocks for MT6797: "mm", "mfg", "vdec"
-       Required clocks for MT7622: "hif_sel"
-       Required clocks for MT7622A: "ethif"
+       Required clocks for MT7622 or MT7629: "hif_sel"
+       Required clocks for MT7623A: "ethif"
        Required clocks for MT8173: "mm", "mfg", "venc", "venc_lt"
 
 Optional properties:

diff --git a/Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt b/Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt
index ff7c567..74c3ead 100644 (file)
--- a/Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt
+++ b/Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt
@@ -17,6 +17,7 @@ Required properties:
        * "mediatek,mt8127-timer" for MT8127 compatible timers (GPT)
        * "mediatek,mt8135-timer" for MT8135 compatible timers (GPT)
        * "mediatek,mt8173-timer" for MT8173 compatible timers (GPT)
+       * "mediatek,mt8516-timer" for MT8516 compatible timers (GPT)
        * "mediatek,mt6577-timer" for MT6577 and all above compatible timers (GPT)
 
        For those SoCs that use SYST

diff --git a/Documentation/devicetree/bindings/ufs/ufshcd-pltfrm.txt b/Documentation/devicetree/bindings/ufs/ufshcd-pltfrm.txt
index 56bccde..a747204 100644 (file)
--- a/Documentation/devicetree/bindings/ufs/ufshcd-pltfrm.txt
+++ b/Documentation/devicetree/bindings/ufs/ufshcd-pltfrm.txt
@@ -11,6 +11,7 @@ Required properties:
                          the appropriate jedec string:
                            "qcom,msm8994-ufshc", "qcom,ufshc", "jedec,ufs-2.0"
                            "qcom,msm8996-ufshc", "qcom,ufshc", "jedec,ufs-2.0"
+                           "qcom,msm8998-ufshc", "qcom,ufshc", "jedec,ufs-2.0"
                            "qcom,sdm845-ufshc", "qcom,ufshc", "jedec,ufs-2.0"
 - interrupts        : <interrupt mapping for UFS host controller IRQ>
 - reg               : <registers mapping>

diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt
index e0e2160..e9034a6 100644 (file)
--- a/Documentation/devicetree/bindings/vendor-prefixes.txt
+++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
@@ -56,6 +56,7 @@ avnet Avnet, Inc.
 axentia        Axentia Technologies AB
 axis   Axis Communications AB
 azoteq Azoteq (Pty) Ltd
+azw     Shenzhen AZW Technology Co., Ltd.
 bananapi BIPAI KEJI LIMITED
 bhf    Beckhoff Automation GmbH & Co. KG
 bitmain        Bitmain Technologies
@@ -213,6 +214,7 @@ kinetic Kinetic Technologies
 kingdisplay    King & Display Technology Co., Ltd.
 kingnovel      Kingnovel Technology Co., Ltd.
 kionix Kionix, Inc.
+kobo   Rakuten Kobo Inc.
 koe    Kaohsiung Opto-Electronics Inc.
 kosagi Sutajio Ko-Usagi PTE Ltd.
 kyo    Kyocera Corporation
@@ -248,6 +250,7 @@ melexis     Melexis N.V.
 melfas MELFAS Inc.
 mellanox       Mellanox Technologies
 memsic MEMSIC Inc.
+menlo  Menlo Systems GmbH
 merrii Merrii Technology Co., Ltd.
 micrel Micrel Inc.
 microchip      Microchip Technology Inc.
@@ -291,6 +294,7 @@ nuvoton     Nuvoton Technology Corporation
 nvd    New Vision Display
 nvidia NVIDIA
 nxp    NXP Semiconductors
+oceanic        Oceanic Systems (UK) Ltd.
 okaya  Okaya Electric America, Inc.
 oki    Oki Electric Industry Co., Ltd.
 olimex OLIMEX Ltd.
@@ -360,6 +364,7 @@ sandisk     Sandisk Corporation
 sbs    Smart Battery System
 schindler      Schindler
 seagate        Seagate Technology PLC
+seirobotics    Shenzhen SEI Robotics Co., Ltd
 semtech        Semtech Corporation
 sensirion      Sensirion AG
 sff    Small Form Factor Committee
@@ -368,6 +373,7 @@ sgx SGX Sensortech
 sharp  Sharp Corporation
 shimafuji      Shimafuji Electric, Inc.
 si-en  Si-En Technology Ltd.
+si-linux       Silicon Linux Corporation
 sifive SiFive, Inc.
 sigma  Sigma Designs, Inc.
 sii    Seiko Instruments, Inc.
@@ -422,6 +428,7 @@ toumaz      Toumaz
 tpk    TPK U.S.A. LLC
 tplink TP-LINK Technologies Co., Ltd.
 tpo    TPO
+tq     TQ Systems GmbH
 tronfy Tronfy
 tronsmart      Tronsmart
 truly  Truly Semiconductors Limited

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 7af4e32..dab2914 100644 (file)
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -366,7 +366,8 @@ dtb-$(CONFIG_SOC_IMX35) += \
        imx35-eukrea-mbimxsd35-baseboard.dtb \
        imx35-pdk.dtb
 dtb-$(CONFIG_SOC_IMX50) += \
-       imx50-evk.dtb
+       imx50-evk.dtb \
+       imx50-kobo-aura.dtb
 dtb-$(CONFIG_SOC_IMX51) += \
        imx51-apf51.dtb \
        imx51-apf51dev.dtb \
@@ -383,6 +384,7 @@ dtb-$(CONFIG_SOC_IMX53) += \
        imx53-kp-ddc.dtb \
        imx53-kp-hsc.dtb \
        imx53-m53evk.dtb \
+       imx53-m53menlo.dtb \
        imx53-mba53.dtb \
        imx53-ppd.dtb \
        imx53-qsb.dtb \
@@ -403,6 +405,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
        imx6dl-cubox-i-emmc-som-v15.dtb \
        imx6dl-cubox-i-som-v15.dtb \
        imx6dl-dfi-fs700-m60.dtb \
+       imx6dl-eckelmann-ci4x10.dtb \
        imx6dl-emcon-avari.dtb \
        imx6dl-gw51xx.dtb \
        imx6dl-gw52xx.dtb \
@@ -582,6 +585,7 @@ dtb-$(CONFIG_SOC_IMX7D) += \
        imx7d-cl-som-imx7.dtb \
        imx7d-colibri-emmc-eval-v3.dtb \
        imx7d-colibri-eval-v3.dtb \
+       imx7d-mba7.dtb \
        imx7d-nitrogen7.dtb \
        imx7d-pico-hobbit.dtb \
        imx7d-pico-pi.dtb \
@@ -589,7 +593,9 @@ dtb-$(CONFIG_SOC_IMX7D) += \
        imx7d-sdb.dtb \
        imx7d-sdb-reva.dtb \
        imx7d-sdb-sht11.dtb \
+       imx7d-zii-rpu2.dtb \
        imx7s-colibri-eval-v3.dtb \
+       imx7s-mba7.dtb \
        imx7s-warp.dtb
 dtb-$(CONFIG_SOC_IMX7ULP) += \
        imx7ulp-evk.dtb
@@ -609,6 +615,7 @@ dtb-$(CONFIG_SOC_VF610) += \
        vf610-zii-dev-rev-b.dtb \
        vf610-zii-dev-rev-c.dtb \
        vf610-zii-scu4-aib.dtb \
+       vf610-zii-spb4.dtb \
        vf610-zii-ssmb-dtu.dtb \
        vf610-zii-ssmb-spu3.dtb
 dtb-$(CONFIG_ARCH_MXS) += \
@@ -912,6 +919,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
        rk3288-veyron-jaq.dtb \
        rk3288-veyron-jerry.dtb \
        rk3288-veyron-mickey.dtb \
+       rk3288-veyron-mighty.dtb \
        rk3288-veyron-minnie.dtb \
        rk3288-veyron-pinky.dtb \
        rk3288-veyron-speedy.dtb \
@@ -967,6 +975,8 @@ dtb-$(CONFIG_ARCH_STM32) += \
        stm32746g-eval.dtb \
        stm32h743i-eval.dtb \
        stm32h743i-disco.dtb \
+       stm32mp157a-dk1.dtb \
+       stm32mp157c-dk2.dtb \
        stm32mp157c-ed1.dtb \
        stm32mp157c-ev1.dtb
 dtb-$(CONFIG_MACH_SUN4I) += \
@@ -1094,6 +1104,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \
        sun8i-h3-orangepi-plus.dtb \
        sun8i-h3-orangepi-plus2e.dtb \
        sun8i-h3-orangepi-zero-plus2.dtb \
+       sun8i-h3-rervision-dvk.dtb \
        sun8i-r16-bananapi-m2m.dtb \
        sun8i-r16-nintendo-nes-classic.dtb \
        sun8i-r16-nintendo-super-nes-classic.dtb \

diff --git a/arch/arm/boot/dts/am335x-baltos-ir2110.dts b/arch/arm/boot/dts/am335x-baltos-ir2110.dts
index 50dcf12..2f650a7 100644 (file)
--- a/arch/arm/boot/dts/am335x-baltos-ir2110.dts
+++ b/arch/arm/boot/dts/am335x-baltos-ir2110.dts
@@ -23,14 +23,14 @@
 &am33xx_pinmux {
        uart1_pins: pinmux_uart1_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x980, PIN_INPUT | MUX_MODE0)      /* uart1_rxd */
-                       AM33XX_IOPAD(0x984, PIN_INPUT | MUX_MODE0)      /* uart1_txd */
-                       AM33XX_IOPAD(0x978, PIN_INPUT_PULLDOWN | MUX_MODE0)      /* uart1_ctsn */
-                       AM33XX_IOPAD(0x97c, PIN_OUTPUT_PULLDOWN | MUX_MODE0)      /* uart1_rtsn */
-                       AM33XX_IOPAD(0x8e0, PIN_OUTPUT_PULLDOWN | MUX_MODE7)      /* lcd_vsync.gpio2[22] DTR */
-                       AM33XX_IOPAD(0x8e4, PIN_INPUT_PULLDOWN | MUX_MODE7)      /* lcd_hsync.gpio2[23] DSR */
-                       AM33XX_IOPAD(0x8e8, PIN_INPUT_PULLDOWN | MUX_MODE7)      /* lcd_pclk.gpio2[24] DCD */
-                       AM33XX_IOPAD(0x8ec, PIN_INPUT_PULLDOWN | MUX_MODE7)      /* lcd_ac_bias_en.gpio2[25] RI */
+                       AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_INPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLDOWN, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT_PULLDOWN, MUX_MODE7)      /* lcd_vsync.gpio2[22] DTR */
+                       AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_INPUT_PULLDOWN, MUX_MODE7)      /* lcd_hsync.gpio2[23] DSR */
+                       AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_INPUT_PULLDOWN, MUX_MODE7)      /* lcd_pclk.gpio2[24] DCD */
+                       AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_INPUT_PULLDOWN, MUX_MODE7)      /* lcd_ac_bias_en.gpio2[25] RI */
                >;
        };
 };

diff --git a/arch/arm/boot/dts/am335x-baltos-ir3220.dts b/arch/arm/boot/dts/am335x-baltos-ir3220.dts
index f3f1abd..1ba66d5 100644 (file)
--- a/arch/arm/boot/dts/am335x-baltos-ir3220.dts
+++ b/arch/arm/boot/dts/am335x-baltos-ir3220.dts
@@ -23,35 +23,35 @@
 &am33xx_pinmux {
        tca6416_pins: pinmux_tca6416_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x9b4, PIN_INPUT_PULLUP | MUX_MODE7)      /* xdma_event_intr1.gpio0[20] tca6416 stuff */
+                       AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR1, PIN_INPUT_PULLUP, MUX_MODE7)      /* xdma_event_intr1.gpio0[20] tca6416 stuff */
                >;
        };
 
        uart1_pins: pinmux_uart1_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x980, PIN_INPUT | MUX_MODE0)      /* uart1_rxd */
-                       AM33XX_IOPAD(0x984, PIN_INPUT | MUX_MODE0)      /* uart1_txd */
-                       AM33XX_IOPAD(0x978, PIN_INPUT_PULLDOWN | MUX_MODE0)      /* uart1_ctsn */
-                       AM33XX_IOPAD(0x97c, PIN_OUTPUT_PULLDOWN | MUX_MODE0)      /* uart1_rtsn */
-                       AM33XX_IOPAD(0x8e0, PIN_OUTPUT_PULLDOWN | MUX_MODE7)      /* lcd_vsync.gpio2[22] DTR */
-                       AM33XX_IOPAD(0x8e4, PIN_INPUT_PULLDOWN | MUX_MODE7)      /* lcd_hsync.gpio2[23] DSR */
-                       AM33XX_IOPAD(0x8e8, PIN_INPUT_PULLDOWN | MUX_MODE7)      /* lcd_pclk.gpio2[24] DCD */
-                       AM33XX_IOPAD(0x8ec, PIN_INPUT_PULLDOWN | MUX_MODE7)      /* lcd_ac_bias_en.gpio2[25] RI */
+                       AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_INPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLDOWN, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT_PULLDOWN, MUX_MODE7)      /* lcd_vsync.gpio2[22] DTR */
+                       AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_INPUT_PULLDOWN, MUX_MODE7)      /* lcd_hsync.gpio2[23] DSR */
+                       AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_INPUT_PULLDOWN, MUX_MODE7)      /* lcd_pclk.gpio2[24] DCD */
+                       AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_INPUT_PULLDOWN, MUX_MODE7)      /* lcd_ac_bias_en.gpio2[25] RI */
                >;
        };
 
        uart2_pins: pinmux_uart2_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x950, PIN_INPUT | MUX_MODE1)      /* spi0_sclk.uart2_rxd_mux3 */
-                       AM33XX_IOPAD(0x954, PIN_OUTPUT | MUX_MODE1)      /* spi0_d0.uart2_txd_mux3 */
-                       AM33XX_IOPAD(0x988, PIN_INPUT_PULLDOWN | MUX_MODE2)      /* i2c0_sda.uart2_ctsn_mux0 */
-                       AM33XX_IOPAD(0x98c, PIN_OUTPUT_PULLDOWN | MUX_MODE2)      /* i2c0_scl.uart2_rtsn_mux0 */
-                       AM33XX_IOPAD(0x830, PIN_OUTPUT_PULLDOWN | MUX_MODE7)      /* gpmc_ad12.gpio1[12] DTR */
-                       AM33XX_IOPAD(0x834, PIN_INPUT_PULLDOWN | MUX_MODE7)      /* gpmc_ad13.gpio1[13] DSR */
-                       AM33XX_IOPAD(0x838, PIN_INPUT_PULLDOWN | MUX_MODE7)      /* gpmc_ad14.gpio1[14] DCD */
-                       AM33XX_IOPAD(0x83c, PIN_INPUT_PULLDOWN | MUX_MODE7)     /* gpmc_ad15.gpio1[15] RI */
-
-                       AM33XX_IOPAD(0x9a0, PIN_INPUT_PULLUP | MUX_MODE7)      /* mcasp0_aclkr.gpio3[18], INPUT_PULLDOWN | MODE7 */
+                       AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT, MUX_MODE1)      /* spi0_sclk.uart2_rxd_mux3 */
+                       AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_OUTPUT, MUX_MODE1)      /* spi0_d0.uart2_txd_mux3 */
+                       AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLDOWN, MUX_MODE2)      /* i2c0_sda.uart2_ctsn_mux0 */
+                       AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_OUTPUT_PULLDOWN, MUX_MODE2)      /* i2c0_scl.uart2_rtsn_mux0 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_OUTPUT_PULLDOWN, MUX_MODE7)      /* gpmc_ad12.gpio1[12] DTR */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT_PULLDOWN, MUX_MODE7)      /* gpmc_ad13.gpio1[13] DSR */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_INPUT_PULLDOWN, MUX_MODE7)      /* gpmc_ad14.gpio1[14] DCD */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_INPUT_PULLDOWN, MUX_MODE7)     /* gpmc_ad15.gpio1[15] RI */
+
+                       AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKR, PIN_INPUT_PULLUP, MUX_MODE7)      /* mcasp0_aclkr.gpio3[18], INPUT_PULLDOWN | MODE7 */
                >;
        };
 };

diff --git a/arch/arm/boot/dts/am335x-baltos-ir5221.dts b/arch/arm/boot/dts/am335x-baltos-ir5221.dts
index 42f473f..eed65fc 100644 (file)
--- a/arch/arm/boot/dts/am335x-baltos-ir5221.dts
+++ b/arch/arm/boot/dts/am335x-baltos-ir5221.dts
@@ -23,43 +23,43 @@
 &am33xx_pinmux {
        tca6416_pins: pinmux_tca6416_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x9b4, PIN_INPUT_PULLUP | MUX_MODE7)      /* xdma_event_intr1.gpio0[20] tca6416 stuff */
+                       AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR1, PIN_INPUT_PULLUP, MUX_MODE7)      /* xdma_event_intr1.gpio0[20] tca6416 stuff */
                >;
        };
 
 
        dcan1_pins: pinmux_dcan1_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x968, PIN_OUTPUT | MUX_MODE2)      /* uart0_ctsn.dcan1_tx_mux0 */
-                       AM33XX_IOPAD(0x96c, PIN_INPUT | MUX_MODE2)      /* uart0_rtsn.dcan1_rx_mux0 */
+                       AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_OUTPUT, MUX_MODE2)      /* uart0_ctsn.dcan1_tx_mux0 */
+                       AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT, MUX_MODE2)      /* uart0_rtsn.dcan1_rx_mux0 */
                >;
        };
 
        uart1_pins: pinmux_uart1_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x980, PIN_INPUT | MUX_MODE0)      /* uart1_rxd */
-                       AM33XX_IOPAD(0x984, PIN_INPUT | MUX_MODE0)      /* uart1_txd */
-                       AM33XX_IOPAD(0x978, PIN_INPUT_PULLDOWN | MUX_MODE0)      /* uart1_ctsn */
-                       AM33XX_IOPAD(0x97c, PIN_OUTPUT_PULLDOWN | MUX_MODE0)      /* uart1_rtsn */
-                       AM33XX_IOPAD(0x8e0, PIN_OUTPUT_PULLDOWN | MUX_MODE7)      /* lcd_vsync.gpio2[22] DTR */
-                       AM33XX_IOPAD(0x8e4, PIN_INPUT_PULLDOWN | MUX_MODE7)      /* lcd_hsync.gpio2[23] DSR */
-                       AM33XX_IOPAD(0x8e8, PIN_INPUT_PULLDOWN | MUX_MODE7)      /* lcd_pclk.gpio2[24] DCD */
-                       AM33XX_IOPAD(0x8ec, PIN_INPUT_PULLDOWN | MUX_MODE7)      /* lcd_ac_bias_en.gpio2[25] RI */
+                       AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_INPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLDOWN, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT_PULLDOWN, MUX_MODE7)      /* lcd_vsync.gpio2[22] DTR */
+                       AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_INPUT_PULLDOWN, MUX_MODE7)      /* lcd_hsync.gpio2[23] DSR */
+                       AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_INPUT_PULLDOWN, MUX_MODE7)      /* lcd_pclk.gpio2[24] DCD */
+                       AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_INPUT_PULLDOWN, MUX_MODE7)      /* lcd_ac_bias_en.gpio2[25] RI */
                >;
        };
 
        uart2_pins: pinmux_uart2_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x950, PIN_INPUT | MUX_MODE1)      /* spi0_sclk.uart2_rxd_mux3 */
-                       AM33XX_IOPAD(0x954, PIN_OUTPUT | MUX_MODE1)      /* spi0_d0.uart2_txd_mux3 */
-                       AM33XX_IOPAD(0x988, PIN_INPUT_PULLDOWN | MUX_MODE2)      /* i2c0_sda.uart2_ctsn_mux0 */
-                       AM33XX_IOPAD(0x98c, PIN_OUTPUT_PULLDOWN | MUX_MODE2)      /* i2c0_scl.uart2_rtsn_mux0 */
-                       AM33XX_IOPAD(0x830, PIN_OUTPUT_PULLDOWN | MUX_MODE7)      /* gpmc_ad12.gpio1[12] DTR */
-                       AM33XX_IOPAD(0x834, PIN_INPUT_PULLDOWN | MUX_MODE7)      /* gpmc_ad13.gpio1[13] DSR */
-                       AM33XX_IOPAD(0x838, PIN_INPUT_PULLDOWN | MUX_MODE7)      /* gpmc_ad14.gpio1[14] DCD */
-                       AM33XX_IOPAD(0x83c, PIN_INPUT_PULLDOWN | MUX_MODE7)     /* gpmc_ad15.gpio1[15] RI */
-
-                       AM33XX_IOPAD(0x9a0, PIN_INPUT_PULLUP | MUX_MODE7)      /* mcasp0_aclkr.gpio3[18], INPUT_PULLDOWN | MODE7 */
+                       AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT, MUX_MODE1)      /* spi0_sclk.uart2_rxd_mux3 */
+                       AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_OUTPUT, MUX_MODE1)      /* spi0_d0.uart2_txd_mux3 */
+                       AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLDOWN, MUX_MODE2)      /* i2c0_sda.uart2_ctsn_mux0 */
+                       AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_OUTPUT_PULLDOWN, MUX_MODE2)      /* i2c0_scl.uart2_rtsn_mux0 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_OUTPUT_PULLDOWN, MUX_MODE7)      /* gpmc_ad12.gpio1[12] DTR */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT_PULLDOWN, MUX_MODE7)      /* gpmc_ad13.gpio1[13] DSR */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_INPUT_PULLDOWN, MUX_MODE7)      /* gpmc_ad14.gpio1[14] DCD */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_INPUT_PULLDOWN, MUX_MODE7)     /* gpmc_ad15.gpio1[15] RI */
+
+                       AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKR, PIN_INPUT_PULLUP, MUX_MODE7)      /* mcasp0_aclkr.gpio3[18], INPUT_PULLDOWN | MODE7 */
                >;
        };
 

diff --git a/arch/arm/boot/dts/am335x-baltos-leds.dtsi b/arch/arm/boot/dts/am335x-baltos-leds.dtsi
index 3ab1767..fe75050 100644 (file)
--- a/arch/arm/boot/dts/am335x-baltos-leds.dtsi
+++ b/arch/arm/boot/dts/am335x-baltos-leds.dtsi
@@ -42,9 +42,9 @@
 &am33xx_pinmux {
        user_leds: pinmux_user_leds {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x908, PIN_OUTPUT_PULLDOWN | MUX_MODE7)    /* mii1_col.gpio3_0 PWR LED */
-                       AM33XX_IOPAD(0x91c, PIN_OUTPUT_PULLDOWN | MUX_MODE7)    /* mii1_txd3.gpio0_16 WLAN LED */
-                       AM33XX_IOPAD(0x920, PIN_OUTPUT_PULLDOWN | MUX_MODE7)    /* mii1_txd2.gpio0_17 APP LED */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_OUTPUT_PULLDOWN, MUX_MODE7)     /* mii1_col.gpio3_0 PWR LED */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT_PULLDOWN, MUX_MODE7)    /* mii1_txd3.gpio0_16 WLAN LED */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE7)    /* mii1_txd2.gpio0_17 APP LED */
                >;
        };
 };

diff --git a/arch/arm/boot/dts/am335x-baltos.dtsi b/arch/arm/boot/dts/am335x-baltos.dtsi
index 8c6fc41..b572ad1 100644 (file)
--- a/arch/arm/boot/dts/am335x-baltos.dtsi
+++ b/arch/arm/boot/dts/am335x-baltos.dtsi
@@ -53,130 +53,130 @@
 &am33xx_pinmux {
        mmc2_pins: pinmux_mmc2_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x820, PIN_INPUT_PULLUP | MUX_MODE2)      /* gpmc_ad8.mmc1_dat0_mux0 */
-                       AM33XX_IOPAD(0x824, PIN_INPUT_PULLUP | MUX_MODE2)      /* gpmc_ad9.mmc1_dat1_mux0 */
-                       AM33XX_IOPAD(0x828, PIN_INPUT_PULLUP | MUX_MODE2)      /* gpmc_ad10.mmc1_dat2_mux0 */
-                       AM33XX_IOPAD(0x82c, PIN_INPUT_PULLUP | MUX_MODE2)      /* gpmc_ad11.mmc1_dat3_mux0 */
-                       AM33XX_IOPAD(0x880, PIN_INPUT_PULLUP | MUX_MODE2)      /* gpmc_csn1.mmc1_clk_mux0 */
-                       AM33XX_IOPAD(0x884, PIN_INPUT_PULLUP | MUX_MODE2)      /* gpmc_csn2.mmc1_cmd_mux0 */
-                       AM33XX_IOPAD(0x9e4, PIN_INPUT_PULLUP | MUX_MODE7)      /* emu0.gpio3[7] */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_INPUT_PULLUP, MUX_MODE2)      /* gpmc_ad8.mmc1_dat0_mux0 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_INPUT_PULLUP, MUX_MODE2)      /* gpmc_ad9.mmc1_dat1_mux0 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_INPUT_PULLUP, MUX_MODE2)      /* gpmc_ad10.mmc1_dat2_mux0 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_INPUT_PULLUP, MUX_MODE2)      /* gpmc_ad11.mmc1_dat3_mux0 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_INPUT_PULLUP, MUX_MODE2)      /* gpmc_csn1.mmc1_clk_mux0 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_INPUT_PULLUP, MUX_MODE2)      /* gpmc_csn2.mmc1_cmd_mux0 */
+                       AM33XX_PADCONF(AM335X_PIN_EMU0, PIN_INPUT_PULLUP, MUX_MODE7)      /* emu0.gpio3[7] */
                >;
        };
 
        wl12xx_gpio: pinmux_wl12xx_gpio {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x9e8, PIN_OUTPUT_PULLUP | MUX_MODE7)      /* emu1.gpio3[8] */
+                       AM33XX_PADCONF(AM335X_PIN_EMU1, PIN_OUTPUT_PULLUP, MUX_MODE7)      /* emu1.gpio3[8] */
                >;
        };
 
        tps65910_pins: pinmux_tps65910_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x878, PIN_INPUT_PULLUP | MUX_MODE7)      /* gpmc_ben1.gpio1[28] */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_BEN1, PIN_INPUT_PULLUP, MUX_MODE7)      /* gpmc_ben1.gpio1[28] */
                >;
        };
 
        i2c1_pins: pinmux_i2c1_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x958, PIN_INPUT | MUX_MODE2)      /* spi0_d1.i2c1_sda_mux3 */
-                       AM33XX_IOPAD(0x95c, PIN_INPUT | MUX_MODE2)      /* spi0_cs0.i2c1_scl_mux3 */
+                       AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT, MUX_MODE2)      /* spi0_d1.i2c1_sda_mux3 */
+                       AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT, MUX_MODE2)      /* spi0_cs0.i2c1_scl_mux3 */
                >;
        };
 
        uart0_pins: pinmux_uart0_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0)       /* uart0_rxd.uart0_rxd */
-                       AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0)            /* uart0_txd.uart0_txd */
+                       AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
                >;
        };
 
        cpsw_default: cpsw_default {
                pinctrl-single,pins = <
                        /* Slave 1 */
-                       AM33XX_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE1)       /* mii1_crs.rmii1_crs_dv */
-                       AM33XX_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE1)      /* mii1_tx_en.rmii1_txen */
-                       AM33XX_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE1)      /* mii1_txd1.rmii1_txd1 */
-                       AM33XX_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE1)      /* mii1_txd0.rmii1_txd0 */
-                       AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE1)      /* mii1_rxd1.rmii1_rxd1 */
-                       AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE1)      /* mii1_rxd0.rmii1_rxd0 */
-                       AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE0)      /* rmii1_ref_clk.rmii1_refclk */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE1)       /* mii1_crs.rmii1_crs_dv */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE1)      /* mii1_tx_en.rmii1_txen */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE1)      /* mii1_txd1.rmii1_txd1 */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE1)      /* mii1_txd0.rmii1_txd0 */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE1)      /* mii1_rxd1.rmii1_rxd1 */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE1)      /* mii1_rxd0.rmii1_rxd0 */
+                       AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE0)      /* rmii1_ref_clk.rmii1_refclk */
 
 
                        /* Slave 2 */
-                       AM33XX_IOPAD(0x840, PIN_OUTPUT_PULLDOWN | MUX_MODE2)    /* gpmc_a0.rgmii2_tctl */
-                       AM33XX_IOPAD(0x844, PIN_INPUT_PULLDOWN | MUX_MODE2)     /* gpmc_a1.rgmii2_rctl */
-                       AM33XX_IOPAD(0x848, PIN_OUTPUT_PULLDOWN | MUX_MODE2)    /* gpmc_a2.rgmii2_td3 */
-                       AM33XX_IOPAD(0x84c, PIN_OUTPUT_PULLDOWN | MUX_MODE2)    /* gpmc_a3.rgmii2_td2 */
-                       AM33XX_IOPAD(0x850, PIN_OUTPUT_PULLDOWN | MUX_MODE2)    /* gpmc_a4.rgmii2_td1 */
-                       AM33XX_IOPAD(0x854, PIN_OUTPUT_PULLDOWN | MUX_MODE2)    /* gpmc_a5.rgmii2_td0 */
-                       AM33XX_IOPAD(0x858, PIN_OUTPUT_PULLDOWN | MUX_MODE2)    /* gpmc_a6.rgmii2_tclk */
-                       AM33XX_IOPAD(0x85c, PIN_INPUT_PULLDOWN | MUX_MODE2)     /* gpmc_a7.rgmii2_rclk */
-                       AM33XX_IOPAD(0x860, PIN_INPUT_PULLDOWN | MUX_MODE2)     /* gpmc_a8.rgmii2_rd3 */
-                       AM33XX_IOPAD(0x864, PIN_INPUT_PULLDOWN | MUX_MODE2)     /* gpmc_a9.rgmii2_rd2 */
-                       AM33XX_IOPAD(0x868, PIN_INPUT_PULLDOWN | MUX_MODE2)     /* gpmc_a10.rgmii2_rd1 */
-                       AM33XX_IOPAD(0x86c, PIN_INPUT_PULLDOWN | MUX_MODE2)     /* gpmc_a11.rgmii2_rd0 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT_PULLDOWN, MUX_MODE2)      /* gpmc_a0.rgmii2_tctl */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLDOWN, MUX_MODE2)       /* gpmc_a1.rgmii2_rctl */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_OUTPUT_PULLDOWN, MUX_MODE2)      /* gpmc_a2.rgmii2_td3 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_OUTPUT_PULLDOWN, MUX_MODE2)      /* gpmc_a3.rgmii2_td2 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT_PULLDOWN, MUX_MODE2)      /* gpmc_a4.rgmii2_td1 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT_PULLDOWN, MUX_MODE2)      /* gpmc_a5.rgmii2_td0 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_OUTPUT_PULLDOWN, MUX_MODE2)      /* gpmc_a6.rgmii2_tclk */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_INPUT_PULLDOWN, MUX_MODE2)       /* gpmc_a7.rgmii2_rclk */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_INPUT_PULLDOWN, MUX_MODE2)       /* gpmc_a8.rgmii2_rd3 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLDOWN, MUX_MODE2)       /* gpmc_a9.rgmii2_rd2 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE2)      /* gpmc_a10.rgmii2_rd1 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE2)      /* gpmc_a11.rgmii2_rd0 */
                >;
        };
 
        cpsw_sleep: cpsw_sleep {
                pinctrl-single,pins = <
                        /* Slave 1 reset value */
-                       AM33XX_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7)
 
                        /* Slave 2 reset value*/
-                       AM33XX_IOPAD(0x840, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x844, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x848, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x84c, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x850, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x854, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x858, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x85c, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x860, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x864, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x868, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x86c, PIN_INPUT_PULLDOWN | MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE7)
                >;
        };
 
        davinci_mdio_default: davinci_mdio_default {
                pinctrl-single,pins = <
                        /* MDIO */
-                       AM33XX_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)       /* mdio_data.mdio_data */
-                       AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0)                      /* mdio_clk.mdio_clk */
+                       AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0)    /* mdio_data.mdio_data */
+                       AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0)                    /* mdio_clk.mdio_clk */
                >;
        };
 
        davinci_mdio_sleep: davinci_mdio_sleep {
                pinctrl-single,pins = <
                        /* MDIO reset value */
-                       AM33XX_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7)
                >;
        };
 
        nandflash_pins_s0: nandflash_pins_s0 {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE0)       /* gpmc_ad0.gpmc_ad0 */
-                       AM33XX_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE0)       /* gpmc_ad1.gpmc_ad1 */
-                       AM33XX_IOPAD(0x808, PIN_INPUT_PULLUP | MUX_MODE0)       /* gpmc_ad2.gpmc_ad2 */
-                       AM33XX_IOPAD(0x80c, PIN_INPUT_PULLUP | MUX_MODE0)       /* gpmc_ad3.gpmc_ad3 */
-                       AM33XX_IOPAD(0x810, PIN_INPUT_PULLUP | MUX_MODE0)       /* gpmc_ad4.gpmc_ad4 */
-                       AM33XX_IOPAD(0x814, PIN_INPUT_PULLUP | MUX_MODE0)       /* gpmc_ad5.gpmc_ad5 */
-                       AM33XX_IOPAD(0x818, PIN_INPUT_PULLUP | MUX_MODE0)       /* gpmc_ad6.gpmc_ad6 */
-                       AM33XX_IOPAD(0x81c, PIN_INPUT_PULLUP | MUX_MODE0)       /* gpmc_ad7.gpmc_ad7 */
-                       AM33XX_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE0)       /* gpmc_wait0.gpmc_wait0 */
-                       AM33XX_IOPAD(0x874, PIN_INPUT_PULLUP | MUX_MODE7)       /* gpmc_wpn.gpio0_30 */
-                       AM33XX_IOPAD(0x87c, PIN_OUTPUT | MUX_MODE0)             /* gpmc_csn0.gpmc_csn0  */
-                       AM33XX_IOPAD(0x890, PIN_OUTPUT | MUX_MODE0)             /* gpmc_advn_ale.gpmc_advn_ale */
-                       AM33XX_IOPAD(0x894, PIN_OUTPUT | MUX_MODE0)             /* gpmc_oen_ren.gpmc_oen_ren */
-                       AM33XX_IOPAD(0x898, PIN_OUTPUT | MUX_MODE0)             /* gpmc_wen.gpmc_wen */
-                       AM33XX_IOPAD(0x89c, PIN_OUTPUT | MUX_MODE0)             /* gpmc_be0n_cle.gpmc_be0n_cle */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE0)        /* gpmc_ad0.gpmc_ad0 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE0)        /* gpmc_ad1.gpmc_ad1 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE0)        /* gpmc_ad2.gpmc_ad2 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE0)        /* gpmc_ad3.gpmc_ad3 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE0)        /* gpmc_ad4.gpmc_ad4 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE0)        /* gpmc_ad5.gpmc_ad5 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE0)        /* gpmc_ad6.gpmc_ad6 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE0)        /* gpmc_ad7.gpmc_ad7 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE0)      /* gpmc_wait0.gpmc_wait0 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLUP, MUX_MODE7)        /* gpmc_wpn.gpio0_30 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_OUTPUT, MUX_MODE0)             /* gpmc_csn0.gpmc_csn0  */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_OUTPUT, MUX_MODE0)         /* gpmc_advn_ale.gpmc_advn_ale */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_OUTPUT, MUX_MODE0)          /* gpmc_oen_ren.gpmc_oen_ren */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_WEN, PIN_OUTPUT, MUX_MODE0)              /* gpmc_wen.gpmc_wen */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_BEN0_CLE, PIN_OUTPUT, MUX_MODE0)         /* gpmc_be0n_cle.gpmc_be0n_cle */
                >;
        };
 };

diff --git a/arch/arm/boot/dts/am335x-base0033.dts b/arch/arm/boot/dts/am335x-base0033.dts
index 29782be..cbd5bd8 100644 (file)
--- a/arch/arm/boot/dts/am335x-base0033.dts
+++ b/arch/arm/boot/dts/am335x-base0033.dts
@@ -46,39 +46,39 @@
 &am33xx_pinmux {
        nxp_hdmi_pins: pinmux_nxp_hdmi_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x9b0, PIN_OUTPUT | MUX_MODE3)     /* xdma_event_intr0.clkout1 */
-                       AM33XX_IOPAD(0x8a0, PIN_OUTPUT | MUX_MODE0)     /* lcd_data0 */
-                       AM33XX_IOPAD(0x8a4, PIN_OUTPUT | MUX_MODE0)     /* lcd_data1 */
-                       AM33XX_IOPAD(0x8a8, PIN_OUTPUT | MUX_MODE0)     /* lcd_data2 */
-                       AM33XX_IOPAD(0x8ac, PIN_OUTPUT | MUX_MODE0)     /* lcd_data3 */
-                       AM33XX_IOPAD(0x8b0, PIN_OUTPUT | MUX_MODE0)     /* lcd_data4 */
-                       AM33XX_IOPAD(0x8b4, PIN_OUTPUT | MUX_MODE0)     /* lcd_data5 */
-                       AM33XX_IOPAD(0x8b8, PIN_OUTPUT | MUX_MODE0)     /* lcd_data6 */
-                       AM33XX_IOPAD(0x8bc, PIN_OUTPUT | MUX_MODE0)     /* lcd_data7 */
-                       AM33XX_IOPAD(0x8c0, PIN_OUTPUT | MUX_MODE0)     /* lcd_data8 */
-                       AM33XX_IOPAD(0x8c4, PIN_OUTPUT | MUX_MODE0)     /* lcd_data9 */
-                       AM33XX_IOPAD(0x8c8, PIN_OUTPUT | MUX_MODE0)     /* lcd_data10 */
-                       AM33XX_IOPAD(0x8cc, PIN_OUTPUT | MUX_MODE0)     /* lcd_data11 */
-                       AM33XX_IOPAD(0x8d0, PIN_OUTPUT | MUX_MODE0)     /* lcd_data12 */
-                       AM33XX_IOPAD(0x8d4, PIN_OUTPUT | MUX_MODE0)     /* lcd_data13 */
-                       AM33XX_IOPAD(0x8d8, PIN_OUTPUT | MUX_MODE0)     /* lcd_data14 */
-                       AM33XX_IOPAD(0x8dc, PIN_OUTPUT | MUX_MODE0)     /* lcd_data15 */
-                       AM33XX_IOPAD(0x8e0, PIN_OUTPUT | MUX_MODE0)     /* lcd_vsync */
-                       AM33XX_IOPAD(0x8e4, PIN_OUTPUT | MUX_MODE0)     /* lcd_hsync */
-                       AM33XX_IOPAD(0x8e8, PIN_OUTPUT | MUX_MODE0)     /* lcd_pclk */
-                       AM33XX_IOPAD(0x8ec, PIN_OUTPUT | MUX_MODE0)     /* lcd_ac_bias_en */
+                       AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_OUTPUT, MUX_MODE3)      /* xdma_event_intr0.clkout1 */
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT, MUX_MODE0)
                >;
        };
        nxp_hdmi_off_pins: pinmux_nxp_hdmi_off_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x9b0, PIN_OUTPUT | MUX_MODE3)     /* xdma_event_intr0.clkout1 */
+                       AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_OUTPUT, MUX_MODE3)      /* xdma_event_intr0.clkout1 */
                >;
        };
 
        leds_base_pins: pinmux_leds_base_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x854, PIN_OUTPUT_PULLDOWN | MUX_MODE7)    /* gpmc_a5.gpio1_21 */
-                       AM33XX_IOPAD(0x888, PIN_OUTPUT_PULLDOWN | MUX_MODE7)    /* gpmc_csn3.gpio2_0 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT_PULLDOWN, MUX_MODE7)      /* gpmc_a5.gpio1_21 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_CSN3, PIN_OUTPUT_PULLDOWN, MUX_MODE7)    /* gpmc_csn3.gpio2_0 */
                >;
        };
 };

diff --git a/arch/arm/boot/dts/am335x-bone-common.dtsi b/arch/arm/boot/dts/am335x-bone-common.dtsi
index 456eef5..42cfc3b 100644 (file)
--- a/arch/arm/boot/dts/am335x-bone-common.dtsi
+++ b/arch/arm/boot/dts/am335x-bone-common.dtsi
@@ -71,118 +71,118 @@
 
        user_leds_s0: user_leds_s0 {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x854, PIN_OUTPUT_PULLDOWN | MUX_MODE7)    /* gpmc_a5.gpio1_21 */
-                       AM33XX_IOPAD(0x858, PIN_OUTPUT_PULLUP | MUX_MODE7)      /* gpmc_a6.gpio1_22 */
-                       AM33XX_IOPAD(0x85c, PIN_OUTPUT_PULLDOWN | MUX_MODE7)    /* gpmc_a7.gpio1_23 */
-                       AM33XX_IOPAD(0x860, PIN_OUTPUT_PULLUP | MUX_MODE7)      /* gpmc_a8.gpio1_24 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT_PULLDOWN, MUX_MODE7)      /* gpmc_a5.gpio1_21 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_OUTPUT_PULLUP, MUX_MODE7)        /* gpmc_a6.gpio1_22 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_OUTPUT_PULLDOWN, MUX_MODE7)      /* gpmc_a7.gpio1_23 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_OUTPUT_PULLUP, MUX_MODE7)        /* gpmc_a8.gpio1_24 */
                >;
        };
 
        i2c0_pins: pinmux_i2c0_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x988, PIN_INPUT_PULLUP | MUX_MODE0)       /* i2c0_sda.i2c0_sda */
-                       AM33XX_IOPAD(0x98c, PIN_INPUT_PULLUP | MUX_MODE0)       /* i2c0_scl.i2c0_scl */
+                       AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0)        /* i2c0_sda.i2c0_sda */
+                       AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0)        /* i2c0_scl.i2c0_scl */
                >;
        };
 
        i2c2_pins: pinmux_i2c2_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x978, PIN_INPUT_PULLUP | MUX_MODE3)       /* uart1_ctsn.i2c2_sda */
-                       AM33XX_IOPAD(0x97c, PIN_INPUT_PULLUP | MUX_MODE3)       /* uart1_rtsn.i2c2_scl */
+                       AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLUP, MUX_MODE3)      /* uart1_ctsn.i2c2_sda */
+                       AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_INPUT_PULLUP, MUX_MODE3)      /* uart1_rtsn.i2c2_scl */
                >;
        };
 
        uart0_pins: pinmux_uart0_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0)       /* uart0_rxd.uart0_rxd */
-                       AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0)    /* uart0_txd.uart0_txd */
+                       AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
                >;
        };
 
        clkout2_pin: pinmux_clkout2_pin {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x9b4, PIN_OUTPUT_PULLDOWN | MUX_MODE3)    /* xdma_event_intr1.clkout2 */
+                       AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR1, PIN_OUTPUT_PULLDOWN, MUX_MODE3)     /* xdma_event_intr1.clkout2 */
                >;
        };
 
        cpsw_default: cpsw_default {
                pinctrl-single,pins = <
                        /* Slave 1 */
-                       AM33XX_IOPAD(0x910, PIN_INPUT_PULLUP | MUX_MODE0)       /* mii1_rxerr.mii1_rxerr */
-                       AM33XX_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE0)    /* mii1_txen.mii1_txen */
-                       AM33XX_IOPAD(0x918, PIN_INPUT_PULLUP | MUX_MODE0)       /* mii1_rxdv.mii1_rxdv */
-                       AM33XX_IOPAD(0x91c, PIN_OUTPUT_PULLDOWN | MUX_MODE0)    /* mii1_txd3.mii1_txd3 */
-                       AM33XX_IOPAD(0x920, PIN_OUTPUT_PULLDOWN | MUX_MODE0)    /* mii1_txd2.mii1_txd2 */
-                       AM33XX_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE0)    /* mii1_txd1.mii1_txd1 */
-                       AM33XX_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE0)    /* mii1_txd0.mii1_txd0 */
-                       AM33XX_IOPAD(0x92c, PIN_INPUT_PULLUP | MUX_MODE0)       /* mii1_txclk.mii1_txclk */
-                       AM33XX_IOPAD(0x930, PIN_INPUT_PULLUP | MUX_MODE0)       /* mii1_rxclk.mii1_rxclk */
-                       AM33XX_IOPAD(0x934, PIN_INPUT_PULLUP | MUX_MODE0)       /* mii1_rxd3.mii1_rxd3 */
-                       AM33XX_IOPAD(0x938, PIN_INPUT_PULLUP | MUX_MODE0)       /* mii1_rxd2.mii1_rxd2 */
-                       AM33XX_IOPAD(0x93c, PIN_INPUT_PULLUP | MUX_MODE0)       /* mii1_rxd1.mii1_rxd1 */
-                       AM33XX_IOPAD(0x940, PIN_INPUT_PULLUP | MUX_MODE0)       /* mii1_rxd0.mii1_rxd0 */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLUP, MUX_MODE0)
                >;
        };
 
        cpsw_sleep: cpsw_sleep {
                pinctrl-single,pins = <
                        /* Slave 1 reset value */
-                       AM33XX_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x91c, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x920, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x92c, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7)
                >;
        };
 
        davinci_mdio_default: davinci_mdio_default {
                pinctrl-single,pins = <
                        /* MDIO */
-                       AM33XX_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)       /* mdio_data.mdio_data */
-                       AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0)                      /* mdio_clk.mdio_clk */
+                       AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0)
                >;
        };
 
        davinci_mdio_sleep: davinci_mdio_sleep {
                pinctrl-single,pins = <
                        /* MDIO reset value */
-                       AM33XX_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7)
                >;
        };
 
        mmc1_pins: pinmux_mmc1_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x960, PIN_INPUT | MUX_MODE7)              /* spio0_cs1.gpio0_6 */
-                       AM33XX_IOPAD(0x8fc, PIN_INPUT_PULLUP | MUX_MODE0)       /* mmc0_dat0.mmc0_dat0 */
-                       AM33XX_IOPAD(0x8f8, PIN_INPUT_PULLUP | MUX_MODE0)       /* mmc0_dat1.mmc0_dat1 */
-                       AM33XX_IOPAD(0x8f4, PIN_INPUT_PULLUP | MUX_MODE0)       /* mmc0_dat2.mmc0_dat2 */
-                       AM33XX_IOPAD(0x8f0, PIN_INPUT_PULLUP | MUX_MODE0)       /* mmc0_dat3.mmc0_dat3 */
-                       AM33XX_IOPAD(0x904, PIN_INPUT_PULLUP | MUX_MODE0)       /* mmc0_cmd.mmc0_cmd */
-                       AM33XX_IOPAD(0x900, PIN_INPUT_PULLUP | MUX_MODE0)       /* mmc0_clk.mmc0_clk */
+                       AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT, MUX_MODE7)               /* spio0_cs1.gpio0_6 */
+                       AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0)
                >;
        };
 
        emmc_pins: pinmux_emmc_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x880, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn1.mmc1_clk */
-                       AM33XX_IOPAD(0x884, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn2.mmc1_cmd */
-                       AM33XX_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */
-                       AM33XX_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */
-                       AM33XX_IOPAD(0x808, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */
-                       AM33XX_IOPAD(0x80c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */
-                       AM33XX_IOPAD(0x810, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad4.mmc1_dat4 */
-                       AM33XX_IOPAD(0x814, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad5.mmc1_dat5 */
-                       AM33XX_IOPAD(0x818, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad6.mmc1_dat6 */
-                       AM33XX_IOPAD(0x81c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn1.mmc1_clk */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn2.mmc1_cmd */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad4.mmc1_dat4 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad5.mmc1_dat5 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad6.mmc1_dat6 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */
                >;
        };
 };

diff --git a/arch/arm/boot/dts/am335x-boneblack-common.dtsi b/arch/arm/boot/dts/am335x-boneblack-common.dtsi
index e543c2b..283e288 100644 (file)
--- a/arch/arm/boot/dts/am335x-boneblack-common.dtsi
+++ b/arch/arm/boot/dts/am335x-boneblack-common.dtsi
@@ -30,43 +30,43 @@
 &am33xx_pinmux {
        nxp_hdmi_bonelt_pins: nxp_hdmi_bonelt_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x9b0, PIN_OUTPUT_PULLDOWN | MUX_MODE3)    /* xdma_event_intr0 */
-                       AM33XX_IOPAD(0x8a0, PIN_OUTPUT | MUX_MODE0)             /* lcd_data0.lcd_data0 */
-                       AM33XX_IOPAD(0x8a4, PIN_OUTPUT | MUX_MODE0)             /* lcd_data1.lcd_data1 */
-                       AM33XX_IOPAD(0x8a8, PIN_OUTPUT | MUX_MODE0)             /* lcd_data2.lcd_data2 */
-                       AM33XX_IOPAD(0x8ac, PIN_OUTPUT | MUX_MODE0)             /* lcd_data3.lcd_data3 */
-                       AM33XX_IOPAD(0x8b0, PIN_OUTPUT | MUX_MODE0)             /* lcd_data4.lcd_data4 */
-                       AM33XX_IOPAD(0x8b4, PIN_OUTPUT | MUX_MODE0)             /* lcd_data5.lcd_data5 */
-                       AM33XX_IOPAD(0x8b8, PIN_OUTPUT | MUX_MODE0)             /* lcd_data6.lcd_data6 */
-                       AM33XX_IOPAD(0x8bc, PIN_OUTPUT | MUX_MODE0)             /* lcd_data7.lcd_data7 */
-                       AM33XX_IOPAD(0x8c0, PIN_OUTPUT | MUX_MODE0)             /* lcd_data8.lcd_data8 */
-                       AM33XX_IOPAD(0x8c4, PIN_OUTPUT | MUX_MODE0)             /* lcd_data9.lcd_data9 */
-                       AM33XX_IOPAD(0x8c8, PIN_OUTPUT | MUX_MODE0)             /* lcd_data10.lcd_data10 */
-                       AM33XX_IOPAD(0x8cc, PIN_OUTPUT | MUX_MODE0)             /* lcd_data11.lcd_data11 */
-                       AM33XX_IOPAD(0x8d0, PIN_OUTPUT | MUX_MODE0)             /* lcd_data12.lcd_data12 */
-                       AM33XX_IOPAD(0x8d4, PIN_OUTPUT | MUX_MODE0)             /* lcd_data13.lcd_data13 */
-                       AM33XX_IOPAD(0x8d8, PIN_OUTPUT | MUX_MODE0)             /* lcd_data14.lcd_data14 */
-                       AM33XX_IOPAD(0x8dc, PIN_OUTPUT | MUX_MODE0)             /* lcd_data15.lcd_data15 */
-                       AM33XX_IOPAD(0x8e0, PIN_OUTPUT_PULLDOWN | MUX_MODE0)    /* lcd_vsync.lcd_vsync */
-                       AM33XX_IOPAD(0x8e4, PIN_OUTPUT_PULLDOWN | MUX_MODE0)    /* lcd_hsync.lcd_hsync */
-                       AM33XX_IOPAD(0x8e8, PIN_OUTPUT_PULLDOWN | MUX_MODE0)    /* lcd_pclk.lcd_pclk */
-                       AM33XX_IOPAD(0x8ec, PIN_OUTPUT_PULLDOWN | MUX_MODE0)    /* lcd_ac_bias_en.lcd_ac_bias_en */
+                       AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_OUTPUT_PULLDOWN, MUX_MODE3)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
                >;
        };
 
        nxp_hdmi_bonelt_off_pins: nxp_hdmi_bonelt_off_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x9b0, PIN_OUTPUT_PULLDOWN | MUX_MODE3)    /* xdma_event_intr0 */
+                       AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_OUTPUT_PULLDOWN, MUX_MODE3)
                >;
        };
 
        mcasp0_pins: mcasp0_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x9ac, PIN_INPUT_PULLUP | MUX_MODE0) /* mcasp0_ahcklx.mcasp0_ahclkx */
-                       AM33XX_IOPAD(0x99c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mcasp0_ahclkr.mcasp0_axr2*/
-                       AM33XX_IOPAD(0x994, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mcasp0_fsx.mcasp0_fsx */
-                       AM33XX_IOPAD(0x990, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp0_aclkx.mcasp0_aclkx */
-                       AM33XX_IOPAD(0x86c, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a11.GPIO1_27 */
+                       AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKX, PIN_INPUT_PULLUP, MUX_MODE0) /* mcasp0_ahcklx.mcasp0_ahclkx */
+                       AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKR, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mcasp0_ahclkr.mcasp0_axr2*/
+                       AM33XX_PADCONF(AM335X_PIN_MCASP0_FSX, PIN_OUTPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKX, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_a11.GPIO1_27 */
                >;
        };
 };

diff --git a/arch/arm/boot/dts/am335x-boneblack-wireless.dts b/arch/arm/boot/dts/am335x-boneblack-wireless.dts
index 83f49f6..5b275c9 100644 (file)
--- a/arch/arm/boot/dts/am335x-boneblack-wireless.dts
+++ b/arch/arm/boot/dts/am335x-boneblack-wireless.dts
@@ -32,35 +32,35 @@
 &am33xx_pinmux {
        bt_pins: pinmux_bt_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x928, PIN_OUTPUT_PULLUP | MUX_MODE7)      /* gmii1_txd0.gpio0_28 - BT_EN */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLUP, MUX_MODE7)      /* gmii1_txd0.gpio0_28 - BT_EN */
                >;
        };
 
        mmc3_pins: pinmux_mmc3_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x93c, PIN_INPUT_PULLUP | MUX_MODE6 ) /* (L15) gmii1_rxd1.mmc2_clk */
-                       AM33XX_IOPAD(0x914, PIN_INPUT_PULLUP | MUX_MODE6 ) /* (J16) gmii1_txen.mmc2_cmd */
-                       AM33XX_IOPAD(0x918, PIN_INPUT_PULLUP | MUX_MODE5 ) /* (J17) gmii1_rxdv.mmc2_dat0 */
-                       AM33XX_IOPAD(0x91c, PIN_INPUT_PULLUP | MUX_MODE5 ) /* (J18) gmii1_txd3.mmc2_dat1 */
-                       AM33XX_IOPAD(0x920, PIN_INPUT_PULLUP | MUX_MODE5 ) /* (K15) gmii1_txd2.mmc2_dat2 */
-                       AM33XX_IOPAD(0x908, PIN_INPUT_PULLUP | MUX_MODE5 ) /* (H16) gmii1_col.mmc2_dat3 */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLUP, MUX_MODE6 ) /* (L15) gmii1_rxd1.mmc2_clk */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLUP, MUX_MODE6 ) /* (J16) gmii1_txen.mmc2_cmd */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLUP, MUX_MODE5 ) /* (J17) gmii1_rxdv.mmc2_dat0 */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_INPUT_PULLUP, MUX_MODE5 ) /* (J18) gmii1_txd3.mmc2_dat1 */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_INPUT_PULLUP, MUX_MODE5 ) /* (K15) gmii1_txd2.mmc2_dat2 */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT_PULLUP, MUX_MODE5 ) /* (H16) gmii1_col.mmc2_dat3 */
                >;
        };
 
        uart3_pins: pinmux_uart3_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x934, PIN_INPUT_PULLUP | MUX_MODE1)       /* gmii1_rxd3.uart3_rxd */
-                       AM33XX_IOPAD(0x938, PIN_OUTPUT_PULLDOWN | MUX_MODE1)    /* gmii1_rxd2.uart3_txd */
-                       AM33XX_IOPAD(0x948, PIN_INPUT | MUX_MODE3)              /* mdio_data.uart3_ctsn */
-                       AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLDOWN | MUX_MODE3)    /* mdio_clk.uart3_rtsn */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLUP, MUX_MODE1)       /* gmii1_rxd3.uart3_rxd */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE1)    /* gmii1_rxd2.uart3_txd */
+                       AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT, MUX_MODE3)           /* mdio_data.uart3_ctsn */
+                       AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLDOWN, MUX_MODE3)  /* mdio_clk.uart3_rtsn */
                >;
        };
 
        wl18xx_pins: pinmux_wl18xx_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x92c, PIN_OUTPUT_PULLDOWN | MUX_MODE7)    /* gmii1_txclk.gpio3_9 WL_EN */
-                       AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE7)     /* rmii1_refclk.gpio0_29 WL_IRQ */
-                       AM33XX_IOPAD(0x930, PIN_OUTPUT_PULLUP | MUX_MODE7)      /* gmii1_rxclk.gpio3_10 LS_BUF_EN */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE7)  /* gmii1_txclk.gpio3_9 WL_EN */
+                       AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii1_refclk.gpio0_29 WL_IRQ */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_OUTPUT_PULLUP, MUX_MODE7)    /* gmii1_rxclk.gpio3_10 LS_BUF_EN */
                >;
        };
 };

diff --git a/arch/arm/boot/dts/am335x-boneblue.dts b/arch/arm/boot/dts/am335x-boneblue.dts
index ccb147e..8d241c8 100644 (file)
--- a/arch/arm/boot/dts/am335x-boneblue.dts
+++ b/arch/arm/boot/dts/am335x-boneblue.dts
@@ -130,135 +130,135 @@
 &am33xx_pinmux {
        user_leds_s0: user_leds_s0 {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x854, PIN_OUTPUT | MUX_MODE7) /* (V15) gpmc_a5.gpio1[21] - USR_LED_0 */
-                       AM33XX_IOPAD(0x858, PIN_OUTPUT | MUX_MODE7) /* (U15) gpmc_a6.gpio1[22] - USR_LED_1 */
-                       AM33XX_IOPAD(0x85c, PIN_OUTPUT | MUX_MODE7) /* (T15) gpmc_a7.gpio1[23] - USR_LED_2 */
-                       AM33XX_IOPAD(0x860, PIN_OUTPUT | MUX_MODE7) /* (V16) gpmc_a8.gpio1[24] - USR_LED_3 */
-                       AM33XX_IOPAD(0x9b0, PIN_OUTPUT | MUX_MODE7) /* (A15) xdma_event_intr0.gpio0[19] - WIFI_LED */
-                       AM33XX_IOPAD(0x890, PIN_OUTPUT | MUX_MODE7) /* (R7) gpmc_advn_ale.gpio2[2] - P8.7, LED_RED, GP1_PIN_5 */
-                       AM33XX_IOPAD(0x894, PIN_OUTPUT | MUX_MODE7) /* (T7) gpmc_oen_ren.gpio2[3] - P8.8, LED_GREEN, GP1_PIN_6 */
-                       AM33XX_IOPAD(0x82c, PIN_OUTPUT | MUX_MODE7) /* (U12) gpmc_ad11.gpio0[27] - P8.17, BATT_LED_1 */
-                       AM33XX_IOPAD(0x8dc, PIN_OUTPUT | MUX_MODE7) /* (T5) lcd_data15.gpio0[11] - P8.32, BATT_LED_2 */
-                       AM33XX_IOPAD(0x87c, PIN_OUTPUT | MUX_MODE7) /* (V6) gpmc_csn0.gpio1[29] - P8.26, BATT_LED_3 */
-                       AM33XX_IOPAD(0x828, PIN_OUTPUT | MUX_MODE7) /* (T11) gpmc_ad10.gpio0[26] - P8.14, BATT_LED_4 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT, MUX_MODE7) /* (V15) gpmc_a5.gpio1[21] - USR_LED_0 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_OUTPUT, MUX_MODE7) /* (U15) gpmc_a6.gpio1[22] - USR_LED_1 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_OUTPUT, MUX_MODE7) /* (T15) gpmc_a7.gpio1[23] - USR_LED_2 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_OUTPUT, MUX_MODE7) /* (V16) gpmc_a8.gpio1[24] - USR_LED_3 */
+                       AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_OUTPUT, MUX_MODE7) /* (A15) xdma_event_intr0.gpio0[19] - WIFI_LED */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_OUTPUT, MUX_MODE7) /* (R7) gpmc_advn_ale.gpio2[2] - P8.7, LED_RED, GP1_PIN_5 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_OUTPUT, MUX_MODE7) /* (T7) gpmc_oen_ren.gpio2[3] - P8.8, LED_GREEN, GP1_PIN_6 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_OUTPUT, MUX_MODE7) /* (U12) gpmc_ad11.gpio0[27] - P8.17, BATT_LED_1 */
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE7) /* (T5) lcd_data15.gpio0[11] - P8.32, BATT_LED_2 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_OUTPUT, MUX_MODE7) /* (V6) gpmc_csn0.gpio1[29] - P8.26, BATT_LED_3 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_OUTPUT, MUX_MODE7) /* (T11) gpmc_ad10.gpio0[26] - P8.14, BATT_LED_4 */
 
                >;
        };
 
        i2c0_pins: pinmux_i2c0_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x988, PIN_INPUT_PULLUP | MUX_MODE0)       /* (C17) I2C0_SDA.I2C0_SDA */
-                       AM33XX_IOPAD(0x98c, PIN_INPUT_PULLUP | MUX_MODE0)       /* (C16) I2C0_SCL.I2C0_SCL */
+                       AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0)        /* (C17) I2C0_SDA.I2C0_SDA */
+                       AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0)        /* (C16) I2C0_SCL.I2C0_SCL */
                >;
        };
 
        i2c2_pins: pinmux_i2c2_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x978, PIN_INPUT_PULLUP | MUX_MODE3)       /* (D18) uart1_ctsn.I2C2_SDA */
-                       AM33XX_IOPAD(0x97c, PIN_INPUT_PULLUP | MUX_MODE3)       /* (D17) uart1_rtsn.I2C2_SCL */
+                       AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLUP, MUX_MODE3)      /* (D18) uart1_ctsn.I2C2_SDA */
+                       AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_INPUT_PULLUP, MUX_MODE3)      /* (D17) uart1_rtsn.I2C2_SCL */
                >;
        };
 
        /* UT0 */
        uart0_pins: pinmux_uart0_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0)       /* (E15) uart0_rxd.uart0_rxd */
-                       AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0)    /* (E16) uart0_txd.uart0_txd */
+                       AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
                >;
        };
 
        /* UT1 */
        uart1_pins: pinmux_uart1_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x980, PIN_INPUT_PULLUP | MUX_MODE0)       /* (D16) uart1_rxd.uart1_rxd */
-                       AM33XX_IOPAD(0x984, PIN_OUTPUT_PULLDOWN | MUX_MODE0)    /* (D15) uart1_txd.uart1_txd */
+                       AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
                >;
        };
 
        /* GPS */
        uart2_pins: pinmux_uart2_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x950, PIN_INPUT_PULLUP | MUX_MODE1)       /* (A17) spi0_sclk.uart2_rxd */
-                       AM33XX_IOPAD(0x954, PIN_OUTPUT_PULLDOWN | MUX_MODE1)    /* (B17) spi0_d0.uart2_txd */
+                       AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT_PULLUP, MUX_MODE1)       /* (A17) spi0_sclk.uart2_rxd */
+                       AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_OUTPUT_PULLDOWN, MUX_MODE1)      /* (B17) spi0_d0.uart2_txd */
                >;
        };
 
        /* DSM2 */
        uart4_pins: pinmux_uart4_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE6)       /* (T17) gpmc_wait0.uart4_rxd */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE6)      /* (T17) gpmc_wait0.uart4_rxd */
                >;
        };
 
        /* UT5 */
        uart5_pins: pinmux_uart5_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x8C4, PIN_INPUT_PULLUP | MUX_MODE4)       /* (U2) lcd_data9.uart5_rxd */
-                       AM33XX_IOPAD(0x8C0, PIN_OUTPUT_PULLDOWN | MUX_MODE4)    /* (U1) lcd_data8.uart5_txd */
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_INPUT_PULLUP, MUX_MODE4)       /* (U2) lcd_data9.uart5_rxd */
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT_PULLDOWN, MUX_MODE4)    /* (U1) lcd_data8.uart5_txd */
                >;
        };
 
        mmc1_pins: pinmux_mmc1_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x960, PIN_INPUT | MUX_MODE7)              /* (C15) spi0_cs1.gpio0[6] */
+                       AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT, MUX_MODE7)               /* (C15) spi0_cs1.gpio0[6] */
                >;
        };
 
        mmc2_pins: pinmux_mmc2_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x880, PIN_INPUT_PULLUP | MUX_MODE2)       /* (U9) gpmc_csn1.mmc1_clk */
-                       AM33XX_IOPAD(0x884, PIN_INPUT_PULLUP | MUX_MODE2)       /* (V9) gpmc_csn2.mmc1_cmd */
-                       AM33XX_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE1)       /* (U7) gpmc_ad0.mmc1_dat0 */
-                       AM33XX_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE1)       /* (V7) gpmc_ad1.mmc1_dat1 */
-                       AM33XX_IOPAD(0x808, PIN_INPUT_PULLUP | MUX_MODE1)       /* (R8) gpmc_ad2.mmc1_dat2 */
-                       AM33XX_IOPAD(0x80c, PIN_INPUT_PULLUP | MUX_MODE1)       /* (T8) gpmc_ad3.mmc1_dat3 */
-                       AM33XX_IOPAD(0x810, PIN_INPUT_PULLUP | MUX_MODE1)       /* (U8) gpmc_ad4.mmc1_dat4 */
-                       AM33XX_IOPAD(0x814, PIN_INPUT_PULLUP | MUX_MODE1)       /* (V8) gpmc_ad5.mmc1_dat5 */
-                       AM33XX_IOPAD(0x818, PIN_INPUT_PULLUP | MUX_MODE1)       /* (R9) gpmc_ad6.mmc1_dat6 */
-                       AM33XX_IOPAD(0x81c, PIN_INPUT_PULLUP | MUX_MODE1)       /* (T9) gpmc_ad7.mmc1_dat7 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_INPUT_PULLUP, MUX_MODE2)       /* (U9) gpmc_csn1.mmc1_clk */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_INPUT_PULLUP, MUX_MODE2)       /* (V9) gpmc_csn2.mmc1_cmd */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE1)        /* (U7) gpmc_ad0.mmc1_dat0 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE1)        /* (V7) gpmc_ad1.mmc1_dat1 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE1)        /* (R8) gpmc_ad2.mmc1_dat2 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE1)        /* (T8) gpmc_ad3.mmc1_dat3 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE1)        /* (U8) gpmc_ad4.mmc1_dat4 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE1)        /* (V8) gpmc_ad5.mmc1_dat5 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE1)        /* (R9) gpmc_ad6.mmc1_dat6 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE1)        /* (T9) gpmc_ad7.mmc1_dat7 */
                >;
        };
 
        mmc3_pins: pinmux_mmc3_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x93c, PIN_INPUT_PULLUP | MUX_MODE6)       /* (L15) gmii1_rxd1.mmc2_clk */
-                       AM33XX_IOPAD(0x914, PIN_INPUT_PULLUP | MUX_MODE6)       /* (J16) gmii1_txen.mmc2_cmd */
-                       AM33XX_IOPAD(0x918, PIN_INPUT_PULLUP | MUX_MODE5)       /* (J17) gmii1_rxdv.mmc2_dat0 */
-                       AM33XX_IOPAD(0x91c, PIN_INPUT_PULLUP | MUX_MODE5)       /* (J18) gmii1_txd3.mmc2_dat1 */
-                       AM33XX_IOPAD(0x920, PIN_INPUT_PULLUP | MUX_MODE5)       /* (K15) gmii1_txd2.mmc2_dat2 */
-                       AM33XX_IOPAD(0x908, PIN_INPUT_PULLUP | MUX_MODE5)       /* (H16) gmii1_col.mmc2_dat3 */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLUP, MUX_MODE6)       /* (L15) gmii1_rxd1.mmc2_clk */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLUP, MUX_MODE6)      /* (J16) gmii1_txen.mmc2_cmd */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLUP, MUX_MODE5)      /* (J17) gmii1_rxdv.mmc2_dat0 */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_INPUT_PULLUP, MUX_MODE5)       /* (J18) gmii1_txd3.mmc2_dat1 */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_INPUT_PULLUP, MUX_MODE5)       /* (K15) gmii1_txd2.mmc2_dat2 */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT_PULLUP, MUX_MODE5)        /* (H16) gmii1_col.mmc2_dat3 */
                >;
        };
 
        bt_pins: pinmux_bt_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x928, PIN_OUTPUT_PULLUP | MUX_MODE7)      /* (K17) gmii1_txd0.gpio0[28] - BT_EN */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLUP, MUX_MODE7)      /* (K17) gmii1_txd0.gpio0[28] - BT_EN */
                >;
        };
 
        uart3_pins: pinmux_uart3_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x934, PIN_INPUT_PULLUP | MUX_MODE1)       /* (L17) gmii1_rxd3.uart3_rxd */
-                       AM33XX_IOPAD(0x938, PIN_OUTPUT_PULLDOWN | MUX_MODE1)    /* (L16) gmii1_rxd2.uart3_txd */
-                       AM33XX_IOPAD(0x948, PIN_INPUT | MUX_MODE3)              /* (M17) mdio_data.uart3_ctsn */
-                       AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLDOWN | MUX_MODE3)    /* (M18) mdio_clk.uart3_rtsn */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLUP, MUX_MODE1)       /* (L17) gmii1_rxd3.uart3_rxd */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE1)    /* (L16) gmii1_rxd2.uart3_txd */
+                       AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT, MUX_MODE3)           /* (M17) mdio_data.uart3_ctsn */
+                       AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLDOWN, MUX_MODE3)  /* (M18) mdio_clk.uart3_rtsn */
                >;
        };
 
        wl18xx_pins: pinmux_wl18xx_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x92c, PIN_OUTPUT_PULLDOWN | MUX_MODE7)    /* (K18) gmii1_txclk.gpio3[9] - WL_EN */
-                       AM33XX_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7)     /* (K16) gmii1_txd1.gpio0[21] - WL_IRQ */
-                       AM33XX_IOPAD(0x930, PIN_OUTPUT_PULLUP | MUX_MODE7)      /* (L18) gmii1_rxclk.gpio3[10] - LS_BUF_EN */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE7)  /* (K18) gmii1_txclk.gpio3[9] - WL_EN */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7)     /* (K16) gmii1_txd1.gpio0[21] - WL_IRQ */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_OUTPUT_PULLUP, MUX_MODE7)    /* (L18) gmii1_rxclk.gpio3[10] - LS_BUF_EN */
                >;
        };
 
        /* DCAN */
        dcan1_pins: pinmux_dcan1_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x96c, PIN_INPUT | MUX_MODE2)              /* (E17) uart0_rtsn.dcan1_rx */
-                       AM33XX_IOPAD(0x968, PIN_OUTPUT | MUX_MODE2)             /* (E18) uart0_ctsn.dcan1_tx */
-                       AM33XX_IOPAD(0x940, PIN_OUTPUT | MUX_MODE7)             /* (M16) gmii1_rxd0.gpio2[21] */
+                       AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT, MUX_MODE2)             /* (E17) uart0_rtsn.dcan1_rx */
+                       AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_OUTPUT, MUX_MODE2)            /* (E18) uart0_ctsn.dcan1_tx */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_OUTPUT, MUX_MODE7)             /* (M16) gmii1_rxd0.gpio2[21] */
                >;
        };
 };

diff --git a/arch/arm/boot/dts/am335x-bonegreen-common.dtsi b/arch/arm/boot/dts/am335x-bonegreen-common.dtsi
index 853e6d3..71317e3 100644 (file)
--- a/arch/arm/boot/dts/am335x-bonegreen-common.dtsi
+++ b/arch/arm/boot/dts/am335x-bonegreen-common.dtsi
@@ -27,8 +27,8 @@
 &am33xx_pinmux {
        uart2_pins: uart2_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x950, PIN_INPUT | MUX_MODE1)      /* spi0_sclk.uart2_rxd */
-                       AM33XX_IOPAD(0x954, PIN_OUTPUT | MUX_MODE1)     /* spi0_d0.uart2_txd */
+                       AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT, MUX_MODE1)      /* spi0_sclk.uart2_rxd */
+                       AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_OUTPUT, MUX_MODE1)       /* spi0_d0.uart2_txd */
                >;
        };
 };

diff --git a/arch/arm/boot/dts/am335x-bonegreen-wireless.dts b/arch/arm/boot/dts/am335x-bonegreen-wireless.dts
index 57731f0..7db86a9 100644 (file)
--- a/arch/arm/boot/dts/am335x-bonegreen-wireless.dts
+++ b/arch/arm/boot/dts/am335x-bonegreen-wireless.dts
@@ -32,35 +32,35 @@
 &am33xx_pinmux {
        bt_pins: pinmux_bt_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x878, PIN_OUTPUT_PULLUP | MUX_MODE7)      /* gpmc_ad12.gpio1_28 BT_EN */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_BEN1, PIN_OUTPUT_PULLUP, MUX_MODE7)      /* gpmc_ad12.gpio1_28 BT_EN */
                >;
        };
 
        mmc3_pins: pinmux_mmc3_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x830, PIN_INPUT_PULLUP | MUX_MODE3)       /* gpmc_ad12.mmc2_dat0 */
-                       AM33XX_IOPAD(0x834, PIN_INPUT_PULLUP | MUX_MODE3)       /* gpmc_ad13.mmc2_dat1 */
-                       AM33XX_IOPAD(0x838, PIN_INPUT_PULLUP | MUX_MODE3)       /* gpmc_ad14.mmc2_dat2 */
-                       AM33XX_IOPAD(0x83c, PIN_INPUT_PULLUP | MUX_MODE3)       /* gpmc_ad15.mmc2_dat3 */
-                       AM33XX_IOPAD(0x888, PIN_INPUT_PULLUP | MUX_MODE3)       /* gpmc_csn3.mmc2_cmd */
-                       AM33XX_IOPAD(0x88c, PIN_INPUT_PULLUP | MUX_MODE3)       /* gpmc_clk.mmc2_clk */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_INPUT_PULLUP, MUX_MODE3)       /* gpmc_ad12.mmc2_dat0 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT_PULLUP, MUX_MODE3)       /* gpmc_ad13.mmc2_dat1 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_INPUT_PULLUP, MUX_MODE3)       /* gpmc_ad14.mmc2_dat2 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_INPUT_PULLUP, MUX_MODE3)       /* gpmc_ad15.mmc2_dat3 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_CSN3, PIN_INPUT_PULLUP, MUX_MODE3)       /* gpmc_csn3.mmc2_cmd */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_CLK, PIN_INPUT_PULLUP, MUX_MODE3)        /* gpmc_clk.mmc2_clk */
                >;
        };
 
        uart3_pins: pinmux_uart3_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x934, PIN_INPUT_PULLUP | MUX_MODE1)       /* gmii1_rxd3.uart3_rxd */
-                       AM33XX_IOPAD(0x938, PIN_OUTPUT_PULLDOWN | MUX_MODE1)    /* gmii1_rxd2.uart3_txd */
-                       AM33XX_IOPAD(0x948, PIN_INPUT | MUX_MODE3)              /* mdio_data.uart3_ctsn */
-                       AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLDOWN | MUX_MODE3)    /* mdio_clk.uart3_rtsn */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLUP, MUX_MODE1)       /* gmii1_rxd3.uart3_rxd */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE1)    /* gmii1_rxd2.uart3_txd */
+                       AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT, MUX_MODE3)           /* mdio_data.uart3_ctsn */
+                       AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLDOWN, MUX_MODE3)  /* mdio_clk.uart3_rtsn */
                >;
        };
 
        wl18xx_pins: pinmux_wl18xx_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x828, PIN_OUTPUT_PULLDOWN | MUX_MODE7)    /* gpmc_ad10.gpio0_26 WL_EN */
-                       AM33XX_IOPAD(0x82C, PIN_INPUT_PULLDOWN | MUX_MODE7)     /* gpmc_ad11.gpio0_27 WL_IRQ */
-                       AM33XX_IOPAD(0x87C, PIN_OUTPUT_PULLUP | MUX_MODE7)      /* gpmc_csn0.gpio1_29 LS_BUF_EN */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_OUTPUT_PULLDOWN, MUX_MODE7)    /* gpmc_ad10.gpio0_26 WL_EN */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_INPUT_PULLDOWN, MUX_MODE7)     /* gpmc_ad11.gpio0_27 WL_IRQ */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_OUTPUT_PULLUP, MUX_MODE7)      /* gpmc_csn0.gpio1_29 LS_BUF_EN */
                >;
        };
 };

diff --git a/arch/arm/boot/dts/am335x-chiliboard.dts b/arch/arm/boot/dts/am335x-chiliboard.dts
index bffa5dc..31da683 100644 (file)
--- a/arch/arm/boot/dts/am335x-chiliboard.dts
+++ b/arch/arm/boot/dts/am335x-chiliboard.dts
@@ -41,79 +41,79 @@
 &am33xx_pinmux {
        uart0_pins: pinmux_uart0_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0)       /* uart0_rxd.uart0_rxd */
-                       AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0)    /* uart0_txd.uart0_txd */
+                       AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
                >;
        };
 
        cpsw_default: cpsw_default {
                pinctrl-single,pins = <
                        /* Slave 1 */
-                       AM33XX_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE1)  /* mii1_crs.rmii1_crs */
-                       AM33XX_IOPAD(0x910, PIN_INPUT_PULLUP | MUX_MODE1)       /* mii1_rxerr.rmii1_rxerr */
-                       AM33XX_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE1)    /* mii1_txen.rmii1_txen */
-                       AM33XX_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE1)    /* mii1_txd1.rmii1_txd1 */
-                       AM33XX_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE1)    /* mii1_txd0.rmii1_txd0 */
-                       AM33XX_IOPAD(0x93c, PIN_INPUT_PULLUP | MUX_MODE1)       /* mii1_rxd1.rmii1_rxd1 */
-                       AM33XX_IOPAD(0x940, PIN_INPUT_PULLUP | MUX_MODE1)       /* mii1_rxd0.rmii1_rxd0 */
-                       AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE0)     /* rmii1_ref_clk.rmii_ref_clk */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE1)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLUP, MUX_MODE1)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE1)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE1)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE1)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLUP, MUX_MODE1)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLUP, MUX_MODE1)
+                       AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE0)
                >;
        };
 
        cpsw_sleep: cpsw_sleep {
                pinctrl-single,pins = <
                        /* Slave 1 reset value */
-                       AM33XX_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7)
                >;
        };
 
        davinci_mdio_default: davinci_mdio_default {
                pinctrl-single,pins = <
                        /* mdio_data.mdio_data */
-                       AM33XX_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0)
                        /* mdio_clk.mdio_clk */
-                       AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0)
                >;
        };
 
        davinci_mdio_sleep: davinci_mdio_sleep {
                pinctrl-single,pins = <
                        /* MDIO reset value */
-                       AM33XX_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7)
                >;
        };
 
        usb1_drvvbus: usb1_drvvbus {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0xa34, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* usb1_drvvbus.usb1_drvvbus */
+                       AM33XX_PADCONF(AM335X_PIN_USB1_DRVVBUS, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
                >;
        };
 
        sd_pins: pinmux_sd_card {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x8f0, PIN_INPUT | MUX_MODE0) /* mmc0_dat0.mmc0_dat0 */
-                       AM33XX_IOPAD(0x8f4, PIN_INPUT | MUX_MODE0) /* mmc0_dat1.mmc0_dat1 */
-                       AM33XX_IOPAD(0x8f8, PIN_INPUT | MUX_MODE0) /* mmc0_dat2.mmc0_dat2 */
-                       AM33XX_IOPAD(0x8fc, PIN_INPUT | MUX_MODE0) /* mmc0_dat3.mmc0_dat3 */
-                       AM33XX_IOPAD(0x900, PIN_INPUT | MUX_MODE0) /* mmc0_clk.mmc0_clk */
-                       AM33XX_IOPAD(0x904, PIN_INPUT | MUX_MODE0) /* mmc0_cmd.mmc0_cmd */
-                       AM33XX_IOPAD(0x960, PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */
+                       AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT, MUX_MODE7) /* spi0_cs1.gpio0_6 */
                >;
        };
 
        led_gpio_pins: led_gpio_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x9e4, PIN_OUTPUT | MUX_MODE7) /* emu0.gpio3_7 */
-                       AM33XX_IOPAD(0x9e8, PIN_OUTPUT | MUX_MODE7) /* emu1.gpio3_8 */
+                       AM33XX_PADCONF(AM335X_PIN_EMU0, PIN_OUTPUT, MUX_MODE7) /* emu0.gpio3_7 */
+                       AM33XX_PADCONF(AM335X_PIN_EMU1, PIN_OUTPUT, MUX_MODE7) /* emu1.gpio3_8 */
                >;
        };
 };

diff --git a/arch/arm/boot/dts/am335x-chilisom.dtsi b/arch/arm/boot/dts/am335x-chilisom.dtsi
index 1b43ebd..8b88bf6 100644 (file)
--- a/arch/arm/boot/dts/am335x-chilisom.dtsi
+++ b/arch/arm/boot/dts/am335x-chilisom.dtsi
@@ -30,28 +30,28 @@
 
        i2c0_pins: pinmux_i2c0_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x988, PIN_INPUT_PULLUP | MUX_MODE0)       /* i2c0_sda.i2c0_sda */
-                       AM33XX_IOPAD(0x98c, PIN_INPUT_PULLUP | MUX_MODE0)       /* i2c0_scl.i2c0_scl */
+                       AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0)
                >;
        };
 
        nandflash_pins: nandflash_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x800, PIN_INPUT_PULLDOWN | MUX_MODE0)     /* gpmc_ad0.gpmc_ad0 */
-                       AM33XX_IOPAD(0x804, PIN_INPUT_PULLDOWN | MUX_MODE0)     /* gpmc_ad1.gpmc_ad1 */
-                       AM33XX_IOPAD(0x808, PIN_INPUT_PULLDOWN | MUX_MODE0)     /* gpmc_ad2.gpmc_ad2 */
-                       AM33XX_IOPAD(0x80c, PIN_INPUT_PULLDOWN | MUX_MODE0)     /* gpmc_ad3.gpmc_ad3 */
-                       AM33XX_IOPAD(0x810, PIN_INPUT_PULLDOWN | MUX_MODE0)     /* gpmc_ad4.gpmc_ad4 */
-                       AM33XX_IOPAD(0x814, PIN_INPUT_PULLDOWN | MUX_MODE0)     /* gpmc_ad5.gpmc_ad5 */
-                       AM33XX_IOPAD(0x818, PIN_INPUT_PULLDOWN | MUX_MODE0)     /* gpmc_ad6.gpmc_ad6 */
-                       AM33XX_IOPAD(0x81c, PIN_INPUT_PULLDOWN | MUX_MODE0)     /* gpmc_ad7.gpmc_ad7 */
-
-                       AM33XX_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE0)       /* gpmc_wait0.gpmc_wait0 */
-                       AM33XX_IOPAD(0x87c, PIN_OUTPUT_PULLUP | MUX_MODE0)      /* gpmc_csn0.gpmc_csn0 */
-                       AM33XX_IOPAD(0x890, PIN_OUTPUT_PULLUP | MUX_MODE0)      /* gpmc_advn_ale.gpmc_advn_ale */
-                       AM33XX_IOPAD(0x894, PIN_OUTPUT_PULLUP | MUX_MODE0)      /* gpmc_oen_ren.gpmc_oen_ren */
-                       AM33XX_IOPAD(0x898, PIN_OUTPUT_PULLUP | MUX_MODE0)      /* gpmc_wen.gpmc_wen */
-                       AM33XX_IOPAD(0x89c, PIN_OUTPUT_PULLUP | MUX_MODE0)      /* gpmc_be0n_cle.gpmc_be0n_cle */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLDOWN, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLDOWN, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLDOWN, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLDOWN, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLDOWN, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLDOWN, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLDOWN, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLDOWN, MUX_MODE0)
+
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_OUTPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_OUTPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_OUTPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_WEN, PIN_OUTPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_BEN0_CLE, PIN_OUTPUT_PULLUP, MUX_MODE0)
                >;
        };
 };

diff --git a/arch/arm/boot/dts/am335x-cm-t335.dts b/arch/arm/boot/dts/am335x-cm-t335.dts
index 2c724bb..3b0bb88 100644 (file)
--- a/arch/arm/boot/dts/am335x-cm-t335.dts
+++ b/arch/arm/boot/dts/am335x-cm-t335.dts
@@ -94,108 +94,85 @@
 
        i2c0_pins: pinmux_i2c0_pins {
                pinctrl-single,pins = <
-                       /* i2c0_sda.i2c0_sda */
-                       AM33XX_IOPAD(0x988, PIN_INPUT_PULLUP | MUX_MODE0)
-                       /* i2c0_scl.i2c0_scl */
-                       AM33XX_IOPAD(0x98c, PIN_INPUT_PULLUP | MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0)
                >;
        };
 
        i2c1_pins: pinmux_i2c1_pins {
                pinctrl-single,pins = <
                        /* uart0_ctsn.i2c1_sda */
-                       AM33XX_IOPAD(0x968, PIN_INPUT_PULLUP | MUX_MODE2)
+                       AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_INPUT_PULLUP, MUX_MODE2)
                        /* uart0_rtsn.i2c1_scl */
-                       AM33XX_IOPAD(0x96c, PIN_INPUT_PULLUP | MUX_MODE2)
+                       AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT_PULLUP, MUX_MODE2)
                >;
        };
 
        gpio_led_pins: pinmux_gpio_led_pins {
                pinctrl-single,pins = <
                        /* gpmc_csn3.gpio2_0 */
-                       AM33XX_IOPAD(0x888, PIN_OUTPUT | MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_CSN3, PIN_OUTPUT, MUX_MODE7)
                >;
        };
 
        nandflash_pins: pinmux_nandflash_pins {
                pinctrl-single,pins = <
-                       /* gpmc_ad0.gpmc_ad0 */
-                       AM33XX_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE0)
-                       /* gpmc_ad1.gpmc_ad1 */
-                       AM33XX_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE0)
-                       /* gpmc_ad2.gpmc_ad2 */
-                       AM33XX_IOPAD(0x808, PIN_INPUT_PULLUP | MUX_MODE0)
-                       /* gpmc_ad3.gpmc_ad3 */
-                       AM33XX_IOPAD(0x80c, PIN_INPUT_PULLUP | MUX_MODE0)
-                       /* gpmc_ad4.gpmc_ad4 */
-                       AM33XX_IOPAD(0x810, PIN_INPUT_PULLUP | MUX_MODE0)
-                       /* gpmc_ad5.gpmc_ad5 */
-                       AM33XX_IOPAD(0x814, PIN_INPUT_PULLUP | MUX_MODE0)
-                       /* gpmc_ad6.gpmc_ad6 */
-                       AM33XX_IOPAD(0x818, PIN_INPUT_PULLUP | MUX_MODE0)
-                       /* gpmc_ad7.gpmc_ad7 */
-                       AM33XX_IOPAD(0x81c, PIN_INPUT_PULLUP | MUX_MODE0)
-                       /* gpmc_wait0.gpmc_wait0 */
-                       AM33XX_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE0)
                        /* gpmc_wpn.gpio0_30 */
-                       AM33XX_IOPAD(0x874, PIN_INPUT_PULLUP | MUX_MODE7)
-                       /* gpmc_csn0.gpmc_csn0  */
-                       AM33XX_IOPAD(0x87c, PIN_OUTPUT | MUX_MODE0)
-                       /* gpmc_advn_ale.gpmc_advn_ale */
-                       AM33XX_IOPAD(0x890, PIN_OUTPUT | MUX_MODE0)
-                       /* gpmc_oen_ren.gpmc_oen_ren */
-                       AM33XX_IOPAD(0x894, PIN_OUTPUT | MUX_MODE0)
-                       /* gpmc_wen.gpmc_wen */
-                       AM33XX_IOPAD(0x898, PIN_OUTPUT | MUX_MODE0)
-                       /* gpmc_ben0_cle.gpmc_ben0_cle */
-                       AM33XX_IOPAD(0x89c, PIN_OUTPUT | MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLUP, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_WEN, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_BEN0_CLE, PIN_OUTPUT, MUX_MODE0)
                >;
        };
 
        uart0_pins: pinmux_uart0_pins {
                pinctrl-single,pins = <
-                       /* uart0_rxd.uart0_rxd */
-                       AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0)
-                       /* uart0_txd.uart0_txd */
-                       AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
                >;
        };
 
        uart1_pins: pinmux_uart1_pins {
                pinctrl-single,pins = <
-                       /* uart1_ctsn.uart1_ctsn */
-                       AM33XX_IOPAD(0x978, PIN_INPUT | MUX_MODE0)
-                       /* uart1_rtsn.uart1_rtsn */
-                       AM33XX_IOPAD(0x97C, PIN_OUTPUT_PULLDOWN | MUX_MODE0)
-                       /* uart1_rxd.uart1_rxd */
-                       AM33XX_IOPAD(0x980, PIN_INPUT_PULLUP | MUX_MODE0)
-                       /* uart1_txd.uart1_txd */
-                       AM33XX_IOPAD(0x984, PIN_OUTPUT_PULLDOWN | MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
                >;
        };
 
        dcan0_pins: pinmux_dcan0_pins {
                pinctrl-single,pins = <
                        /* uart1_ctsn.dcan0_tx */
-                       AM33XX_IOPAD(0x978, PIN_OUTPUT | MUX_MODE2)
+                       AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_OUTPUT, MUX_MODE2)
                        /* uart1_rtsn.dcan0_rx */
-                       AM33XX_IOPAD(0x97C, PIN_INPUT | MUX_MODE2)
+                       AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_INPUT, MUX_MODE2)
                >;
        };
 
        dcan1_pins: pinmux_dcan1_pins {
                pinctrl-single,pins = <
                        /* uart1_rxd.dcan1_tx */
-                       AM33XX_IOPAD(0x980, PIN_OUTPUT | MUX_MODE2)
+                       AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_OUTPUT, MUX_MODE2)
                        /* uart1_txd.dcan1_rx */
-                       AM33XX_IOPAD(0x984, PIN_INPUT | MUX_MODE2)
+                       AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_INPUT, MUX_MODE2)
                >;
        };
 
        ecap0_pins: pinmux_ecap0_pins {
                pinctrl-single,pins = <
-                       /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */
-                       AM33XX_IOPAD(0x964, 0x0)
+                       AM33XX_PADCONF(AM335X_PIN_ECAP0_IN_PWM0_OUT, 0x0, MUX_MODE0)
                >;
        };
 
@@ -203,96 +180,83 @@
                pinctrl-single,pins = <
                        /* Slave 1 */
                        /* mii1_tx_en.rgmii1_tctl */
-                       AM33XX_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE2)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE2)
                        /* mii1_rxdv.rgmii1_rctl */
-                       AM33XX_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE2)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE2)
                        /* mii1_txd3.rgmii1_td3 */
-                       AM33XX_IOPAD(0x91c, PIN_OUTPUT_PULLDOWN | MUX_MODE2)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT_PULLDOWN, MUX_MODE2)
                        /* mii1_txd2.rgmii1_td2 */
-                       AM33XX_IOPAD(0x920, PIN_OUTPUT_PULLDOWN | MUX_MODE2)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE2)
                        /* mii1_txd1.rgmii1_td1 */
-                       AM33XX_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE2)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE2)
                        /* mii1_txd0.rgmii1_td0 */
-                       AM33XX_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE2)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE2)
                        /* mii1_txclk.rgmii1_tclk */
-                       AM33XX_IOPAD(0x92c, PIN_OUTPUT_PULLDOWN | MUX_MODE2)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE2)
                        /* mii1_rxclk.rgmii1_rclk */
-                       AM33XX_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE2)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE2)
                        /* mii1_rxd3.rgmii1_rd3 */
-                       AM33XX_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE2)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE2)
                        /* mii1_rxd2.rgmii1_rd2 */
-                       AM33XX_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE2)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE2)
                        /* mii1_rxd1.rgmii1_rd1 */
-                       AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE2)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE2)
                        /* mii1_rxd0.rgmii1_rd0 */
-                       AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE2)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE2)
                >;
        };
 
        cpsw_sleep: cpsw_sleep {
                pinctrl-single,pins = <
                        /* Slave 1 reset value */
-                       AM33XX_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x91c, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x920, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x92c, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7)
                >;
        };
 
        davinci_mdio_default: davinci_mdio_default {
                pinctrl-single,pins = <
-                       /* mdio_data.mdio_data */
-                       AM33XX_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)
-                       /* mdio_clk.mdio_clk */
-                       AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0)
                >;
        };
 
        davinci_mdio_sleep: davinci_mdio_sleep {
                pinctrl-single,pins = <
                        /* MDIO reset value */
-                       AM33XX_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7)
                >;
        };
 
        mmc1_pins: pinmux_mmc1_pins {
                pinctrl-single,pins = <
-                       /* mmc0_dat3.mmc0_dat3 */
-                       AM33XX_IOPAD(0x8f0, PIN_INPUT_PULLUP | MUX_MODE0)
-                       /* mmc0_dat2.mmc0_dat2 */
-                       AM33XX_IOPAD(0x8f4, PIN_INPUT_PULLUP | MUX_MODE0)
-                       /* mmc0_dat1.mmc0_dat1 */
-                       AM33XX_IOPAD(0x8f8, PIN_INPUT_PULLUP | MUX_MODE0)
-                       /* mmc0_dat0.mmc0_dat0 */
-                       AM33XX_IOPAD(0x8fc, PIN_INPUT_PULLUP | MUX_MODE0)
-                       /* mmc0_clk.mmc0_clk */
-                       AM33XX_IOPAD(0x900, PIN_INPUT_PULLUP | MUX_MODE0)
-                       /* mmc0_cmd.mmc0_cmd */
-                       AM33XX_IOPAD(0x904, PIN_INPUT_PULLUP | MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0)
                >;
        };
 
        spi0_pins: pinmux_spi0_pins {
                pinctrl-single,pins = <
-                       /* spi0_sclk.spi0_sclk */
-                       AM33XX_IOPAD(0x950, PIN_INPUT | MUX_MODE0)
-                       /* spi0_d0.spi0_d0 */
-                       AM33XX_IOPAD(0x954, PIN_OUTPUT_PULLUP | MUX_MODE0)
-                       /* spi0_d1.spi0_d1 */
-                       AM33XX_IOPAD(0x958, PIN_INPUT | MUX_MODE0)
-                       /* spi0_cs0.spi0_cs0 */
-                       AM33XX_IOPAD(0x95C, PIN_OUTPUT | MUX_MODE0)
-                       /* spi0_cs1.spi0_cs1 */
-                       AM33XX_IOPAD(0x960, PIN_OUTPUT | MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_OUTPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_OUTPUT, MUX_MODE0)
                >;
        };
 
@@ -300,7 +264,7 @@
        bluetooth_pins: pinmux_bluetooth_pins {
                pinctrl-single,pins = <
                        /* XDMA_EVENT_INTR0.gpio0_19 - bluetooth enable */
-                       AM33XX_IOPAD(0x9b0, PIN_OUTPUT_PULLUP | MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_OUTPUT_PULLUP, MUX_MODE7)
                >;
        };
 
@@ -308,13 +272,13 @@
        mcasp1_pins: pinmux_mcasp1_pins {
                pinctrl-single,pins = <
                        /* MII1_CRS.mcasp1_aclkx */
-                       AM33XX_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE4)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE4)
                        /* MII1_RX_ER.mcasp1_fsx */
-                       AM33XX_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE4)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE4)
                        /* MII1_COL.mcasp1_axr2 */
-                       AM33XX_IOPAD(0x908, PIN_INPUT_PULLDOWN | MUX_MODE4)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT_PULLDOWN, MUX_MODE4)
                        /* RMII1_REF_CLK.mcasp1_axr3 */
-                       AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE4)
+                       AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE4)
                >;
        };
 
@@ -322,9 +286,9 @@
        wifi_pins: pinmux_wifi_pins {
                pinctrl-single,pins = <
                        /* EMU1.gpio3_8 - WiFi IRQ */
-                       AM33XX_IOPAD(0x9e8, PIN_INPUT_PULLUP | MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_EMU1, PIN_INPUT_PULLUP, MUX_MODE7)
                        /* XDMA_EVENT_INTR1.gpio0_20 - WiFi enable */
-                       AM33XX_IOPAD(0x9b4, PIN_OUTPUT | MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR1, PIN_OUTPUT, MUX_MODE7)
                >;
        };
 };

diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts
index edcff79..55d4392 100644 (file)
--- a/arch/arm/boot/dts/am335x-evm.dts
+++ b/arch/arm/boot/dts/am335x-evm.dts
@@ -190,222 +190,222 @@
 
        matrix_keypad_s0: matrix_keypad_s0 {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x854, PIN_OUTPUT_PULLDOWN | MUX_MODE7)    /* gpmc_a5.gpio1_21 */
-                       AM33XX_IOPAD(0x858, PIN_OUTPUT_PULLDOWN | MUX_MODE7)    /* gpmc_a6.gpio1_22 */
-                       AM33XX_IOPAD(0x864, PIN_INPUT_PULLDOWN | MUX_MODE7)     /* gpmc_a9.gpio1_25 */
-                       AM33XX_IOPAD(0x868, PIN_INPUT_PULLDOWN | MUX_MODE7)     /* gpmc_a10.gpio1_26 */
-                       AM33XX_IOPAD(0x86c, PIN_INPUT_PULLDOWN | MUX_MODE7)     /* gpmc_a11.gpio1_27 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT_PULLDOWN, MUX_MODE7)      /* gpmc_a5.gpio1_21 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_OUTPUT_PULLDOWN, MUX_MODE7)      /* gpmc_a6.gpio1_22 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLDOWN, MUX_MODE7)       /* gpmc_a9.gpio1_25 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE7)      /* gpmc_a10.gpio1_26 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE7)      /* gpmc_a11.gpio1_27 */
                >;
        };
 
        volume_keys_s0: volume_keys_s0 {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x950, PIN_INPUT_PULLDOWN | MUX_MODE7)     /* spi0_sclk.gpio0_2 */
-                       AM33XX_IOPAD(0x954, PIN_INPUT_PULLDOWN | MUX_MODE7)     /* spi0_d0.gpio0_3 */
+                       AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT_PULLDOWN, MUX_MODE7)     /* spi0_sclk.gpio0_2 */
+                       AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_INPUT_PULLDOWN, MUX_MODE7)       /* spi0_d0.gpio0_3 */
                >;
        };
 
        i2c0_pins: pinmux_i2c0_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x988, PIN_INPUT_PULLUP | MUX_MODE0)       /* i2c0_sda.i2c0_sda */
-                       AM33XX_IOPAD(0x98c, PIN_INPUT_PULLUP | MUX_MODE0)       /* i2c0_scl.i2c0_scl */
+                       AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0)        /* i2c0_sda.i2c0_sda */
+                       AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0)        /* i2c0_scl.i2c0_scl */
                >;
        };
 
        i2c1_pins: pinmux_i2c1_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x958, PIN_INPUT_PULLUP | MUX_MODE2)       /* spi0_d1.i2c1_sda */
-                       AM33XX_IOPAD(0x95c, PIN_INPUT_PULLUP | MUX_MODE2)       /* spi0_cs0.i2c1_scl */
+                       AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT_PULLUP, MUX_MODE2) /* spi0_d1.i2c1_sda */
+                       AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT_PULLUP, MUX_MODE2)        /* spi0_cs0.i2c1_scl */
                >;
        };
 
        uart0_pins: pinmux_uart0_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0)       /* uart0_rxd.uart0_rxd */
-                       AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0)    /* uart0_txd.uart0_txd */
+                       AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
                >;
        };
 
        uart1_pins: pinmux_uart1_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x978, PIN_INPUT | MUX_MODE0)              /* uart1_ctsn.uart1_ctsn */
-                       AM33XX_IOPAD(0x97C, PIN_OUTPUT_PULLDOWN | MUX_MODE0)    /* uart1_rtsn.uart1_rtsn */
-                       AM33XX_IOPAD(0x980, PIN_INPUT_PULLUP | MUX_MODE0)       /* uart1_rxd.uart1_rxd */
-                       AM33XX_IOPAD(0x984, PIN_OUTPUT_PULLDOWN | MUX_MODE0)    /* uart1_txd.uart1_txd */
+                       AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
                >;
        };
 
        clkout2_pin: pinmux_clkout2_pin {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x9b4, PIN_OUTPUT_PULLDOWN | MUX_MODE3)    /* xdma_event_intr1.clkout2 */
+                       AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR1, PIN_OUTPUT_PULLDOWN, MUX_MODE3)     /* xdma_event_intr1.clkout2 */
                >;
        };
 
        nandflash_pins_s0: nandflash_pins_s0 {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE0)       /* gpmc_ad0.gpmc_ad0 */
-                       AM33XX_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE0)       /* gpmc_ad1.gpmc_ad1 */
-                       AM33XX_IOPAD(0x808, PIN_INPUT_PULLUP | MUX_MODE0)       /* gpmc_ad2.gpmc_ad2 */
-                       AM33XX_IOPAD(0x80c, PIN_INPUT_PULLUP | MUX_MODE0)       /* gpmc_ad3.gpmc_ad3 */
-                       AM33XX_IOPAD(0x810, PIN_INPUT_PULLUP | MUX_MODE0)       /* gpmc_ad4.gpmc_ad4 */
-                       AM33XX_IOPAD(0x814, PIN_INPUT_PULLUP | MUX_MODE0)       /* gpmc_ad5.gpmc_ad5 */
-                       AM33XX_IOPAD(0x818, PIN_INPUT_PULLUP | MUX_MODE0)       /* gpmc_ad6.gpmc_ad6 */
-                       AM33XX_IOPAD(0x81c, PIN_INPUT_PULLUP | MUX_MODE0)       /* gpmc_ad7.gpmc_ad7 */
-                       AM33XX_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE0)       /* gpmc_wait0.gpmc_wait0 */
-                       AM33XX_IOPAD(0x874, PIN_INPUT_PULLUP | MUX_MODE7)       /* gpmc_wpn.gpio0_30 */
-                       AM33XX_IOPAD(0x87c, PIN_OUTPUT | MUX_MODE0)             /* gpmc_csn0.gpmc_csn0  */
-                       AM33XX_IOPAD(0x890, PIN_OUTPUT | MUX_MODE0)             /* gpmc_advn_ale.gpmc_advn_ale */
-                       AM33XX_IOPAD(0x894, PIN_OUTPUT | MUX_MODE0)             /* gpmc_oen_ren.gpmc_oen_ren */
-                       AM33XX_IOPAD(0x898, PIN_OUTPUT | MUX_MODE0)             /* gpmc_wen.gpmc_wen */
-                       AM33XX_IOPAD(0x89c, PIN_OUTPUT | MUX_MODE0)             /* gpmc_be0n_cle.gpmc_be0n_cle */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLUP, MUX_MODE7)        /* gpmc_wpn.gpio0_30 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_WEN, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_BEN0_CLE, PIN_OUTPUT, MUX_MODE0)
                >;
        };
 
        ecap0_pins: backlight_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x964, MUX_MODE0)  /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out */
+                       AM33XX_PADCONF(AM335X_PIN_ECAP0_IN_PWM0_OUT, 0x0, MUX_MODE0)
                >;
        };
 
        cpsw_default: cpsw_default {
                pinctrl-single,pins = <
                        /* Slave 1 */
-                       AM33XX_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE2)    /* mii1_txen.rgmii1_tctl */
-                       AM33XX_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE2)     /* mii1_rxdv.rgmii1_rctl */
-                       AM33XX_IOPAD(0x91c, PIN_OUTPUT_PULLDOWN | MUX_MODE2)    /* mii1_txd3.rgmii1_td3 */
-                       AM33XX_IOPAD(0x920, PIN_OUTPUT_PULLDOWN | MUX_MODE2)    /* mii1_txd2.rgmii1_td2 */
-                       AM33XX_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE2)    /* mii1_txd1.rgmii1_td1 */
-                       AM33XX_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE2)    /* mii1_txd0.rgmii1_td0 */
-                       AM33XX_IOPAD(0x92c, PIN_OUTPUT_PULLDOWN | MUX_MODE2)    /* mii1_txclk.rgmii1_tclk */
-                       AM33XX_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE2)     /* mii1_rxclk.rgmii1_rclk */
-                       AM33XX_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE2)     /* mii1_rxd3.rgmii1_rd3 */
-                       AM33XX_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE2)     /* mii1_rxd2.rgmii1_rd2 */
-                       AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE2)     /* mii1_rxd1.rgmii1_rd1 */
-                       AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE2)     /* mii1_rxd0.rgmii1_rd0 */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE2)   /* mii1_txen.rgmii1_tctl */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE2)    /* mii1_rxdv.rgmii1_rctl */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT_PULLDOWN, MUX_MODE2)    /* mii1_txd3.rgmii1_td3 */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE2)    /* mii1_txd2.rgmii1_td2 */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE2)    /* mii1_txd1.rgmii1_td1 */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE2)    /* mii1_txd0.rgmii1_td0 */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE2)  /* mii1_txclk.rgmii1_tclk */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE2)   /* mii1_rxclk.rgmii1_rclk */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE2)     /* mii1_rxd3.rgmii1_rd3 */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE2)     /* mii1_rxd2.rgmii1_rd2 */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE2)     /* mii1_rxd1.rgmii1_rd1 */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE2)     /* mii1_rxd0.rgmii1_rd0 */
                >;
        };
 
        cpsw_sleep: cpsw_sleep {
                pinctrl-single,pins = <
                        /* Slave 1 reset value */
-                       AM33XX_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x91c, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x920, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x92c, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7)
                >;
        };
 
        davinci_mdio_default: davinci_mdio_default {
                pinctrl-single,pins = <
                        /* MDIO */
-                       AM33XX_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)       /* mdio_data.mdio_data */
-                       AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0)                      /* mdio_clk.mdio_clk */
+                       AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0)
                >;
        };
 
        davinci_mdio_sleep: davinci_mdio_sleep {
                pinctrl-single,pins = <
                        /* MDIO reset value */
-                       AM33XX_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7)
                >;
        };
 
        mmc1_pins: pinmux_mmc1_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x960, PIN_INPUT | MUX_MODE7)              /* spi0_cs1.gpio0_6 */
-                       AM33XX_IOPAD(0x8fc, PIN_INPUT_PULLUP | MUX_MODE0)       /* mmc0_dat0.mmc0_dat0 */
-                       AM33XX_IOPAD(0x8f8, PIN_INPUT_PULLUP | MUX_MODE0)       /* mmc0_dat1.mmc0_dat1 */
-                       AM33XX_IOPAD(0x8f4, PIN_INPUT_PULLUP | MUX_MODE0)       /* mmc0_dat2.mmc0_dat2 */
-                       AM33XX_IOPAD(0x8f0, PIN_INPUT_PULLUP | MUX_MODE0)       /* mmc0_dat3.mmc0_dat3 */
-                       AM33XX_IOPAD(0x904, PIN_INPUT_PULLUP | MUX_MODE0)       /* mmc0_cmd.mmc0_cmd */
-                       AM33XX_IOPAD(0x900, PIN_INPUT_PULLUP | MUX_MODE0)       /* mmc0_clk.mmc0_clk */
-                       AM33XX_IOPAD(0x9a0, PIN_INPUT | MUX_MODE4)              /* mcasp0_aclkr.mmc0_sdwp */
+                       AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT, MUX_MODE7)               /* spi0_cs1.gpio0_6 */
+                       AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKR, PIN_INPUT, MUX_MODE4)           /* mcasp0_aclkr.mmc0_sdwp */
                >;
        };
 
        mmc3_pins: pinmux_mmc3_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x844, PIN_INPUT_PULLUP | MUX_MODE3)       /* gpmc_a1.mmc2_dat0, INPUT_PULLUP | MODE3 */
-                       AM33XX_IOPAD(0x848, PIN_INPUT_PULLUP | MUX_MODE3)       /* gpmc_a2.mmc2_dat1, INPUT_PULLUP | MODE3 */
-                       AM33XX_IOPAD(0x84c, PIN_INPUT_PULLUP | MUX_MODE3)       /* gpmc_a3.mmc2_dat2, INPUT_PULLUP | MODE3 */
-                       AM33XX_IOPAD(0x878, PIN_INPUT_PULLUP | MUX_MODE3)       /* gpmc_ben1.mmc2_dat3, INPUT_PULLUP | MODE3 */
-                       AM33XX_IOPAD(0x888, PIN_INPUT_PULLUP | MUX_MODE3)       /* gpmc_csn3.mmc2_cmd, INPUT_PULLUP | MODE3 */
-                       AM33XX_IOPAD(0x88c, PIN_INPUT_PULLUP | MUX_MODE3)       /* gpmc_clk.mmc2_clk, INPUT_PULLUP | MODE3 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_a1.mmc2_dat0, INPUT_PULLUP | MODE3 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_a2.mmc2_dat1, INPUT_PULLUP | MODE3 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_a3.mmc2_dat2, INPUT_PULLUP | MODE3 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_BEN1, PIN_INPUT_PULLUP, MUX_MODE3)       /* gpmc_ben1.mmc2_dat3, INPUT_PULLUP | MODE3 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_CSN3, PIN_INPUT_PULLUP, MUX_MODE3)       /* gpmc_csn3.mmc2_cmd, INPUT_PULLUP | MODE3 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_CLK, PIN_INPUT_PULLUP, MUX_MODE3)        /* gpmc_clk.mmc2_clk, INPUT_PULLUP | MODE3 */
                >;
        };
 
        wlan_pins: pinmux_wlan_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x840, PIN_OUTPUT_PULLDOWN | MUX_MODE7)    /* gpmc_a0.gpio1_16 */
-                       AM33XX_IOPAD(0x99c, PIN_INPUT | MUX_MODE7)              /* mcasp0_ahclkr.gpio3_17 */
-                       AM33XX_IOPAD(0x9ac, PIN_OUTPUT_PULLDOWN | MUX_MODE7)    /* mcasp0_ahclkx.gpio3_21 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT_PULLDOWN, MUX_MODE7)      /* gpmc_a0.gpio1_16 */
+                       AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKR, PIN_INPUT, MUX_MODE7)          /* mcasp0_ahclkr.gpio3_17 */
+                       AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKX, PIN_OUTPUT_PULLDOWN, MUX_MODE7)        /* mcasp0_ahclkx.gpio3_21 */
                >;
        };
 
        lcd_pins_s0: lcd_pins_s0 {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x820, PIN_OUTPUT | MUX_MODE1)             /* gpmc_ad8.lcd_data23 */
-                       AM33XX_IOPAD(0x824, PIN_OUTPUT | MUX_MODE1)             /* gpmc_ad9.lcd_data22 */
-                       AM33XX_IOPAD(0x828, PIN_OUTPUT | MUX_MODE1)             /* gpmc_ad10.lcd_data21 */
-                       AM33XX_IOPAD(0x82c, PIN_OUTPUT | MUX_MODE1)             /* gpmc_ad11.lcd_data20 */
-                       AM33XX_IOPAD(0x830, PIN_OUTPUT | MUX_MODE1)             /* gpmc_ad12.lcd_data19 */
-                       AM33XX_IOPAD(0x834, PIN_OUTPUT | MUX_MODE1)             /* gpmc_ad13.lcd_data18 */
-                       AM33XX_IOPAD(0x838, PIN_OUTPUT | MUX_MODE1)             /* gpmc_ad14.lcd_data17 */
-                       AM33XX_IOPAD(0x83c, PIN_OUTPUT | MUX_MODE1)             /* gpmc_ad15.lcd_data16 */
-                       AM33XX_IOPAD(0x8a0, PIN_OUTPUT | MUX_MODE0)             /* lcd_data0.lcd_data0 */
-                       AM33XX_IOPAD(0x8a4, PIN_OUTPUT | MUX_MODE0)             /* lcd_data1.lcd_data1 */
-                       AM33XX_IOPAD(0x8a8, PIN_OUTPUT | MUX_MODE0)             /* lcd_data2.lcd_data2 */
-                       AM33XX_IOPAD(0x8ac, PIN_OUTPUT | MUX_MODE0)             /* lcd_data3.lcd_data3 */
-                       AM33XX_IOPAD(0x8b0, PIN_OUTPUT | MUX_MODE0)             /* lcd_data4.lcd_data4 */
-                       AM33XX_IOPAD(0x8b4, PIN_OUTPUT | MUX_MODE0)             /* lcd_data5.lcd_data5 */
-                       AM33XX_IOPAD(0x8b8, PIN_OUTPUT | MUX_MODE0)             /* lcd_data6.lcd_data6 */
-                       AM33XX_IOPAD(0x8bc, PIN_OUTPUT | MUX_MODE0)             /* lcd_data7.lcd_data7 */
-                       AM33XX_IOPAD(0x8c0, PIN_OUTPUT | MUX_MODE0)             /* lcd_data8.lcd_data8 */
-                       AM33XX_IOPAD(0x8c4, PIN_OUTPUT | MUX_MODE0)             /* lcd_data9.lcd_data9 */
-                       AM33XX_IOPAD(0x8c8, PIN_OUTPUT | MUX_MODE0)             /* lcd_data10.lcd_data10 */
-                       AM33XX_IOPAD(0x8cc, PIN_OUTPUT | MUX_MODE0)             /* lcd_data11.lcd_data11 */
-                       AM33XX_IOPAD(0x8d0, PIN_OUTPUT | MUX_MODE0)             /* lcd_data12.lcd_data12 */
-                       AM33XX_IOPAD(0x8d4, PIN_OUTPUT | MUX_MODE0)             /* lcd_data13.lcd_data13 */
-                       AM33XX_IOPAD(0x8d8, PIN_OUTPUT | MUX_MODE0)             /* lcd_data14.lcd_data14 */
-                       AM33XX_IOPAD(0x8dc, PIN_OUTPUT | MUX_MODE0)             /* lcd_data15.lcd_data15 */
-                       AM33XX_IOPAD(0x8e0, PIN_OUTPUT | MUX_MODE0)             /* lcd_vsync.lcd_vsync */
-                       AM33XX_IOPAD(0x8e4, PIN_OUTPUT | MUX_MODE0)             /* lcd_hsync.lcd_hsync */
-                       AM33XX_IOPAD(0x8e8, PIN_OUTPUT | MUX_MODE0)             /* lcd_pclk.lcd_pclk */
-                       AM33XX_IOPAD(0x8ec, PIN_OUTPUT | MUX_MODE0)             /* lcd_ac_bias_en.lcd_ac_bias_en */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_OUTPUT, MUX_MODE1)              /* gpmc_ad8.lcd_data23 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_OUTPUT, MUX_MODE1)              /* gpmc_ad9.lcd_data22 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_OUTPUT, MUX_MODE1)             /* gpmc_ad10.lcd_data21 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_OUTPUT, MUX_MODE1)             /* gpmc_ad11.lcd_data20 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_OUTPUT, MUX_MODE1)             /* gpmc_ad12.lcd_data19 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_OUTPUT, MUX_MODE1)             /* gpmc_ad13.lcd_data18 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_OUTPUT, MUX_MODE1)             /* gpmc_ad14.lcd_data17 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_OUTPUT, MUX_MODE1)             /* gpmc_ad15.lcd_data16 */
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT, MUX_MODE0)
                >;
        };
 
        mcasp1_pins: mcasp1_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_crs.mcasp1_aclkx */
-                       AM33XX_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_rxerr.mcasp1_fsx */
-                       AM33XX_IOPAD(0x908, PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* mii1_col.mcasp1_axr2 */
-                       AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE4) /* mii1_crs.mcasp1_aclkx */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE4) /* mii1_rxerr.mcasp1_fsx */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_OUTPUT_PULLDOWN, MUX_MODE4) /* mii1_col.mcasp1_axr2 */
+                       AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */
                >;
        };
 
        mcasp1_pins_sleep: mcasp1_pins_sleep {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x908, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7)
                >;
        };
 
        dcan1_pins_default: dcan1_pins_default {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x968, PIN_OUTPUT | MUX_MODE2) /* uart0_ctsn.d_can1_tx */
-                       AM33XX_IOPAD(0x96c, PIN_INPUT_PULLDOWN | MUX_MODE2) /* uart0_rtsn.d_can1_rx */
+                       AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_OUTPUT, MUX_MODE2) /* uart0_ctsn.d_can1_tx */
+                       AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT_PULLDOWN, MUX_MODE2) /* uart0_rtsn.d_can1_rx */
                >;
        };
 };

diff --git a/arch/arm/boot/dts/am335x-evmsk.dts b/arch/arm/boot/dts/am335x-evmsk.dts
index 2c2d8b5..8fc8056 100644 (file)
--- a/arch/arm/boot/dts/am335x-evmsk.dts
+++ b/arch/arm/boot/dts/am335x-evmsk.dts
@@ -227,241 +227,241 @@
 
        lcd_pins_default: lcd_pins_default {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x820, PIN_OUTPUT | MUX_MODE1)     /* gpmc_ad8.lcd_data23 */
-                       AM33XX_IOPAD(0x824, PIN_OUTPUT | MUX_MODE1)     /* gpmc_ad9.lcd_data22 */
-                       AM33XX_IOPAD(0x828, PIN_OUTPUT | MUX_MODE1)     /* gpmc_ad10.lcd_data21 */
-                       AM33XX_IOPAD(0x82c, PIN_OUTPUT | MUX_MODE1)     /* gpmc_ad11.lcd_data20 */
-                       AM33XX_IOPAD(0x830, PIN_OUTPUT | MUX_MODE1)     /* gpmc_ad12.lcd_data19 */
-                       AM33XX_IOPAD(0x834, PIN_OUTPUT | MUX_MODE1)     /* gpmc_ad13.lcd_data18 */
-                       AM33XX_IOPAD(0x838, PIN_OUTPUT | MUX_MODE1)     /* gpmc_ad14.lcd_data17 */
-                       AM33XX_IOPAD(0x83c, PIN_OUTPUT | MUX_MODE1)     /* gpmc_ad15.lcd_data16 */
-                       AM33XX_IOPAD(0x8a0, PIN_OUTPUT | MUX_MODE0)     /* lcd_data0.lcd_data0 */
-                       AM33XX_IOPAD(0x8a4, PIN_OUTPUT | MUX_MODE0)     /* lcd_data1.lcd_data1 */
-                       AM33XX_IOPAD(0x8a8, PIN_OUTPUT | MUX_MODE0)     /* lcd_data2.lcd_data2 */
-                       AM33XX_IOPAD(0x8ac, PIN_OUTPUT | MUX_MODE0)     /* lcd_data3.lcd_data3 */
-                       AM33XX_IOPAD(0x8b0, PIN_OUTPUT | MUX_MODE0)     /* lcd_data4.lcd_data4 */
-                       AM33XX_IOPAD(0x8b4, PIN_OUTPUT | MUX_MODE0)     /* lcd_data5.lcd_data5 */
-                       AM33XX_IOPAD(0x8b8, PIN_OUTPUT | MUX_MODE0)     /* lcd_data6.lcd_data6 */
-                       AM33XX_IOPAD(0x8bc, PIN_OUTPUT | MUX_MODE0)     /* lcd_data7.lcd_data7 */
-                       AM33XX_IOPAD(0x8c0, PIN_OUTPUT | MUX_MODE0)     /* lcd_data8.lcd_data8 */
-                       AM33XX_IOPAD(0x8c4, PIN_OUTPUT | MUX_MODE0)     /* lcd_data9.lcd_data9 */
-                       AM33XX_IOPAD(0x8c8, PIN_OUTPUT | MUX_MODE0)     /* lcd_data10.lcd_data10 */
-                       AM33XX_IOPAD(0x8cc, PIN_OUTPUT | MUX_MODE0)     /* lcd_data11.lcd_data11 */
-                       AM33XX_IOPAD(0x8d0, PIN_OUTPUT | MUX_MODE0)     /* lcd_data12.lcd_data12 */
-                       AM33XX_IOPAD(0x8d4, PIN_OUTPUT | MUX_MODE0)     /* lcd_data13.lcd_data13 */
-                       AM33XX_IOPAD(0x8d8, PIN_OUTPUT | MUX_MODE0)     /* lcd_data14.lcd_data14 */
-                       AM33XX_IOPAD(0x8dc, PIN_OUTPUT | MUX_MODE0)     /* lcd_data15.lcd_data15 */
-                       AM33XX_IOPAD(0x8e0, PIN_OUTPUT | MUX_MODE0)     /* lcd_vsync.lcd_vsync */
-                       AM33XX_IOPAD(0x8e4, PIN_OUTPUT | MUX_MODE0)     /* lcd_hsync.lcd_hsync */
-                       AM33XX_IOPAD(0x8e8, PIN_OUTPUT | MUX_MODE0)     /* lcd_pclk.lcd_pclk */
-                       AM33XX_IOPAD(0x8ec, PIN_OUTPUT | MUX_MODE0)     /* lcd_ac_bias_en.lcd_ac_bias_en */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_OUTPUT, MUX_MODE1)      /* gpmc_ad8.lcd_data23 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_OUTPUT, MUX_MODE1)      /* gpmc_ad9.lcd_data22 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_OUTPUT, MUX_MODE1)     /* gpmc_ad10.lcd_data21 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_OUTPUT, MUX_MODE1)     /* gpmc_ad11.lcd_data20 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_OUTPUT, MUX_MODE1)     /* gpmc_ad12.lcd_data19 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_OUTPUT, MUX_MODE1)     /* gpmc_ad13.lcd_data18 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_OUTPUT, MUX_MODE1)     /* gpmc_ad14.lcd_data17 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_OUTPUT, MUX_MODE1)     /* gpmc_ad15.lcd_data16 */
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT, MUX_MODE0)
                >;
        };
 
        lcd_pins_sleep: lcd_pins_sleep {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x820, PIN_INPUT_PULLDOWN | MUX_MODE7)     /* gpmc_ad8.lcd_data23 */
-                       AM33XX_IOPAD(0x824, PIN_INPUT_PULLDOWN | MUX_MODE7)     /* gpmc_ad9.lcd_data22 */
-                       AM33XX_IOPAD(0x828, PIN_INPUT_PULLDOWN | MUX_MODE7)     /* gpmc_ad10.lcd_data21 */
-                       AM33XX_IOPAD(0x82c, PIN_INPUT_PULLDOWN | MUX_MODE7)     /* gpmc_ad11.lcd_data20 */
-                       AM33XX_IOPAD(0x830, PIN_INPUT_PULLDOWN | MUX_MODE7)     /* gpmc_ad12.lcd_data19 */
-                       AM33XX_IOPAD(0x834, PIN_INPUT_PULLDOWN | MUX_MODE7)     /* gpmc_ad13.lcd_data18 */
-                       AM33XX_IOPAD(0x838, PIN_INPUT_PULLDOWN | MUX_MODE7)     /* gpmc_ad14.lcd_data17 */
-                       AM33XX_IOPAD(0x83c, PIN_INPUT_PULLDOWN | MUX_MODE7)     /* gpmc_ad15.lcd_data16 */
-                       AM33XX_IOPAD(0x8a0, PULL_DISABLE | MUX_MODE7)   /* lcd_data0.lcd_data0 */
-                       AM33XX_IOPAD(0x8a4, PULL_DISABLE | MUX_MODE7)   /* lcd_data1.lcd_data1 */
-                       AM33XX_IOPAD(0x8a8, PULL_DISABLE | MUX_MODE7)   /* lcd_data2.lcd_data2 */
-                       AM33XX_IOPAD(0x8ac, PULL_DISABLE | MUX_MODE7)   /* lcd_data3.lcd_data3 */
-                       AM33XX_IOPAD(0x8b0, PULL_DISABLE | MUX_MODE7)   /* lcd_data4.lcd_data4 */
-                       AM33XX_IOPAD(0x8b4, PULL_DISABLE | MUX_MODE7)   /* lcd_data5.lcd_data5 */
-                       AM33XX_IOPAD(0x8b8, PULL_DISABLE | MUX_MODE7)   /* lcd_data6.lcd_data6 */
-                       AM33XX_IOPAD(0x8bc, PULL_DISABLE | MUX_MODE7)   /* lcd_data7.lcd_data7 */
-                       AM33XX_IOPAD(0x8c0, PULL_DISABLE | MUX_MODE7)   /* lcd_data8.lcd_data8 */
-                       AM33XX_IOPAD(0x8c4, PULL_DISABLE | MUX_MODE7)   /* lcd_data9.lcd_data9 */
-                       AM33XX_IOPAD(0x8c8, PULL_DISABLE | MUX_MODE7)   /* lcd_data10.lcd_data10 */
-                       AM33XX_IOPAD(0x8cc, PULL_DISABLE | MUX_MODE7)   /* lcd_data11.lcd_data11 */
-                       AM33XX_IOPAD(0x8d0, PULL_DISABLE | MUX_MODE7)   /* lcd_data12.lcd_data12 */
-                       AM33XX_IOPAD(0x8d4, PULL_DISABLE | MUX_MODE7)   /* lcd_data13.lcd_data13 */
-                       AM33XX_IOPAD(0x8d8, PULL_DISABLE | MUX_MODE7)   /* lcd_data14.lcd_data14 */
-                       AM33XX_IOPAD(0x8dc, PULL_DISABLE | MUX_MODE7)   /* lcd_data15.lcd_data15 */
-                       AM33XX_IOPAD(0x8e0, PIN_INPUT_PULLDOWN | MUX_MODE7)     /* lcd_vsync.lcd_vsync */
-                       AM33XX_IOPAD(0x8e4, PIN_INPUT_PULLDOWN | MUX_MODE7)     /* lcd_hsync.lcd_hsync */
-                       AM33XX_IOPAD(0x8e8, PIN_INPUT_PULLDOWN | MUX_MODE7)     /* lcd_pclk.lcd_pclk */
-                       AM33XX_IOPAD(0x8ec, PIN_INPUT_PULLDOWN | MUX_MODE7)     /* lcd_ac_bias_en.lcd_ac_bias_en */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_INPUT_PULLDOWN, MUX_MODE7)      /* gpmc_ad8.lcd_data23 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_INPUT_PULLDOWN, MUX_MODE7)      /* gpmc_ad9.lcd_data22 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_INPUT_PULLDOWN, MUX_MODE7)     /* gpmc_ad10.lcd_data21 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_INPUT_PULLDOWN, MUX_MODE7)     /* gpmc_ad11.lcd_data20 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_INPUT_PULLDOWN, MUX_MODE7)     /* gpmc_ad12.lcd_data19 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT_PULLDOWN, MUX_MODE7)     /* gpmc_ad13.lcd_data18 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_INPUT_PULLDOWN, MUX_MODE7)     /* gpmc_ad14.lcd_data17 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_INPUT_PULLDOWN, MUX_MODE7)     /* gpmc_ad15.lcd_data16 */
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PULL_DISABLE, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PULL_DISABLE, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PULL_DISABLE, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PULL_DISABLE, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PULL_DISABLE, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PULL_DISABLE, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PULL_DISABLE, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PULL_DISABLE, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PULL_DISABLE, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PULL_DISABLE, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PULL_DISABLE, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PULL_DISABLE, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PULL_DISABLE, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PULL_DISABLE, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PULL_DISABLE, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PULL_DISABLE, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_INPUT_PULLDOWN, MUX_MODE7)
                >;
        };
 
 
        user_leds_s0: user_leds_s0 {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x810, PIN_OUTPUT_PULLDOWN | MUX_MODE7)    /* gpmc_ad4.gpio1_4 */
-                       AM33XX_IOPAD(0x814, PIN_OUTPUT_PULLDOWN | MUX_MODE7)    /* gpmc_ad5.gpio1_5 */
-                       AM33XX_IOPAD(0x818, PIN_OUTPUT_PULLDOWN | MUX_MODE7)    /* gpmc_ad6.gpio1_6 */
-                       AM33XX_IOPAD(0x81c, PIN_OUTPUT_PULLDOWN | MUX_MODE7)    /* gpmc_ad7.gpio1_7 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_OUTPUT_PULLDOWN, MUX_MODE7)     /* gpmc_ad4.gpio1_4 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_OUTPUT_PULLDOWN, MUX_MODE7)     /* gpmc_ad5.gpio1_5 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_OUTPUT_PULLDOWN, MUX_MODE7)     /* gpmc_ad6.gpio1_6 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_OUTPUT_PULLDOWN, MUX_MODE7)     /* gpmc_ad7.gpio1_7 */
                >;
        };
 
        gpio_keys_s0: gpio_keys_s0 {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x894, PIN_INPUT_PULLDOWN | MUX_MODE7)     /* gpmc_oen_ren.gpio2_3 */
-                       AM33XX_IOPAD(0x890, PIN_INPUT_PULLDOWN | MUX_MODE7)     /* gpmc_advn_ale.gpio2_2 */
-                       AM33XX_IOPAD(0x870, PIN_INPUT_PULLDOWN | MUX_MODE7)     /* gpmc_wait0.gpio0_30 */
-                       AM33XX_IOPAD(0x89c, PIN_INPUT_PULLDOWN | MUX_MODE7)     /* gpmc_ben0_cle.gpio2_5 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_INPUT_PULLDOWN, MUX_MODE7)  /* gpmc_oen_ren.gpio2_3 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_advn_ale.gpio2_2 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLDOWN, MUX_MODE7)    /* gpmc_wait0.gpio0_30 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_BEN0_CLE, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_ben0_cle.gpio2_5 */
                >;
        };
 
        i2c0_pins: pinmux_i2c0_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x988, PIN_INPUT_PULLUP | MUX_MODE0)       /* i2c0_sda.i2c0_sda */
-                       AM33XX_IOPAD(0x98c, PIN_INPUT_PULLUP | MUX_MODE0)       /* i2c0_scl.i2c0_scl */
+                       AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0)
                >;
        };
 
        uart0_pins: pinmux_uart0_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0)       /* uart0_rxd.uart0_rxd */
-                       AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0)    /* uart0_txd.uart0_txd */
+                       AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
                >;
        };
 
        clkout2_pin: pinmux_clkout2_pin {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x9b4, PIN_OUTPUT_PULLDOWN | MUX_MODE3)    /* xdma_event_intr1.clkout2 */
+                       AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR1, PIN_OUTPUT_PULLDOWN, MUX_MODE3)     /* xdma_event_intr1.clkout2 */
                >;
        };
 
        ecap2_pins: backlight_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x99c, MUX_MODE4)  /* mcasp0_ahclkr.ecap2_in_pwm2_out */
+                       AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKR, 0x0, MUX_MODE4)        /* mcasp0_ahclkr.ecap2_in_pwm2_out */
                >;
        };
 
        cpsw_default: cpsw_default {
                pinctrl-single,pins = <
                        /* Slave 1 */
-                       AM33XX_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE2)    /* mii1_txen.rgmii1_tctl */
-                       AM33XX_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE2)     /* mii1_rxdv.rgmii1_rctl */
-                       AM33XX_IOPAD(0x91c, PIN_OUTPUT_PULLDOWN | MUX_MODE2)    /* mii1_txd3.rgmii1_td3 */
-                       AM33XX_IOPAD(0x920, PIN_OUTPUT_PULLDOWN | MUX_MODE2)    /* mii1_txd2.rgmii1_td2 */
-                       AM33XX_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE2)    /* mii1_txd1.rgmii1_td1 */
-                       AM33XX_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE2)    /* mii1_txd0.rgmii1_td0 */
-                       AM33XX_IOPAD(0x92c, PIN_OUTPUT_PULLDOWN | MUX_MODE2)    /* mii1_txclk.rgmii1_tclk */
-                       AM33XX_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE2)     /* mii1_rxclk.rgmii1_rclk */
-                       AM33XX_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE2)     /* mii1_rxd3.rgmii1_rd3 */
-                       AM33XX_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE2)     /* mii1_rxd2.rgmii1_rd2 */
-                       AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE2)     /* mii1_rxd1.rgmii1_rd1 */
-                       AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE2)     /* mii1_rxd0.rgmii1_rd0 */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE2)   /* mii1_txen.rgmii1_tctl */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE2)    /* mii1_rxdv.rgmii1_rctl */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT_PULLDOWN, MUX_MODE2)    /* mii1_txd3.rgmii1_td3 */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE2)    /* mii1_txd2.rgmii1_td2 */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE2)    /* mii1_txd1.rgmii1_td1 */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE2)    /* mii1_txd0.rgmii1_td0 */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE2)  /* mii1_txclk.rgmii1_tclk */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE2)   /* mii1_rxclk.rgmii1_rclk */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE2)     /* mii1_rxd3.rgmii1_rd3 */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE2)     /* mii1_rxd2.rgmii1_rd2 */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE2)     /* mii1_rxd1.rgmii1_rd1 */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE2)     /* mii1_rxd0.rgmii1_rd0 */
 
                        /* Slave 2 */
-                       AM33XX_IOPAD(0x840, PIN_OUTPUT_PULLDOWN | MUX_MODE2)    /* gpmc_a0.rgmii2_tctl */
-                       AM33XX_IOPAD(0x844, PIN_INPUT_PULLDOWN | MUX_MODE2)     /* gpmc_a1.rgmii2_rctl */
-                       AM33XX_IOPAD(0x848, PIN_OUTPUT_PULLDOWN | MUX_MODE2)    /* gpmc_a2.rgmii2_td3 */
-                       AM33XX_IOPAD(0x84c, PIN_OUTPUT_PULLDOWN | MUX_MODE2)    /* gpmc_a3.rgmii2_td2 */
-                       AM33XX_IOPAD(0x850, PIN_OUTPUT_PULLDOWN | MUX_MODE2)    /* gpmc_a4.rgmii2_td1 */
-                       AM33XX_IOPAD(0x854, PIN_OUTPUT_PULLDOWN | MUX_MODE2)    /* gpmc_a5.rgmii2_td0 */
-                       AM33XX_IOPAD(0x858, PIN_OUTPUT_PULLDOWN | MUX_MODE2)    /* gpmc_a6.rgmii2_tclk */
-                       AM33XX_IOPAD(0x85c, PIN_INPUT_PULLDOWN | MUX_MODE2)     /* gpmc_a7.rgmii2_rclk */
-                       AM33XX_IOPAD(0x860, PIN_INPUT_PULLDOWN | MUX_MODE2)     /* gpmc_a8.rgmii2_rd3 */
-                       AM33XX_IOPAD(0x864, PIN_INPUT_PULLDOWN | MUX_MODE2)     /* gpmc_a9.rgmii2_rd2 */
-                       AM33XX_IOPAD(0x868, PIN_INPUT_PULLDOWN | MUX_MODE2)     /* gpmc_a10.rgmii2_rd1 */
-                       AM33XX_IOPAD(0x86c, PIN_INPUT_PULLDOWN | MUX_MODE2)     /* gpmc_a11.rgmii2_rd0 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT_PULLDOWN, MUX_MODE2)      /* gpmc_a0.rgmii2_tctl */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLDOWN, MUX_MODE2)       /* gpmc_a1.rgmii2_rctl */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_OUTPUT_PULLDOWN, MUX_MODE2)      /* gpmc_a2.rgmii2_td3 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_OUTPUT_PULLDOWN, MUX_MODE2)      /* gpmc_a3.rgmii2_td2 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT_PULLDOWN, MUX_MODE2)      /* gpmc_a4.rgmii2_td1 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT_PULLDOWN, MUX_MODE2)      /* gpmc_a5.rgmii2_td0 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_OUTPUT_PULLDOWN, MUX_MODE2)      /* gpmc_a6.rgmii2_tclk */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_INPUT_PULLDOWN, MUX_MODE2)       /* gpmc_a7.rgmii2_rclk */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_INPUT_PULLDOWN, MUX_MODE2)       /* gpmc_a8.rgmii2_rd3 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLDOWN, MUX_MODE2)       /* gpmc_a9.rgmii2_rd2 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE2)      /* gpmc_a10.rgmii2_rd1 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE2)      /* gpmc_a11.rgmii2_rd0 */
                >;
        };
 
        cpsw_sleep: cpsw_sleep {
                pinctrl-single,pins = <
                        /* Slave 1 reset value */
-                       AM33XX_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x91c, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x920, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x92c, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7)
 
                        /* Slave 2 reset value*/
-                       AM33XX_IOPAD(0x840, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x844, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x848, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x84c, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x850, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x854, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x858, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x85c, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x860, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x864, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x868, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x86c, PIN_INPUT_PULLDOWN | MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE7)
                >;
        };
 
        davinci_mdio_default: davinci_mdio_default {
                pinctrl-single,pins = <
                        /* MDIO */
-                       AM33XX_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)       /* mdio_data.mdio_data */
-                       AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0)                      /* mdio_clk.mdio_clk */
+                       AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0)
                >;
        };
 
        davinci_mdio_sleep: davinci_mdio_sleep {
                pinctrl-single,pins = <
                        /* MDIO reset value */
-                       AM33XX_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7)
                >;
        };
 
        mmc1_pins: pinmux_mmc1_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x960, PIN_INPUT | MUX_MODE7)              /* spi0_cs1.gpio0_6 */
-                       AM33XX_IOPAD(0x8fc, PIN_INPUT_PULLUP | MUX_MODE0)       /* mmc0_dat0.mmc0_dat0 */
-                       AM33XX_IOPAD(0x8f8, PIN_INPUT_PULLUP | MUX_MODE0)       /* mmc0_dat1.mmc0_dat1 */
-                       AM33XX_IOPAD(0x8f4, PIN_INPUT_PULLUP | MUX_MODE0)       /* mmc0_dat2.mmc0_dat2 */
-                       AM33XX_IOPAD(0x8f0, PIN_INPUT_PULLUP | MUX_MODE0)       /* mmc0_dat3.mmc0_dat3 */
-                       AM33XX_IOPAD(0x904, PIN_INPUT_PULLUP | MUX_MODE0)       /* mmc0_cmd.mmc0_cmd */
-                       AM33XX_IOPAD(0x900, PIN_INPUT_PULLUP | MUX_MODE0)       /* mmc0_clk.mmc0_clk */
-                       AM33XX_IOPAD(0x9a0, PIN_INPUT | MUX_MODE4)              /* mcasp0_aclkr.mmc0_sdwp */
+                       AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT, MUX_MODE7)               /* spi0_cs1.gpio0_6 */
+                       AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKR, PIN_INPUT, MUX_MODE4)           /* mcasp0_aclkr.mmc0_sdwp */
                >;
        };
 
        mcasp1_pins: mcasp1_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_crs.mcasp1_aclkx */
-                       AM33XX_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_rxerr.mcasp1_fsx */
-                       AM33XX_IOPAD(0x908, PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* mii1_col.mcasp1_axr2 */
-                       AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE4) /* mii1_crs.mcasp1_aclkx */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE4) /* mii1_rxerr.mcasp1_fsx */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_OUTPUT_PULLDOWN, MUX_MODE4) /* mii1_col.mcasp1_axr2 */
+                       AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */
                >;
        };
 
        mcasp1_pins_sleep: mcasp1_pins_sleep {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x908, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7)
                >;
        };
 
        mmc2_pins: pinmux_mmc2_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x874, PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpio0_31 */
-                       AM33XX_IOPAD(0x880, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn1.mmc1_clk */
-                       AM33XX_IOPAD(0x884, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn2.mmc1_cmd */
-                       AM33XX_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */
-                       AM33XX_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */
-                       AM33XX_IOPAD(0x808, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */
-                       AM33XX_IOPAD(0x80c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLUP, MUX_MODE7) /* gpmc_wpn.gpio0_31 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn1.mmc1_clk */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn2.mmc1_cmd */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */
                >;
        };
 
        wl12xx_gpio: pinmux_wl12xx_gpio {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x87c, PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_csn0.gpio1_29 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_OUTPUT_PULLUP, MUX_MODE7) /* gpmc_csn0.gpio1_29 */
                >;
        };
 };

diff --git a/arch/arm/boot/dts/am335x-icev2.dts b/arch/arm/boot/dts/am335x-icev2.dts
index 9ac775c..4365684 100644 (file)
--- a/arch/arm/boot/dts/am335x-icev2.dts
+++ b/arch/arm/boot/dts/am335x-icev2.dts
@@ -157,111 +157,111 @@
 &am33xx_pinmux {
        user_leds: user_leds {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x91c, PIN_OUTPUT | MUX_MODE7) /* (J18) gmii1_txd3.gpio0[16] */
-                       AM33XX_IOPAD(0x920, PIN_OUTPUT | MUX_MODE7) /* (K15) gmii1_txd2.gpio0[17] */
-                       AM33XX_IOPAD(0x9b0, PIN_OUTPUT | MUX_MODE7) /* (A15) xdma_event_intr0.gpio0[19] */
-                       AM33XX_IOPAD(0x9b4, PIN_OUTPUT | MUX_MODE7) /* (D14) xdma_event_intr1.gpio0[20] */
-                       AM33XX_IOPAD(0x880, PIN_OUTPUT | MUX_MODE7) /* (U9) gpmc_csn1.gpio1[30] */
-                       AM33XX_IOPAD(0x92c, PIN_OUTPUT | MUX_MODE7) /* (K18) gmii1_txclk.gpio3[9] */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT, MUX_MODE7) /* (J18) gmii1_txd3.gpio0[16] */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT, MUX_MODE7) /* (K15) gmii1_txd2.gpio0[17] */
+                       AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_OUTPUT, MUX_MODE7) /* (A15) xdma_event_intr0.gpio0[19] */
+                       AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR1, PIN_OUTPUT, MUX_MODE7) /* (D14) xdma_event_intr1.gpio0[20] */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_OUTPUT, MUX_MODE7) /* (U9) gpmc_csn1.gpio1[30] */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_OUTPUT, MUX_MODE7) /* (K18) gmii1_txclk.gpio3[9] */
                >;
        };
 
        mmc0_pins_default: mmc0_pins_default {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x8f0, PIN_INPUT_PULLUP | MUX_MODE0) /* (F17) mmc0_dat3.mmc0_dat3 */
-                       AM33XX_IOPAD(0x8f4, PIN_INPUT_PULLUP | MUX_MODE0) /* (F18) mmc0_dat2.mmc0_dat2 */
-                       AM33XX_IOPAD(0x8f8, PIN_INPUT_PULLUP | MUX_MODE0) /* (G15) mmc0_dat1.mmc0_dat1 */
-                       AM33XX_IOPAD(0x8fc, PIN_INPUT_PULLUP | MUX_MODE0) /* (G16) mmc0_dat0.mmc0_dat0 */
-                       AM33XX_IOPAD(0x900, PIN_INPUT_PULLUP | MUX_MODE0) /* (G17) mmc0_clk.mmc0_clk */
-                       AM33XX_IOPAD(0x904, PIN_INPUT_PULLUP | MUX_MODE0) /* (G18) mmc0_cmd.mmc0_cmd */
+                       AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0)
                >;
        };
 
        i2c0_pins_default: i2c0_pins_default {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x988, PIN_INPUT | MUX_MODE0) /* (C17) I2C0_SDA.I2C0_SDA */
-                       AM33XX_IOPAD(0x98c, PIN_INPUT | MUX_MODE0) /* (C16) I2C0_SCL.I2C0_SCL */
+                       AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT, MUX_MODE0)
                >;
        };
 
        spi0_pins_default: spi0_pins_default {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x950, PIN_INPUT_PULLUP | MUX_MODE0) /* (A17) spi0_sclk.spi0_sclk */
-                       AM33XX_IOPAD(0x954, PIN_INPUT_PULLUP | MUX_MODE0) /* (B17) spi0_d0.spi0_d0 */
-                       AM33XX_IOPAD(0x958, PIN_INPUT_PULLUP | MUX_MODE0) /* (B16) spi0_d1.spi0_d1 */
-                       AM33XX_IOPAD(0x95c, PIN_INPUT_PULLUP | MUX_MODE0) /* (A16) spi0_cs0.spi0_cs0 */
-                       AM33XX_IOPAD(0x960, PIN_INPUT_PULLUP | MUX_MODE0) /* (C15) spi0_cs1.spi0_cs1 */
-                       AM33XX_IOPAD(0x9a0, PIN_INPUT_PULLUP | MUX_MODE7) /* (B12) mcasp0_aclkr.gpio3[18] */
+                       AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKR, PIN_INPUT_PULLUP, MUX_MODE7) /* (B12) mcasp0_aclkr.gpio3[18] */
                >;
        };
 
        uart3_pins_default: uart3_pins_default {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x934, PIN_INPUT_PULLUP | MUX_MODE1) /* (L17) gmii1_rxd3.uart3_rxd */
-                       AM33XX_IOPAD(0x938, PIN_OUTPUT_PULLUP | MUX_MODE1) /* (L16) gmii1_rxd2.uart3_txd */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLUP, MUX_MODE1) /* (L17) gmii1_rxd3.uart3_rxd */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_OUTPUT_PULLUP, MUX_MODE1) /* (L16) gmii1_rxd2.uart3_txd */
                >;
        };
 
        cpsw_default: cpsw_default {
                pinctrl-single,pins = <
                        /* Slave 1, RMII mode */
-                       AM33XX_IOPAD(0x90c, (PIN_INPUT_PULLUP | MUX_MODE1))     /* mii1_crs.rmii1_crs_dv */
-                       AM33XX_IOPAD(0x944, (PIN_INPUT_PULLUP | MUX_MODE0))     /* rmii1_refclk.rmii1_refclk */
-                       AM33XX_IOPAD(0x940, (PIN_INPUT_PULLUP | MUX_MODE1))     /* mii1_rxd0.rmii1_rxd0 */
-                       AM33XX_IOPAD(0x93c, (PIN_INPUT_PULLUP | MUX_MODE1))     /* mii1_rxd1.rmii1_rxd1 */
-                       AM33XX_IOPAD(0x910, (PIN_INPUT_PULLUP | MUX_MODE1))     /* mii1_rxerr.rmii1_rxerr */
-                       AM33XX_IOPAD(0x928, (PIN_OUTPUT_PULLDOWN | MUX_MODE1))  /* mii1_txd0.rmii1_txd0 */
-                       AM33XX_IOPAD(0x924, (PIN_OUTPUT_PULLDOWN | MUX_MODE1))  /* mii1_txd1.rmii1_txd1 */
-                       AM33XX_IOPAD(0x914, (PIN_OUTPUT_PULLDOWN | MUX_MODE1))  /* mii1_txen.rmii1_txen */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLUP, MUX_MODE1)        /* mii1_crs.rmii1_crs_dv */
+                       AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLUP, MUX_MODE1)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLUP, MUX_MODE1)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLUP, MUX_MODE1)      /* mii1_rxerr.rmii1_rxerr */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE1)    /* mii1_txd0.rmii1_txd0 */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE1)    /* mii1_txd1.rmii1_txd1 */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE1)   /* mii1_txen.rmii1_txen */
                        /* Slave 2, RMII mode */
-                       AM33XX_IOPAD(0x870, (PIN_INPUT_PULLUP | MUX_MODE3))     /* gpmc_wait0.rmii2_crs_dv */
-                       AM33XX_IOPAD(0x908, (PIN_INPUT_PULLUP | MUX_MODE1))     /* mii1_col.rmii2_refclk */
-                       AM33XX_IOPAD(0x86c, (PIN_INPUT_PULLUP | MUX_MODE3))     /* gpmc_a11.rmii2_rxd0 */
-                       AM33XX_IOPAD(0x868, (PIN_INPUT_PULLUP | MUX_MODE3))     /* gpmc_a10.rmii2_rxd1 */
-                       AM33XX_IOPAD(0x874, (PIN_INPUT_PULLUP | MUX_MODE3))     /* gpmc_wpn.rmii2_rxerr */
-                       AM33XX_IOPAD(0x854, (PIN_OUTPUT_PULLDOWN | MUX_MODE3))  /* gpmc_a5.rmii2_txd0 */
-                       AM33XX_IOPAD(0x850, (PIN_OUTPUT_PULLDOWN | MUX_MODE3))  /* gpmc_a4.rmii2_txd1 */
-                       AM33XX_IOPAD(0x840, (PIN_OUTPUT_PULLDOWN | MUX_MODE3))  /* gpmc_a0.rmii2_txen */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE3)      /* gpmc_wait0.rmii2_crs_dv */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT_PULLUP, MUX_MODE1)        /* mii1_col.rmii2_refclk */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLUP, MUX_MODE3)        /* gpmc_a11.rmii2_rxd0 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLUP, MUX_MODE3)        /* gpmc_a10.rmii2_rxd1 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLUP, MUX_MODE3)        /* gpmc_wpn.rmii2_rxerr */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT_PULLDOWN, MUX_MODE3)      /* gpmc_a5.rmii2_txd0 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT_PULLDOWN, MUX_MODE3)      /* gpmc_a4.rmii2_txd1 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT_PULLDOWN, MUX_MODE3)      /* gpmc_a0.rmii2_txen */
                >;
        };
 
        cpsw_sleep: cpsw_sleep {
                pinctrl-single,pins = <
                        /* Slave 1 reset value */
-                       AM33XX_IOPAD(0x90c, (PIN_INPUT_PULLDOWN | MUX_MODE7))
-                       AM33XX_IOPAD(0x944, (PIN_INPUT_PULLDOWN | MUX_MODE7))
-                       AM33XX_IOPAD(0x940, (PIN_INPUT_PULLDOWN | MUX_MODE7))
-                       AM33XX_IOPAD(0x93c, (PIN_INPUT_PULLDOWN | MUX_MODE7))
-                       AM33XX_IOPAD(0x910, (PIN_INPUT_PULLDOWN | MUX_MODE7))
-                       AM33XX_IOPAD(0x928, (PIN_INPUT_PULLDOWN | MUX_MODE7))
-                       AM33XX_IOPAD(0x924, (PIN_INPUT_PULLDOWN | MUX_MODE7))
-                       AM33XX_IOPAD(0x914, (PIN_INPUT_PULLDOWN | MUX_MODE7))
+                       AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7)
 
                        /* Slave 2 reset value */
-                       AM33XX_IOPAD(0x870, (PIN_INPUT_PULLDOWN | MUX_MODE7))
-                       AM33XX_IOPAD(0x908, (PIN_INPUT_PULLDOWN | MUX_MODE7))
-                       AM33XX_IOPAD(0x86c, (PIN_INPUT_PULLDOWN | MUX_MODE7))
-                       AM33XX_IOPAD(0x868, (PIN_INPUT_PULLDOWN | MUX_MODE7))
-                       AM33XX_IOPAD(0x874, (PIN_INPUT_PULLDOWN | MUX_MODE7))
-                       AM33XX_IOPAD(0x854, (PIN_INPUT_PULLDOWN | MUX_MODE7))
-                       AM33XX_IOPAD(0x850, (PIN_INPUT_PULLDOWN | MUX_MODE7))
-                       AM33XX_IOPAD(0x840, (PIN_INPUT_PULLDOWN | MUX_MODE7))
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_INPUT_PULLDOWN, MUX_MODE7)
                >;
        };
 
        davinci_mdio_default: davinci_mdio_default {
                pinctrl-single,pins = <
                        /* MDIO */
-                       AM33XX_IOPAD(0x948, (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0))     /* mdio_data.mdio_data */
-                       AM33XX_IOPAD(0x94c, (PIN_OUTPUT_PULLUP | MUX_MODE0))                    /* mdio_clk.mdio_clk */
+                       AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0)
                >;
        };
 
        davinci_mdio_sleep: davinci_mdio_sleep {
                pinctrl-single,pins = <
                        /* MDIO reset value */
-                       AM33XX_IOPAD(0x948, (PIN_INPUT_PULLDOWN | MUX_MODE7))
-                       AM33XX_IOPAD(0x94c, (PIN_INPUT_PULLDOWN | MUX_MODE7))
+                       AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7)
                >;
        };
 };

diff --git a/arch/arm/boot/dts/am335x-igep0033.dtsi b/arch/arm/boot/dts/am335x-igep0033.dtsi
index cbd22f2..312deb6 100644 (file)
--- a/arch/arm/boot/dts/am335x-igep0033.dtsi
+++ b/arch/arm/boot/dts/am335x-igep0033.dtsi
@@ -57,41 +57,41 @@
 &am33xx_pinmux {
        i2c0_pins: pinmux_i2c0_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x988, PIN_INPUT_PULLUP | MUX_MODE0)       /* i2c0_sda.i2c0_sda */
-                       AM33XX_IOPAD(0x98c, PIN_INPUT_PULLUP | MUX_MODE0)       /* i2c0_scl.i2c0_scl */
+                       AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0)
                >;
        };
 
        nandflash_pins: pinmux_nandflash_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE0)       /* gpmc_ad0.gpmc_ad0 */
-                       AM33XX_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE0)       /* gpmc_ad1.gpmc_ad1 */
-                       AM33XX_IOPAD(0x808, PIN_INPUT_PULLUP | MUX_MODE0)       /* gpmc_ad2.gpmc_ad2 */
-                       AM33XX_IOPAD(0x80c, PIN_INPUT_PULLUP | MUX_MODE0)       /* gpmc_ad3.gpmc_ad3 */
-                       AM33XX_IOPAD(0x810, PIN_INPUT_PULLUP | MUX_MODE0)       /* gpmc_ad4.gpmc_ad4 */
-                       AM33XX_IOPAD(0x814, PIN_INPUT_PULLUP | MUX_MODE0)       /* gpmc_ad5.gpmc_ad5 */
-                       AM33XX_IOPAD(0x818, PIN_INPUT_PULLUP | MUX_MODE0)       /* gpmc_ad6.gpmc_ad6 */
-                       AM33XX_IOPAD(0x81c, PIN_INPUT_PULLUP | MUX_MODE0)       /* gpmc_ad7.gpmc_ad7 */
-                       AM33XX_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE0)       /* gpmc_wait0.gpmc_wait0 */
-                       AM33XX_IOPAD(0x874, PIN_INPUT_PULLUP | MUX_MODE7)       /* gpmc_wpn.gpio0_30 */
-                       AM33XX_IOPAD(0x87c, PIN_OUTPUT | MUX_MODE0)             /* gpmc_csn0.gpmc_csn0 */
-                       AM33XX_IOPAD(0x890, PIN_OUTPUT | MUX_MODE0)             /* gpmc_advn_ale.gpmc_advn_ale */
-                       AM33XX_IOPAD(0x894, PIN_OUTPUT | MUX_MODE0)             /* gpmc_oen_ren.gpmc_oen_ren */
-                       AM33XX_IOPAD(0x898, PIN_OUTPUT | MUX_MODE0)             /* gpmc_wen.gpmc_wen */
-                       AM33XX_IOPAD(0x89c, PIN_OUTPUT | MUX_MODE0)             /* gpmc_be0n_cle.gpmc_be0n_cle */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLUP, MUX_MODE7)        /* gpmc_wpn.gpio0_30 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_WEN, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_BEN0_CLE, PIN_OUTPUT, MUX_MODE0)
                >;
        };
 
        uart0_pins: pinmux_uart0_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0)       /* uart0_rxd.uart0_rxd */
-                       AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0)    /* uart0_txd.uart0_txd */
+                       AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
                >;
        };
 
        leds_pins: pinmux_leds_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x85c, PIN_OUTPUT_PULLDOWN | MUX_MODE7)    /* gpmc_a7.gpio1_23 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_OUTPUT_PULLDOWN, MUX_MODE7)      /* gpmc_a7.gpio1_23 */
                >;
        };
 };

diff --git a/arch/arm/boot/dts/am335x-lxm.dts b/arch/arm/boot/dts/am335x-lxm.dts
index d0e8e72..aa4cd2b 100644 (file)
--- a/arch/arm/boot/dts/am335x-lxm.dts
+++ b/arch/arm/boot/dts/am335x-lxm.dts
@@ -46,109 +46,109 @@
 &am33xx_pinmux {
        mmc1_pins: pinmux_mmc1_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x8f0, PIN_INPUT_PULLUP | MUX_MODE0)       /* mmc0_dat3 */
-                       AM33XX_IOPAD(0x8f4, PIN_INPUT_PULLUP | MUX_MODE0)       /* mmc0_dat2 */
-                       AM33XX_IOPAD(0x8f8, PIN_INPUT_PULLUP | MUX_MODE0)       /* mmc0_dat1 */
-                       AM33XX_IOPAD(0x8fc, PIN_INPUT_PULLUP | MUX_MODE0)       /* mmc0_dat0 */
-                       AM33XX_IOPAD(0x900, PIN_INPUT_PULLUP | MUX_MODE0)       /* mmc0_clk */
-                       AM33XX_IOPAD(0x904, PIN_INPUT_PULLUP | MUX_MODE0)       /* mmc0_cmd */
+                       AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0)
                >;
        };
 
        i2c0_pins: pinmux_i2c0_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x988, PIN_INPUT | MUX_MODE0)      /* i2c0_sda.i2c0_sda */
-                       AM33XX_IOPAD(0x98c, PIN_INPUT | MUX_MODE0)      /* i2c0_scl.i2c0_scl */
+                       AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT, MUX_MODE0)
                >;
        };
 
        cpsw_default: cpsw_default {
                pinctrl-single,pins = <
                        /* Slave 1 */
-                       AM33XX_IOPAD(0x864, PIN_INPUT_PULLDOWN | MUX_MODE7)     /* rmii1_int */
-                       AM33XX_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE1)     /* rmii1_crs_dv */
-                       AM33XX_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE1)     /* rmii1_rxer */
-                       AM33XX_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE1)    /* rmii1_txen */
-                       AM33XX_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE1)    /* rmii1_td1 */
-                       AM33XX_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE1)    /* rmii1_td0 */
-                       AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE1)     /* rmii1_rd1 */
-                       AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE1)     /* rmii1_rd0 */
-                       AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE0)     /* rmii1_refclk */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLDOWN, MUX_MODE7)       /* rmii1_int */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE1)      /* rmii1_crs_dv */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE1)    /* rmii1_rxer */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE1)   /* rmii1_txen */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE1)    /* rmii1_td1 */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE1)    /* rmii1_td0 */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE1)     /* rmii1_rd1 */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE1)     /* rmii1_rd0 */
+                       AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE0)
 
                        /* Slave 2 */
-                       AM33XX_IOPAD(0x840, PIN_OUTPUT_PULLDOWN | MUX_MODE3)    /* rmii2_txen */
-                       AM33XX_IOPAD(0x850, PIN_OUTPUT_PULLDOWN | MUX_MODE3)    /* rmii2_td1 */
-                       AM33XX_IOPAD(0x854, PIN_OUTPUT_PULLDOWN | MUX_MODE3)    /* rmii2_td0 */
-                       AM33XX_IOPAD(0x868, PIN_INPUT_PULLDOWN | MUX_MODE3)     /* rmii2_rd1 */
-                       AM33XX_IOPAD(0x86c, PIN_INPUT_PULLDOWN | MUX_MODE3)     /* rmii2_rd0 */
-                       AM33XX_IOPAD(0x870, PIN_INPUT_PULLDOWN | MUX_MODE3)     /* rmii2_crs_dv */
-                       AM33XX_IOPAD(0x874, PIN_INPUT_PULLDOWN | MUX_MODE3)     /* rmii2_rxer */
-                       AM33XX_IOPAD(0x878, PIN_INPUT_PULLDOWN | MUX_MODE7)     /* rmii2_int */
-                       AM33XX_IOPAD(0x908, PIN_INPUT_PULLDOWN | MUX_MODE1)     /* rmii2_refclk */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT_PULLDOWN, MUX_MODE3)      /* rmii2_txen */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT_PULLDOWN, MUX_MODE3)      /* rmii2_td1 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT_PULLDOWN, MUX_MODE3)      /* rmii2_td0 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE3)      /* rmii2_rd1 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE3)      /* rmii2_rd0 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLDOWN, MUX_MODE3)    /* rmii2_crs_dv */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLDOWN, MUX_MODE3)      /* rmii2_rxer */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_BEN1, PIN_INPUT_PULLDOWN, MUX_MODE7)     /* rmii2_int */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT_PULLDOWN, MUX_MODE1)      /* rmii2_refclk */
                >;
        };
 
        cpsw_sleep: cpsw_sleep {
                pinctrl-single,pins = <
                        /* Slave 1 reset value */
-                       AM33XX_IOPAD(0x864, PIN_INPUT_PULLDOWN | MUX_MODE7)     /* rmii1_int */
-                       AM33XX_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE7)     /* rmii1_crs_dv */
-                       AM33XX_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE7)     /* rmii1_rxer */
-                       AM33XX_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7)     /* rmii1_txen */
-                       AM33XX_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7)     /* rmii1_td1 */
-                       AM33XX_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7)     /* rmii1_td0 */
-                       AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7)     /* rmii1_rd1 */
-                       AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7)     /* rmii1_rd0 */
-                       AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE7)     /* rmii1_refclk */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLDOWN, MUX_MODE7)       /* rmii1_int */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE7)      /* rmii1_crs_dv */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE7)    /* rmii1_rxer */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7)    /* rmii1_txen */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7)     /* rmii1_td1 */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7)     /* rmii1_td0 */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7)     /* rmii1_rd1 */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7)     /* rmii1_rd0 */
+                       AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii1_refclk */
 
                        /* Slave 2 reset value*/
-                       AM33XX_IOPAD(0x840, PIN_INPUT_PULLDOWN | MUX_MODE7)     /* rmii2_txen */
-                       AM33XX_IOPAD(0x850, PIN_INPUT_PULLDOWN | MUX_MODE7)     /* rmii2_td1 */
-                       AM33XX_IOPAD(0x854, PIN_INPUT_PULLDOWN | MUX_MODE7)     /* rmii2_td0 */
-                       AM33XX_IOPAD(0x868, PIN_INPUT_PULLDOWN | MUX_MODE7)     /* rmii2_rd1 */
-                       AM33XX_IOPAD(0x86c, PIN_INPUT_PULLDOWN | MUX_MODE7)     /* rmii2_rd0 */
-                       AM33XX_IOPAD(0x870, PIN_INPUT_PULLDOWN | MUX_MODE7)     /* rmii2_crs_dv */
-                       AM33XX_IOPAD(0x874, PIN_INPUT_PULLDOWN | MUX_MODE7)     /* rmii2_rxer */
-                       AM33XX_IOPAD(0x878, PIN_INPUT_PULLDOWN | MUX_MODE7)     /* rmii2_int */
-                       AM33XX_IOPAD(0x908, PIN_INPUT_PULLDOWN | MUX_MODE7)     /* rmii2_refclk */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_INPUT_PULLDOWN, MUX_MODE7)       /* rmii2_txen */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_INPUT_PULLDOWN, MUX_MODE7)       /* rmii2_td1 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_INPUT_PULLDOWN, MUX_MODE7)       /* rmii2_td0 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE7)      /* rmii2_rd1 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE7)      /* rmii2_rd0 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLDOWN, MUX_MODE7)    /* rmii2_crs_dv */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLDOWN, MUX_MODE7)      /* rmii2_rxer */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_BEN1, PIN_INPUT_PULLDOWN, MUX_MODE7)     /* rmii2_int */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT_PULLDOWN, MUX_MODE7)      /* rmii2_refclk */
                >;
        };
 
        davinci_mdio_default: davinci_mdio_default {
                pinctrl-single,pins = <
                        /* MDIO */
-                       AM33XX_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)       /* mdio_data.mdio_data */
-                       AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0)                      /* mdio_clk.mdio_clk */
+                       AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0)
                >;
        };
 
        davinci_mdio_sleep: davinci_mdio_sleep {
                pinctrl-single,pins = <
                        /* MDIO reset value */
-                       AM33XX_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7)
                >;
        };
 
        emmc_pins: pinmux_emmc_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x880, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn1.mmc1_clk */
-                       AM33XX_IOPAD(0x884, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn2.mmc1_cmd */
-                       AM33XX_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */
-                       AM33XX_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */
-                       AM33XX_IOPAD(0x808, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */
-                       AM33XX_IOPAD(0x80c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */
-                       AM33XX_IOPAD(0x810, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad4.mmc1_dat4 */
-                       AM33XX_IOPAD(0x814, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad5.mmc1_dat5 */
-                       AM33XX_IOPAD(0x818, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad6.mmc1_dat6 */
-                       AM33XX_IOPAD(0x81c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn1.mmc1_clk */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn2.mmc1_cmd */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad4.mmc1_dat4 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad5.mmc1_dat5 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad6.mmc1_dat6 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */
                >;
        };
 
        uart0_pins: pinmux_uart0_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0)       /* uart0_rxd.uart0_rxd */
-                       AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0)    /* uart0_txd.uart0_txd */
+                       AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
                >;
        };
 };

diff --git a/arch/arm/boot/dts/am335x-moxa-uc-2100-common.dtsi b/arch/arm/boot/dts/am335x-moxa-uc-2100-common.dtsi
index cb5913a..671d4a5 100644 (file)
--- a/arch/arm/boot/dts/am335x-moxa-uc-2100-common.dtsi
+++ b/arch/arm/boot/dts/am335x-moxa-uc-2100-common.dtsi
@@ -33,54 +33,54 @@
 
        i2c0_pins: pinmux_i2c0_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x988, PIN_INPUT_PULLUP | MUX_MODE0)       /* i2c0_sda.i2c0_sda */
-                       AM33XX_IOPAD(0x98c, PIN_INPUT_PULLUP | MUX_MODE0)       /* i2c0_scl.i2c0_scl */
+                       AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0)
                >;
        };
 
        push_button_pins: pinmux_push_button {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x8e4, PIN_INPUT_PULLDOWN | MUX_MODE7)     /* lcd_hsync.gpio2_23 */
+                       AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_INPUT_PULLDOWN, MUX_MODE7)     /* lcd_hsync.gpio2_23 */
                >;
        };
 
        uart0_pins: pinmux_uart0_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0)       /* uart0_rxd.uart0_rxd */
-                       AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0)    /* uart0_txd.uart0_txd */
+                       AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
                >;
        };
 
        davinci_mdio_default: davinci_mdio_default {
                pinctrl-single,pins = <
                        /* MDIO */
-                       AM33XX_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)       /* mdio_data.mdio_data */
-                       AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0)                      /* mdio_clk.mdio_clk */
+                       AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0)
                >;
        };
 
        mmc1_pins_default: pinmux_mmc1_pins {
                pinctrl-single,pins = <
                        /* eMMC */
-                       AM33XX_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE1)       /* gpmc_ad12.mmc1_dat0 */
-                       AM33XX_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE1)       /* gpmc_ad13.mmc1_dat1 */
-                       AM33XX_IOPAD(0x808, PIN_INPUT_PULLUP | MUX_MODE1)       /* gpmc_ad14.mmc1_dat2 */
-                       AM33XX_IOPAD(0x80c, PIN_INPUT_PULLUP | MUX_MODE1)       /* gpmc_ad15.mmc1_dat3 */
-                       AM33XX_IOPAD(0x810, PIN_INPUT_PULLUP | MUX_MODE1)       /* gpmc_ad8.mmc1_dat4 */
-                       AM33XX_IOPAD(0x814, PIN_INPUT_PULLUP | MUX_MODE1)       /* gpmc_ad9.mmc1_dat5 */
-                       AM33XX_IOPAD(0x818, PIN_INPUT_PULLUP | MUX_MODE1)       /* gpmc_ad10.mmc1_dat6 */
-                       AM33XX_IOPAD(0x81c, PIN_INPUT_PULLUP | MUX_MODE1)       /* gpmc_ad11.mmc1_dat7 */
-                       AM33XX_IOPAD(0x884, PIN_INPUT_PULLUP | MUX_MODE2)       /* gpmc_csn2.mmc1_cmd */
-                       AM33XX_IOPAD(0x880, PIN_INPUT_PULLUP | MUX_MODE2)       /* gpmc_csn1.mmc1_clk */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE1)        /* gpmc_ad12.mmc1_dat0 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE1)        /* gpmc_ad13.mmc1_dat1 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE1)        /* gpmc_ad14.mmc1_dat2 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE1)        /* gpmc_ad15.mmc1_dat3 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE1)        /* gpmc_ad8.mmc1_dat4 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE1)        /* gpmc_ad9.mmc1_dat5 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE1)        /* gpmc_ad10.mmc1_dat6 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE1)        /* gpmc_ad11.mmc1_dat7 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_INPUT_PULLUP, MUX_MODE2)       /* gpmc_csn2.mmc1_cmd */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_INPUT_PULLUP, MUX_MODE2)       /* gpmc_csn1.mmc1_clk */
                >;
        };
 
        spi0_pins: pinmux_spi0 {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x950, PIN_INPUT_PULLUP | MUX_MODE0)        /* spi0_sclk.spi0_sclk */
-                       AM33XX_IOPAD(0x95c, PIN_INPUT_PULLUP | MUX_MODE0)        /* spi0_cs0.spi0_cs0 */
-                       AM33XX_IOPAD(0x954, PIN_INPUT_PULLUP | MUX_MODE0)        /* spi0_d0.spi0_d0 */
-                       AM33XX_IOPAD(0x958, PIN_INPUT_PULLUP | MUX_MODE0)        /* spi0_d1.spi0_d1 */
+                       AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT_PULLUP, MUX_MODE0)
                >;
        };
 };

diff --git a/arch/arm/boot/dts/am335x-moxa-uc-2101.dts b/arch/arm/boot/dts/am335x-moxa-uc-2101.dts
index 48aee6d..5923b6e 100644 (file)
--- a/arch/arm/boot/dts/am335x-moxa-uc-2101.dts
+++ b/arch/arm/boot/dts/am335x-moxa-uc-2101.dts
@@ -31,23 +31,23 @@
        cpsw_default: cpsw_default {
                pinctrl-single,pins = <
                        /* Slave 1 */
-                       AM33XX_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE1)     /* mii1_crs.rmii1_crs_dv */
-                       AM33XX_IOPAD(0x910, PIN_INPUT_PULLUP | MUX_MODE1)       /* mii1_rxerr.rmii1_rxerr */
-                       AM33XX_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE1)    /* mii1_txen.rmii1_txen */
-                       AM33XX_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE1)    /* mii1_txd1.rmii1_txd1 */
-                       AM33XX_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE1)    /* mii1_txd0.rmii1_txd0 */
-                       AM33XX_IOPAD(0x93c, PIN_INPUT_PULLUP | MUX_MODE1)       /* mii1_rxd1.rmii1_rxd1 */
-                       AM33XX_IOPAD(0x940, PIN_INPUT_PULLUP | MUX_MODE1)       /* mii1_rxd0.rmii1_rxd0 */
-                       AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE0)     /* mii1_refclk.rmii1_refclk */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE1)      /* mii1_crs.rmii1_crs_dv */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLUP, MUX_MODE1)      /* mii1_rxerr.rmii1_rxerr */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE1)   /* mii1_txen.rmii1_txen */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE1)    /* mii1_txd1.rmii1_txd1 */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE1)    /* mii1_txd0.rmii1_txd0 */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLUP, MUX_MODE1)       /* mii1_rxd1.rmii1_rxd1 */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLUP, MUX_MODE1)       /* mii1_rxd0.rmii1_rxd0 */
+                       AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE0)
                >;
        };
 
        spi1_pins: pinmux_spi1 {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x964, PIN_INPUT_PULLUP | MUX_MODE4)        /* ecap0_in_pwm0_out.spi1_sclk */
-                       AM33XX_IOPAD(0x978, PIN_INPUT_PULLUP | MUX_MODE4)        /* uart1_ctsn.spi1_cs0 */
-                       AM33XX_IOPAD(0x968, PIN_INPUT_PULLUP | MUX_MODE4)        /* uart0_ctsn.spi1_d0 */
-                       AM33XX_IOPAD(0x96c, PIN_INPUT_PULLUP | MUX_MODE4)        /* uart0_rtsn.spi1_d1 */
+                       AM33XX_PADCONF(AM335X_PIN_ECAP0_IN_PWM0_OUT, PIN_INPUT_PULLUP, MUX_MODE4)        /* ecap0_in_pwm0_out.spi1_sclk */
+                       AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLUP, MUX_MODE4)       /* uart1_ctsn.spi1_cs0 */
+                       AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_INPUT_PULLUP, MUX_MODE4)       /* uart0_ctsn.spi1_d0 */
+                       AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT_PULLUP, MUX_MODE4)       /* uart0_rtsn.spi1_d1 */
                >;
        };
 };

diff --git a/arch/arm/boot/dts/am335x-moxa-uc-8100-me-t.dts b/arch/arm/boot/dts/am335x-moxa-uc-8100-me-t.dts
index e562ce4..5a2fb4b 100644 (file)
--- a/arch/arm/boot/dts/am335x-moxa-uc-8100-me-t.dts
+++ b/arch/arm/boot/dts/am335x-moxa-uc-8100-me-t.dts
@@ -104,79 +104,79 @@
 
        minipcie_pins: pinmux_minipcie {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x8e8, PIN_INPUT_PULLDOWN | MUX_MODE7)     /* lcd_pclk.gpio2_24 */
-                       AM33XX_IOPAD(0x8ec, PIN_INPUT_PULLDOWN | MUX_MODE7)     /* lcd_ac_bias_en.gpio2_25 */
-                       AM33XX_IOPAD(0x8e0, PIN_INPUT_PULLDOWN | MUX_MODE7)     /* lcd_vsync.gpio2_22  Power off PIN*/
+                       AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_INPUT_PULLDOWN, MUX_MODE7)      /* lcd_pclk.gpio2_24 */
+                       AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_INPUT_PULLDOWN, MUX_MODE7)        /* lcd_ac_bias_en.gpio2_25 */
+                       AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_INPUT_PULLDOWN, MUX_MODE7)     /* lcd_vsync.gpio2_22  Power off PIN*/
                >;
        };
 
        push_button_pins: pinmux_push_button {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x9ac, PIN_INPUT_PULLDOWN | MUX_MODE7)     /* mcasp0_ahcklx.gpio3_21 */
+                       AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKX, PIN_INPUT_PULLDOWN, MUX_MODE7) /* mcasp0_ahcklx.gpio3_21 */
                >;
        };
 
        i2c0_pins: pinmux_i2c0_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x988, PIN_INPUT_PULLUP | MUX_MODE0)    /* i2c0_sda.i2c0_sda */
-                       AM33XX_IOPAD(0x98c, PIN_INPUT_PULLUP | MUX_MODE0)    /* i2c0_scl.i2c0_scl */
+                       AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0)
                >;
        };
 
 
        i2c1_pins: pinmux_i2c1_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x968, PIN_INPUT_PULLUP | MUX_MODE3)       /* uart0_ctsn.i2c1_sda */
-                       AM33XX_IOPAD(0x96c, PIN_INPUT_PULLUP | MUX_MODE3)       /* uart0_rtsn.i2c1_scl */
+                       AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_INPUT_PULLUP, MUX_MODE3)      /* uart0_ctsn.i2c1_sda */
+                       AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT_PULLUP, MUX_MODE3)      /* uart0_rtsn.i2c1_scl */
                >;
        };
 
        uart0_pins: pinmux_uart0_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0)       /* uart0_rxd.uart0_rxd */
-                       AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0)    /* uart0_txd.uart0_txd */
+                       AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
                >;
        };
 
        uart1_pins: pinmux_uart1_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x978, PIN_INPUT | MUX_MODE0)              /* uart1_ctsn.uart1_ctsn */
-                       AM33XX_IOPAD(0x97C, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart1_rtsn.uart1_rtsn */
-                       AM33XX_IOPAD(0x980, PIN_INPUT_PULLUP | MUX_MODE0)    /* uart1_rxd.uart1_rxd */
-                       AM33XX_IOPAD(0x984, PIN_OUTPUT | MUX_MODE0)             /* uart1_txd.uart1_txd */
+                       AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT, MUX_MODE0)
                >;
        };
 
        uart2_pins: pinmux_uart2_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x8d8, PIN_INPUT | MUX_MODE6)              /* lcd_data14.uart5_ctsn */
-                       AM33XX_IOPAD(0x8dc, PIN_OUTPUT_PULLDOWN | MUX_MODE6)  /* lcd_data15.uart5_rtsn */
-                       AM33XX_IOPAD(0x8c4, PIN_INPUT_PULLUP | MUX_MODE4)     /* lcd_data9.uart5_rxd */
-                       AM33XX_IOPAD(0x8c0, PIN_OUTPUT | MUX_MODE4)             /* lcd_data8.uart5_txd */
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_INPUT, MUX_MODE6)             /* lcd_data14.uart5_ctsn */
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT_PULLDOWN, MUX_MODE6)  /* lcd_data15.uart5_rtsn */
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_INPUT_PULLUP, MUX_MODE4)     /* lcd_data9.uart5_rxd */
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE4)             /* lcd_data8.uart5_txd */
                >;
        };
 
        cpsw_default: cpsw_default {
                pinctrl-single,pins = <
                        /* Slave 1 */
-                       AM33XX_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE1)  /* mii1_crs.rmii1_crs_dv */
-                       AM33XX_IOPAD(0x910, PIN_INPUT_PULLUP | MUX_MODE1)    /* mii1_rxerr.rmii1_rxerr */
-                       AM33XX_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txen.rmii1_txen */
-                       AM33XX_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd1.rmii1_txd1 */
-                       AM33XX_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd0.rmii1_txd0 */
-                       AM33XX_IOPAD(0x93c, PIN_INPUT_PULLUP | MUX_MODE1)    /* mii1_rxd1.rmii1_rxd1 */
-                       AM33XX_IOPAD(0x940, PIN_INPUT_PULLUP | MUX_MODE1)    /* mii1_rxd0.rmii1_rxd0 */
-                       AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE0)  /* mii1_refclk.rmii1_refclk */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE1)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLUP, MUX_MODE1)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE1)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE1)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE1)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLUP, MUX_MODE1)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLUP, MUX_MODE1)
+                       AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE0)
 
                        /* Slave 2 */
-                       AM33XX_IOPAD(0x870, PIN_INPUT_PULLDOWN | MUX_MODE3)   /* rmii2_crs_dv */
-                       AM33XX_IOPAD(0x874, PIN_INPUT_PULLDOWN | MUX_MODE3)   /* rmii2_rxer */
-                       AM33XX_IOPAD(0x840, PIN_OUTPUT_PULLDOWN | MUX_MODE3)  /* rmii2_txen */
-                       AM33XX_IOPAD(0x850, PIN_OUTPUT_PULLDOWN | MUX_MODE3)  /* rmii2_td1 */
-                       AM33XX_IOPAD(0x854, PIN_OUTPUT_PULLDOWN | MUX_MODE3)  /* rmii2_td0 */
-                       AM33XX_IOPAD(0x868, PIN_INPUT_PULLDOWN | MUX_MODE3)   /* rmii2_rd1 */
-                       AM33XX_IOPAD(0x86c, PIN_INPUT_PULLDOWN | MUX_MODE3)   /* rmii2_rd0 */
-                       AM33XX_IOPAD(0x908, PIN_INPUT_PULLDOWN | MUX_MODE1)  /* rmii2_refclk */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLDOWN, MUX_MODE3)   /* rmii2_crs_dv */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLDOWN, MUX_MODE3)   /* rmii2_rxer */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT_PULLDOWN, MUX_MODE3)  /* rmii2_txen */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT_PULLDOWN, MUX_MODE3)  /* rmii2_td1 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT_PULLDOWN, MUX_MODE3)  /* rmii2_td0 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE3)   /* rmii2_rd1 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE3)   /* rmii2_rd0 */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT_PULLDOWN, MUX_MODE1)  /* rmii2_refclk */
 
                >;
        };
@@ -184,46 +184,46 @@
        davinci_mdio_default: davinci_mdio_default {
                pinctrl-single,pins = <
                        /* MDIO */
-                       AM33XX_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)       /* mdio_data.mdio_data */
-                       AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0)                      /* mdio_clk.mdio_clk */
+                       AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0)
                >;
        };
 
        mmc0_pins_default: pinmux_mmc0_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x8f0, PIN_INPUT_PULLUP | MUX_MODE0)       /* mmc0_dat3 */
-                       AM33XX_IOPAD(0x8f4, PIN_INPUT_PULLUP | MUX_MODE0)       /* mmc0_dat2 */
-                       AM33XX_IOPAD(0x8f8, PIN_INPUT_PULLUP | MUX_MODE0)       /* mmc0_dat1 */
-                       AM33XX_IOPAD(0x8fc, PIN_INPUT_PULLUP | MUX_MODE0)       /* mmc0_dat0 */
-                       AM33XX_IOPAD(0x900, PIN_INPUT_PULLUP | MUX_MODE0)       /* mmc0_clk */
-                       AM33XX_IOPAD(0x904, PIN_INPUT_PULLUP | MUX_MODE0)       /* mmc0_cmd */
-                       AM33XX_IOPAD(0x990, PIN_INPUT_PULLUP | MUX_MODE7)       /* mcasp0_aclkx.gpio3_14 */
-                       AM33XX_IOPAD(0x9a0, PIN_INPUT_PULLUP | MUX_MODE7)    /* mcasp0_aclkx.gpio3_18 */
+                       AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKX, PIN_INPUT_PULLUP, MUX_MODE7)    /* mcasp0_aclkx.gpio3_14 */
+                       AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKR, PIN_INPUT_PULLUP, MUX_MODE7)    /* mcasp0_aclkx.gpio3_18 */
                >;
        };
 
        mmc2_pins_default: pinmux_mmc2_pins {
                pinctrl-single,pins = <
                        /* eMMC */
-                       AM33XX_IOPAD(0x830, PIN_INPUT_PULLUP | MUX_MODE3)       /* gpmc_ad12.mmc2_dat0 */
-                       AM33XX_IOPAD(0x834, PIN_INPUT_PULLUP | MUX_MODE3)       /* gpmc_ad13.mmc2_dat1 */
-                       AM33XX_IOPAD(0x838, PIN_INPUT_PULLUP | MUX_MODE3)       /* gpmc_ad14.mmc2_dat2 */
-                       AM33XX_IOPAD(0x83c, PIN_INPUT_PULLUP | MUX_MODE3)       /* gpmc_ad15.mmc2_dat3 */
-                       AM33XX_IOPAD(0x820, PIN_INPUT_PULLUP | MUX_MODE3)       /* gpmc_ad8.mmc2_dat4 */
-                       AM33XX_IOPAD(0x824, PIN_INPUT_PULLUP | MUX_MODE3)       /* gpmc_ad9.mmc2_dat5 */
-                       AM33XX_IOPAD(0x828, PIN_INPUT_PULLUP | MUX_MODE3)       /* gpmc_ad10.mmc2_dat6 */
-                       AM33XX_IOPAD(0x82c, PIN_INPUT_PULLUP | MUX_MODE3)       /* gpmc_ad11.mmc2_dat7 */
-                       AM33XX_IOPAD(0x888, PIN_INPUT_PULLUP | MUX_MODE3)     /* gpmc_csn3.mmc2_cmd */
-                       AM33XX_IOPAD(0x88c, PIN_INPUT_PULLUP | MUX_MODE3)       /* gpmc_clk.mmc2_clk */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_INPUT_PULLUP, MUX_MODE3)       /* gpmc_ad12.mmc2_dat0 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT_PULLUP, MUX_MODE3)       /* gpmc_ad13.mmc2_dat1 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_INPUT_PULLUP, MUX_MODE3)       /* gpmc_ad14.mmc2_dat2 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_INPUT_PULLUP, MUX_MODE3)       /* gpmc_ad15.mmc2_dat3 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_INPUT_PULLUP, MUX_MODE3)        /* gpmc_ad8.mmc2_dat4 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_INPUT_PULLUP, MUX_MODE3)        /* gpmc_ad9.mmc2_dat5 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_INPUT_PULLUP, MUX_MODE3)       /* gpmc_ad10.mmc2_dat6 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_INPUT_PULLUP, MUX_MODE3)       /* gpmc_ad11.mmc2_dat7 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_CSN3, PIN_INPUT_PULLUP, MUX_MODE3)     /* gpmc_csn3.mmc2_cmd */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_CLK, PIN_INPUT_PULLUP, MUX_MODE3)        /* gpmc_clk.mmc2_clk */
                >;
        };
 
        spi0_pins: pinmux_spi0 {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x950, PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_sclk.spi0_sclk */
-                       AM33XX_IOPAD(0x95C, PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_cs0.spi0_cs0 */
-                       AM33XX_IOPAD(0x954, PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_d0.spi0_d0 */
-                       AM33XX_IOPAD(0x958, PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_d1.spi0_d1 */
+                       AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT_PULLUP, MUX_MODE0)
                >;
        };
 

diff --git a/arch/arm/boot/dts/am335x-nano.dts b/arch/arm/boot/dts/am335x-nano.dts
index 9c9143e..0052657 100644 (file)
--- a/arch/arm/boot/dts/am335x-nano.dts
+++ b/arch/arm/boot/dts/am335x-nano.dts
@@ -41,121 +41,121 @@
 
        misc_pins: misc_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x95c, PIN_OUTPUT | MUX_MODE7)     /* spi0_cs0.gpio0_5 */
+                       AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_OUTPUT, MUX_MODE7)      /* spi0_cs0.gpio0_5 */
                >;
        };
 
        gpmc_pins: gpmc_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE0)       /* gpmc_ad0.gpmc_ad0 */
-                       AM33XX_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE0)       /* gpmc_ad1.gpmc_ad1 */
-                       AM33XX_IOPAD(0x808, PIN_INPUT_PULLUP | MUX_MODE0)       /* gpmc_ad2.gpmc_ad2 */
-                       AM33XX_IOPAD(0x80c, PIN_INPUT_PULLUP | MUX_MODE0)       /* gpmc_ad3.gpmc_ad3 */
-                       AM33XX_IOPAD(0x810, PIN_INPUT_PULLUP | MUX_MODE0)       /* gpmc_ad4.gpmc_ad4 */
-                       AM33XX_IOPAD(0x814, PIN_INPUT_PULLUP | MUX_MODE0)       /* gpmc_ad5.gpmc_ad5 */
-                       AM33XX_IOPAD(0x818, PIN_INPUT_PULLUP | MUX_MODE0)       /* gpmc_ad6.gpmc_ad6 */
-                       AM33XX_IOPAD(0x81c, PIN_INPUT_PULLUP | MUX_MODE0)       /* gpmc_ad7.gpmc_ad7 */
-                       AM33XX_IOPAD(0x820, PIN_INPUT_PULLUP | MUX_MODE0)       /* gpmc_ad8.gpmc_ad8 */
-                       AM33XX_IOPAD(0x824, PIN_INPUT_PULLUP | MUX_MODE0)       /* gpmc_ad9.gpmc_ad9 */
-                       AM33XX_IOPAD(0x828, PIN_INPUT_PULLUP | MUX_MODE0)       /* gpmc_ad10.gpmc_ad10 */
-                       AM33XX_IOPAD(0x82c, PIN_INPUT_PULLUP | MUX_MODE0)       /* gpmc_ad11.gpmc_ad11 */
-                       AM33XX_IOPAD(0x830, PIN_INPUT_PULLUP | MUX_MODE0)       /* gpmc_ad12.gpmc_ad12 */
-                       AM33XX_IOPAD(0x834, PIN_INPUT_PULLUP | MUX_MODE0)       /* gpmc_ad13.gpmc_ad13 */
-                       AM33XX_IOPAD(0x838, PIN_INPUT_PULLUP | MUX_MODE0)       /* gpmc_ad14.gpmc_ad14 */
-                       AM33XX_IOPAD(0x83c, PIN_INPUT_PULLUP | MUX_MODE0)       /* gpmc_ad15.gpmc_ad15 */
-
-                       AM33XX_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE0)       /* gpmc_wait0.gpmc_wait0 */
-                       AM33XX_IOPAD(0x87c, PIN_OUTPUT | MUX_MODE0)             /* gpmc_csn0.gpmc_csn0 */
-                       AM33XX_IOPAD(0x880, PIN_OUTPUT | MUX_MODE0)             /* gpmc_csn1.gpmc_csn1 */
-                       AM33XX_IOPAD(0x884, PIN_OUTPUT | MUX_MODE0)             /* gpmc_csn2.gpmc_csn2 */
-                       AM33XX_IOPAD(0x888, PIN_OUTPUT | MUX_MODE0)             /* gpmc_csn3.gpmc_csn3 */
-
-                       AM33XX_IOPAD(0x890, PIN_OUTPUT | MUX_MODE0)             /* gpmc_advn_ale.gpmc_advn_ale */
-                       AM33XX_IOPAD(0x894, PIN_OUTPUT | MUX_MODE0)             /* gpmc_oen_ren.gpmc_oen_ren */
-                       AM33XX_IOPAD(0x898, PIN_OUTPUT | MUX_MODE0)             /* gpmc_wen.gpmc_wen */
-                       AM33XX_IOPAD(0x89c, PIN_OUTPUT | MUX_MODE0)             /* gpmc_ben0_cle.gpmc_ben0_cle */
-
-                       AM33XX_IOPAD(0x8a4, PIN_OUTPUT | MUX_MODE1)             /* lcd_data1.gpmc_a1 */
-                       AM33XX_IOPAD(0x8a8, PIN_OUTPUT | MUX_MODE1)             /* lcd_data2.gpmc_a2 */
-                       AM33XX_IOPAD(0x8ac, PIN_OUTPUT | MUX_MODE1)             /* lcd_data3.gpmc_a3 */
-                       AM33XX_IOPAD(0x8b0, PIN_OUTPUT | MUX_MODE1)             /* lcd_data4.gpmc_a4 */
-                       AM33XX_IOPAD(0x8b4, PIN_OUTPUT | MUX_MODE1)             /* lcd_data5.gpmc_a5 */
-                       AM33XX_IOPAD(0x8b8, PIN_OUTPUT | MUX_MODE1)             /* lcd_data6.gpmc_a6 */
-                       AM33XX_IOPAD(0x8bc, PIN_OUTPUT | MUX_MODE1)             /* lcd_data7.gpmc_a7 */
-
-                       AM33XX_IOPAD(0x8e0, PIN_OUTPUT | MUX_MODE1)             /* lcd_vsync.gpmc_a8 */
-                       AM33XX_IOPAD(0x8e4, PIN_OUTPUT | MUX_MODE1)             /* lcd_hsync.gpmc_a9 */
-                       AM33XX_IOPAD(0x8e8, PIN_OUTPUT | MUX_MODE1)             /* lcd_pclk.gpmc_a10 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_INPUT_PULLUP, MUX_MODE0)
+
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_CSN3, PIN_OUTPUT, MUX_MODE0)
+
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_WEN, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_BEN0_CLE, PIN_OUTPUT, MUX_MODE0)
+
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE1)             /* lcd_data1.gpmc_a1 */
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE1)             /* lcd_data2.gpmc_a2 */
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE1)             /* lcd_data3.gpmc_a3 */
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE1)             /* lcd_data4.gpmc_a4 */
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE1)             /* lcd_data5.gpmc_a5 */
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE1)             /* lcd_data6.gpmc_a6 */
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE1)             /* lcd_data7.gpmc_a7 */
+
+                       AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT, MUX_MODE1)             /* lcd_vsync.gpmc_a8 */
+                       AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT, MUX_MODE1)             /* lcd_hsync.gpmc_a9 */
+                       AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT, MUX_MODE1)              /* lcd_pclk.gpmc_a10 */
                >;
        };
 
        i2c0_pins: i2c0_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x988, PIN_INPUT_PULLDOWN | MUX_MODE0)     /* i2c0_sda.i2c0_sda */
-                       AM33XX_IOPAD(0x98c, PIN_INPUT_PULLDOWN | MUX_MODE0)     /* i2c0_scl.i2c0_scl */
+                       AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLDOWN, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLDOWN, MUX_MODE0)
                >;
        };
 
        uart0_pins: uart0_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0)       /* uart0_rxd.uart0_rxd */
-                       AM33XX_IOPAD(0x974, PIN_OUTPUT | MUX_MODE0)             /* uart0_txd.uart0_txd */
+                       AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT, MUX_MODE0)
                >;
        };
 
        uart1_pins: uart1_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x978, PIN_OUTPUT | MUX_MODE7)             /* uart1_ctsn.uart1_ctsn */
-                       AM33XX_IOPAD(0x97c, PIN_OUTPUT | MUX_MODE7)             /* uart1_rtsn.uart1_rtsn */
-                       AM33XX_IOPAD(0x980, PIN_INPUT_PULLUP | MUX_MODE0)       /* uart1_rxd.uart1_rxd */
-                       AM33XX_IOPAD(0x984, PIN_OUTPUT | MUX_MODE0)             /* uart1_txd.uart1_txd */
+                       AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_OUTPUT, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT, MUX_MODE0)
                >;
        };
 
        uart2_pins: uart2_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x8c0, PIN_INPUT_PULLUP | MUX_MODE7)       /* lcd_data8.gpio2[14] */
-                       AM33XX_IOPAD(0x8c4, PIN_OUTPUT | MUX_MODE7)             /* lcd_data9.gpio2[15] */
-                       AM33XX_IOPAD(0x950, PIN_INPUT | MUX_MODE1)              /* spi0_sclk.uart2_rxd */
-                       AM33XX_IOPAD(0x954, PIN_OUTPUT | MUX_MODE1)             /* spi0_d0.uart2_txd */
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_INPUT_PULLUP, MUX_MODE7)       /* lcd_data8.gpio2[14] */
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE7)             /* lcd_data9.gpio2[15] */
+                       AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT, MUX_MODE1)              /* spi0_sclk.uart2_rxd */
+                       AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_OUTPUT, MUX_MODE1)               /* spi0_d0.uart2_txd */
                >;
        };
 
        uart3_pins: uart3_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x8c8, PIN_INPUT_PULLUP | MUX_MODE6)       /* lcd_data10.uart3_ctsn */
-                       AM33XX_IOPAD(0x8cc, PIN_OUTPUT | MUX_MODE6)             /* lcd_data11.uart3_rtsn */
-                       AM33XX_IOPAD(0x960, PIN_INPUT | MUX_MODE1)              /* spi0_cs1.uart3_rxd */
-                       AM33XX_IOPAD(0x964, PIN_OUTPUT | MUX_MODE1)             /* ecap0_in_pwm0_out.uart3_txd */
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_INPUT_PULLUP, MUX_MODE6)      /* lcd_data10.uart3_ctsn */
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE6)            /* lcd_data11.uart3_rtsn */
+                       AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT, MUX_MODE1)               /* spi0_cs1.uart3_rxd */
+                       AM33XX_PADCONF(AM335X_PIN_ECAP0_IN_PWM0_OUT, PIN_OUTPUT, MUX_MODE1)             /* ecap0_in_pwm0_out.uart3_txd */
                >;
        };
 
        uart4_pins: uart4_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x8d0, PIN_INPUT_PULLUP | MUX_MODE6)       /* lcd_data12.uart4_ctsn */
-                       AM33XX_IOPAD(0x8d4, PIN_OUTPUT | MUX_MODE6)             /* lcd_data13.uart4_rtsn */
-                       AM33XX_IOPAD(0x968, PIN_INPUT | MUX_MODE1)              /* uart0_ctsn.uart4_rxd */
-                       AM33XX_IOPAD(0x96c, PIN_OUTPUT | MUX_MODE1)             /* uart0_rtsn.uart4_txd */
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_INPUT_PULLUP, MUX_MODE6)      /* lcd_data12.uart4_ctsn */
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE6)            /* lcd_data13.uart4_rtsn */
+                       AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_INPUT, MUX_MODE1)             /* uart0_ctsn.uart4_rxd */
+                       AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_OUTPUT, MUX_MODE1)            /* uart0_rtsn.uart4_txd */
                >;
        };
 
        uart5_pins: uart5_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x8d8, PIN_INPUT | MUX_MODE4)              /* lcd_data14.uart5_rxd */
-                       AM33XX_IOPAD(0x944, PIN_OUTPUT | MUX_MODE3)             /* rmiii1_refclk.uart5_txd */
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_INPUT, MUX_MODE4)             /* lcd_data14.uart5_rxd */
+                       AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_OUTPUT, MUX_MODE3)         /* rmiii1_refclk.uart5_txd */
                >;
        };
 
        mmc1_pins: mmc1_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x8f0, PIN_INPUT_PULLUP | MUX_MODE0)       /* mmc0_dat0.mmc0_dat0 */
-                       AM33XX_IOPAD(0x8f4, PIN_INPUT_PULLUP | MUX_MODE0)       /* mmc0_dat1.mmc0_dat1 */
-                       AM33XX_IOPAD(0x8f8, PIN_INPUT_PULLUP | MUX_MODE0)       /* mmc0_dat2.mmc0_dat2 */
-                       AM33XX_IOPAD(0x8fc, PIN_INPUT_PULLUP | MUX_MODE0)       /* mmc0_dat3.mmc0_dat3 */
-                       AM33XX_IOPAD(0x900, PIN_INPUT_PULLUP | MUX_MODE0)       /* mmc0_clk.mmc0_clk */
-                       AM33XX_IOPAD(0x904, PIN_INPUT_PULLUP | MUX_MODE0)       /* mmc0_cmd.mmc0_cmd */
-                       AM33XX_IOPAD(0x9e8, PIN_INPUT_PULLUP | MUX_MODE7)       /* emu1.gpio3[8] */
-                       AM33XX_IOPAD(0x9a0, PIN_INPUT_PULLUP | MUX_MODE7)       /* mcasp0_aclkr.gpio3[18] */
+                       AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0)        /* mmc0_clk.mmc0_clk */
+                       AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0)        /* mmc0_cmd.mmc0_cmd */
+                       AM33XX_PADCONF(AM335X_PIN_EMU1, PIN_INPUT_PULLUP, MUX_MODE7)    /* emu1.gpio3[8] */
+                       AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKR, PIN_INPUT_PULLUP, MUX_MODE7)    /* mcasp0_aclkr.gpio3[18] */
                >;
        };
 };

diff --git a/arch/arm/boot/dts/am335x-osd3358-sm-red.dts b/arch/arm/boot/dts/am335x-osd3358-sm-red.dts
index 95d54cf..f47cc9f 100644 (file)
--- a/arch/arm/boot/dts/am335x-osd3358-sm-red.dts
+++ b/arch/arm/boot/dts/am335x-osd3358-sm-red.dts
@@ -40,61 +40,61 @@
 &am33xx_pinmux {
        nxp_hdmi_bonelt_pins: nxp-hdmi-bonelt-pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x9b0, PIN_OUTPUT_PULLDOWN | MUX_MODE3)    /* xdma_event_intr0 */
-                       AM33XX_IOPAD(0x8a0, PIN_OUTPUT | MUX_MODE0)             /* lcd_data0.lcd_data0 */
-                       AM33XX_IOPAD(0x8a4, PIN_OUTPUT | MUX_MODE0)             /* lcd_data1.lcd_data1 */
-                       AM33XX_IOPAD(0x8a8, PIN_OUTPUT | MUX_MODE0)             /* lcd_data2.lcd_data2 */
-                       AM33XX_IOPAD(0x8ac, PIN_OUTPUT | MUX_MODE0)             /* lcd_data3.lcd_data3 */
-                       AM33XX_IOPAD(0x8b0, PIN_OUTPUT | MUX_MODE0)             /* lcd_data4.lcd_data4 */
-                       AM33XX_IOPAD(0x8b4, PIN_OUTPUT | MUX_MODE0)             /* lcd_data5.lcd_data5 */
-                       AM33XX_IOPAD(0x8b8, PIN_OUTPUT | MUX_MODE0)             /* lcd_data6.lcd_data6 */
-                       AM33XX_IOPAD(0x8bc, PIN_OUTPUT | MUX_MODE0)             /* lcd_data7.lcd_data7 */
-                       AM33XX_IOPAD(0x8c0, PIN_OUTPUT | MUX_MODE0)             /* lcd_data8.lcd_data8 */
-                       AM33XX_IOPAD(0x8c4, PIN_OUTPUT | MUX_MODE0)             /* lcd_data9.lcd_data9 */
-                       AM33XX_IOPAD(0x8c8, PIN_OUTPUT | MUX_MODE0)             /* lcd_data10.lcd_data10 */
-                       AM33XX_IOPAD(0x8cc, PIN_OUTPUT | MUX_MODE0)             /* lcd_data11.lcd_data11 */
-                       AM33XX_IOPAD(0x8d0, PIN_OUTPUT | MUX_MODE0)             /* lcd_data12.lcd_data12 */
-                       AM33XX_IOPAD(0x8d4, PIN_OUTPUT | MUX_MODE0)             /* lcd_data13.lcd_data13 */
-                       AM33XX_IOPAD(0x8d8, PIN_OUTPUT | MUX_MODE0)             /* lcd_data14.lcd_data14 */
-                       AM33XX_IOPAD(0x8dc, PIN_OUTPUT | MUX_MODE0)             /* lcd_data15.lcd_data15 */
-                       AM33XX_IOPAD(0x8e0, PIN_OUTPUT_PULLDOWN | MUX_MODE0)    /* lcd_vsync.lcd_vsync */
-                       AM33XX_IOPAD(0x8e4, PIN_OUTPUT_PULLDOWN | MUX_MODE0)    /* lcd_hsync.lcd_hsync */
-                       AM33XX_IOPAD(0x8e8, PIN_OUTPUT_PULLDOWN | MUX_MODE0)    /* lcd_pclk.lcd_pclk */
-                       AM33XX_IOPAD(0x8ec, PIN_OUTPUT_PULLDOWN | MUX_MODE0)    /* lcd_ac_bias_en.lcd_ac_bias_en */
+                       AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_OUTPUT_PULLDOWN, MUX_MODE3)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
                >;
        };
 
        nxp_hdmi_bonelt_off_pins: nxp-hdmi-bonelt-off-pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x9b0, PIN_OUTPUT_PULLDOWN | MUX_MODE3)    /* xdma_event_intr0 */
+                       AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_OUTPUT_PULLDOWN, MUX_MODE3)
                >;
        };
 
        mcasp0_pins: mcasp0-pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x9ac, PIN_INPUT_PULLUP | MUX_MODE0) /* mcasp0_ahcklx.mcasp0_ahclkx */
-                       AM33XX_IOPAD(0x99c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mcasp0_ahclkr.mcasp0_axr2*/
-                       AM33XX_IOPAD(0x994, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mcasp0_fsx.mcasp0_fsx */
-                       AM33XX_IOPAD(0x990, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp0_aclkx.mcasp0_aclkx */
-                       AM33XX_IOPAD(0x86c, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a11.GPIO1_27 */
+                       AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKX, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKR, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mcasp0_ahclkr.mcasp0_axr2*/
+                       AM33XX_PADCONF(AM335X_PIN_MCASP0_FSX, PIN_OUTPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKX, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_a11.GPIO1_27 */
                >;
        };
 
        flash_enable: flash-enable {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x944, PIN_OUTPUT_PULLDOWN | MUX_MODE7)    /* rmii1_ref_clk.gpio0_29 */
+                       AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE7)        /* rmii1_ref_clk.gpio0_29 */
                >;
        };
 
        imu_interrupt: imu-interrupt {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE7)             /* mii1_rx_er.gpio3_2 */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE7)            /* mii1_rx_er.gpio3_2 */
                >;
        };
 
        ethernet_interrupt: ethernet-interrupt{
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x908, PIN_INPUT_PULLDOWN | MUX_MODE7)             /* mii1_col.gpio3_0 */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT_PULLDOWN, MUX_MODE7)              /* mii1_col.gpio3_0 */
                >;
        };
 };
@@ -269,109 +269,109 @@
 
        user_leds_s0: user-leds-s0 {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x854, PIN_OUTPUT_PULLDOWN | MUX_MODE7)    /* gpmc_a5.gpio1_21 */
-                       AM33XX_IOPAD(0x858, PIN_OUTPUT_PULLUP | MUX_MODE7)      /* gpmc_a6.gpio1_22 */
-                       AM33XX_IOPAD(0x85c, PIN_OUTPUT_PULLDOWN | MUX_MODE7)    /* gpmc_a7.gpio1_23 */
-                       AM33XX_IOPAD(0x860, PIN_OUTPUT_PULLUP | MUX_MODE7)      /* gpmc_a8.gpio1_24 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT_PULLDOWN, MUX_MODE7)      /* gpmc_a5.gpio1_21 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_OUTPUT_PULLUP, MUX_MODE7)        /* gpmc_a6.gpio1_22 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_OUTPUT_PULLDOWN, MUX_MODE7)      /* gpmc_a7.gpio1_23 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_OUTPUT_PULLUP, MUX_MODE7)        /* gpmc_a8.gpio1_24 */
                >;
        };
 
        i2c2_pins: pinmux-i2c2-pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x978, PIN_INPUT_PULLUP | MUX_MODE3)       /* uart1_ctsn.i2c2_sda */
-                       AM33XX_IOPAD(0x97c, PIN_INPUT_PULLUP | MUX_MODE3)       /* uart1_rtsn.i2c2_scl */
+                       AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLUP, MUX_MODE3)      /* uart1_ctsn.i2c2_sda */
+                       AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_INPUT_PULLUP, MUX_MODE3)      /* uart1_rtsn.i2c2_scl */
                >;
        };
 
        uart0_pins: pinmux-uart0-pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0)       /* uart0_rxd.uart0_rxd */
-                       AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0)    /* uart0_txd.uart0_txd */
+                       AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
                >;
        };
 
        clkout2_pin: pinmux-clkout2-pin {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x9b4, PIN_OUTPUT_PULLDOWN | MUX_MODE3)    /* xdma_event_intr1.clkout2 */
+                       AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR1, PIN_OUTPUT_PULLDOWN, MUX_MODE3)     /* xdma_event_intr1.clkout2 */
                >;
        };
 
        cpsw_default: cpsw-default {
                pinctrl-single,pins = <
                        /* Slave 1 */
-                       AM33XX_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE2)    /* mii1_txen.rgmii1_tctl */
-                       AM33XX_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE2)             /* mii1_rxdv.rgmii1_rctl */
-                       AM33XX_IOPAD(0x91c, PIN_OUTPUT_PULLDOWN | MUX_MODE2)    /* mii1_txd3.rgmii1_txd3 */
-                       AM33XX_IOPAD(0x920, PIN_OUTPUT_PULLDOWN | MUX_MODE2)    /* mii1_txd2.rgmii1_txd2 */
-                       AM33XX_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE2)    /* mii1_txd1.rgmii1_txd1 */
-                       AM33XX_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE2)    /* mii1_txd0.rgmii1_txd0 */
-                       AM33XX_IOPAD(0x92c, PIN_OUTPUT_PULLDOWN | MUX_MODE2)    /* mii1_txclk.rgmii1_txclk */
-                       AM33XX_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE2)             /* mii1_rxclk.rgmii1_rxclk */
-                       AM33XX_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE2)             /* mii1_rxd3.rgmii1_rxd3 */
-                       AM33XX_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE2)             /* mii1_rxd2.rgmii1_rxd2 */
-                       AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE2)             /* mii1_rxd1.rgmii1_rxd1 */
-                       AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE2)             /* mii1_rxd0.rgmii1_rxd0 */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE2)   /* mii1_txen.rgmii1_tctl */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE2)            /* mii1_rxdv.rgmii1_rctl */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT_PULLDOWN, MUX_MODE2)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE2)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE2)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE2)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE2)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE2)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE2)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE2)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE2)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE2)
                >;
        };
 
        cpsw_sleep: cpsw-sleep {
                pinctrl-single,pins = <
                        /* Slave 1 reset value */
-                       AM33XX_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x91c, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x920, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x92c, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7)
                >;
        };
 
        davinci_mdio_default: davinci-mdio-default {
                pinctrl-single,pins = <
                        /* MDIO */
-                       AM33XX_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)       /* mdio_data.mdio_data */
-                       AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0)                      /* mdio_clk.mdio_clk */
+                       AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0)
                >;
        };
 
        davinci_mdio_sleep: davinci-mdio-sleep {
                pinctrl-single,pins = <
                        /* MDIO reset value */
-                       AM33XX_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7)
                >;
        };
 
        mmc1_pins: pinmux-mmc1-pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x960, PIN_INPUT | MUX_MODE7) /* (C15) spi0_cs1.gpio0[6] */
-                       AM33XX_IOPAD(0x8fc, PIN_INPUT_PULLUP | MUX_MODE0) /* (G16) mmc0_dat0.mmc0_dat0 */
-                       AM33XX_IOPAD(0x8f8, PIN_INPUT_PULLUP | MUX_MODE0) /* (G15) mmc0_dat1.mmc0_dat1 */
-                       AM33XX_IOPAD(0x8f4, PIN_INPUT_PULLUP | MUX_MODE0) /* (F18) mmc0_dat2.mmc0_dat2 */
-                       AM33XX_IOPAD(0x8f0, PIN_INPUT_PULLUP | MUX_MODE0) /* (F17) mmc0_dat3.mmc0_dat3 */
-                       AM33XX_IOPAD(0x904, PIN_INPUT_PULLUP | MUX_MODE0) /* (G18) mmc0_cmd.mmc0_cmd */
-                       AM33XX_IOPAD(0x900, PIN_INPUT_PULLUP | MUX_MODE0) /* (G17) mmc0_clk.mmc0_clk */
+                       AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT, MUX_MODE7) /* (C15) spi0_cs1.gpio0[6] */
+                       AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0)
                >;
        };
 
        emmc_pins: pinmux-emmc-pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x880, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn1.mmc1_clk */
-                       AM33XX_IOPAD(0x884, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn2.mmc1_cmd */
-                       AM33XX_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */
-                       AM33XX_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */
-                       AM33XX_IOPAD(0x808, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */
-                       AM33XX_IOPAD(0x80c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */
-                       AM33XX_IOPAD(0x810, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad4.mmc1_dat4 */
-                       AM33XX_IOPAD(0x814, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad5.mmc1_dat5 */
-                       AM33XX_IOPAD(0x818, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad6.mmc1_dat6 */
-                       AM33XX_IOPAD(0x81c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn1.mmc1_clk */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn2.mmc1_cmd */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad4.mmc1_dat4 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad5.mmc1_dat5 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad6.mmc1_dat6 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */
                >;
        };
 };

diff --git a/arch/arm/boot/dts/am335x-osd335x-common.dtsi b/arch/arm/boot/dts/am335x-osd335x-common.dtsi
index f8ff473..a8b6842 100644 (file)
--- a/arch/arm/boot/dts/am335x-osd335x-common.dtsi
+++ b/arch/arm/boot/dts/am335x-osd335x-common.dtsi
@@ -36,8 +36,8 @@
 &am33xx_pinmux {
        i2c0_pins: pinmux-i2c0-pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x988, PIN_INPUT_PULLUP | MUX_MODE0)       /* (C17) I2C0_SDA.I2C0_SDA */
-                       AM33XX_IOPAD(0x98c, PIN_INPUT_PULLUP | MUX_MODE0)       /* (C16) I2C0_SCL.I2C0_SCL */
+                       AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0)
                >;
        };
 };

diff --git a/arch/arm/boot/dts/am335x-pcm-953.dtsi b/arch/arm/boot/dts/am335x-pcm-953.dtsi
index 1ec8e0d..baceaa7 100644 (file)
--- a/arch/arm/boot/dts/am335x-pcm-953.dtsi
+++ b/arch/arm/boot/dts/am335x-pcm-953.dtsi
@@ -79,15 +79,15 @@
 &am33xx_pinmux {
        user_buttons_pins: pinmux_user_buttons {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x9e4, PIN_INPUT_PULLDOWN | MUX_MODE7)     /* emu0.gpio3_7 */
-                       AM33XX_IOPAD(0x9e8, PIN_INPUT_PULLDOWN | MUX_MODE7)     /* emu1.gpio3_8 */
+                       AM33XX_PADCONF(AM335X_PIN_EMU0, PIN_INPUT_PULLDOWN, MUX_MODE7)  /* emu0.gpio3_7 */
+                       AM33XX_PADCONF(AM335X_PIN_EMU1, PIN_INPUT_PULLDOWN, MUX_MODE7)  /* emu1.gpio3_8 */
                >;
        };
 
        user_leds_pins: pinmux_user_leds {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x880, PIN_OUTPUT_PULLDOWN | MUX_MODE7)    /* gpmc_csn1.gpio1_30 */
-                       AM33XX_IOPAD(0x884, PIN_OUTPUT_PULLDOWN | MUX_MODE7)    /* gpmc_csn2.gpio1_31 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_OUTPUT_PULLDOWN, MUX_MODE7)    /* gpmc_csn1.gpio1_30 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_OUTPUT_PULLDOWN, MUX_MODE7)    /* gpmc_csn2.gpio1_31 */
                >;
        };
 };
@@ -96,8 +96,8 @@
 &am33xx_pinmux {
        dcan1_pins: pinmux_dcan1 {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x980, PIN_OUTPUT_PULLUP | MUX_MODE2)      /* uart1_rxd.dcan1_tx_mux2 */
-                       AM33XX_IOPAD(0x984, PIN_INPUT_PULLUP | MUX_MODE2)       /* uart1_txd.dcan1_rx_mux2 */
+                       AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_OUTPUT_PULLUP, MUX_MODE2)      /* uart1_rxd.dcan1_tx_mux2 */
+                       AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_INPUT_PULLUP, MUX_MODE2)       /* uart1_txd.dcan1_rx_mux2 */
                >;
        };
 };
@@ -112,18 +112,18 @@
 &am33xx_pinmux {
        ethernet1_pins: pinmux_ethernet1 {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x840, PIN_OUTPUT_PULLDOWN | MUX_MODE2)    /* gpmc_a0.rgmii2_tctl */
-                       AM33XX_IOPAD(0x844, PIN_INPUT_PULLDOWN | MUX_MODE2)     /* gpmc_a1.rgmii2_rctl */
-                       AM33XX_IOPAD(0x848, PIN_OUTPUT_PULLDOWN | MUX_MODE2)    /* gpmc_a2.rgmii2_td3 */
-                       AM33XX_IOPAD(0x84c, PIN_OUTPUT_PULLDOWN | MUX_MODE2)    /* gpmc_a3.rgmii2_td2 */
-                       AM33XX_IOPAD(0x850, PIN_OUTPUT_PULLDOWN | MUX_MODE2)    /* gpmc_a4.rgmii2_td1 */
-                       AM33XX_IOPAD(0x854, PIN_OUTPUT_PULLDOWN | MUX_MODE2)    /* gpmc_a5.rgmii2_td0 */
-                       AM33XX_IOPAD(0x858, PIN_OUTPUT_PULLDOWN | MUX_MODE2)    /* gpmc_a6.rgmii2_tclk */
-                       AM33XX_IOPAD(0x85c, PIN_INPUT_PULLDOWN | MUX_MODE2)     /* gpmc_a7.rgmii2_rclk */
-                       AM33XX_IOPAD(0x860, PIN_INPUT_PULLDOWN | MUX_MODE2)     /* gpmc_a8.rgmii2_rd3 */
-                       AM33XX_IOPAD(0x864, PIN_INPUT_PULLDOWN | MUX_MODE2)     /* gpmc_a9.rgmii2_rd2 */
-                       AM33XX_IOPAD(0x868, PIN_INPUT_PULLDOWN | MUX_MODE2)     /* gpmc_a10.rgmii2_rd1 */
-                       AM33XX_IOPAD(0x86c, PIN_INPUT_PULLDOWN | MUX_MODE2)     /* gpmc_a11.rgmii2_rd0 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT_PULLDOWN, MUX_MODE2)      /* gpmc_a0.rgmii2_tctl */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLDOWN, MUX_MODE2)       /* gpmc_a1.rgmii2_rctl */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_OUTPUT_PULLDOWN, MUX_MODE2)      /* gpmc_a2.rgmii2_td3 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_OUTPUT_PULLDOWN, MUX_MODE2)      /* gpmc_a3.rgmii2_td2 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT_PULLDOWN, MUX_MODE2)      /* gpmc_a4.rgmii2_td1 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT_PULLDOWN, MUX_MODE2)      /* gpmc_a5.rgmii2_td0 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_OUTPUT_PULLDOWN, MUX_MODE2)      /* gpmc_a6.rgmii2_tclk */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_INPUT_PULLDOWN, MUX_MODE2)       /* gpmc_a7.rgmii2_rclk */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_INPUT_PULLDOWN, MUX_MODE2)       /* gpmc_a8.rgmii2_rd3 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLDOWN, MUX_MODE2)       /* gpmc_a9.rgmii2_rd2 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE2)      /* gpmc_a10.rgmii2_rd1 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE2)      /* gpmc_a11.rgmii2_rd0 */
                >;
        };
 };
@@ -171,8 +171,8 @@
 
        cb_gpio_pins: pinmux_cb_gpio {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x968, PIN_OUTPUT_PULLDOWN | MUX_MODE7)    /* uart0_ctsn.gpio1_8 */
-                       AM33XX_IOPAD(0x96c, PIN_OUTPUT_PULLDOWN | MUX_MODE7)    /* uart0_rtsn.gpio1_9 */
+                       AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_OUTPUT_PULLDOWN, MUX_MODE7)   /* uart0_ctsn.gpio1_8 */
+                       AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_OUTPUT_PULLDOWN, MUX_MODE7)   /* uart0_rtsn.gpio1_9 */
                >;
        };
 };
@@ -181,13 +181,13 @@
 &am33xx_pinmux {
        mmc1_pins: pinmux_mmc1_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x8f0, PIN_INPUT_PULLUP | MUX_MODE0)       /* mmc0_dat3.mmc0_dat3 */
-                       AM33XX_IOPAD(0x8f4, PIN_INPUT_PULLUP | MUX_MODE0)       /* mmc0_dat2.mmc0_dat2 */
-                       AM33XX_IOPAD(0x8f8, PIN_INPUT_PULLUP | MUX_MODE0)       /* mmc0_dat1.mmc0_dat1 */
-                       AM33XX_IOPAD(0x8fc, PIN_INPUT_PULLUP | MUX_MODE0)       /* mmc0_dat0.mmc0_dat0 */
-                       AM33XX_IOPAD(0x900, PIN_INPUT_PULLUP | MUX_MODE0)       /* mmc0_clk.mmc0_clk */
-                       AM33XX_IOPAD(0x904, PIN_INPUT_PULLUP | MUX_MODE0)       /* mmc0_cmd.mmc0_cmd */
-                       AM33XX_IOPAD(0x960, PIN_INPUT_PULLUP | MUX_MODE7)       /* spi0_cs1.mmc0_sdcd */
+                       AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT_PULLUP, MUX_MODE7)        /* spi0_cs1.mmc0_sdcd */
                >;
        };
 };
@@ -205,31 +205,31 @@
 &am33xx_pinmux {
        uart0_pins: pinmux_uart0 {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0)       /* uart0_rxd.uart0_rxd */
-                       AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0)    /* uart0_txd.uart0_txd */
+                       AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
                >;
        };
 
        uart1_pins: pinmux_uart1 {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x980, PIN_INPUT_PULLUP | MUX_MODE0)       /* uart1_rxd.uart1_rxd */
-                       AM33XX_IOPAD(0x984, PIN_OUTPUT_PULLDOWN | MUX_MODE0)    /* uart1_txd.uart1_txd */
-                       AM33XX_IOPAD(0x978, PIN_INPUT | MUX_MODE0)              /* uart1_ctsn.uart1_ctsn */
-                       AM33XX_IOPAD(0x97c, PIN_OUTPUT_PULLDOWN | MUX_MODE0)    /* uart1_rtsn.uart1_rtsn */
+                       AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
                >;
        };
 
        uart2_pins: pinmux_uart2 {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x92c, PIN_INPUT_PULLUP | MUX_MODE1)       /* mii1_tx_clk.uart2_rxd */
-                       AM33XX_IOPAD(0x930, PIN_OUTPUT_PULLDOWN | MUX_MODE1)    /* mii1_rx_clk.uart2_txd */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLUP, MUX_MODE1)     /* mii1_tx_clk.uart2_rxd */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE1)  /* mii1_rx_clk.uart2_txd */
                >;
        };
 
        uart3_pins: pinmux_uart3 {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x934, PIN_INPUT_PULLUP | MUX_MODE1)       /* mii1_rxd3.uart3_rxd */
-                       AM33XX_IOPAD(0x938, PIN_OUTPUT_PULLDOWN | MUX_MODE1)    /* mii1_rxd2.uart3_txd */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLUP, MUX_MODE1)       /* mii1_rxd3.uart3_rxd */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE1)    /* mii1_rxd2.uart3_txd */
                >;
        };
 };

diff --git a/arch/arm/boot/dts/am335x-pdu001.dts b/arch/arm/boot/dts/am335x-pdu001.dts
index ae43d61..3141255 100644 (file)
--- a/arch/arm/boot/dts/am335x-pdu001.dts
+++ b/arch/arm/boot/dts/am335x-pdu001.dts
@@ -92,162 +92,162 @@
 
        i2c0_pins: pinmux_i2c0_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x988, PIN_INPUT_PULLUP | MUX_MODE0)       /* i2c0_sda.i2c0_sda */
-                       AM33XX_IOPAD(0x98c, PIN_INPUT_PULLUP | MUX_MODE0)       /* i2c0_scl.i2c0_scl */
+                       AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0)
                >;
        };
 
        i2c1_pins: pinmux_i2c1_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x958, PIN_INPUT_PULLUP | MUX_MODE2)       /* spi0_d1.i2c1_sda */
-                       AM33XX_IOPAD(0x95c, PIN_INPUT_PULLUP | MUX_MODE2)       /* spi0_cs0.i2c1_scl */
+                       AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT_PULLUP, MUX_MODE2) /* spi0_d1.i2c1_sda */
+                       AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT_PULLUP, MUX_MODE2)        /* spi0_cs0.i2c1_scl */
                >;
        };
 
        i2c2_pins: pinmux_i2c2_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x950, PIN_INPUT_PULLUP | MUX_MODE2)       /* spi0_clk.i2c2_sda */
-                       AM33XX_IOPAD(0x954, PIN_INPUT_PULLUP | MUX_MODE2)       /* spi0_d0.i2c2_scl */
+                       AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT_PULLUP, MUX_MODE2)       /* spi0_clk.i2c2_sda */
+                       AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_INPUT_PULLUP, MUX_MODE2) /* spi0_d0.i2c2_scl */
                >;
        };
 
        spi1_pins: pinmux_spi1_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x990, PIN_OUTPUT | MUX_MODE3)             /* mcasp0_aclkx.spi1_sclk */
-                       AM33XX_IOPAD(0x994, PIN_OUTPUT | MUX_MODE3)             /* mcasp0_fsx.spi1_d0 */
-                       AM33XX_IOPAD(0x998, PIN_INPUT_PULLDOWN | MUX_MODE3)     /* mcasp0_axr0.spi1_d1 */
-                       AM33XX_IOPAD(0x99C, PIN_OUTPUT | MUX_MODE3)             /* mcasp0_ahclkr.spi1_cs0 */
+                       AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKX, PIN_OUTPUT, MUX_MODE3)          /* mcasp0_aclkx.spi1_sclk */
+                       AM33XX_PADCONF(AM335X_PIN_MCASP0_FSX, PIN_OUTPUT, MUX_MODE3)            /* mcasp0_fsx.spi1_d0 */
+                       AM33XX_PADCONF(AM335X_PIN_MCASP0_AXR0, PIN_INPUT_PULLDOWN, MUX_MODE3)   /* mcasp0_axr0.spi1_d1 */
+                       AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKR, PIN_OUTPUT, MUX_MODE3)         /* mcasp0_ahclkr.spi1_cs0 */
                >;
        };
 
        uart0_pins: pinmux_uart0_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x96C, PIN_OUTPUT | MUX_MODE7)             /* uart0_rtsn.gpio1_9 */
-                       AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0)       /* uart0_rxd.uart0_rxd */
-                       AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0)    /* uart0_txd.uart0_txd */
+                       AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_OUTPUT, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
                >;
        };
 
        uart1_pins: pinmux_uart1_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x980, PIN_INPUT_PULLUP | MUX_MODE0)       /* uart1_rxd.uart1_rxd */
-                       AM33XX_IOPAD(0x984, PIN_OUTPUT_PULLDOWN | MUX_MODE0)    /* uart1_txd.uart1_txd */
+                       AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
                >;
        };
 
        uart3_pins: pinmux_uart3_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x960, PIN_INPUT_PULLUP | MUX_MODE1)       /* spi0_cs1.uart3_rxd */
-                       AM33XX_IOPAD(0x964, PIN_OUTPUT_PULLDOWN | MUX_MODE1)    /* ecap0_in_pwm0_out.uart3_txd */
+                       AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT_PULLUP, MUX_MODE1)        /* spi0_cs1.uart3_rxd */
+                       AM33XX_PADCONF(AM335X_PIN_ECAP0_IN_PWM0_OUT, PIN_OUTPUT_PULLDOWN, MUX_MODE1)    /* ecap0_in_pwm0_out.uart3_txd */
                >;
        };
 
        clkout2_pin: pinmux_clkout2_pin {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x9b4, PIN_OUTPUT_PULLDOWN | MUX_MODE3)    /* xdma_event_intr1.clkout2 */
+                       AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR1, PIN_OUTPUT_PULLDOWN, MUX_MODE3)     /* xdma_event_intr1.clkout2 */
                >;
        };
 
        cpsw_default: cpsw_default {
                pinctrl-single,pins = <
                        /* Port 1 (emac0) */
-                       AM33XX_IOPAD(0x908, PIN_INPUT | MUX_MODE0)              /* mii1_col.mii1_col */
-                       AM33XX_IOPAD(0x90C, PIN_INPUT | MUX_MODE0)              /* mii1_crs.mii1_crs */
-                       AM33XX_IOPAD(0x910, PIN_INPUT | MUX_MODE0)              /* mii1_rxer.mii1_rxer */
-                       AM33XX_IOPAD(0x914, PIN_OUTPUT | MUX_MODE0)             /* mii1_txen.mii1_txen */
-                       AM33XX_IOPAD(0x918, PIN_INPUT | MUX_MODE0)              /* mii1_rxdv.mii1_rxdv */
-                       AM33XX_IOPAD(0x91c, PIN_OUTPUT | MUX_MODE0)             /* mii1_txd3.mii1_txd3 */
-                       AM33XX_IOPAD(0x920, PIN_OUTPUT | MUX_MODE0)             /* mii1_txd2.mii1_txd2 */
-                       AM33XX_IOPAD(0x924, PIN_OUTPUT | MUX_MODE0)             /* mii1_txd1.mii1_txd1 */
-                       AM33XX_IOPAD(0x928, PIN_OUTPUT | MUX_MODE0)             /* mii1_txd0.mii1_txd0 */
-                       AM33XX_IOPAD(0x92c, PIN_INPUT | MUX_MODE0)              /* mii1_txclk.mii1_txclk */
-                       AM33XX_IOPAD(0x930, PIN_INPUT | MUX_MODE0)              /* mii1_rxclk.mii1_rxclk */
-                       AM33XX_IOPAD(0x934, PIN_INPUT | MUX_MODE0)              /* mii1_rxd3.mii1_rxd3 */
-                       AM33XX_IOPAD(0x938, PIN_INPUT | MUX_MODE0)              /* mii1_rxd2.mii1_rxd2 */
-                       AM33XX_IOPAD(0x93c, PIN_INPUT | MUX_MODE0)              /* mii1_rxd1.mii1_rxd1 */
-                       AM33XX_IOPAD(0x940, PIN_INPUT | MUX_MODE0)              /* mii1_rxd0.mii1_rxd0 */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT, MUX_MODE0)
 
                        /* Port 2 (emac1) */
-                       AM33XX_IOPAD(0x840, PIN_OUTPUT | MUX_MODE1)             /* mii2_txen.gpmc_a0 */
-                       AM33XX_IOPAD(0x844, PIN_INPUT | MUX_MODE1)              /* mii2_rxdv.gpmc_a1 */
-                       AM33XX_IOPAD(0x848, PIN_OUTPUT | MUX_MODE1)             /* mii2_txd3.gpmc_a2 */
-                       AM33XX_IOPAD(0x84c, PIN_OUTPUT | MUX_MODE1)             /* mii2_txd2.gpmc_a3 */
-                       AM33XX_IOPAD(0x850, PIN_OUTPUT | MUX_MODE1)             /* mii2_txd1.gpmc_a4 */
-                       AM33XX_IOPAD(0x854, PIN_OUTPUT | MUX_MODE1)             /* mii2_txd0.gpmc_a5 */
-                       AM33XX_IOPAD(0x858, PIN_INPUT | MUX_MODE1)              /* mii2_txclk.gpmc_a6 */
-                       AM33XX_IOPAD(0x85c, PIN_INPUT | MUX_MODE1)              /* mii2_rxclk.gpmc_a7 */
-                       AM33XX_IOPAD(0x860, PIN_INPUT | MUX_MODE1)              /* mii2_rxd3.gpmc_a8 */
-                       AM33XX_IOPAD(0x864, PIN_INPUT | MUX_MODE1)              /* mii2_rxd2.gpmc_a9 */
-                       AM33XX_IOPAD(0x868, PIN_INPUT | MUX_MODE1)              /* mii2_rxd1.gpmc_a10 */
-                       AM33XX_IOPAD(0x86C, PIN_INPUT | MUX_MODE1)              /* mii2_rxd0.gpmc_a11 */
-                       AM33XX_IOPAD(0x870, PIN_INPUT | MUX_MODE1)              /* mii2_crs.gpmc_wait0 */
-                       AM33XX_IOPAD(0x874, PIN_INPUT | MUX_MODE1)              /* mii2_rxer.gpmc_wpn */
-                       AM33XX_IOPAD(0x878, PIN_INPUT | MUX_MODE1)              /* mii2_col.gpmc_ben1 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT, MUX_MODE1)               /* mii2_txen.gpmc_a0 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT, MUX_MODE1)                /* mii2_rxdv.gpmc_a1 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_OUTPUT, MUX_MODE1)               /* mii2_txd3.gpmc_a2 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_OUTPUT, MUX_MODE1)               /* mii2_txd2.gpmc_a3 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT, MUX_MODE1)               /* mii2_txd1.gpmc_a4 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT, MUX_MODE1)               /* mii2_txd0.gpmc_a5 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_INPUT, MUX_MODE1)                /* mii2_txclk.gpmc_a6 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_INPUT, MUX_MODE1)                /* mii2_rxclk.gpmc_a7 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_INPUT, MUX_MODE1)                /* mii2_rxd3.gpmc_a8 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT, MUX_MODE1)                /* mii2_rxd2.gpmc_a9 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT, MUX_MODE1)               /* mii2_rxd1.gpmc_a10 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT, MUX_MODE1)               /* mii2_rxd0.gpmc_a11 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT, MUX_MODE1)             /* mii2_crs.gpmc_wait0 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT, MUX_MODE1)               /* mii2_rxer.gpmc_wpn */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_BEN1, PIN_INPUT, MUX_MODE1)              /* mii2_col.gpmc_ben1 */
                >;
        };
 
        davinci_mdio_default: davinci_mdio_default {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)       /* mdio_data.mdio_data */
-                       AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0)                      /* mdio_clk.mdio_clk */
+                       AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0)
                >;
        };
 
        mmc1_pins: pinmux_mmc1_pins {
                /* eMMC */
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x8f0, PIN_INPUT_PULLUP | MUX_MODE0)       /* mmc0_dat3 */
-                       AM33XX_IOPAD(0x8f4, PIN_INPUT_PULLUP | MUX_MODE0)       /* mmc0_dat2 */
-                       AM33XX_IOPAD(0x8f8, PIN_INPUT_PULLUP | MUX_MODE0)       /* mmc0_dat1 */
-                       AM33XX_IOPAD(0x8fc, PIN_INPUT_PULLUP | MUX_MODE0)       /* mmc0_dat0 */
-                       AM33XX_IOPAD(0x900, PIN_INPUT_PULLUP | MUX_MODE0)       /* mmc0_clk */
-                       AM33XX_IOPAD(0x904, PIN_INPUT_PULLUP | MUX_MODE0)       /* mmc0_cmd */
+                       AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0)
                >;
        };
 
        mmc2_pins: pinmux_mmc2_pins {
                /* SD cardcage */
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x80c, PIN_INPUT_PULLUP | MUX_MODE1)       /* gpmc_ad3.mmc1_dat3 */
-                       AM33XX_IOPAD(0x808, PIN_INPUT_PULLUP | MUX_MODE1)       /* gpmc_ad2.mmc1_dat2 */
-                       AM33XX_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE1)       /* gpmc_ad1.mmc1_dat1 */
-                       AM33XX_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE1)       /* gpmc_ad0.mmc1_dat0 */
-                       AM33XX_IOPAD(0x880, PIN_INPUT_PULLUP | MUX_MODE2)       /* gpmc_csn1.mmc1_clk */
-                       AM33XX_IOPAD(0x884, PIN_INPUT_PULLUP | MUX_MODE2)       /* gpmc_csn2.mmc1_cmd */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE1)        /* gpmc_ad3.mmc1_dat3 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE1)        /* gpmc_ad2.mmc1_dat2 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE1)        /* gpmc_ad1.mmc1_dat1 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE1)        /* gpmc_ad0.mmc1_dat0 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_INPUT_PULLUP, MUX_MODE2)       /* gpmc_csn1.mmc1_clk */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_INPUT_PULLUP, MUX_MODE2)       /* gpmc_csn2.mmc1_cmd */
                        /* card change signal for frontpanel SD cardcage */
-                       AM33XX_IOPAD(0x890, PIN_INPUT | MUX_MODE7)              /* gpmc_advn_ale.gpio2_2 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_INPUT, MUX_MODE7)          /* gpmc_advn_ale.gpio2_2 */
                >;
        };
 
        lcd_pins_s0: lcd_pins_s0 {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x8a0, PIN_OUTPUT | MUX_MODE0)             /* lcd_data0.lcd_data0 */
-                       AM33XX_IOPAD(0x8a4, PIN_OUTPUT | MUX_MODE0)             /* lcd_data1.lcd_data1 */
-                       AM33XX_IOPAD(0x8a8, PIN_OUTPUT | MUX_MODE0)             /* lcd_data2.lcd_data2 */
-                       AM33XX_IOPAD(0x8ac, PIN_OUTPUT | MUX_MODE0)             /* lcd_data3.lcd_data3 */
-                       AM33XX_IOPAD(0x8b0, PIN_OUTPUT | MUX_MODE0)             /* lcd_data4.lcd_data4 */
-                       AM33XX_IOPAD(0x8b4, PIN_OUTPUT | MUX_MODE0)             /* lcd_data5.lcd_data5 */
-                       AM33XX_IOPAD(0x8b8, PIN_OUTPUT | MUX_MODE0)             /* lcd_data6.lcd_data6 */
-                       AM33XX_IOPAD(0x8bc, PIN_OUTPUT | MUX_MODE0)             /* lcd_data7.lcd_data7 */
-                       AM33XX_IOPAD(0x8c0, PIN_OUTPUT | MUX_MODE0)             /* lcd_data8.lcd_data8 */
-                       AM33XX_IOPAD(0x8c4, PIN_OUTPUT | MUX_MODE0)             /* lcd_data9.lcd_data9 */
-                       AM33XX_IOPAD(0x8c8, PIN_OUTPUT | MUX_MODE0)             /* lcd_data10.lcd_data10 */
-                       AM33XX_IOPAD(0x8cc, PIN_OUTPUT | MUX_MODE0)             /* lcd_data11.lcd_data11 */
-                       AM33XX_IOPAD(0x8d0, PIN_OUTPUT | MUX_MODE0)             /* lcd_data12.lcd_data12 */
-                       AM33XX_IOPAD(0x8d4, PIN_OUTPUT | MUX_MODE0)             /* lcd_data13.lcd_data13 */
-                       AM33XX_IOPAD(0x8d8, PIN_OUTPUT | MUX_MODE0)             /* lcd_data14.lcd_data14 */
-                       AM33XX_IOPAD(0x8dc, PIN_OUTPUT | MUX_MODE0)             /* lcd_data15.lcd_data15 */
-                       AM33XX_IOPAD(0x8e0, PIN_OUTPUT | MUX_MODE0)             /* lcd_vsync.lcd_vsync */
-                       AM33XX_IOPAD(0x8e4, PIN_OUTPUT | MUX_MODE0)             /* lcd_hsync.lcd_hsync */
-                       AM33XX_IOPAD(0x8e8, PIN_OUTPUT | MUX_MODE0)             /* lcd_pclk.lcd_pclk */
-                       AM33XX_IOPAD(0x8ec, PIN_OUTPUT | MUX_MODE0)             /* lcd_ac_bias_en.lcd_ac_bias_en */
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT, MUX_MODE0)
                >;
        };
 
        dcan0_pins: pinmux_dcan0_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x978, PIN_OUTPUT | MUX_MODE2)             /* uart1_ctsn.d_can0_tx */
-                       AM33XX_IOPAD(0x97c, PIN_INPUT_PULLDOWN | MUX_MODE2)     /* uart1_rtsn.d_can0_rx */
+                       AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_OUTPUT, MUX_MODE2)            /* uart1_ctsn.d_can0_tx */
+                       AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_INPUT_PULLDOWN, MUX_MODE2)    /* uart1_rtsn.d_can0_rx */
                >;
        };
 };

diff --git a/arch/arm/boot/dts/am335x-pepper.dts b/arch/arm/boot/dts/am335x-pepper.dts
index 6be79b8..5c3e49f 100644 (file)
--- a/arch/arm/boot/dts/am335x-pepper.dts
+++ b/arch/arm/boot/dts/am335x-pepper.dts
@@ -93,14 +93,14 @@
 &am33xx_pinmux {
        i2c0_pins: pinmux_i2c0 {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x988, PIN_INPUT_PULLUP | MUX_MODE0)       /* i2c0_sda.i2c0_sda */
-                       AM33XX_IOPAD(0x98c, PIN_INPUT_PULLUP | MUX_MODE0)       /* i2c0_scl.i2c0_scl */
+                       AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0)
                >;
        };
        i2c1_pins: pinmux_i2c1 {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x90C, PIN_INPUT_PULLUP | MUX_MODE3)       /* mii1_crs,i2c1_sda */
-                       AM33XX_IOPAD(0x910, PIN_INPUT_PULLUP | MUX_MODE3)       /* mii1_rxerr,i2c1_scl */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLUP, MUX_MODE3)        /* mii1_crs,i2c1_sda */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLUP, MUX_MODE3)      /* mii1_rxerr,i2c1_scl */
                >;
        };
 };
@@ -130,7 +130,7 @@
 &am33xx_pinmux {
        accel_pins: pinmux_accel {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x898, PIN_INPUT | MUX_MODE7)   /* gpmc_wen.gpio2_4 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_WEN, PIN_INPUT, MUX_MODE7)   /* gpmc_wen.gpio2_4 */
                >;
        };
 };
@@ -177,12 +177,12 @@
 &am33xx_pinmux {
        audio_pins: pinmux_audio {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x9ac, PIN_INPUT_PULLDOWN | MUX_MODE0)     /* mcasp0_ahcklx.mcasp0_ahclkx */
-                       AM33XX_IOPAD(0x994, PIN_INPUT_PULLDOWN | MUX_MODE0)     /* mcasp0_fsx.mcasp0_fsx */
-                       AM33XX_IOPAD(0x990, PIN_INPUT_PULLDOWN | MUX_MODE0)     /* mcasp0_aclkx.mcasp0_aclkx */
-                       AM33XX_IOPAD(0x998, PIN_INPUT_PULLDOWN | MUX_MODE0)     /* mcasp0_axr0.mcasp0_axr0 */
-                       AM33XX_IOPAD(0x9a8, PIN_INPUT_PULLDOWN | MUX_MODE0)     /* mcasp0_axr1.mcasp0_axr1 */
-                       AM33XX_IOPAD(0x840, PIN_OUTPUT | MUX_MODE7)     /* gpmc_a0.gpio1_16 */
+                       AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKX, PIN_INPUT_PULLDOWN, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MCASP0_FSX, PIN_INPUT_PULLDOWN, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKX, PIN_INPUT_PULLDOWN, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MCASP0_AXR0, PIN_INPUT_PULLDOWN, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MCASP0_AXR1, PIN_INPUT_PULLDOWN, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT, MUX_MODE7)       /* gpmc_a0.gpio1_16 */
                >;
        };
 };
@@ -228,36 +228,36 @@
 &am33xx_pinmux {
        lcd_pins: pinmux_lcd {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x8a0, PIN_OUTPUT | MUX_MODE0)     /* lcd_data0.lcd_data0 */
-                       AM33XX_IOPAD(0x8a4, PIN_OUTPUT | MUX_MODE0)     /* lcd_data1.lcd_data1 */
-                       AM33XX_IOPAD(0x8a8, PIN_OUTPUT | MUX_MODE0)     /* lcd_data2.lcd_data2 */
-                       AM33XX_IOPAD(0x8ac, PIN_OUTPUT | MUX_MODE0)     /* lcd_data3.lcd_data3 */
-                       AM33XX_IOPAD(0x8b0, PIN_OUTPUT | MUX_MODE0)     /* lcd_data4.lcd_data4 */
-                       AM33XX_IOPAD(0x8b4, PIN_OUTPUT | MUX_MODE0)     /* lcd_data5.lcd_data5 */
-                       AM33XX_IOPAD(0x8b8, PIN_OUTPUT | MUX_MODE0)     /* lcd_data6.lcd_data6 */
-                       AM33XX_IOPAD(0x8bc, PIN_OUTPUT | MUX_MODE0)     /* lcd_data7.lcd_data7 */
-                       AM33XX_IOPAD(0x8c0, PIN_OUTPUT | MUX_MODE0)     /* lcd_data8.lcd_data8 */
-                       AM33XX_IOPAD(0x8c4, PIN_OUTPUT | MUX_MODE0)     /* lcd_data9.lcd_data9 */
-                       AM33XX_IOPAD(0x8c8, PIN_OUTPUT | MUX_MODE0)     /* lcd_data10.lcd_data10 */
-                       AM33XX_IOPAD(0x8cc, PIN_OUTPUT | MUX_MODE0)     /* lcd_data11.lcd_data11 */
-                       AM33XX_IOPAD(0x8d0, PIN_OUTPUT | MUX_MODE0)     /* lcd_data12.lcd_data12 */
-                       AM33XX_IOPAD(0x8d4, PIN_OUTPUT | MUX_MODE0)     /* lcd_data13.lcd_data13 */
-                       AM33XX_IOPAD(0x8d8, PIN_OUTPUT | MUX_MODE0)     /* lcd_data14.lcd_data14 */
-                       AM33XX_IOPAD(0x8dc, PIN_OUTPUT | MUX_MODE0)     /* lcd_data15.lcd_data15 */
-                       AM33XX_IOPAD(0x820, PIN_OUTPUT | MUX_MODE1)     /* gpmc_ad8.lcd_data16 */
-                       AM33XX_IOPAD(0x824, PIN_OUTPUT | MUX_MODE1)     /* gpmc_ad9.lcd_data17 */
-                       AM33XX_IOPAD(0x828, PIN_OUTPUT | MUX_MODE1)     /* gpmc_ad10.lcd_data18 */
-                       AM33XX_IOPAD(0x82c, PIN_OUTPUT | MUX_MODE1)     /* gpmc_ad11.lcd_data19 */
-                       AM33XX_IOPAD(0x830, PIN_OUTPUT | MUX_MODE1)     /* gpmc_ad12.lcd_data20 */
-                       AM33XX_IOPAD(0x834, PIN_OUTPUT | MUX_MODE1)     /* gpmc_ad13.lcd_data21 */
-                       AM33XX_IOPAD(0x838, PIN_OUTPUT | MUX_MODE1)     /* gpmc_ad14.lcd_data22 */
-                       AM33XX_IOPAD(0x83c, PIN_OUTPUT | MUX_MODE1)     /* gpmc_ad15.lcd_data23 */
-                       AM33XX_IOPAD(0x8e0, PIN_OUTPUT | MUX_MODE0)     /* lcd_vsync.lcd_vsync */
-                       AM33XX_IOPAD(0x8e4, PIN_OUTPUT | MUX_MODE0)     /* lcd_hsync.lcd_hsync */
-                       AM33XX_IOPAD(0x8e8, PIN_OUTPUT | MUX_MODE0)     /* lcd_pclk.lcd_pclk */
-                       AM33XX_IOPAD(0x8ec, PIN_OUTPUT | MUX_MODE0)     /* lcd_ac_bias_en.lcd_ac_bias_en */
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_OUTPUT, MUX_MODE1)      /* gpmc_ad8.lcd_data16 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_OUTPUT, MUX_MODE1)      /* gpmc_ad9.lcd_data17 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_OUTPUT, MUX_MODE1)     /* gpmc_ad10.lcd_data18 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_OUTPUT, MUX_MODE1)     /* gpmc_ad11.lcd_data19 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_OUTPUT, MUX_MODE1)     /* gpmc_ad12.lcd_data20 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_OUTPUT, MUX_MODE1)     /* gpmc_ad13.lcd_data21 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_OUTPUT, MUX_MODE1)     /* gpmc_ad14.lcd_data22 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_OUTPUT, MUX_MODE1)     /* gpmc_ad15.lcd_data23 */
+                       AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT, MUX_MODE0)
                        /* Display Enable */
-                       AM33XX_IOPAD(0x86c, PIN_OUTPUT_PULLUP | MUX_MODE7)      /* gpmc_a11.gpio1_27 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_OUTPUT_PULLUP, MUX_MODE7)       /* gpmc_a11.gpio1_27 */
                >;
        };
 };
@@ -299,29 +299,29 @@
 &am33xx_pinmux {
        ethernet_pins: pinmux_ethernet {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE2)    /* mii1_txen.rgmii1_tctl */
-                       AM33XX_IOPAD(0x918, PIN_INPUT_PULLUP | MUX_MODE2)       /* mii1_rxdv.rgmii1_rctl */
-                       AM33XX_IOPAD(0x91c, PIN_OUTPUT_PULLDOWN | MUX_MODE2)    /* mii1_txd3.rgmii1_td3 */
-                       AM33XX_IOPAD(0x920, PIN_OUTPUT_PULLDOWN | MUX_MODE2)    /* mii1_txd2.rgmii1_td2 */
-                       AM33XX_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE2)    /* mii1_txd1.rgmii1_td1 */
-                       AM33XX_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE2)    /* mii1_txd0.rgmii1_td0 */
-                       AM33XX_IOPAD(0x92c, PIN_INPUT_PULLUP | MUX_MODE2)       /* mii1_txclk.rgmii1_tclk */
-                       AM33XX_IOPAD(0x930, PIN_INPUT_PULLUP | MUX_MODE2)       /* mii1_rxclk.rgmii1_rclk */
-                       AM33XX_IOPAD(0x934, PIN_INPUT_PULLUP | MUX_MODE2)       /* mii1_rxd3.rgmii1_rxd3 */
-                       AM33XX_IOPAD(0x938, PIN_INPUT_PULLUP | MUX_MODE2)       /* mii1_rxd2.rgmii1_rxd2 */
-                       AM33XX_IOPAD(0x93c, PIN_INPUT_PULLUP | MUX_MODE2)       /* mii1_rxd1.rgmii1_rxd1 */
-                       AM33XX_IOPAD(0x940, PIN_INPUT_PULLUP | MUX_MODE2)       /* mii1_rxd0.rgmii1_rxd0 */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE2)   /* mii1_txen.rgmii1_tctl */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLUP, MUX_MODE2)      /* mii1_rxdv.rgmii1_rctl */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT_PULLDOWN, MUX_MODE2)    /* mii1_txd3.rgmii1_td3 */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE2)    /* mii1_txd2.rgmii1_td2 */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE2)    /* mii1_txd1.rgmii1_td1 */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE2)    /* mii1_txd0.rgmii1_td0 */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLUP, MUX_MODE2)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLUP, MUX_MODE2)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLUP, MUX_MODE2)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLUP, MUX_MODE2)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLUP, MUX_MODE2)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLUP, MUX_MODE2)
                        /* ethernet interrupt */
-                       AM33XX_IOPAD(0x944, PIN_INPUT_PULLUP | MUX_MODE7)       /* rmii2_refclk.gpio0_29 */
+                       AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLUP, MUX_MODE7)   /* rmii2_refclk.gpio0_29 */
                        /* ethernet PHY nReset */
-                       AM33XX_IOPAD(0x908, PIN_OUTPUT_PULLUP | MUX_MODE7)      /* mii1_col.gpio3_0 */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_OUTPUT_PULLUP, MUX_MODE7)       /* mii1_col.gpio3_0 */
                >;
        };
 
        mdio_pins: pinmux_mdio {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)       /* mdio_data.mdio_data */
-                       AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0)                      /* mdio_clk.mdio_clk */
+                       AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0)
                >;
        };
 };
@@ -364,45 +364,45 @@
 &am33xx_pinmux {
        sd_pins: pinmux_sd_card {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x8f0, PIN_INPUT_PULLUP | MUX_MODE0)       /* mmc0_dat0.mmc0_dat0 */
-                       AM33XX_IOPAD(0x8f4, PIN_INPUT_PULLUP | MUX_MODE0)       /* mmc0_dat1.mmc0_dat1 */
-                       AM33XX_IOPAD(0x8f8, PIN_INPUT_PULLUP | MUX_MODE0)       /* mmc0_dat2.mmc0_dat2 */
-                       AM33XX_IOPAD(0x8fc, PIN_INPUT_PULLUP | MUX_MODE0)       /* mmc0_dat3.mmc0_dat3 */
-                       AM33XX_IOPAD(0x900, PIN_INPUT_PULLUP | MUX_MODE0)       /* mmc0_clk.mmc0_clk */
-                       AM33XX_IOPAD(0x904, PIN_INPUT_PULLUP | MUX_MODE0)       /* mmc0_cmd.mmc0_cmd */
-                       AM33XX_IOPAD(0x960, PIN_INPUT | MUX_MODE7)              /* spi0_cs1.gpio0_6 */
+                       AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT, MUX_MODE7)               /* spi0_cs1.gpio0_6 */
                >;
        };
        emmc_pins: pinmux_emmc {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x880, PIN_INPUT_PULLUP | MUX_MODE2)       /* gpmc_csn1.mmc1_clk */
-                       AM33XX_IOPAD(0x884, PIN_INPUT_PULLUP | MUX_MODE2)       /* gpmc_csn2.mmc1_cmd */
-                       AM33XX_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE1)       /* gpmc_ad0.mmc1_dat0 */
-                       AM33XX_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE1)       /* gpmc_ad1.mmc1_dat1 */
-                       AM33XX_IOPAD(0x808, PIN_INPUT_PULLUP | MUX_MODE1)       /* gpmc_ad2.mmc1_dat2 */
-                       AM33XX_IOPAD(0x80c, PIN_INPUT_PULLUP | MUX_MODE1)       /* gpmc_ad3.mmc1_dat3 */
-                       AM33XX_IOPAD(0x810, PIN_INPUT_PULLUP | MUX_MODE1)       /* gpmc_ad4.mmc1_dat4 */
-                       AM33XX_IOPAD(0x814, PIN_INPUT_PULLUP | MUX_MODE1)       /* gpmc_ad5.mmc1_dat5 */
-                       AM33XX_IOPAD(0x818, PIN_INPUT_PULLUP | MUX_MODE1)       /* gpmc_ad6.mmc1_dat6 */
-                       AM33XX_IOPAD(0x81c, PIN_INPUT_PULLUP | MUX_MODE1)       /* gpmc_ad7.mmc1_dat7 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_INPUT_PULLUP, MUX_MODE2)       /* gpmc_csn1.mmc1_clk */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_INPUT_PULLUP, MUX_MODE2)       /* gpmc_csn2.mmc1_cmd */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE1)        /* gpmc_ad0.mmc1_dat0 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE1)        /* gpmc_ad1.mmc1_dat1 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE1)        /* gpmc_ad2.mmc1_dat2 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE1)        /* gpmc_ad3.mmc1_dat3 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE1)        /* gpmc_ad4.mmc1_dat4 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE1)        /* gpmc_ad5.mmc1_dat5 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE1)        /* gpmc_ad6.mmc1_dat6 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE1)        /* gpmc_ad7.mmc1_dat7 */
                        /* EMMC nReset */
-                       AM33XX_IOPAD(0x874, PIN_OUTPUT_PULLUP | MUX_MODE7)      /* gpmc_wpn.gpio0_31 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_OUTPUT_PULLUP, MUX_MODE7)       /* gpmc_wpn.gpio0_31 */
                >;
        };
        wireless_pins: pinmux_wireless {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x844, PIN_INPUT_PULLUP | MUX_MODE3)       /* gpmc_a1.mmc2_dat0 */
-                       AM33XX_IOPAD(0x848, PIN_INPUT_PULLUP | MUX_MODE3)       /* gpmc_a2.mmc2_dat1 */
-                       AM33XX_IOPAD(0x84c, PIN_INPUT_PULLUP | MUX_MODE3)       /* gpmc_a3.mmc2_dat2 */
-                       AM33XX_IOPAD(0x878, PIN_INPUT_PULLUP | MUX_MODE3)       /* gpmc_ben1.mmc2_dat3 */
-                       AM33XX_IOPAD(0x888, PIN_INPUT_PULLUP | MUX_MODE3)       /* gpmc_csn3.mmc2_cmd */
-                       AM33XX_IOPAD(0x88c, PIN_INPUT_PULLUP | MUX_MODE3)       /* gpmc_clk.mmc1_clk */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_a1.mmc2_dat0 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_a2.mmc2_dat1 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_a3.mmc2_dat2 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_BEN1, PIN_INPUT_PULLUP, MUX_MODE3)       /* gpmc_ben1.mmc2_dat3 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_CSN3, PIN_INPUT_PULLUP, MUX_MODE3)       /* gpmc_csn3.mmc2_cmd */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_CLK, PIN_INPUT_PULLUP, MUX_MODE3)        /* gpmc_clk.mmc1_clk */
                        /* WLAN nReset */
-                       AM33XX_IOPAD(0x860, PIN_OUTPUT_PULLUP | MUX_MODE7)      /* gpmc_a8.gpio1_24 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_OUTPUT_PULLUP, MUX_MODE7)        /* gpmc_a8.gpio1_24 */
                        /* WLAN nPower down */
-                       AM33XX_IOPAD(0x870, PIN_OUTPUT_PULLUP | MUX_MODE7)      /* gpmc_wait0.gpio0_30 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_OUTPUT_PULLUP, MUX_MODE7)     /* gpmc_wait0.gpio0_30 */
                        /* 32kHz Clock */
-                       AM33XX_IOPAD(0x9b4, PIN_OUTPUT_PULLDOWN | MUX_MODE3)    /* xdma_event_intr1.clkout2 */
+                       AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR1, PIN_OUTPUT_PULLDOWN, MUX_MODE3)     /* xdma_event_intr1.clkout2 */
                >;
        };
 };
@@ -498,10 +498,10 @@
 &am33xx_pinmux {
        spi0_pins: pinmux_spi0 {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x950, PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_sclk.spi0_sclk */
-                       AM33XX_IOPAD(0x95C, PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_cs0.spi0_cs0 */
-                       AM33XX_IOPAD(0x954, PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_d0.spi0_d0 */
-                       AM33XX_IOPAD(0x958, PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_d1.spi0_d1 */
+                       AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT_PULLUP, MUX_MODE0)
                >;
        };
 };
@@ -539,16 +539,16 @@
 &am33xx_pinmux {
        uart0_pins: pinmux_uart0 {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0)       /* uart0_rxd.uart0_rxd */
-                       AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0)    /* uart0_txd.uart0_txd */
+                       AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
                >;
        };
        uart1_pins: pinmux_uart1 {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x978, PIN_INPUT_PULLUP | MUX_MODE0)       /* uart1_ctsn.uart1_ctsn */
-                       AM33XX_IOPAD(0x97C, PIN_OUTPUT_PULLDOWN | MUX_MODE0)    /* uart1_rtsn.uart1_rtsn */
-                       AM33XX_IOPAD(0x980, PIN_INPUT_PULLUP | MUX_MODE0)       /* uart1_rxd.uart1_rxd */
-                       AM33XX_IOPAD(0x984, PIN_OUTPUT_PULLDOWN | MUX_MODE0)    /* uart1_txd.uart1_txd */
+                       AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
                >;
        };
 };
@@ -591,9 +591,9 @@
        usb_pins: pinmux_usb {
                pinctrl-single,pins = <
                        /* USB0 Over-Current (active low) */
-                       AM33XX_IOPAD(0x864, PIN_INPUT | MUX_MODE7)      /* gpmc_a9.gpio1_25 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT, MUX_MODE7)        /* gpmc_a9.gpio1_25 */
                        /* USB1 Over-Current (active low) */
-                       AM33XX_IOPAD(0x868, PIN_INPUT | MUX_MODE7)      /* gpmc_a10.gpio1_26 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT, MUX_MODE7)       /* gpmc_a10.gpio1_26 */
                >;
        };
 };
@@ -649,16 +649,16 @@
 &am33xx_pinmux {
        user_leds_pins: pinmux_user_leds {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x850, PIN_OUTPUT | MUX_MODE7)     /* gpmc_a4.gpio1_20 */
-                       AM33XX_IOPAD(0x854, PIN_OUTPUT | MUX_MODE7)     /* gpmc_a5.gpio1_21 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT, MUX_MODE7)       /* gpmc_a4.gpio1_20 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT, MUX_MODE7)       /* gpmc_a5.gpio1_21 */
                >;
        };
 
        user_buttons_pins: pinmux_user_buttons {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x858, PIN_INPUT_PULLUP | MUX_MODE7)       /* gpmc_a6.gpio1_22 */
-                       AM33XX_IOPAD(0x85C, PIN_INPUT_PULLUP | MUX_MODE7)       /* gpmc_a7.gpio1_21 */
-                       AM33XX_IOPAD(0x964, PIN_INPUT_PULLUP | MUX_MODE7)       /* gpmc_a8.gpio0_7 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_INPUT_PULLUP, MUX_MODE7) /* gpmc_a6.gpio1_22 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_INPUT_PULLUP, MUX_MODE7) /* gpmc_a7.gpio1_21 */
+                       AM33XX_PADCONF(AM335X_PIN_ECAP0_IN_PWM0_OUT, PIN_INPUT_PULLUP, MUX_MODE7)       /* gpmc_a8.gpio0_7 */
                >;
        };
 };

diff --git a/arch/arm/boot/dts/am335x-phycore-som.dtsi b/arch/arm/boot/dts/am335x-phycore-som.dtsi
index 015adb6..23c3039 100644 (file)
--- a/arch/arm/boot/dts/am335x-phycore-som.dtsi
+++ b/arch/arm/boot/dts/am335x-phycore-som.dtsi
@@ -57,22 +57,22 @@
 &am33xx_pinmux {
        ethernet0_pins: pinmux_ethernet0 {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE1)     /* mii1_crs.rmii1_crs_dv */
-                       AM33XX_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE1)     /* mii1_rxerr.rmii1_rxerr */
-                       AM33XX_IOPAD(0x914, PIN_OUTPUT | MUX_MODE1)             /* mii1_txen.rmii1_txen */
-                       AM33XX_IOPAD(0x924, PIN_OUTPUT | MUX_MODE1)             /* mii1_txd1.rmii1_txd1 */
-                       AM33XX_IOPAD(0x928, PIN_OUTPUT | MUX_MODE1)             /* mii1_txd0.rmii1_txd0 */
-                       AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE1)     /* mii1_rxd1.rmii1_rxd1 */
-                       AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE1)     /* mii1_rxd0.rmii1_rxd0 */
-                       AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE0)     /* rmii1_refclk.rmii1_refclk */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE1)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE1)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT, MUX_MODE1)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT, MUX_MODE1)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT, MUX_MODE1)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE1)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE1)
+                       AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE0)
                >;
        };
 
        mdio_pins: pinmux_mdio {
                pinctrl-single,pins = <
                        /* MDIO */
-                       AM33XX_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)       /* mdio_data.mdio_data */
-                       AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0)                      /* mdio_clk.mdio_clk */
+                       AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0)
                >;
        };
 };
@@ -104,8 +104,8 @@
 &am33xx_pinmux {
        i2c0_pins: pinmux_i2c0 {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x988, PIN_INPUT | MUX_MODE0)      /* i2c0_sda.i2c0_sda */
-                       AM33XX_IOPAD(0x98c, PIN_INPUT | MUX_MODE0)      /* i2c0_scl.i2c0_scl */
+                       AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT, MUX_MODE0)
                >;
        };
 };
@@ -144,20 +144,20 @@
 &am33xx_pinmux {
                nandflash_pins: pinmux_nandflash {
                        pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE0)       /* gpmc_ad0.gpmc_ad0 */
-                       AM33XX_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE0)       /* gpmc_ad1.gpmc_ad1 */
-                       AM33XX_IOPAD(0x808, PIN_INPUT_PULLUP | MUX_MODE0)       /* gpmc_ad2.gpmc_ad2 */
-                       AM33XX_IOPAD(0x80c, PIN_INPUT_PULLUP | MUX_MODE0)       /* gpmc_ad3.gpmc_ad3 */
-                       AM33XX_IOPAD(0x810, PIN_INPUT_PULLUP | MUX_MODE0)       /* gpmc_ad4.gpmc_ad4 */
-                       AM33XX_IOPAD(0x814, PIN_INPUT_PULLUP | MUX_MODE0)       /* gpmc_ad5.gpmc_ad5 */
-                       AM33XX_IOPAD(0x818, PIN_INPUT_PULLUP | MUX_MODE0)       /* gpmc_ad6.gpmc_ad6 */
-                       AM33XX_IOPAD(0x81c, PIN_INPUT_PULLUP | MUX_MODE0)       /* gpmc_ad7.gpmc_ad7 */
-                       AM33XX_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE0)       /* gpmc_wait0.gpmc_wait0 */
-                       AM33XX_IOPAD(0x87c, PIN_OUTPUT | MUX_MODE0)             /* gpmc_csn0.gpmc_csn0 */
-                       AM33XX_IOPAD(0x890, PIN_OUTPUT | MUX_MODE0)             /* gpmc_advn_ale.gpmc_advn_ale */
-                       AM33XX_IOPAD(0x894, PIN_OUTPUT | MUX_MODE0)             /* gpmc_oen_ren.gpmc_oen_ren */
-                       AM33XX_IOPAD(0x898, PIN_OUTPUT | MUX_MODE0)             /* gpmc_wen.gpmc_wen */
-                       AM33XX_IOPAD(0x89c, PIN_OUTPUT | MUX_MODE0)             /* gpmc_be0n_cle.gpmc_be0n_cle */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_WEN, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_BEN0_CLE, PIN_OUTPUT, MUX_MODE0)
                >;
        };
 };
@@ -296,10 +296,10 @@
 &am33xx_pinmux {
        spi0_pins: pinmux_spi0 {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x950, PIN_INPUT_PULLDOWN | MUX_MODE0)     /* spi0_clk.spi0_clk */
-                       AM33XX_IOPAD(0x954, PIN_INPUT_PULLDOWN | MUX_MODE0)     /* spi0_d0.spi0_d0 */
-                       AM33XX_IOPAD(0x958, PIN_INPUT_PULLUP | MUX_MODE0)       /* spi0_d1.spi0_d1 */
-                       AM33XX_IOPAD(0x95c, PIN_INPUT_PULLUP | MUX_MODE0)       /* spi0_cs0.spi0_cs0 */
+                       AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT_PULLDOWN, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_INPUT_PULLDOWN, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT_PULLUP, MUX_MODE0)
                >;
        };
 };

diff --git a/arch/arm/boot/dts/am335x-pocketbeagle.dts b/arch/arm/boot/dts/am335x-pocketbeagle.dts
index 62fe5ca..ff4f919 100644 (file)
--- a/arch/arm/boot/dts/am335x-pocketbeagle.dts
+++ b/arch/arm/boot/dts/am335x-pocketbeagle.dts
@@ -62,74 +62,74 @@
 &am33xx_pinmux {
        i2c2_pins: pinmux-i2c2-pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x97c, PIN_INPUT_PULLUP | MUX_MODE3)       /* (D17) uart1_rtsn.I2C2_SCL */
-                       AM33XX_IOPAD(0x978, PIN_INPUT_PULLUP | MUX_MODE3)       /* (D18) uart1_ctsn.I2C2_SDA */
+                       AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_INPUT_PULLUP, MUX_MODE3)      /* (D17) uart1_rtsn.I2C2_SCL */
+                       AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLUP, MUX_MODE3)      /* (D18) uart1_ctsn.I2C2_SDA */
                >;
        };
 
        ehrpwm0_pins: pinmux-ehrpwm0-pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x990, PIN_OUTPUT_PULLDOWN | MUX_MODE1)    /* (A13) mcasp0_aclkx.ehrpwm0A */
+                       AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKX, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* (A13) mcasp0_aclkx.ehrpwm0A */
                >;
        };
 
        ehrpwm1_pins: pinmux-ehrpwm1-pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x848, PIN_OUTPUT_PULLDOWN | MUX_MODE6)    /* (U14) gpmc_a2.ehrpwm1A */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_OUTPUT_PULLDOWN, MUX_MODE6)      /* (U14) gpmc_a2.ehrpwm1A */
                >;
        };
 
        mmc0_pins: pinmux-mmc0-pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x960, PIN_INPUT | MUX_MODE7)              /* (C15) spi0_cs1.gpio0[6] */
-                       AM33XX_IOPAD(0x8fc, PIN_INPUT_PULLUP | MUX_MODE0)       /* (G16) mmc0_dat0.mmc0_dat0 */
-                       AM33XX_IOPAD(0x8f8, PIN_INPUT_PULLUP | MUX_MODE0)       /* (G15) mmc0_dat1.mmc0_dat1 */
-                       AM33XX_IOPAD(0x8f4, PIN_INPUT_PULLUP | MUX_MODE0)       /* (F18) mmc0_dat2.mmc0_dat2 */
-                       AM33XX_IOPAD(0x8f0, PIN_INPUT_PULLUP | MUX_MODE0)       /* (F17) mmc0_dat3.mmc0_dat3 */
-                       AM33XX_IOPAD(0x904, PIN_INPUT_PULLUP | MUX_MODE0)       /* (G18) mmc0_cmd.mmc0_cmd */
-                       AM33XX_IOPAD(0x900, PIN_INPUT_PULLUP | MUX_MODE0)       /* (G17) mmc0_clk.mmc0_clk */
-                       AM33XX_IOPAD(0x9a0, PIN_INPUT | MUX_MODE4)              /* (B12) mcasp0_aclkr.mmc0_sdwp */
+                       AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT, MUX_MODE7)               /* (C15) spi0_cs1.gpio0[6] */
+                       AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKR, PIN_INPUT, MUX_MODE4)           /* (B12) mcasp0_aclkr.mmc0_sdwp */
                >;
        };
 
        spi0_pins: pinmux-spi0-pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x950, PIN_INPUT_PULLUP | MUX_MODE0)       /* (A17) spi0_sclk.spi0_sclk */
-                       AM33XX_IOPAD(0x954, PIN_INPUT_PULLUP | MUX_MODE0)       /* (B17) spi0_d0.spi0_d0 */
-                       AM33XX_IOPAD(0x958, PIN_INPUT_PULLUP | MUX_MODE0)       /* (B16) spi0_d1.spi0_d1 */
-                       AM33XX_IOPAD(0x95c, PIN_INPUT_PULLUP | MUX_MODE0)       /* (A16) spi0_cs0.spi0_cs0 */
+                       AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT_PULLUP, MUX_MODE0)
                >;
        };
 
        spi1_pins: pinmux-spi1-pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x964, PIN_INPUT_PULLUP | MUX_MODE4)       /* (C18) eCAP0_in_PWM0_out.spi1_sclk */
-                       AM33XX_IOPAD(0x968, PIN_INPUT_PULLUP | MUX_MODE4)       /* (E18) uart0_ctsn.spi1_d0 */
-                       AM33XX_IOPAD(0x96c, PIN_INPUT_PULLUP | MUX_MODE4)       /* (E17) uart0_rtsn.spi1_d1 */
-                       AM33XX_IOPAD(0x9b0, PIN_INPUT_PULLUP | MUX_MODE4)       /* (A15) xdma_event_intr0.spi1_cs1 */
+                       AM33XX_PADCONF(AM335X_PIN_ECAP0_IN_PWM0_OUT, PIN_INPUT_PULLUP, MUX_MODE4)       /* (C18) eCAP0_in_PWM0_out.spi1_sclk */
+                       AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_INPUT_PULLUP, MUX_MODE4)      /* (E18) uart0_ctsn.spi1_d0 */
+                       AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT_PULLUP, MUX_MODE4)      /* (E17) uart0_rtsn.spi1_d1 */
+                       AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_INPUT_PULLUP, MUX_MODE4)        /* (A15) xdma_event_intr0.spi1_cs1 */
                >;
        };
 
        usr_leds_pins: pinmux-usr-leds-pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x854, PIN_OUTPUT | MUX_MODE7)             /* (V15) gpmc_a5.gpio1[21] - USR_LED_0 */
-                       AM33XX_IOPAD(0x858, PIN_OUTPUT | MUX_MODE7)             /* (U15) gpmc_a6.gpio1[22] - USR_LED_1 */
-                       AM33XX_IOPAD(0x85c, PIN_OUTPUT | MUX_MODE7)             /* (T15) gpmc_a7.gpio1[23] - USR_LED_2 */
-                       AM33XX_IOPAD(0x860, PIN_OUTPUT | MUX_MODE7)             /* (V16) gpmc_a8.gpio1[24] - USR_LED_3 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT, MUX_MODE7)               /* (V15) gpmc_a5.gpio1[21] - USR_LED_0 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_OUTPUT, MUX_MODE7)               /* (U15) gpmc_a6.gpio1[22] - USR_LED_1 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_OUTPUT, MUX_MODE7)               /* (T15) gpmc_a7.gpio1[23] - USR_LED_2 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_OUTPUT, MUX_MODE7)               /* (V16) gpmc_a8.gpio1[24] - USR_LED_3 */
                >;
        };
 
        uart0_pins: pinmux-uart0-pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0)       /* (E15) uart0_rxd.uart0_rxd */
-                       AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0)    /* (E16) uart0_txd.uart0_txd */
+                       AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
                >;
        };
 
        uart4_pins: pinmux-uart4-pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE6)       /* (T17) gpmc_wait0.uart4_rxd */
-                       AM33XX_IOPAD(0x874, PIN_OUTPUT_PULLDOWN | MUX_MODE6)    /* (U17) gpmc_wpn.uart4_txd */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE6)      /* (T17) gpmc_wait0.uart4_rxd */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_OUTPUT_PULLDOWN, MUX_MODE6)     /* (U17) gpmc_wpn.uart4_txd */
                >;
        };
 };

diff --git a/arch/arm/boot/dts/am335x-sancloud-bbe.dts b/arch/arm/boot/dts/am335x-sancloud-bbe.dts
index 35527fd..7ed27b5 100644 (file)
--- a/arch/arm/boot/dts/am335x-sancloud-bbe.dts
+++ b/arch/arm/boot/dts/am335x-sancloud-bbe.dts
@@ -23,70 +23,70 @@
        cpsw_default: cpsw_default {
                pinctrl-single,pins = <
                        /* Slave 1 */
-                       AM33XX_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE2)    /* mii1_txen.rgmii1_tctl */
-                       AM33XX_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE2)     /* mii1_rxdv.rgmii1_rctl */
-                       AM33XX_IOPAD(0x91c, PIN_OUTPUT_PULLDOWN | MUX_MODE2)    /* mii1_txd3.rgmii1_td3 */
-                       AM33XX_IOPAD(0x920, PIN_OUTPUT_PULLDOWN | MUX_MODE2)    /* mii1_txd2.rgmii1_td2 */
-                       AM33XX_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE2)    /* mii1_txd1.rgmii1_td1 */
-                       AM33XX_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE2)    /* mii1_txd0.rgmii1_td0 */
-                       AM33XX_IOPAD(0x92c, PIN_OUTPUT_PULLDOWN | MUX_MODE2)    /* mii1_txclk.rgmii1_tclk */
-                       AM33XX_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE2)     /* mii1_rxclk.rgmii1_rclk */
-                       AM33XX_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE2)     /* mii1_rxd3.rgmii1_rd3 */
-                       AM33XX_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE2)     /* mii1_rxd2.rgmii1_rd2 */
-                       AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE2)     /* mii1_rxd1.rgmii1_rd1 */
-                       AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE2)     /* mii1_rxd0.rgmii1_rd0 */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE2)   /* mii1_txen.rgmii1_tctl */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE2)    /* mii1_rxdv.rgmii1_rctl */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT_PULLDOWN, MUX_MODE2)    /* mii1_txd3.rgmii1_td3 */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE2)    /* mii1_txd2.rgmii1_td2 */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE2)    /* mii1_txd1.rgmii1_td1 */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE2)    /* mii1_txd0.rgmii1_td0 */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE2)  /* mii1_txclk.rgmii1_tclk */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE2)   /* mii1_rxclk.rgmii1_rclk */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE2)     /* mii1_rxd3.rgmii1_rd3 */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE2)     /* mii1_rxd2.rgmii1_rd2 */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE2)     /* mii1_rxd1.rgmii1_rd1 */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE2)     /* mii1_rxd0.rgmii1_rd0 */
                >;
        };
 
        cpsw_sleep: cpsw_sleep {
                pinctrl-single,pins = <
                        /* Slave 1 reset value */
-                       AM33XX_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x91c, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x920, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x92c, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7)
                >;
        };
 
        davinci_mdio_default: davinci_mdio_default {
                pinctrl-single,pins = <
                        /* MDIO */
-                       AM33XX_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)       /* mdio_data.mdio_data */
-                       AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0)                      /* mdio_clk.mdio_clk */
+                       AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0)
                >;
        };
 
        davinci_mdio_sleep: davinci_mdio_sleep {
                pinctrl-single,pins = <
                        /* MDIO reset value */
-                       AM33XX_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7)
                >;
        };
 
        usb_hub_ctrl: usb_hub_ctrl {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x944, PIN_OUTPUT_PULLUP | MUX_MODE7)     /* rmii1_refclk.gpio0_29 */
+                       AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_OUTPUT_PULLUP, MUX_MODE7)     /* rmii1_refclk.gpio0_29 */
                >;
        };
 
        mpu6050_pins: pinmux_mpu6050_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x968, PIN_INPUT | MUX_MODE7)    /* uart0_ctsn.gpio1_8 */
+                       AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_INPUT, MUX_MODE7)    /* uart0_ctsn.gpio1_8 */
                >;
        };
 
        lps3331ap_pins: pinmux_lps3331ap_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x868, PIN_INPUT | MUX_MODE7)     /* gpmc_a10.gpio1_26 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT, MUX_MODE7)     /* gpmc_a10.gpio1_26 */
                >;
        };
 };

diff --git a/arch/arm/boot/dts/am335x-sbc-t335.dts b/arch/arm/boot/dts/am335x-sbc-t335.dts
index 917d7cc..07c46a5 100644 (file)
--- a/arch/arm/boot/dts/am335x-sbc-t335.dts
+++ b/arch/arm/boot/dts/am335x-sbc-t335.dts
@@ -70,122 +70,82 @@
        lcd_pins_default: lcd_pins_default {
                pinctrl-single,pins = <
                        /* gpmc_ad8.lcd_data23 */
-                       AM33XX_IOPAD(0x820, PIN_OUTPUT | MUX_MODE1)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_OUTPUT, MUX_MODE1)
                        /* gpmc_ad9.lcd_data22 */
-                       AM33XX_IOPAD(0x824, PIN_OUTPUT | MUX_MODE1)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_OUTPUT, MUX_MODE1)
                        /* gpmc_ad10.lcd_data21 */
-                       AM33XX_IOPAD(0x828, PIN_OUTPUT | MUX_MODE1)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_OUTPUT, MUX_MODE1)
                        /* gpmc_ad11.lcd_data20 */
-                       AM33XX_IOPAD(0x82c, PIN_OUTPUT | MUX_MODE1)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_OUTPUT, MUX_MODE1)
                        /* gpmc_ad12.lcd_data19 */
-                       AM33XX_IOPAD(0x830, PIN_OUTPUT | MUX_MODE1)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_OUTPUT, MUX_MODE1)
                        /* gpmc_ad13.lcd_data18 */
-                       AM33XX_IOPAD(0x834, PIN_OUTPUT | MUX_MODE1)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_OUTPUT, MUX_MODE1)
                        /* gpmc_ad14.lcd_data17 */
-                       AM33XX_IOPAD(0x838, PIN_OUTPUT | MUX_MODE1)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_OUTPUT, MUX_MODE1)
                        /* gpmc_ad15.lcd_data16 */
-                       AM33XX_IOPAD(0x83c, PIN_OUTPUT | MUX_MODE1)
-                       /* lcd_data0.lcd_data0 */
-                       AM33XX_IOPAD(0x8a0, PIN_OUTPUT | MUX_MODE0)
-                       /* lcd_data1.lcd_data1 */
-                       AM33XX_IOPAD(0x8a4, PIN_OUTPUT | MUX_MODE0)
-                       /* lcd_data2.lcd_data2 */
-                       AM33XX_IOPAD(0x8a8, PIN_OUTPUT | MUX_MODE0)
-                       /* lcd_data3.lcd_data3 */
-                       AM33XX_IOPAD(0x8ac, PIN_OUTPUT | MUX_MODE0)
-                       /* lcd_data4.lcd_data4 */
-                       AM33XX_IOPAD(0x8b0, PIN_OUTPUT | MUX_MODE0)
-                       /* lcd_data5.lcd_data5 */
-                       AM33XX_IOPAD(0x8b4, PIN_OUTPUT | MUX_MODE0)
-                       /* lcd_data6.lcd_data6 */
-                       AM33XX_IOPAD(0x8b8, PIN_OUTPUT | MUX_MODE0)
-                       /* lcd_data7.lcd_data7 */
-                       AM33XX_IOPAD(0x8bc, PIN_OUTPUT | MUX_MODE0)
-                       /* lcd_data8.lcd_data8 */
-                       AM33XX_IOPAD(0x8c0, PIN_OUTPUT | MUX_MODE0)
-                       /* lcd_data9.lcd_data9 */
-                       AM33XX_IOPAD(0x8c4, PIN_OUTPUT | MUX_MODE0)
-                       /* lcd_data10.lcd_data10 */
-                       AM33XX_IOPAD(0x8c8, PIN_OUTPUT | MUX_MODE0)
-                       /* lcd_data11.lcd_data11 */
-                       AM33XX_IOPAD(0x8cc, PIN_OUTPUT | MUX_MODE0)
-                       /* lcd_data12.lcd_data12 */
-                       AM33XX_IOPAD(0x8d0, PIN_OUTPUT | MUX_MODE0)
-                       /* lcd_data13.lcd_data13 */
-                       AM33XX_IOPAD(0x8d4, PIN_OUTPUT | MUX_MODE0)
-                       /* lcd_data14.lcd_data14 */
-                       AM33XX_IOPAD(0x8d8, PIN_OUTPUT | MUX_MODE0)
-                       /* lcd_data15.lcd_data15 */
-                       AM33XX_IOPAD(0x8dc, PIN_OUTPUT | MUX_MODE0)
-                       /* lcd_vsync.lcd_vsync */
-                       AM33XX_IOPAD(0x8e0, PIN_OUTPUT | MUX_MODE0)
-                       /* lcd_hsync.lcd_hsync */
-                       AM33XX_IOPAD(0x8e4, PIN_OUTPUT | MUX_MODE0)
-                       /* lcd_pclk.lcd_pclk */
-                       AM33XX_IOPAD(0x8e8, PIN_OUTPUT | MUX_MODE0)
-                       /* lcd_ac_bias_en.lcd_ac_bias_en */
-                       AM33XX_IOPAD(0x8ec, PIN_OUTPUT | MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_OUTPUT, MUX_MODE1)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT, MUX_MODE0)
                >;
        };
 
        lcd_pins_sleep: lcd_pins_sleep {
                pinctrl-single,pins = <
                        /* gpmc_ad8.lcd_data23 */
-                       AM33XX_IOPAD(0x820, PIN_INPUT_PULLDOWN | MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_INPUT_PULLDOWN, MUX_MODE7)
                        /* gpmc_ad9.lcd_data22 */
-                       AM33XX_IOPAD(0x824, PIN_INPUT_PULLDOWN | MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_INPUT_PULLDOWN, MUX_MODE7)
                        /* gpmc_ad10.lcd_data21 */
-                       AM33XX_IOPAD(0x828, PIN_INPUT_PULLDOWN | MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_INPUT_PULLDOWN, MUX_MODE7)
                        /* gpmc_ad11.lcd_data20 */
-                       AM33XX_IOPAD(0x82c, PIN_INPUT_PULLDOWN | MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_INPUT_PULLDOWN, MUX_MODE7)
                        /* gpmc_ad12.lcd_data19 */
-                       AM33XX_IOPAD(0x830, PIN_INPUT_PULLDOWN | MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_INPUT_PULLDOWN, MUX_MODE7)
                        /* gpmc_ad13.lcd_data18 */
-                       AM33XX_IOPAD(0x834, PIN_INPUT_PULLDOWN | MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT_PULLDOWN, MUX_MODE7)
                        /* gpmc_ad14.lcd_data17 */
-                       AM33XX_IOPAD(0x838, PIN_INPUT_PULLDOWN | MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_INPUT_PULLDOWN, MUX_MODE7)
                        /* gpmc_ad15.lcd_data16 */
-                       AM33XX_IOPAD(0x83c, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       /* lcd_data0.lcd_data0 */
-                       AM33XX_IOPAD(0x8a0, PULL_DISABLE | MUX_MODE7)
-                       /* lcd_data1.lcd_data1 */
-                       AM33XX_IOPAD(0x8a4, PULL_DISABLE | MUX_MODE7)
-                       /* lcd_data2.lcd_data2 */
-                       AM33XX_IOPAD(0x8a8, PULL_DISABLE | MUX_MODE7)
-                       /* lcd_data3.lcd_data3 */
-                       AM33XX_IOPAD(0x8ac, PULL_DISABLE | MUX_MODE7)
-                       /* lcd_data4.lcd_data4 */
-                       AM33XX_IOPAD(0x8b0, PULL_DISABLE | MUX_MODE7)
-                       /* lcd_data5.lcd_data5 */
-                       AM33XX_IOPAD(0x8b4, PULL_DISABLE | MUX_MODE7)
-                       /* lcd_data6.lcd_data6 */
-                       AM33XX_IOPAD(0x8b8, PULL_DISABLE | MUX_MODE7)
-                       /* lcd_data7.lcd_data7 */
-                       AM33XX_IOPAD(0x8bc, PULL_DISABLE | MUX_MODE7)
-                       /* lcd_data8.lcd_data8 */
-                       AM33XX_IOPAD(0x8c0, PULL_DISABLE | MUX_MODE7)
-                       /* lcd_data9.lcd_data9 */
-                       AM33XX_IOPAD(0x8c4, PULL_DISABLE | MUX_MODE7)
-                       /* lcd_data10.lcd_data10 */
-                       AM33XX_IOPAD(0x8c8, PULL_DISABLE | MUX_MODE7)
-                       /* lcd_data11.lcd_data11 */
-                       AM33XX_IOPAD(0x8cc, PULL_DISABLE | MUX_MODE7)
-                       /* lcd_data12.lcd_data12 */
-                       AM33XX_IOPAD(0x8d0, PULL_DISABLE | MUX_MODE7)
-                       /* lcd_data13.lcd_data13 */
-                       AM33XX_IOPAD(0x8d4, PULL_DISABLE | MUX_MODE7)
-                       /* lcd_data14.lcd_data14 */
-                       AM33XX_IOPAD(0x8d8, PULL_DISABLE | MUX_MODE7)
-                       /* lcd_data15.lcd_data15 */
-                       AM33XX_IOPAD(0x8dc, PULL_DISABLE | MUX_MODE7)
-                       /* lcd_vsync.lcd_vsync */
-                       AM33XX_IOPAD(0x8e0, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       /* lcd_hsync.lcd_hsync */
-                       AM33XX_IOPAD(0x8e4, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       /* lcd_pclk.lcd_pclk */
-                       AM33XX_IOPAD(0x8e8, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       /* lcd_ac_bias_en.lcd_ac_bias_en */
-                       AM33XX_IOPAD(0x8ec, PIN_INPUT_PULLDOWN | MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PULL_DISABLE, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PULL_DISABLE, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PULL_DISABLE, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PULL_DISABLE, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PULL_DISABLE, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PULL_DISABLE, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PULL_DISABLE, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PULL_DISABLE, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PULL_DISABLE, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PULL_DISABLE, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PULL_DISABLE, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PULL_DISABLE, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PULL_DISABLE, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PULL_DISABLE, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PULL_DISABLE, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PULL_DISABLE, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_INPUT_PULLDOWN, MUX_MODE7)
                >;
        };
 };

diff --git a/arch/arm/boot/dts/am335x-shc.dts b/arch/arm/boot/dts/am335x-shc.dts
index bfbe27a..5b03685 100644 (file)
--- a/arch/arm/boot/dts/am335x-shc.dts
+++ b/arch/arm/boot/dts/am335x-shc.dts
@@ -382,193 +382,191 @@
        clkout2_pin: pinmux_clkout2_pin {
                pinctrl-single,pins = <
                        /* xdma_event_intr1.clkout2 */
-                       AM33XX_IOPAD(0x9b4, PIN_INPUT | MUX_MODE6)
+                       AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR1, PIN_INPUT, MUX_MODE6)
                >;
        };
 
        cpsw_default: cpsw_default {
                pinctrl-single,pins = <
                        /* Slave 1 */
-                       AM33XX_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE0)
-                       AM33XX_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE0)
-                       AM33XX_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE0)
-                       AM33XX_IOPAD(0x91c, PIN_OUTPUT_PULLDOWN | MUX_MODE0)
-                       AM33XX_IOPAD(0x920, PIN_OUTPUT_PULLDOWN | MUX_MODE0)
-                       AM33XX_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE0)
-                       AM33XX_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE0)
-                       AM33XX_IOPAD(0x92c, PIN_INPUT_PULLUP | MUX_MODE0)
-                       AM33XX_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE0)
-                       AM33XX_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE0)
-                       AM33XX_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE0)
-                       AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE0)
-                       AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE0)
                >;
        };
 
        cpsw_sleep: cpsw_sleep {
                pinctrl-single,pins = <
                        /* Slave 1 reset value */
-                       AM33XX_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x91c, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x920, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x92c, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7)
                >;
        };
 
        davinci_mdio_default: davinci_mdio_default {
                pinctrl-single,pins = <
-                       /* mdio_data.mdio_data */
-                       AM33XX_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)
-                       /* mdio_clk.mdio_clk */
-                       AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0)
                >;
        };
 
        davinci_mdio_sleep: davinci_mdio_sleep {
                pinctrl-single,pins = <
                        /* MDIO reset value */
-                       AM33XX_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7)
                >;
        };
 
        ehrpwm1_pins: pinmux_ehrpwm1 {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x84c, PIN_OUTPUT | MUX_MODE6) /* gpmc_a3.gpio1_19 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_OUTPUT, MUX_MODE6) /* gpmc_a3.gpio1_19 */
                >;
        };
 
        emmc_pins: pinmux_emmc_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x880, PIN_INPUT | MUX_MODE2)
-                       AM33XX_IOPAD(0x884, PIN_INPUT_PULLUP | MUX_MODE2)
-                       AM33XX_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE1)
-                       AM33XX_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE1)
-                       AM33XX_IOPAD(0x808, PIN_INPUT_PULLUP | MUX_MODE1)
-                       AM33XX_IOPAD(0x80c, PIN_INPUT_PULLUP | MUX_MODE1)
-                       AM33XX_IOPAD(0x810, PIN_INPUT_PULLUP | MUX_MODE1)
-                       AM33XX_IOPAD(0x814, PIN_INPUT_PULLUP | MUX_MODE1)
-                       AM33XX_IOPAD(0x818, PIN_INPUT_PULLUP | MUX_MODE1)
-                       AM33XX_IOPAD(0x81c, PIN_INPUT_PULLUP | MUX_MODE1)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_INPUT, MUX_MODE2)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_INPUT_PULLUP, MUX_MODE2)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE1)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE1)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE1)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE1)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE1)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE1)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE1)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE1)
                >;
        };
 
        i2c0_pins: pinmux_i2c0_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x988, PIN_INPUT | MUX_MODE0)
-                       AM33XX_IOPAD(0x98c, PIN_INPUT | MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT, MUX_MODE0)
                >;
        };
 
        mmc1_pins: pinmux_mmc1_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x960, PIN_INPUT | MUX_MODE5)
+                       AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT, MUX_MODE5)
                >;
        };
 
        mmc3_pins: pinmux_mmc3_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x830, PIN_INPUT | MUX_MODE3)
-                       AM33XX_IOPAD(0x834, PIN_INPUT | MUX_MODE3)
-                       AM33XX_IOPAD(0x838, PIN_INPUT | MUX_MODE3)
-                       AM33XX_IOPAD(0x83c, PIN_INPUT | MUX_MODE3)
-                       AM33XX_IOPAD(0x888, PIN_INPUT | MUX_MODE3)
-                       AM33XX_IOPAD(0x88c, PIN_INPUT | MUX_MODE3)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_INPUT, MUX_MODE3)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT, MUX_MODE3)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_INPUT, MUX_MODE3)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_INPUT, MUX_MODE3)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_CSN3, PIN_INPUT, MUX_MODE3)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_CLK, PIN_INPUT, MUX_MODE3)
                >;
        };
 
        uart0_pins: pinmux_uart0_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x968, PIN_INPUT_PULLDOWN | MUX_MODE0)
-                       AM33XX_IOPAD(0x96c, PIN_OUTPUT | MUX_MODE0)
-                       AM33XX_IOPAD(0x970, PIN_INPUT_PULLDOWN | MUX_MODE0)
-                       AM33XX_IOPAD(0x974, PIN_OUTPUT | MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_INPUT_PULLDOWN, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLDOWN, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT, MUX_MODE0)
                >;
        };
 
        uart1_pins: pinmux_uart1 {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x978, PIN_INPUT_PULLDOWN | MUX_MODE0)
-                       AM33XX_IOPAD(0x97C, PIN_OUTPUT | MUX_MODE0)
-                       AM33XX_IOPAD(0x980, PIN_INPUT | MUX_MODE0)
-                       AM33XX_IOPAD(0x984, PIN_OUTPUT | MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLDOWN, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT, MUX_MODE0)
                >;
        };
 
        uart2_pins: pinmux_uart2_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x950, PIN_INPUT | MUX_MODE1)
-                       AM33XX_IOPAD(0x954, PIN_OUTPUT | MUX_MODE1)
+                       AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT, MUX_MODE1)
+                       AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_OUTPUT, MUX_MODE1)
                >;
        };
 
        uart4_pins: pinmux_uart4_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE6)
-                       AM33XX_IOPAD(0x874, PIN_OUTPUT_PULLUP | MUX_MODE6)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE6)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_OUTPUT_PULLUP, MUX_MODE6)
                >;
        };
 
        user_leds_s0: user_leds_s0 {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x820, PIN_OUTPUT | MUX_MODE7)
-                       AM33XX_IOPAD(0x824, PIN_OUTPUT | MUX_MODE7)
-                       AM33XX_IOPAD(0x828, PIN_OUTPUT | MUX_MODE7)
-                       AM33XX_IOPAD(0x82c, PIN_OUTPUT | MUX_MODE7)
-                       AM33XX_IOPAD(0x840, PIN_OUTPUT | MUX_MODE7)
-                       AM33XX_IOPAD(0x844, PIN_OUTPUT | MUX_MODE7)
-                       AM33XX_IOPAD(0x848, PIN_OUTPUT | MUX_MODE7)
-                       AM33XX_IOPAD(0x850, PIN_OUTPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x854, PIN_OUTPUT | MUX_MODE7)
-                       AM33XX_IOPAD(0x858, PIN_OUTPUT | MUX_MODE7)
-                       AM33XX_IOPAD(0x85c, PIN_OUTPUT_PULLUP | MUX_MODE7)
-                       AM33XX_IOPAD(0x860, PIN_INPUT | MUX_MODE7)
-                       AM33XX_IOPAD(0x864, PIN_INPUT | MUX_MODE7)
-                       AM33XX_IOPAD(0x868, PIN_INPUT | MUX_MODE7)
-                       AM33XX_IOPAD(0x86c, PIN_INPUT | MUX_MODE7)
-                       AM33XX_IOPAD(0x878, PIN_OUTPUT_PULLUP | MUX_MODE7)
-                       AM33XX_IOPAD(0x87c, PIN_INPUT | MUX_MODE7)
-                       AM33XX_IOPAD(0x890, PIN_OUTPUT | MUX_MODE7)
-                       AM33XX_IOPAD(0x894, PIN_INPUT | MUX_MODE7)
-                       AM33XX_IOPAD(0x898, PIN_OUTPUT | MUX_MODE7)
-                       AM33XX_IOPAD(0x89c, PIN_OUTPUT | MUX_MODE7)
-                       AM33XX_IOPAD(0x8a0, PIN_OUTPUT | MUX_MODE7)
-                       AM33XX_IOPAD(0x8a4, PIN_OUTPUT | MUX_MODE7)
-                       AM33XX_IOPAD(0x8a8, PIN_OUTPUT | MUX_MODE7)
-                       AM33XX_IOPAD(0x8ac, PIN_OUTPUT | MUX_MODE7)
-                       AM33XX_IOPAD(0x8b0, PIN_OUTPUT | MUX_MODE7)
-                       AM33XX_IOPAD(0x8b4, PIN_OUTPUT | MUX_MODE7)
-                       AM33XX_IOPAD(0x8b8, PIN_OUTPUT | MUX_MODE7)
-                       AM33XX_IOPAD(0x8bc, PIN_OUTPUT | MUX_MODE7)
-                       AM33XX_IOPAD(0x8c0, PIN_OUTPUT | MUX_MODE7)
-                       AM33XX_IOPAD(0x8c4, PIN_OUTPUT | MUX_MODE7)
-                       AM33XX_IOPAD(0x8c8, PIN_OUTPUT | MUX_MODE7)
-                       AM33XX_IOPAD(0x8cc, PIN_OUTPUT | MUX_MODE7)
-                       AM33XX_IOPAD(0x8d0, PIN_OUTPUT | MUX_MODE7)
-                       AM33XX_IOPAD(0x8d4, PIN_OUTPUT | MUX_MODE7)
-                       AM33XX_IOPAD(0x8d8, PIN_OUTPUT | MUX_MODE7)
-                       AM33XX_IOPAD(0x8dc, PIN_OUTPUT | MUX_MODE7)
-                       AM33XX_IOPAD(0x8e0, PIN_OUTPUT | MUX_MODE7)
-                       AM33XX_IOPAD(0x8e4, PIN_OUTPUT | MUX_MODE7)
-                       AM33XX_IOPAD(0x8e8, PIN_OUTPUT | MUX_MODE7)
-                       AM33XX_IOPAD(0x8ec, PIN_OUTPUT | MUX_MODE7)
-                       AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x958, PIN_OUTPUT | MUX_MODE7)
-                       AM33XX_IOPAD(0x95c, PIN_OUTPUT | MUX_MODE7)
-                       AM33XX_IOPAD(0x964, PIN_OUTPUT_PULLUP | MUX_MODE7)
-                       AM33XX_IOPAD(0x9a0, PIN_OUTPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x9a4, PIN_OUTPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x9a8, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x9ac, PIN_INPUT_PULLUP | MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_OUTPUT, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_OUTPUT, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_OUTPUT, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_OUTPUT, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_OUTPUT, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_OUTPUT, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_OUTPUT, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_OUTPUT_PULLUP, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_INPUT, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_BEN1, PIN_OUTPUT_PULLUP, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_INPUT, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_OUTPUT, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_INPUT, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_WEN, PIN_OUTPUT, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_BEN0_CLE, PIN_OUTPUT, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_OUTPUT, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_OUTPUT, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_OUTPUT, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_OUTPUT, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_OUTPUT, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_ECAP0_IN_PWM0_OUT, PIN_OUTPUT_PULLUP, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKR, PIN_OUTPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MCASP0_FSR, PIN_OUTPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MCASP0_AXR1, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKX, PIN_INPUT_PULLUP, MUX_MODE7)
                >;
        };
 };

diff --git a/arch/arm/boot/dts/am335x-sl50.dts b/arch/arm/boot/dts/am335x-sl50.dts
index 38d57b8..1ac0c8a 100644 (file)
--- a/arch/arm/boot/dts/am335x-sl50.dts
+++ b/arch/arm/boot/dts/am335x-sl50.dts
@@ -218,227 +218,227 @@
 
        audio_pins: pinmux_audio_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x9ac, PIN_INPUT_PULLDOWN | MUX_MODE0)     /* mcasp0_ahcklx.mcasp0_ahclkx */
-                       AM33XX_IOPAD(0x994, PIN_INPUT_PULLDOWN | MUX_MODE0)     /* mcasp0_fsx.mcasp0_fsx */
-                       AM33XX_IOPAD(0x990, PIN_INPUT_PULLDOWN | MUX_MODE0)     /* mcasp0_aclkx.mcasp0_aclkx */
-                       AM33XX_IOPAD(0x998, PIN_INPUT_PULLDOWN | MUX_MODE0)     /* mcasp0_axr0.mcasp0_axr0 */
-                       AM33XX_IOPAD(0x99c, PIN_OUTPUT_PULLDOWN | MUX_MODE2)    /* mcasp0_ahclkr.mcasp0_axr2 */
+                       AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKX, PIN_INPUT_PULLDOWN, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MCASP0_FSX, PIN_INPUT_PULLDOWN, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKX, PIN_INPUT_PULLDOWN, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MCASP0_AXR0, PIN_INPUT_PULLDOWN, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKR, PIN_OUTPUT_PULLDOWN, MUX_MODE2)
                >;
        };
 
        audio_pa_pins: pinmux_audio_pa_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x9a0, PIN_INPUT_PULLDOWN | MUX_MODE7)     /* SoundPA_en - mcasp0_aclkr.gpio3_18 */
+                       AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKR, PIN_INPUT_PULLDOWN, MUX_MODE7)  /* SoundPA_en - mcasp0_aclkr.gpio3_18 */
                >;
        };
 
        audio_mclk_pins: pinmux_audio_mclk_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x86c, PIN_INPUT_PULLDOWN | MUX_MODE7)     /* gpmc_a11.gpio1_27 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE7)      /* gpmc_a11.gpio1_27 */
                >;
        };
 
        backlight0_pins: pinmux_backlight0_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x898, PIN_OUTPUT | MUX_MODE7)     /* gpmc_wen.gpio2_4 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_WEN, PIN_OUTPUT, MUX_MODE7)      /* gpmc_wen.gpio2_4 */
                >;
        };
 
        backlight1_pins: pinmux_backlight1_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x828, PIN_OUTPUT | MUX_MODE7)     /* gpmc_ad10.gpio0_26 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_OUTPUT, MUX_MODE7)     /* gpmc_ad10.gpio0_26 */
                >;
        };
 
        lcd_pins: pinmux_lcd_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x8a0, PIN_OUTPUT | MUX_MODE0)     /* lcd_data0.lcd_data0 */
-                       AM33XX_IOPAD(0x8a4, PIN_OUTPUT | MUX_MODE0)     /* lcd_data1.lcd_data1 */
-                       AM33XX_IOPAD(0x8a8, PIN_OUTPUT | MUX_MODE0)     /* lcd_data2.lcd_data2 */
-                       AM33XX_IOPAD(0x8ac, PIN_OUTPUT | MUX_MODE0)     /* lcd_data3.lcd_data3 */
-                       AM33XX_IOPAD(0x8b0, PIN_OUTPUT | MUX_MODE0)     /* lcd_data4.lcd_data4 */
-                       AM33XX_IOPAD(0x8b4, PIN_OUTPUT | MUX_MODE0)     /* lcd_data5.lcd_data5 */
-                       AM33XX_IOPAD(0x8b8, PIN_OUTPUT | MUX_MODE0)     /* lcd_data6.lcd_data6 */
-                       AM33XX_IOPAD(0x8bc, PIN_OUTPUT | MUX_MODE0)     /* lcd_data7.lcd_data7 */
-                       AM33XX_IOPAD(0x8c0, PIN_OUTPUT | MUX_MODE0)     /* lcd_data8.lcd_data8 */
-                       AM33XX_IOPAD(0x8c4, PIN_OUTPUT | MUX_MODE0)     /* lcd_data9.lcd_data9 */
-                       AM33XX_IOPAD(0x8c8, PIN_OUTPUT | MUX_MODE0)     /* lcd_data10.lcd_data10 */
-                       AM33XX_IOPAD(0x8cc, PIN_OUTPUT | MUX_MODE0)     /* lcd_data11.lcd_data11 */
-                       AM33XX_IOPAD(0x8d0, PIN_OUTPUT | MUX_MODE0)     /* lcd_data12.lcd_data12 */
-                       AM33XX_IOPAD(0x8d4, PIN_OUTPUT | MUX_MODE0)     /* lcd_data13.lcd_data13 */
-                       AM33XX_IOPAD(0x8d8, PIN_OUTPUT | MUX_MODE0)     /* lcd_data14.lcd_data14 */
-                       AM33XX_IOPAD(0x8dc, PIN_OUTPUT | MUX_MODE0)     /* lcd_data15.lcd_data15 */
-                       AM33XX_IOPAD(0x8e0, PIN_OUTPUT_PULLDOWN | MUX_MODE0)    /* lcd_vsync.lcd_vsync */
-                       AM33XX_IOPAD(0x8e4, PIN_OUTPUT_PULLDOWN | MUX_MODE0)    /* lcd_hsync.lcd_hsync */
-                       AM33XX_IOPAD(0x8e8, PIN_OUTPUT_PULLDOWN | MUX_MODE0)    /* lcd_pclk.lcd_pclk */
-                       AM33XX_IOPAD(0x8ec, PIN_OUTPUT_PULLDOWN | MUX_MODE0)    /* lcd_ac_bias_en.lcd_ac_bias_en */
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
                >;
        };
 
        led_pins: pinmux_led_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x854, PIN_OUTPUT | MUX_MODE7)     /* gpmc_a5.gpio1_21 */
-                       AM33XX_IOPAD(0x858, PIN_OUTPUT | MUX_MODE7)     /* gpmc_a6.gpio1_22 */
-                       AM33XX_IOPAD(0x85c, PIN_OUTPUT | MUX_MODE7)     /* gpmc_a7.gpio1_23 */
-                       AM33XX_IOPAD(0x860, PIN_OUTPUT | MUX_MODE7)     /* gpmc_a8.gpio1_24 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT, MUX_MODE7)       /* gpmc_a5.gpio1_21 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_OUTPUT, MUX_MODE7)       /* gpmc_a6.gpio1_22 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_OUTPUT, MUX_MODE7)       /* gpmc_a7.gpio1_23 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_OUTPUT, MUX_MODE7)       /* gpmc_a8.gpio1_24 */
                >;
        };
 
        uart0_pins: pinmux_uart0_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0)       /* uart0_rxd.uart0_rxd */
-                       AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0)    /* uart0_txd.uart0_txd */
+                       AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
                >;
        };
 
        uart1_pins: pinmux_uart1_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x980, PIN_INPUT_PULLUP | MUX_MODE0)       /* uart1_rxd.uart1_rxd */
-                       AM33XX_IOPAD(0x984, PIN_OUTPUT_PULLDOWN | MUX_MODE0)    /* uart1_txd.uart1_txd */
+                       AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
                >;
        };
 
        uart4_pins: pinmux_uart4_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE6)       /* gpmc_wait0.uart4_rxd */
-                       AM33XX_IOPAD(0x874, PIN_OUTPUT_PULLDOWN | MUX_MODE6)    /* gpmc_wpn.uart4_txd */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE6)      /* gpmc_wait0.uart4_rxd */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_OUTPUT_PULLDOWN, MUX_MODE6)     /* gpmc_wpn.uart4_txd */
                >;
        };
 
        i2c0_pins: pinmux_i2c0_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x988, PIN_INPUT_PULLUP | MUX_MODE0)       /* i2c0_sda.i2c0_sda */
-                       AM33XX_IOPAD(0x98c, PIN_INPUT_PULLUP | MUX_MODE0)       /* i2c0_scl.i2c0_scl */
+                       AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0)
                >;
        };
 
        i2c2_pins: pinmux_i2c2_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x978, PIN_INPUT_PULLUP | MUX_MODE3)       /* uart1_ctsn.i2c2_sda */
-                       AM33XX_IOPAD(0x97c, PIN_INPUT_PULLUP | MUX_MODE3)       /* uart1_rtsn.i2c2_scl */
+                       AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLUP, MUX_MODE3)      /* uart1_ctsn.i2c2_sda */
+                       AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_INPUT_PULLUP, MUX_MODE3)      /* uart1_rtsn.i2c2_scl */
                >;
        };
 
        cpsw_default: cpsw_default {
                pinctrl-single,pins = <
                        /* Slave 1 */
-                       AM33XX_IOPAD(0x910, PIN_INPUT_PULLUP | MUX_MODE0)       /* mii1_rxerr.mii1_rxerr */
-                       AM33XX_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE0)    /* mii1_txen.mii1_txen */
-                       AM33XX_IOPAD(0x918, PIN_INPUT_PULLUP | MUX_MODE0)       /* mii1_rxdv.mii1_rxdv */
-                       AM33XX_IOPAD(0x91c, PIN_OUTPUT_PULLDOWN | MUX_MODE0)    /* mii1_txd3.mii1_txd3 */
-                       AM33XX_IOPAD(0x920, PIN_OUTPUT_PULLDOWN | MUX_MODE0)    /* mii1_txd2.mii1_txd2 */
-                       AM33XX_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE0)    /* mii1_txd1.mii1_txd1 */
-                       AM33XX_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE0)    /* mii1_txd0.mii1_txd0 */
-                       AM33XX_IOPAD(0x92c, PIN_INPUT_PULLUP | MUX_MODE0)       /* mii1_txclk.mii1_txclk */
-                       AM33XX_IOPAD(0x930, PIN_INPUT_PULLUP | MUX_MODE0)       /* mii1_rxclk.mii1_rxclk */
-                       AM33XX_IOPAD(0x934, PIN_INPUT_PULLUP | MUX_MODE0)       /* mii1_rxd3.mii1_rxd3 */
-                       AM33XX_IOPAD(0x938, PIN_INPUT_PULLUP | MUX_MODE0)       /* mii1_rxd2.mii1_rxd2 */
-                       AM33XX_IOPAD(0x93c, PIN_INPUT_PULLUP | MUX_MODE0)       /* mii1_rxd1.mii1_rxd1 */
-                       AM33XX_IOPAD(0x940, PIN_INPUT_PULLUP | MUX_MODE0)       /* mii1_rxd0.mii1_rxd0 */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLUP, MUX_MODE0)
                >;
        };
 
        cpsw_sleep: cpsw_sleep {
                pinctrl-single,pins = <
                        /* Slave 1 reset value */
-                       AM33XX_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x91c, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x920, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x92c, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7)
                >;
        };
 
        davinci_mdio_default: davinci_mdio_default {
                pinctrl-single,pins = <
                        /* MDIO */
-                       AM33XX_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)       /* mdio_data.mdio_data */
-                       AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0)                      /* mdio_clk.mdio_clk */
+                       AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0)
                        /* Ethernet */
-                       AM33XX_IOPAD(0x838, PIN_INPUT_PULLUP | MUX_MODE7)       /* Ethernet_nRST - gpmc_ad14.gpio1_14 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_INPUT_PULLUP, MUX_MODE7)       /* Ethernet_nRST - gpmc_ad14.gpio1_14 */
                >;
        };
 
        davinci_mdio_sleep: davinci_mdio_sleep {
                pinctrl-single,pins = <
                        /* MDIO reset value */
-                       AM33XX_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7)
                >;
        };
 
        mmc1_pins: pinmux_mmc1_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x96c, PIN_INPUT | MUX_MODE7)              /* uart0_rtsn.gpio1_9 */
+                       AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT, MUX_MODE7)             /* uart0_rtsn.gpio1_9 */
                >;
        };
 
        emmc_pwrseq_pins: pinmux_emmc_pwrseq_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x850, PIN_OUTPUT_PULLUP | MUX_MODE7)      /* gpmc_a4.gpio1_20 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT_PULLUP, MUX_MODE7)        /* gpmc_a4.gpio1_20 */
                >;
        };
 
        emmc_pins: pinmux_emmc_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x880, PIN_INPUT_PULLUP | MUX_MODE2)       /* gpmc_csn1.mmc1_clk */
-                       AM33XX_IOPAD(0x884, PIN_INPUT_PULLUP | MUX_MODE2)       /* gpmc_csn2.mmc1_cmd */
-                       AM33XX_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE1)       /* gpmc_ad0.mmc1_dat0 */
-                       AM33XX_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE1)       /* gpmc_ad1.mmc1_dat1 */
-                       AM33XX_IOPAD(0x808, PIN_INPUT_PULLUP | MUX_MODE1)       /* gpmc_ad2.mmc1_dat2 */
-                       AM33XX_IOPAD(0x80c, PIN_INPUT_PULLUP | MUX_MODE1)       /* gpmc_ad3.mmc1_dat3 */
-                       AM33XX_IOPAD(0x810, PIN_INPUT_PULLUP | MUX_MODE1)       /* gpmc_ad4.mmc1_dat4 */
-                       AM33XX_IOPAD(0x814, PIN_INPUT_PULLUP | MUX_MODE1)       /* gpmc_ad5.mmc1_dat5 */
-                       AM33XX_IOPAD(0x818, PIN_INPUT_PULLUP | MUX_MODE1)       /* gpmc_ad6.mmc1_dat6 */
-                       AM33XX_IOPAD(0x81c, PIN_INPUT_PULLUP | MUX_MODE1)       /* gpmc_ad7.mmc1_dat7 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_INPUT_PULLUP, MUX_MODE2)       /* gpmc_csn1.mmc1_clk */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_INPUT_PULLUP, MUX_MODE2)       /* gpmc_csn2.mmc1_cmd */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE1)        /* gpmc_ad0.mmc1_dat0 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE1)        /* gpmc_ad1.mmc1_dat1 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE1)        /* gpmc_ad2.mmc1_dat2 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE1)        /* gpmc_ad3.mmc1_dat3 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE1)        /* gpmc_ad4.mmc1_dat4 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE1)        /* gpmc_ad5.mmc1_dat5 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE1)        /* gpmc_ad6.mmc1_dat6 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE1)        /* gpmc_ad7.mmc1_dat7 */
                >;
        };
 
        ehrpwm1_pins: pinmux_ehrpwm1a_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x848, PIN_OUTPUT | MUX_MODE6)     /* gpmc_a2.ehrpwm1a */
-                       AM33XX_IOPAD(0x84c, PIN_OUTPUT | MUX_MODE6)     /* gpmc_a3.ehrpwm1b */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_OUTPUT, MUX_MODE6)       /* gpmc_a2.ehrpwm1a */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_OUTPUT, MUX_MODE6)       /* gpmc_a3.ehrpwm1b */
                >;
        };
 
        rtc0_irq_pins: pinmux_rtc0_irq_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x824, PIN_INPUT_PULLUP | MUX_MODE7)     /* gpmc_ad9.gpio0_23 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_INPUT_PULLUP, MUX_MODE7)     /* gpmc_ad9.gpio0_23 */
                >;
        };
 
        spi0_pins: pinmux_spi0_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x954, PIN_INPUT_PULLUP | MUX_MODE0)       /* SPI0_MOSI - spi0_d0.spi0_d0 */
-                       AM33XX_IOPAD(0x958, PIN_INPUT_PULLUP | MUX_MODE0)       /* SPI0_MISO - spi0_d1.spi0_d1 */
-                       AM33XX_IOPAD(0x950, PIN_INPUT_PULLUP | MUX_MODE0)       /* SPI0_CLK  - spi0_clk.spi0_clk */
-                       AM33XX_IOPAD(0x95c, PIN_INPUT_PULLUP | MUX_MODE0)       /* SPI0_CS0 (NBATTSS) - spi0_cs0.spi0_cs0 */
-                       AM33XX_IOPAD(0x960, PIN_INPUT_PULLUP | MUX_MODE0)       /* SPI0_CS1 (FPGA_FLASH_NCS) - spi0_cs1.spi0_cs1 */
+                       AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_INPUT_PULLUP, MUX_MODE0) /* SPI0_MOSI */
+                       AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT_PULLUP, MUX_MODE0) /* SPI0_MISO */
+                       AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT_PULLUP, MUX_MODE0)        /* SPI0_CS0 (NBATTSS) */
+                       AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT_PULLUP, MUX_MODE0)        /* SPI0_CS1 (FPGA_FLASH_NCS) */
                >;
        };
 
        lwb_pins: pinmux_lwb_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x830, PIN_INPUT_PULLUP | MUX_MODE7)       /* nKbdInt - gpmc_ad12.gpio1_12 */
-                       AM33XX_IOPAD(0x834, PIN_INPUT_PULLUP | MUX_MODE7)       /* nKbdReset - gpmc_ad13.gpio1_13 */
-                       AM33XX_IOPAD(0x844, PIN_INPUT_PULLUP | MUX_MODE7)       /* USB1_enPower - gpmc_a1.gpio1_17 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_INPUT_PULLUP, MUX_MODE7)       /* nKbdInt - gpmc_ad12.gpio1_12 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT_PULLUP, MUX_MODE7)       /* nKbdReset - gpmc_ad13.gpio1_13 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLUP, MUX_MODE7) /* USB1_enPower - gpmc_a1.gpio1_17 */
                        /* PDI Bus - Battery system */
-                       AM33XX_IOPAD(0x840, PIN_INPUT_PULLUP | MUX_MODE7)       /* nBattReset  gpmc_a0.gpio1_16 */
-                       AM33XX_IOPAD(0x83c, PIN_INPUT_PULLUP | MUX_MODE7)       /* BattPDIData gpmc_ad15.gpio1_15 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_INPUT_PULLUP, MUX_MODE7) /* nBattReset  gpmc_a0.gpio1_16 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_INPUT_PULLUP, MUX_MODE7)       /* BattPDIData gpmc_ad15.gpio1_15 */
                        /* FPGA */
-                       AM33XX_IOPAD(0x820, PIN_INPUT_PULLUP | MUX_MODE7)       /* FPGA_DONE - gpmc_ad8.gpio0_22 */
-                       AM33XX_IOPAD(0x840, PIN_INPUT_PULLUP | MUX_MODE7)       /* FPGA_NRST - gpmc_a0.gpio1_16 */
-                       AM33XX_IOPAD(0x844, PIN_INPUT_PULLDOWN | MUX_MODE7)     /* FPGA_RUN - gpmc_a1.gpio1_17 */
-                       AM33XX_IOPAD(0x864, PIN_INPUT_PULLUP | MUX_MODE7)       /* ENFPGA - gpmc_a9.gpio1_25 */
-                       AM33XX_IOPAD(0x868, PIN_INPUT_PULLDOWN | MUX_MODE7)     /* FPGA_PROGRAM - gpmc_a10.gpio1_26 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_INPUT_PULLUP, MUX_MODE7)        /* FPGA_DONE - gpmc_ad8.gpio0_22 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_INPUT_PULLUP, MUX_MODE7) /* FPGA_NRST - gpmc_a0.gpio1_16 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLDOWN, MUX_MODE7)       /* FPGA_RUN - gpmc_a1.gpio1_17 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLUP, MUX_MODE7) /* ENFPGA - gpmc_a9.gpio1_25 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE7)      /* FPGA_PROGRAM - gpmc_a10.gpio1_26 */
                >;
        };
 };

diff --git a/arch/arm/boot/dts/am335x-wega.dtsi b/arch/arm/boot/dts/am335x-wega.dtsi
index 8ce5417..b7d28a2 100644 (file)
--- a/arch/arm/boot/dts/am335x-wega.dtsi
+++ b/arch/arm/boot/dts/am335x-wega.dtsi
@@ -32,11 +32,11 @@
 &am33xx_pinmux {
        mcasp0_pins: pinmux_mcasp0 {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x9AC, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp0_ahclkx.mcasp0_ahclkx */
-                       AM33XX_IOPAD(0x990, PIN_INPUT_PULLDOWN | MUX_MODE0)  /* mcasp0_aclkx.mcasp0_aclkx */
-                       AM33XX_IOPAD(0x994, PIN_INPUT_PULLDOWN | MUX_MODE0)  /* mcasp0_fsx.mcasp0_fsx */
-                       AM33XX_IOPAD(0x998, PIN_INPUT_PULLDOWN | MUX_MODE0)  /* mcasp0_axr0.mcasp0_axr0 */
-                       AM33XX_IOPAD(0x9A8, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp0_axr1.mcasp0_axr1 */
+                       AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKX, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKX, PIN_INPUT_PULLDOWN, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MCASP0_FSX, PIN_INPUT_PULLDOWN, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MCASP0_AXR0, PIN_INPUT_PULLDOWN, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MCASP0_AXR1, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
                >;
        };
 };
@@ -84,8 +84,8 @@
 &am33xx_pinmux {
        dcan1_pins: pinmux_dcan1 {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x968, PIN_OUTPUT_PULLUP | MUX_MODE2) /* uart0_ctsn.d_can1_tx */
-                       AM33XX_IOPAD(0x96c, PIN_INPUT_PULLUP | MUX_MODE2) /* uart0_rtsn.d_can1_rx */
+                       AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_OUTPUT_PULLUP, MUX_MODE2) /* uart0_ctsn.d_can1_tx */
+                       AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT_PULLUP, MUX_MODE2) /* uart0_rtsn.d_can1_rx */
                >;
        };
 };
@@ -100,20 +100,20 @@
 &am33xx_pinmux {
        ethernet1_pins: pinmux_ethernet1 {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x840, PIN_OUTPUT | MUX_MODE1)             /* gpmc_a0.mii2_txen */
-                       AM33XX_IOPAD(0x844, PIN_INPUT_PULLDOWN | MUX_MODE1)     /* gpmc_a1.mii2_rxdv */
-                       AM33XX_IOPAD(0x848, PIN_OUTPUT | MUX_MODE1)             /* gpmc_a2.mii2_txd3 */
-                       AM33XX_IOPAD(0x84c, PIN_OUTPUT | MUX_MODE1)             /* gpmc_a3.mii2_txd2 */
-                       AM33XX_IOPAD(0x850, PIN_OUTPUT | MUX_MODE1)             /* gpmc_a4.mii2_txd1 */
-                       AM33XX_IOPAD(0x854, PIN_OUTPUT | MUX_MODE1)             /* gpmc_a5.mii2_txd0 */
-                       AM33XX_IOPAD(0x858, PIN_INPUT_PULLDOWN | MUX_MODE1)     /* gpmc_a6.mii2_txclk */
-                       AM33XX_IOPAD(0x85c, PIN_INPUT_PULLDOWN | MUX_MODE1)     /* gpmc_a7.mii2_rxclk */
-                       AM33XX_IOPAD(0x860, PIN_INPUT_PULLDOWN | MUX_MODE1)     /* gpmc_a8.mii2_rxd3 */
-                       AM33XX_IOPAD(0x864, PIN_INPUT_PULLDOWN | MUX_MODE1)     /* gpmc_a9.mii2_rxd2 */
-                       AM33XX_IOPAD(0x868, PIN_INPUT_PULLDOWN | MUX_MODE1)     /* gpmc_a10.mii2_rxd1 */
-                       AM33XX_IOPAD(0x86c, PIN_INPUT_PULLDOWN | MUX_MODE1)     /* gpmc_a11.mii2_rxd0 */
-                       AM33XX_IOPAD(0x874, PIN_INPUT_PULLDOWN | MUX_MODE1)     /* gpmc_wpn.mii2_rxerr */
-                       AM33XX_IOPAD(0x878, PIN_INPUT_PULLDOWN | MUX_MODE1)     /* gpmc_ben1.mii2_col */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT, MUX_MODE1)               /* gpmc_a0.mii2_txen */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLDOWN, MUX_MODE1)       /* gpmc_a1.mii2_rxdv */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_OUTPUT, MUX_MODE1)               /* gpmc_a2.mii2_txd3 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_OUTPUT, MUX_MODE1)               /* gpmc_a3.mii2_txd2 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT, MUX_MODE1)               /* gpmc_a4.mii2_txd1 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT, MUX_MODE1)               /* gpmc_a5.mii2_txd0 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_INPUT_PULLDOWN, MUX_MODE1)       /* gpmc_a6.mii2_txclk */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_INPUT_PULLDOWN, MUX_MODE1)       /* gpmc_a7.mii2_rxclk */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_INPUT_PULLDOWN, MUX_MODE1)       /* gpmc_a8.mii2_rxd3 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLDOWN, MUX_MODE1)       /* gpmc_a9.mii2_rxd2 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE1)      /* gpmc_a10.mii2_rxd1 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE1)      /* gpmc_a11.mii2_rxd0 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLDOWN, MUX_MODE1)      /* gpmc_wpn.mii2_rxerr */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_BEN1, PIN_INPUT_PULLDOWN, MUX_MODE1)     /* gpmc_ben1.mii2_col */
                >;
        };
 };
@@ -141,13 +141,13 @@
 &am33xx_pinmux {
        mmc1_pins: pinmux_mmc1 {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x8f0, PIN_INPUT_PULLUP | MUX_MODE0)       /* mmc0_dat3.mmc0_dat3 */
-                       AM33XX_IOPAD(0x8f4, PIN_INPUT_PULLUP | MUX_MODE0)       /* mmc0_dat2.mmc0_dat2 */
-                       AM33XX_IOPAD(0x8f8, PIN_INPUT_PULLUP | MUX_MODE0)       /* mmc0_dat1.mmc0_dat1 */
-                       AM33XX_IOPAD(0x8fc, PIN_INPUT_PULLUP | MUX_MODE0)       /* mmc0_dat0.mmc0_dat0 */
-                       AM33XX_IOPAD(0x900, PIN_INPUT_PULLUP | MUX_MODE0)       /* mmc0_clk.mmc0_clk */
-                       AM33XX_IOPAD(0x904, PIN_INPUT_PULLUP | MUX_MODE0)       /* mmc0_cmd.mmc0_cmd */
-                       AM33XX_IOPAD(0x960, PIN_INPUT_PULLUP | MUX_MODE7)       /* spi0_cs1.mmc0_sdcd */
+                       AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT_PULLUP, MUX_MODE7)        /* spi0_cs1.mmc0_sdcd */
                >;
        };
 };
@@ -171,17 +171,17 @@
 &am33xx_pinmux {
        uart0_pins: pinmux_uart0 {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0)    /* uart0_rxd.uart0_rxd */
-                       AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
+                       AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
                >;
        };
 
        uart1_pins: pinmux_uart1_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x980, PIN_INPUT_PULLUP | MUX_MODE0)       /* uart1_rxd.uart1_rxd */
-                       AM33XX_IOPAD(0x984, PIN_OUTPUT_PULLDOWN | MUX_MODE0)    /* uart1_txd.uart1_txd */
-                       AM33XX_IOPAD(0x978, PIN_INPUT | MUX_MODE0)              /* uart1_ctsn.uart1_ctsn */
-                       AM33XX_IOPAD(0x97c, PIN_OUTPUT_PULLDOWN | MUX_MODE0)    /* uart1_rtsn.uart1_rtsn */
+                       AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
                >;
        };
 };

diff --git a/arch/arm/boot/dts/am43x-epos-evm.dts b/arch/arm/boot/dts/am43x-epos-evm.dts
index 9dfd80e..9b8b132 100644 (file)
--- a/arch/arm/boot/dts/am43x-epos-evm.dts
+++ b/arch/arm/boot/dts/am43x-epos-evm.dts
@@ -80,6 +80,7 @@
                pinctrl-names = "default", "sleep";
                pinctrl-0 = <&matrix_keypad_default>;
                pinctrl-1 = <&matrix_keypad_sleep>;
+               wakeup-source;
 
                row-gpios = <&gpio0 12 GPIO_ACTIVE_HIGH         /* Bank0, pin12 */
                             &gpio0 13 GPIO_ACTIVE_HIGH         /* Bank0, pin13 */
@@ -620,6 +621,12 @@
                        regulator-name = "vdcdc3";
                        regulator-boot-on;
                        regulator-always-on;
+                       regulator-state-mem {
+                               regulator-on-in-suspend;
+                       };
+                       regulator-state-disk {
+                               regulator-off-in-suspend;
+                       };
                };
 
                dcdc4: regulator-dcdc4 {
@@ -634,12 +641,16 @@
                        regulator-name = "v1_0bat";
                        regulator-min-microvolt = <1000000>;
                        regulator-max-microvolt = <1000000>;
+                       regulator-boot-on;
+                       regulator-always-on;
                };
 
                dcdc6: regulator-dcdc6 {
                        regulator-name = "v1_8bat";
                        regulator-min-microvolt = <1800000>;
                        regulator-max-microvolt = <1800000>;
+                       regulator-boot-on;
+                       regulator-always-on;
                };
 
                ldo1: regulator-ldo1 {

diff --git a/arch/arm/boot/dts/am5718.dtsi b/arch/arm/boot/dts/am5718.dtsi
new file mode 100644 (file)
index 0000000..d51007c
--- /dev/null
+++ b/arch/arm/boot/dts/am5718.dtsi
@@ -0,0 +1,32 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
+ */
+
+#include "dra72x.dtsi"
+
+/ {
+       compatible = "ti,am5718", "ti,dra7";
+};
+
+/*
+ * These modules are not present on AM5718
+ *
+ * ATL
+ * VCP1, VCP2
+ * MLB
+ * ISS
+ * USB3, USB4
+ */
+
+&usb3_tm {
+       status = "disabled";
+};
+
+&usb4_tm {
+       status = "disabled";
+};
+
+&atl_tm {
+       status = "disabled";
+};

diff --git a/arch/arm/boot/dts/am571x-idk.dts b/arch/arm/boot/dts/am571x-idk.dts
index 6432309..66116ad 100644 (file)
--- a/arch/arm/boot/dts/am571x-idk.dts
+++ b/arch/arm/boot/dts/am571x-idk.dts
@@ -7,7 +7,7 @@
  */
 /dts-v1/;
 
-#include "dra72x.dtsi"
+#include "am5718.dtsi"
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/interrupt-controller/irq.h>
 #include "dra7-mmc-iodelay.dtsi"

diff --git a/arch/arm/boot/dts/am5728.dtsi b/arch/arm/boot/dts/am5728.dtsi
new file mode 100644 (file)
index 0000000..82e5427
--- /dev/null
+++ b/arch/arm/boot/dts/am5728.dtsi
@@ -0,0 +1,33 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
+ */
+
+#include "dra74x.dtsi"
+
+/ {
+       compatible = "ti,am5728", "ti,dra7";
+};
+
+/*
+ * These modules are not present on AM5728
+ *
+ * EVE1, EVE2
+ * ATL
+ * VCP1, VCP2
+ * MLB
+ * ISS
+ * USB3, USB4
+ */
+
+&usb3_tm {
+       status = "disabled";
+};
+
+&usb4_tm {
+       status = "disabled";
+};
+
+&atl_tm {
+       status = "disabled";
+};

diff --git a/arch/arm/boot/dts/am572x-idk.dts b/arch/arm/boot/dts/am572x-idk.dts
index b2fb6e0..4f83522 100644 (file)
--- a/arch/arm/boot/dts/am572x-idk.dts
+++ b/arch/arm/boot/dts/am572x-idk.dts
@@ -8,15 +8,14 @@
 
 /dts-v1/;
 
-#include "dra74x.dtsi"
+#include "am5728.dtsi"
 #include "dra7-mmc-iodelay.dtsi"
 #include "dra74x-mmc-iodelay.dtsi"
 #include "am572x-idk-common.dtsi"
 
 / {
        model = "TI AM5728 IDK";
-       compatible = "ti,am5728-idk", "ti,am5728", "ti,dra742", "ti,dra74",
-                    "ti,dra7";
+       compatible = "ti,am5728-idk", "ti,am5728", "ti,dra7";
 };
 
 &mmc1 {

diff --git a/arch/arm/boot/dts/am5748.dtsi b/arch/arm/boot/dts/am5748.dtsi
new file mode 100644 (file)
index 0000000..5e12975
--- /dev/null
+++ b/arch/arm/boot/dts/am5748.dtsi
@@ -0,0 +1,33 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
+ */
+
+#include "dra76x.dtsi"
+
+/ {
+       compatible = "ti,am5748", "ti,dra762", "ti,dra7";
+};
+
+/*
+ * These modules are not present on AM5748
+ *
+ * EVE1, EVE2
+ * ATL
+ * VCP1, VCP2
+ * MLB
+ * ISS
+ * USB3, USB4
+ */
+
+&usb3_tm {
+       status = "disabled";
+};
+
+&usb4_tm {
+       status = "disabled";
+};
+
+&atl_tm {
+       status = "disabled";
+};

diff --git a/arch/arm/boot/dts/am574x-idk.dts b/arch/arm/boot/dts/am574x-idk.dts
index 378dfa7..dc5141c 100644 (file)
--- a/arch/arm/boot/dts/am574x-idk.dts
+++ b/arch/arm/boot/dts/am574x-idk.dts
@@ -6,14 +6,14 @@
 
 /dts-v1/;
 
-#include "dra76x.dtsi"
+#include "am5748.dtsi"
 #include "dra7-mmc-iodelay.dtsi"
 #include "dra76x-mmc-iodelay.dtsi"
 #include "am572x-idk-common.dtsi"
 
 / {
        model = "TI AM5748 IDK";
-       compatible = "ti,am5728-idk", "ti,dra762", "ti,dra7";
+       compatible = "ti,am5748-idk", "ti,am5748", "ti,dra762", "ti,dra7";
 };
 
 &qspi {

diff --git a/arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi b/arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi
index 1e6620f..2341a56 100644 (file)
--- a/arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi
+++ b/arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi
@@ -7,7 +7,7 @@
  */
 /dts-v1/;
 
-#include "dra74x.dtsi"
+#include "am5728.dtsi"
 #include "am57xx-commercial-grade.dtsi"
 #include "dra74x-mmc-iodelay.dtsi"
 #include <dt-bindings/gpio/gpio.h>

diff --git a/arch/arm/boot/dts/am57xx-cl-som-am57x.dts b/arch/arm/boot/dts/am57xx-cl-som-am57x.dts
index 4748ce8..0460de0 100644 (file)
--- a/arch/arm/boot/dts/am57xx-cl-som-am57x.dts
+++ b/arch/arm/boot/dts/am57xx-cl-som-am57x.dts
@@ -13,7 +13,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/interrupt-controller/irq.h>
-#include "dra74x.dtsi"
+#include "am5728.dtsi"
 
 / {
        model = "CompuLab CL-SOM-AM57x";

diff --git a/arch/arm/boot/dts/armada-38x.dtsi b/arch/arm/boot/dts/armada-38x.dtsi
index 96c1870..3f4bb44 100644 (file)
--- a/arch/arm/boot/dts/armada-38x.dtsi
+++ b/arch/arm/boot/dts/armada-38x.dtsi
@@ -415,6 +415,8 @@
                                reg = <0x20300 0x34>, <0x20704 0x4>, <0x18260 0x4>;
                                clocks = <&coreclk 2>, <&refclk>;
                                clock-names = "nbclk", "fixed";
+                               interrupts-extended = <&gic GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
+                                                     <&gic GIC_SPI  9 IRQ_TYPE_LEVEL_HIGH>;
                        };
 
                        cpurst: cpurst@20800 {

diff --git a/arch/arm/boot/dts/aspeed-ast2500-evb.dts b/arch/arm/boot/dts/aspeed-ast2500-evb.dts
index 2375449..556ed46 100644 (file)
--- a/arch/arm/boot/dts/aspeed-ast2500-evb.dts
+++ b/arch/arm/boot/dts/aspeed-ast2500-evb.dts
@@ -13,12 +13,25 @@
 
        chosen {
                stdout-path = &uart5;
-               bootargs = "console=ttyS4,115200 earlyprintk";
+               bootargs = "console=tty0 console=ttyS4,115200 earlyprintk";
        };
 
        memory@80000000 {
                reg = <0x80000000 0x20000000>;
        };
+
+       reserved-memory {
+               #address-cells = <1>;
+               #size-cells = <1>;
+               ranges;
+
+               gfx_memory: framebuffer {
+                       size = <0x01000000>;
+                       alignment = <0x01000000>;
+                       compatible = "shared-dma-pool";
+                       reusable;
+               };
+       };
 };
 
 &fmc {
@@ -27,6 +40,7 @@
                status = "okay";
                m25p,fast-read;
                label = "bmc";
+#include "openbmc-flash-layout.dtsi"
        };
 };
 
@@ -97,3 +111,8 @@
 &uhci {
        status = "okay";
 };
+
+&gfx {
+     status = "okay";
+     memory-region = <&gfx_memory>;
+};

diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-cmm.dts b/arch/arm/boot/dts/aspeed-bmc-facebook-cmm.dts
index 9f194b5..43aba40 100644 (file)
--- a/arch/arm/boot/dts/aspeed-bmc-facebook-cmm.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-facebook-cmm.dts
@@ -56,6 +56,12 @@
        memory@80000000 {
                reg = <0x80000000 0x20000000>;
        };
+
+       ast-adc-hwmon {
+               compatible = "iio-hwmon";
+               io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>,
+                             <&adc 4>, <&adc 5>, <&adc 6>, <&adc 7>;
+       };
 };
 
 &pinctrl {

diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts b/arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts
index 4c2dcac..c4521ed 100644 (file)
--- a/arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts
@@ -64,6 +64,11 @@
        status = "okay";
 };
 
+&vuart {
+       // VUART Host Console
+       status = "okay";
+};
+
 &uart1 {
        // Host Console
        status = "okay";

diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts b/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts
index b854ac0..b249da8 100644 (file)
--- a/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts
@@ -32,9 +32,9 @@
                        no-map;
                };
 
-               flash_memory: region@98000000 {
+               flash_memory: region@5c000000 {
                        no-map;
-                       reg = <0x98000000 0x01000000>; /* 16MB */
+                       reg = <0x5C000000 0x02000000>; /* 32MB */
                };
        };
 

diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts b/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts
index 76fe994..418a198 100644 (file)
--- a/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts
@@ -35,6 +35,13 @@
                        reg = <0x9ef00000 0x00100000>;
                        no-map;
                };
+
+               gfx_memory: framebuffer {
+                       size = <0x01000000>;
+                       alignment = <0x01000000>;
+                       compatible = "shared-dma-pool";
+                       reusable;
+               };
        };
 
        leds {
@@ -238,6 +245,7 @@
 
 &gfx {
        status = "okay";
+       memory-region = <&gfx_memory>;
 };
 
 &pinctrl {

diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts b/arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts
index ad54117..f1356ca 100644 (file)
--- a/arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts
@@ -26,6 +26,13 @@
                        no-map;
                        reg = <0x98000000 0x04000000>; /* 64M */
                };
+
+               gfx_memory: framebuffer {
+                       size = <0x01000000>;
+                       alignment = <0x01000000>;
+                       compatible = "shared-dma-pool";
+                       reusable;
+               };
        };
 
        gpio-keys {
@@ -186,13 +193,49 @@
                status = "okay";
                label = "bmc";
                m25p,fast-read;
-#include "openbmc-flash-layout.dtsi"
+
+               partitions {
+                       #address-cells = < 1 >;
+                       #size-cells = < 1 >;
+                       compatible = "fixed-partitions";
+                       u-boot@0 {
+                               reg = < 0 0x60000 >;
+                               label = "u-boot";
+                       };
+                       u-boot-env@60000 {
+                               reg = < 0x60000 0x20000 >;
+                               label = "u-boot-env";
+                       };
+                       obmc-ubi@80000 {
+                               reg = < 0x80000 0x1F80000 >;
+                               label = "obmc-ubi";
+                       };
+               };
        };
 
        flash@1 {
                status = "okay";
-               label = "alt";
+               label = "alt-bmc";
                m25p,fast-read;
+
+               partitions {
+                       #address-cells = < 1 >;
+                       #size-cells = < 1 >;
+                       compatible = "fixed-partitions";
+                       u-boot@0 {
+                               reg = < 0 0x60000 >;
+                               label = "alt-u-boot";
+                       };
+                       u-boot-env@60000 {
+                               reg = < 0x60000 0x20000 >;
+                               label = "alt-u-boot-env";
+                       };
+                       obmc-ubi@80000 {
+                               reg = < 0x80000 0x1F80000 >;
+                               label = "alt-obmc-ubi";
+                       };
+               };
+
        };
 };
 
@@ -565,6 +608,7 @@
 
 &gfx {
        status = "okay";
+       memory-region = <&gfx_memory>;
 };
 
 &pinctrl {
@@ -592,3 +636,7 @@
 &adc {
        status = "okay";
 };
+
+&vhub {
+       status = "okay";
+};

diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi
index 9549f86..5d7050d 100644 (file)
--- a/arch/arm/boot/dts/aspeed-g4.dtsi
+++ b/arch/arm/boot/dts/aspeed-g4.dtsi
@@ -209,6 +209,12 @@
                                clock-names = "PCLK";
                        };
 
+                       rtc: rtc@1e781000 {
+                               compatible = "aspeed,ast2400-rtc";
+                               reg = <0x1e781000 0x18>;
+                               status = "disabled";
+                       };
+
                        uart1: serial@1e783000 {
                                compatible = "ns16550a";
                                reg = <0x1e783000 0x20>;

diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi
index 85ed9db..4345c31 100644 (file)
--- a/arch/arm/boot/dts/aspeed-g5.dtsi
+++ b/arch/arm/boot/dts/aspeed-g5.dtsi
@@ -232,6 +232,10 @@
                                compatible = "aspeed,ast2500-gfx", "syscon";
                                reg = <0x1e6e6000 0x1000>;
                                reg-io-width = <4>;
+                               clocks = <&syscon ASPEED_CLK_GATE_D1CLK>;
+                               resets = <&syscon ASPEED_RESET_CRT1>;
+                               status = "disabled";
+                               interrupts = <0x19>;
                        };
 
                        adc: adc@1e6e9000 {
@@ -243,6 +247,16 @@
                                status = "disabled";
                        };
 
+                       video: video@1e700000 {
+                               compatible = "aspeed,ast2500-video-engine";
+                               reg = <0x1e700000 0x1000>;
+                               clocks = <&syscon ASPEED_CLK_GATE_VCLK>,
+                                        <&syscon ASPEED_CLK_GATE_ECLK>;
+                               clock-names = "vclk", "eclk";
+                               interrupts = <7>;
+                               status = "disabled";
+                       };
+
                        sram: sram@1e720000 {
                                compatible = "mmio-sram";
                                reg = <0x1e720000 0x9000>;      // 36K
@@ -260,6 +274,12 @@
                                #interrupt-cells = <2>;
                        };
 
+                       rtc: rtc@1e781000 {
+                               compatible = "aspeed,ast2500-rtc";
+                               reg = <0x1e781000 0x18>;
+                               status = "disabled";
+                       };
+
                        timer: timer@1e782000 {
                                /* This timer is a Faraday FTTMR010 derivative */
                                compatible = "aspeed,ast2400-timer";

diff --git a/arch/arm/boot/dts/at91-sama5d27_som1.dtsi b/arch/arm/boot/dts/at91-sama5d27_som1.dtsi
index 33a159c..7788d5d 100644 (file)
--- a/arch/arm/boot/dts/at91-sama5d27_som1.dtsi
+++ b/arch/arm/boot/dts/at91-sama5d27_som1.dtsi
@@ -1,47 +1,10 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
 /*
  * at91-sama5d27_som1.dtsi - Device Tree file for SAMA5D27 SoM1 board
  *
  *  Copyright (c) 2017, Microchip Technology Inc.
  *                2017 Cristian Birsan <cristian.birsan@microchip.com>
  *                2017 Claudiu Beznea <claudiu.beznea@microchip.com>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- *  a) This file is free software; you can redistribute it and/or
- *     modify it under the terms of the GNU General Public License as
- *     published by the Free Software Foundation; either version 2 of the
- *     License, or (at your option) any later version.
- *
- *     This file is distributed in the hope that it will be useful,
- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *     GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- *  b) Permission is hereby granted, free of charge, to any person
- *     obtaining a copy of this software and associated documentation
- *     files (the "Software"), to deal in the Software without
- *     restriction, including without limitation the rights to use,
- *     copy, modify, merge, publish, distribute, sublicense, and/or
- *     sell copies of the Software, and to permit persons to whom the
- *     Software is furnished to do so, subject to the following
- *     conditions:
- *
- *     The above copyright notice and this permission notice shall be
- *     included in all copies or substantial portions of the Software.
- *
- *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- *     OTHER DEALINGS IN THE SOFTWARE.
  */
 #include "sama5d2.dtsi"
 #include "sama5d2-pinfunc.h"

diff --git a/arch/arm/boot/dts/at91-sama5d27_som1_ek.dts b/arch/arm/boot/dts/at91-sama5d27_som1_ek.dts
index a481805..89f0c99 100644 (file)
--- a/arch/arm/boot/dts/at91-sama5d27_som1_ek.dts
+++ b/arch/arm/boot/dts/at91-sama5d27_som1_ek.dts
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
 /*
  * at91-sama5d27_som1_ek.dts - Device Tree file for SAMA5D27-SOM1-EK board
  *
@@ -5,44 +6,6 @@
  *                2016 Nicolas Ferre <nicolas.ferre@atmel.com>
  *                2017 Cristian Birsan <cristian.birsan@microchip.com>
  *                2017 Claudiu Beznea <claudiu.beznea@microchip.com>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- *  a) This file is free software; you can redistribute it and/or
- *     modify it under the terms of the GNU General Public License as
- *     published by the Free Software Foundation; either version 2 of the
- *     License, or (at your option) any later version.
- *
- *     This file is distributed in the hope that it will be useful,
- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *     GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- *  b) Permission is hereby granted, free of charge, to any person
- *     obtaining a copy of this software and associated documentation
- *     files (the "Software"), to deal in the Software without
- *     restriction, including without limitation the rights to use,
- *     copy, modify, merge, publish, distribute, sublicense, and/or
- *     sell copies of the Software, and to permit persons to whom the
- *     Software is furnished to do so, subject to the following
- *     conditions:
- *
- *     The above copyright notice and this permission notice shall be
- *     included in all copies or substantial portions of the Software.
- *
- *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- *     OTHER DEALINGS IN THE SOFTWARE.
  */
 /dts-v1/;
 #include "at91-sama5d27_som1.dtsi"

diff --git a/arch/arm/boot/dts/at91-sama5d2_xplained.dts b/arch/arm/boot/dts/at91-sama5d2_xplained.dts
index fa54e88..808e399 100644 (file)
--- a/arch/arm/boot/dts/at91-sama5d2_xplained.dts
+++ b/arch/arm/boot/dts/at91-sama5d2_xplained.dts
@@ -1,52 +1,16 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
 /*
  * at91-sama5d2_xplained.dts - Device Tree file for SAMA5D2 Xplained board
  *
  *  Copyright (C) 2015 Atmel,
  *                2015 Nicolas Ferre <nicolas.ferre@atmel.com>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- *  a) This file is free software; you can redistribute it and/or
- *     modify it under the terms of the GNU General Public License as
- *     published by the Free Software Foundation; either version 2 of the
- *     License, or (at your option) any later version.
- *
- *     This file is distributed in the hope that it will be useful,
- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *     GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- *  b) Permission is hereby granted, free of charge, to any person
- *     obtaining a copy of this software and associated documentation
- *     files (the "Software"), to deal in the Software without
- *     restriction, including without limitation the rights to use,
- *     copy, modify, merge, publish, distribute, sublicense, and/or
- *     sell copies of the Software, and to permit persons to whom the
- *     Software is furnished to do so, subject to the following
- *     conditions:
- *
- *     The above copyright notice and this permission notice shall be
- *     included in all copies or substantial portions of the Software.
- *
- *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- *     OTHER DEALINGS IN THE SOFTWARE.
  */
 /dts-v1/;
 #include "sama5d2.dtsi"
 #include "sama5d2-pinfunc.h"
 #include <dt-bindings/mfd/atmel-flexcom.h>
 #include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/regulator/active-semi,8945a-regulator.h>
 
 / {
        model = "Atmel SAMA5D2 Xplained";
@@ -181,49 +145,102 @@
                                                        regulator-name = "VDD_1V35";
                                                        regulator-min-microvolt = <1350000>;
                                                        regulator-max-microvolt = <1350000>;
+                                                       regulator-allowed-modes = <ACT8945A_REGULATOR_MODE_FIXED>,
+                                                                                 <ACT8945A_REGULATOR_MODE_LOWPOWER>;
+                                                       regulator-initial-mode = <ACT8945A_REGULATOR_MODE_FIXED>;
                                                        regulator-always-on;
+
+                                                       regulator-state-mem {
+                                                               regulator-on-in-suspend;
+                                                               regulator-suspend-min-microvolt=<1400000>;
+                                                               regulator-suspend-max-microvolt=<1400000>;
+                                                               regulator-changeable-in-suspend;
+                                                               regulator-mode=<ACT8945A_REGULATOR_MODE_LOWPOWER>;
+                                                       };
                                                };
 
                                                vdd_1v2_reg: REG_DCDC2 {
                                                        regulator-name = "VDD_1V2";
                                                        regulator-min-microvolt = <1100000>;
                                                        regulator-max-microvolt = <1300000>;
+                                                       regulator-allowed-modes = <ACT8945A_REGULATOR_MODE_FIXED>,
+                                                                                 <ACT8945A_REGULATOR_MODE_LOWPOWER>;
+                                                       regulator-initial-mode = <ACT8945A_REGULATOR_MODE_FIXED>;
                                                        regulator-always-on;
+
+                                                       regulator-state-mem {
+                                                               regulator-off-in-suspend;
+                                                       };
                                                };
 
                                                vdd_3v3_reg: REG_DCDC3 {
                                                        regulator-name = "VDD_3V3";
                                                        regulator-min-microvolt = <3300000>;
                                                        regulator-max-microvolt = <3300000>;
+                                                       regulator-allowed-modes = <ACT8945A_REGULATOR_MODE_FIXED>,
+                                                                                 <ACT8945A_REGULATOR_MODE_LOWPOWER>;
+                                                       regulator-initial-mode = <ACT8945A_REGULATOR_MODE_FIXED>;
                                                        regulator-always-on;
+
+                                                       regulator-state-mem {
+                                                               regulator-off-in-suspend;
+                                                       };
                                                };
 
                                                vdd_fuse_reg: REG_LDO1 {
                                                        regulator-name = "VDD_FUSE";
                                                        regulator-min-microvolt = <2500000>;
                                                        regulator-max-microvolt = <2500000>;
+                                                       regulator-allowed-modes = <ACT8945A_REGULATOR_MODE_NORMAL>,
+                                                                                 <ACT8945A_REGULATOR_MODE_LOWPOWER>;
+                                                       regulator-initial-mode = <ACT8945A_REGULATOR_MODE_NORMAL>;
                                                        regulator-always-on;
+
+                                                       regulator-state-mem {
+                                                               regulator-off-in-suspend;
+                                                       };
                                                };
 
                                                vdd_3v3_lp_reg: REG_LDO2 {
                                                        regulator-name = "VDD_3V3_LP";
                                                        regulator-min-microvolt = <3300000>;
                                                        regulator-max-microvolt = <3300000>;
+                                                       regulator-allowed-modes = <ACT8945A_REGULATOR_MODE_NORMAL>,
+                                                                                 <ACT8945A_REGULATOR_MODE_LOWPOWER>;
+                                                       regulator-initial-mode = <ACT8945A_REGULATOR_MODE_NORMAL>;
                                                        regulator-always-on;
+
+                                                       regulator-state-mem {
+                                                               regulator-off-in-suspend;
+                                                       };
                                                };
 
                                                vdd_led_reg: REG_LDO3 {
                                                        regulator-name = "VDD_LED";
                                                        regulator-min-microvolt = <3300000>;
                                                        regulator-max-microvolt = <3300000>;
+                                                       regulator-allowed-modes = <ACT8945A_REGULATOR_MODE_NORMAL>,
+                                                                                 <ACT8945A_REGULATOR_MODE_LOWPOWER>;
+                                                       regulator-initial-mode = <ACT8945A_REGULATOR_MODE_NORMAL>;
                                                        regulator-always-on;
+
+                                                       regulator-state-mem {
+                                                               regulator-off-in-suspend;
+                                                       };
                                                };
 
                                                vdd_sdhc_1v8_reg: REG_LDO4 {
                                                        regulator-name = "VDD_SDHC_1V8";
                                                        regulator-min-microvolt = <1800000>;
                                                        regulator-max-microvolt = <1800000>;
+                                                       regulator-allowed-modes = <ACT8945A_REGULATOR_MODE_NORMAL>,
+                                                                                 <ACT8945A_REGULATOR_MODE_LOWPOWER>;
+                                                       regulator-initial-mode = <ACT8945A_REGULATOR_MODE_NORMAL>;
                                                        regulator-always-on;
+
+                                                       regulator-state-mem {
+                                                               regulator-off-in-suspend;
+                                                       };
                                                };
                                        };
 

diff --git a/arch/arm/boot/dts/at91-sama5d4_xplained.dts b/arch/arm/boot/dts/at91-sama5d4_xplained.dts
index 43aef56..fdfc37d 100644 (file)
--- a/arch/arm/boot/dts/at91-sama5d4_xplained.dts
+++ b/arch/arm/boot/dts/at91-sama5d4_xplained.dts
@@ -1,46 +1,9 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
 /*
  * at91-sama5d4_xplained.dts - Device Tree file for SAMA5D4 Xplained board
  *
  *  Copyright (C) 2015 Atmel,
  *                2015 Josh Wu <josh.wu@atmel.com>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- *  a) This file is free software; you can redistribute it and/or
- *     modify it under the terms of the GNU General Public License as
- *     published by the Free Software Foundation; either version 2 of the
- *     License, or (at your option) any later version.
- *
- *     This file is distributed in the hope that it will be useful,
- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *     GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- *  b) Permission is hereby granted, free of charge, to any person
- *     obtaining a copy of this software and associated documentation
- *     files (the "Software"), to deal in the Software without
- *     restriction, including without limitation the rights to use,
- *     copy, modify, merge, publish, distribute, sublicense, and/or
- *     sell copies of the Software, and to permit persons to whom the
- *     Software is furnished to do so, subject to the following
- *     conditions:
- *
- *     The above copyright notice and this permission notice shall be
- *     included in all copies or substantial portions of the Software.
- *
- *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- *     OTHER DEALINGS IN THE SOFTWARE.
  */
 /dts-v1/;
 #include "sama5d4.dtsi"

diff --git a/arch/arm/boot/dts/at91-sama5d4ek.dts b/arch/arm/boot/dts/at91-sama5d4ek.dts
index 12d5af9..0cc1cff 100644 (file)
--- a/arch/arm/boot/dts/at91-sama5d4ek.dts
+++ b/arch/arm/boot/dts/at91-sama5d4ek.dts
@@ -1,46 +1,9 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
 /*
  * at91-sama5d4ek.dts - Device Tree file for SAMA5D4 Evaluation Kit
  *
  *  Copyright (C) 2014 Atmel,
  *                2014 Nicolas Ferre <nicolas.ferre@atmel.com>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- *  a) This file is free software; you can redistribute it and/or
- *     modify it under the terms of the GNU General Public License as
- *     published by the Free Software Foundation; either version 2 of the
- *     License, or (at your option) any later version.
- *
- *     This file is distributed in the hope that it will be useful,
- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *     GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- *  b) Permission is hereby granted, free of charge, to any person
- *     obtaining a copy of this software and associated documentation
- *     files (the "Software"), to deal in the Software without
- *     restriction, including without limitation the rights to use,
- *     copy, modify, merge, publish, distribute, sublicense, and/or
- *     sell copies of the Software, and to permit persons to whom the
- *     Software is furnished to do so, subject to the following
- *     conditions:
- *
- *     The above copyright notice and this permission notice shall be
- *     included in all copies or substantial portions of the Software.
- *
- *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- *     OTHER DEALINGS IN THE SOFTWARE.
  */
 /dts-v1/;
 #include "sama5d4.dtsi"

diff --git a/arch/arm/boot/dts/at91-vinco.dts b/arch/arm/boot/dts/at91-vinco.dts
index 4302772..15050fd 100644 (file)
--- a/arch/arm/boot/dts/at91-vinco.dts
+++ b/arch/arm/boot/dts/at91-vinco.dts
@@ -1,47 +1,10 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
 /*
  * Device Tree file for VInCo platform
  *
  *  Copyright (C) 2014 Atmel,
  *                2014 Nicolas Ferre <nicolas.ferre@atmel.com>
  *   2015 Gregory CLEMENT <gregory.clement@free-electrons.com>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- *  a) This file is free software; you can redistribute it and/or
- *     modify it under the terms of the GNU General Public License as
- *     published by the Free Software Foundation; either version 2 of the
- *     License, or (at your option) any later version.
- *
- *     This file is distributed in the hope that it will be useful,
- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *     GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- *  b) Permission is hereby granted, free of charge, to any person
- *     obtaining a copy of this software and associated documentation
- *     files (the "Software"), to deal in the Software without
- *     restriction, including without limitation the rights to use,
- *     copy, modify, merge, publish, distribute, sublicense, and/or
- *     sell copies of the Software, and to permit persons to whom the
- *     Software is furnished to do so, subject to the following
- *     conditions:
- *
- *     The above copyright notice and this permission notice shall be
- *     included in all copies or substantial portions of the Software.
- *
- *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- *     OTHER DEALINGS IN THE SOFTWARE.
  */
 /dts-v1/;
 #include "sama5d4.dtsi"

diff --git a/arch/arm/boot/dts/at91sam9260ek.dts b/arch/arm/boot/dts/at91sam9260ek.dts
index 07d1b57..81f808a 100644 (file)
--- a/arch/arm/boot/dts/at91sam9260ek.dts
+++ b/arch/arm/boot/dts/at91sam9260ek.dts
@@ -1,46 +1,9 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
 /*
  * Device Tree file for Atmel at91sam9260 Evaluation Kit
  *
  *  Copyright (C) 2016 Atmel,
  *               2016 Nicolas Ferre <nicolas.ferre@atmel.com>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- *  a) This file is free software; you can redistribute it and/or
- *     modify it under the terms of the GNU General Public License as
- *     published by the Free Software Foundation; either version 2 of the
- *     License, or (at your option) any later version.
- *
- *     This file is distributed in the hope that it will be useful,
- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *     GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- *  b) Permission is hereby granted, free of charge, to any person
- *     obtaining a copy of this software and associated documentation
- *     files (the "Software"), to deal in the Software without
- *     restriction, including without limitation the rights to use,
- *     copy, modify, merge, publish, distribute, sublicense, and/or
- *     sell copies of the Software, and to permit persons to whom the
- *     Software is furnished to do so, subject to the following
- *     conditions:
- *
- *     The above copyright notice and this permission notice shall be
- *     included in all copies or substantial portions of the Software.
- *
- *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- *     OTHER DEALINGS IN THE SOFTWARE.
  */
 /dts-v1/;
 #include "at91sam9260.dtsi"

diff --git a/arch/arm/boot/dts/at91sam9xe.dtsi b/arch/arm/boot/dts/at91sam9xe.dtsi
index 1304452..3f9d8ca 100644 (file)
--- a/arch/arm/boot/dts/at91sam9xe.dtsi
+++ b/arch/arm/boot/dts/at91sam9xe.dtsi
@@ -1,46 +1,9 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
 /*
  * at91sam9xe.dtsi - Device Tree Include file for AT91SAM9XE family SoC
  *
  *  Copyright (C) 2015 Atmel,
  *                2015 Alexandre Belloni <alexandre.Belloni@free-electrons.com>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- *  a) This file is free software; you can redistribute it and/or
- *     modify it under the terms of the GNU General Public License as
- *     published by the Free Software Foundation; either version 2 of the
- *     License, or (at your option) any later version.
- *
- *     This file is distributed in the hope that it will be useful,
- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *     GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- *  b) Permission is hereby granted, free of charge, to any person
- *     obtaining a copy of this software and associated documentation
- *     files (the "Software"), to deal in the Software without
- *     restriction, including without limitation the rights to use,
- *     copy, modify, merge, publish, distribute, sublicense, and/or
- *     sell copies of the Software, and to permit persons to whom the
- *     Software is furnished to do so, subject to the following
- *     conditions:
- *
- *     The above copyright notice and this permission notice shall be
- *     included in all copies or substantial portions of the Software.
- *
- *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- *     OTHER DEALINGS IN THE SOFTWARE.
  */
 
 #include "at91sam9260.dtsi"

diff --git a/arch/arm/boot/dts/axp81x.dtsi b/arch/arm/boot/dts/axp81x.dtsi
index bd83962..1dfeece 100644 (file)
--- a/arch/arm/boot/dts/axp81x.dtsi
+++ b/arch/arm/boot/dts/axp81x.dtsi
@@ -171,4 +171,8 @@
                        status = "disabled";
                };
        };
+
+       usb_power_supply: usb-power-supply {
+               compatible = "x-powers,axp813-usb-power-supply";
+       };
 };

diff --git a/arch/arm/boot/dts/dra7-l4.dtsi b/arch/arm/boot/dts/dra7-l4.dtsi
index 414f1cd..fe9f0bc 100644 (file)
--- a/arch/arm/boot/dts/dra7-l4.dtsi
+++ b/arch/arm/boot/dts/dra7-l4.dtsi
@@ -2499,7 +2499,7 @@
                        ranges = <0x0 0x3a000 0x1000>;
                };
 
-               target-module@3c000 {                   /* 0x4843c000, ap 23 08.0 */
+               atl_tm: target-module@3c000 {           /* 0x4843c000, ap 23 08.0 */
                        compatible = "ti,sysc-omap4", "ti,sysc";
                        reg = <0x3c000 0x4>;
                        reg-names = "rev";
@@ -4099,7 +4099,7 @@
                        };
                };
 
-               target-module@100000 {                  /* 0x48900000, ap 85 04.0 */
+               usb3_tm: target-module@100000 {         /* 0x48900000, ap 85 04.0 */
                        compatible = "ti,sysc-omap4", "ti,sysc";
                        ti,hwmods = "usb_otg_ss3";
                        reg = <0x100000 0x4>,
@@ -4148,7 +4148,7 @@
                        };
                };
 
-               target-module@140000 {                  /* 0x48940000, ap 75 3c.0 */
+               usb4_tm: target-module@140000 {         /* 0x48940000, ap 75 3c.0 */
                        compatible = "ti,sysc-omap4", "ti,sysc";
                        ti,hwmods = "usb_otg_ss4";
                        reg = <0x140000 0x4>,

diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 2bc9add..d87e932 100644 (file)
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -193,6 +193,7 @@
                                ti,hwmods = "pcie1";
                                phys = <&pcie1_phy>;
                                phy-names = "pcie-phy0";
+                               ti,syscon-lane-sel = <&scm_conf_pcie 0x18>;
                                interrupt-map-mask = <0 0 0 7>;
                                interrupt-map = <0 0 0 1 &pcie1_intc 1>,
                                                <0 0 0 2 &pcie1_intc 2>,
@@ -218,6 +219,7 @@
                                phys = <&pcie1_phy>;
                                phy-names = "pcie-phy0";
                                ti,syscon-unaligned-access = <&scm_conf1 0x14 1>;
+                               ti,syscon-lane-sel = <&scm_conf_pcie 0x18>;
                                status = "disabled";
                        };
                };

diff --git a/arch/arm/boot/dts/emev2-kzm9d.dts b/arch/arm/boot/dts/emev2-kzm9d.dts
index 1bb8e5c..abfff54 100644 (file)
--- a/arch/arm/boot/dts/emev2-kzm9d.dts
+++ b/arch/arm/boot/dts/emev2-kzm9d.dts
@@ -25,7 +25,7 @@
        };
 
        chosen {
-               bootargs = "ignore_loglevel root=/dev/nfs ip=dhcp";
+               bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
                stdout-path = "serial1:115200n8";
        };
 

diff --git a/arch/arm/boot/dts/exynos3250.dtsi b/arch/arm/boot/dts/exynos3250.dtsi
index 5892a9f..8ce3a77 100644 (file)
--- a/arch/arm/boot/dts/exynos3250.dtsi
+++ b/arch/arm/boot/dts/exynos3250.dtsi
@@ -97,42 +97,46 @@
                };
        };
 
-       soc: soc {
-               compatible = "simple-bus";
+       fixed-rate-clocks {
                #address-cells = <1>;
-               #size-cells = <1>;
-               ranges;
-
-               fixed-rate-clocks {
-                       #address-cells = <1>;
-                       #size-cells = <0>;
+               #size-cells = <0>;
 
-                       xusbxti: clock@0 {
-                               compatible = "fixed-clock";
-                               #address-cells = <1>;
-                               #size-cells = <0>;
-                               reg = <0>;
-                               clock-frequency = <0>;
-                               #clock-cells = <0>;
-                               clock-output-names = "xusbxti";
-                       };
+               xusbxti: clock@0 {
+                       compatible = "fixed-clock";
+                       reg = <0>;
+                       clock-frequency = <0>;
+                       #clock-cells = <0>;
+                       clock-output-names = "xusbxti";
+               };
 
-                       xxti: clock@1 {
-                               compatible = "fixed-clock";
-                               reg = <1>;
-                               clock-frequency = <0>;
-                               #clock-cells = <0>;
-                               clock-output-names = "xxti";
-                       };
+               xxti: clock@1 {
+                       compatible = "fixed-clock";
+                       reg = <1>;
+                       clock-frequency = <0>;
+                       #clock-cells = <0>;
+                       clock-output-names = "xxti";
+               };
 
-                       xtcxo: clock@2 {
-                               compatible = "fixed-clock";
-                               reg = <2>;
-                               clock-frequency = <0>;
-                               #clock-cells = <0>;
-                               clock-output-names = "xtcxo";
-                       };
+               xtcxo: clock@2 {
+                       compatible = "fixed-clock";
+                       reg = <2>;
+                       clock-frequency = <0>;
+                       #clock-cells = <0>;
+                       clock-output-names = "xtcxo";
                };
+       };
+
+       pmu {
+               compatible = "arm,cortex-a7-pmu";
+               interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+       };
+
+       soc: soc {
+               compatible = "simple-bus";
+               #address-cells = <1>;
+               #size-cells = <1>;
+               ranges;
 
                sysram@2020000 {
                        compatible = "mmio-sram";
@@ -673,12 +677,6 @@
                        status = "disabled";
                };
 
-               pmu {
-                       compatible = "arm,cortex-a7-pmu";
-                       interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
-                                    <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
-               };
-
                ppmu_dmc0: ppmu_dmc0@106a0000 {
                        compatible = "samsung,exynos-ppmu";
                        reg = <0x106a0000 0x2000>;

diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi
index 6085e92..36ccf22 100644 (file)
--- a/arch/arm/boot/dts/exynos4.dtsi
+++ b/arch/arm/boot/dts/exynos4.dtsi
@@ -51,6 +51,12 @@
                serial3 = &serial_3;
        };
 
+       pmu: pmu {
+               compatible = "arm,cortex-a9-pmu";
+               interrupt-parent = <&combiner>;
+               interrupts = <2 2>, <3 2>;
+       };
+
        soc: soc {
                compatible = "simple-bus";
                #address-cells = <1>;
@@ -169,12 +175,6 @@
                        reg = <0x10440000 0x1000>;
                };
 
-               pmu: pmu {
-                       compatible = "arm,cortex-a9-pmu";
-                       interrupt-parent = <&combiner>;
-                       interrupts = <2 2>, <3 2>;
-               };
-
                sys_reg: syscon@10010000 {
                        compatible = "samsung,exynos4-sysreg", "syscon";
                        reg = <0x10010000 0x400>;
@@ -675,7 +675,7 @@
                        status = "disabled";
                };
 
-               amba {
+               amba: amba {
                        #address-cells = <1>;
                        #size-cells = <1>;
                        compatible = "simple-bus";

diff --git a/arch/arm/boot/dts/exynos4210-origen.dts b/arch/arm/boot/dts/exynos4210-origen.dts
index dd9ec05..36b1ede 100644 (file)
--- a/arch/arm/boot/dts/exynos4210-origen.dts
+++ b/arch/arm/boot/dts/exynos4210-origen.dts
@@ -30,8 +30,8 @@
        };
 
        chosen {
-               bootargs ="root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC2,115200 init=/linuxrc";
-               stdout-path = &serial_2;
+               bootargs = "root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M init=/linuxrc";
+               stdout-path = "serial2:115200n8";
        };
 
        mmc_reg: voltage-regulator {

diff --git a/arch/arm/boot/dts/exynos4210-smdkv310.dts b/arch/arm/boot/dts/exynos4210-smdkv310.dts
index 7a3e621..77fc11e 100644 (file)
--- a/arch/arm/boot/dts/exynos4210-smdkv310.dts
+++ b/arch/arm/boot/dts/exynos4210-smdkv310.dts
@@ -26,8 +26,8 @@
        };
 
        chosen {
-               bootargs = "root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC1,115200 init=/linuxrc";
-               stdout-path = &serial_1;
+               bootargs = "root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M init=/linuxrc";
+               stdout-path = "serial1:115200n8";
        };
 
        fixed-rate-clocks {

diff --git a/arch/arm/boot/dts/exynos4210-trats.dts b/arch/arm/boot/dts/exynos4210-trats.dts
index 8dbc47d..6882480 100644 (file)
--- a/arch/arm/boot/dts/exynos4210-trats.dts
+++ b/arch/arm/boot/dts/exynos4210-trats.dts
@@ -26,8 +26,8 @@
        };
 
        chosen {
-               bootargs = "console=ttySAC2,115200N8 root=/dev/mmcblk0p5 rootwait earlyprintk panic=5";
-               stdout-path = &serial_2;
+               bootargs = "root=/dev/mmcblk0p5 rootwait earlyprintk panic=5";
+               stdout-path = "serial2:115200n8";
        };
 
        regulators {

diff --git a/arch/arm/boot/dts/exynos4210-universal_c210.dts b/arch/arm/boot/dts/exynos4210-universal_c210.dts
index 5c3d986..bf092e9 100644 (file)
--- a/arch/arm/boot/dts/exynos4210-universal_c210.dts
+++ b/arch/arm/boot/dts/exynos4210-universal_c210.dts
@@ -24,8 +24,8 @@
        };
 
        chosen {
-               bootargs = "console=ttySAC2,115200N8 root=/dev/mmcblk0p5 rw rootwait earlyprintk panic=5 maxcpus=1";
-               stdout-path = &serial_2;
+               bootargs = "root=/dev/mmcblk0p5 rw rootwait earlyprintk panic=5 maxcpus=1";
+               stdout-path = "serial2:115200n8";
        };
 
 
@@ -177,6 +177,20 @@
        };
 };
 
+&amba {
+       mdma0: mdma@12840000 {
+               compatible = "arm,pl330", "arm,primecell";
+               reg = <0x12840000 0x1000>;
+               interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&clock CLK_MDMA>;
+               clock-names = "apb_pclk";
+               #dma-cells = <1>;
+               #dma-channels = <8>;
+               #dma-requests = <1>;
+               power-domains = <&pd_lcd0>;
+       };
+};
+
 &camera {
        status = "okay";
 
@@ -491,7 +505,8 @@
 };
 
 &mdma1 {
-       reg = <0x12840000 0x1000>;
+       /* Use the secure mdma0 */
+       status = "disabled";
 };
 
 &mixer {

diff --git a/arch/arm/boot/dts/exynos4412-odroidu3.dts b/arch/arm/boot/dts/exynos4412-odroidu3.dts
index 2bdf899..96d9988 100644 (file)
--- a/arch/arm/boot/dts/exynos4412-odroidu3.dts
+++ b/arch/arm/boot/dts/exynos4412-odroidu3.dts
@@ -34,8 +34,6 @@
        fan0: pwm-fan {
                compatible = "pwm-fan";
                pwms = <&pwm 0 10000 0>;
-               cooling-min-state = <0>;
-               cooling-max-state = <3>;
                #cooling-cells = <2>;
                cooling-levels = <0 102 170 230>;
        };
@@ -66,6 +64,11 @@
        };
 };
 
+&adc {
+       vdd-supply = <&ldo10_reg>;
+       /* Nothing connected to ADC inputs, keep it disabled */
+};
+
 /* Supply for LAN9730/SMSC95xx */
 &buck8_reg {
        regulator-name = "BUCK8_P3V3";

diff --git a/arch/arm/boot/dts/exynos4412-origen.dts b/arch/arm/boot/dts/exynos4412-origen.dts
index 346f719..698de43 100644 (file)
--- a/arch/arm/boot/dts/exynos4412-origen.dts
+++ b/arch/arm/boot/dts/exynos4412-origen.dts
@@ -25,8 +25,7 @@
        };
 
        chosen {
-               bootargs ="console=ttySAC2,115200";
-               stdout-path = &serial_2;
+               stdout-path = "serial2:115200n8";
        };
 
        firmware@203f000 {

diff --git a/arch/arm/boot/dts/exynos4412-smdk4412.dts b/arch/arm/boot/dts/exynos4412-smdk4412.dts
index 5c5c288..e70fb6e 100644 (file)
--- a/arch/arm/boot/dts/exynos4412-smdk4412.dts
+++ b/arch/arm/boot/dts/exynos4412-smdk4412.dts
@@ -23,8 +23,8 @@
        };
 
        chosen {
-               bootargs ="root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC1,115200 init=/linuxrc";
-               stdout-path = &serial_1;
+               bootargs = "root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M init=/linuxrc";
+               stdout-path = "serial1:115200n8";
        };
 
        fixed-rate-clocks {

diff --git a/arch/arm/boot/dts/exynos4412-trats2.dts b/arch/arm/boot/dts/exynos4412-trats2.dts
index 327ee98..aac5339 100644 (file)
--- a/arch/arm/boot/dts/exynos4412-trats2.dts
+++ b/arch/arm/boot/dts/exynos4412-trats2.dts
@@ -22,6 +22,7 @@
        };
 
        chosen {
-               bootargs = "console=ttySAC2,115200N8 root=/dev/mmcblk0p5 rootwait earlyprintk panic=5";
+               bootargs = "root=/dev/mmcblk0p5 rootwait earlyprintk panic=5";
+               stdout-path = "serial2:115200n8";
        };
 };

diff --git a/arch/arm/boot/dts/exynos4412.dtsi b/arch/arm/boot/dts/exynos4412.dtsi
index 26ad6ab..e5c041e 100644 (file)
--- a/arch/arm/boot/dts/exynos4412.dtsi
+++ b/arch/arm/boot/dts/exynos4412.dtsi
@@ -274,7 +274,7 @@
                };
 
                adc: adc@126c0000 {
-                       compatible = "samsung,exynos-adc-v1";
+                       compatible = "samsung,exynos4212-adc";
                        reg = <0x126C0000 0x100>;
                        interrupt-parent = <&combiner>;
                        interrupts = <10 3>;

diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts
index d5e6618..6dc9694 100644 (file)
--- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
+++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
@@ -24,7 +24,8 @@
        };
 
        chosen {
-               bootargs = "root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC2,115200 init=/linuxrc";
+               bootargs = "root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M init=/linuxrc";
+               stdout-path = "serial2:115200n8";
        };
 
        vdd: fixed-regulator-vdd {

diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
index 80986b9..d5e0392 100644 (file)
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -157,6 +157,12 @@
                };
        };
 
+       pmu {
+               compatible = "arm,cortex-a15-pmu";
+               interrupt-parent = <&combiner>;
+               interrupts = <1 2>, <22 4>;
+       };
+
        soc: soc {
                sysram@2020000 {
                        compatible = "mmio-sram";
@@ -227,20 +233,6 @@
                        power-domains = <&pd_mau>;
                };
 
-               timer {
-                       compatible = "arm,armv7-timer";
-                       interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
-                                    <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
-                                    <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
-                                    <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
-                       /*
-                        * Unfortunately we need this since some versions
-                        * of U-Boot on Exynos don't set the CNTFRQ register,
-                        * so we need the value from DT.
-                        */
-                       clock-frequency = <24000000>;
-               };
-
                mct@101c0000 {
                        compatible = "samsung,exynos4210-mct";
                        reg = <0x101C0000 0x800>;
@@ -265,12 +257,6 @@
                        };
                };
 
-               pmu {
-                       compatible = "arm,cortex-a15-pmu";
-                       interrupt-parent = <&combiner>;
-                       interrupts = <1 2>, <22 4>;
-               };
-
                pinctrl_0: pinctrl@11400000 {
                        compatible = "samsung,exynos5250-pinctrl";
                        reg = <0x11400000 0x1000>;
@@ -1097,6 +1083,20 @@
                       };
                };
        };
+
+       timer {
+               compatible = "arm,armv7-timer";
+               interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+                            <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+                            <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+                            <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+               /*
+                * Unfortunately we need this since some versions
+                * of U-Boot on Exynos don't set the CNTFRQ register,
+                * so we need the value from DT.
+                */
+               clock-frequency = <24000000>;
+       };
 };
 
 &dp {

diff --git a/arch/arm/boot/dts/exynos5260-pinctrl.dtsi b/arch/arm/boot/dts/exynos5260-pinctrl.dtsi
index b1edb20..17e2f3e 100644 (file)
--- a/arch/arm/boot/dts/exynos5260-pinctrl.dtsi
+++ b/arch/arm/boot/dts/exynos5260-pinctrl.dtsi
@@ -153,6 +153,14 @@
                #gpio-cells = <2>;
 
                interrupt-controller;
+               interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
                #interrupt-cells = <2>;
        };
 
@@ -161,6 +169,14 @@
                #gpio-cells = <2>;
 
                interrupt-controller;
+               interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
                #interrupt-cells = <2>;
        };
 

diff --git a/arch/arm/boot/dts/exynos5260-xyref5260.dts b/arch/arm/boot/dts/exynos5260-xyref5260.dts
index fa19c59..36a2b77 100644 (file)
--- a/arch/arm/boot/dts/exynos5260-xyref5260.dts
+++ b/arch/arm/boot/dts/exynos5260-xyref5260.dts
@@ -19,7 +19,7 @@
        };
 
        chosen {
-               bootargs = "console=ttySAC2,115200";
+               stdout-path = "serial2:115200n8";
        };
 
        fin_pll: xxti {

diff --git a/arch/arm/boot/dts/exynos5260.dtsi b/arch/arm/boot/dts/exynos5260.dtsi
index 5516785..3581b57 100644 (file)
--- a/arch/arm/boot/dts/exynos5260.dtsi
+++ b/arch/arm/boot/dts/exynos5260.dtsi
@@ -17,6 +17,10 @@
        #size-cells = <1>;
 
        aliases {
+               i2c0 = &hsi2c_0;
+               i2c1 = &hsi2c_1;
+               i2c2 = &hsi2c_2;
+               i2c3 = &hsi2c_3;
                pinctrl0 = &pinctrl_0;
                pinctrl1 = &pinctrl_1;
                pinctrl2 = &pinctrl_2;
@@ -223,7 +227,7 @@
                        wakeup-interrupt-controller {
                                compatible = "samsung,exynos4210-wakeup-eint";
                                interrupt-parent = <&gic>;
-                               interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+                               interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
                        };
                };
 
@@ -288,6 +292,14 @@
                        #size-cells = <0>;
                        clocks = <&clock_fsys FSYS_CLK_MMC0>, <&clock_top TOP_SCLK_MMC0>;
                        clock-names = "biu", "ciu";
+                       assigned-clocks =
+                               <&clock_top TOP_MOUT_SCLK_FSYS_MMC0_SDCLKIN_A>,
+                               <&clock_top TOP_MOUT_SCLK_FSYS_MMC0_SDCLKIN_B>,
+                               <&clock_top TOP_SCLK_MMC0>;
+                       assigned-clock-parents =
+                               <&clock_top TOP_MOUT_BUSTOP_PLL_USER>,
+                               <&clock_top TOP_MOUT_SCLK_FSYS_MMC0_SDCLKIN_A>;
+                       assigned-clock-rates = <0>, <0>, <800000000>;
                        fifo-depth = <64>;
                        status = "disabled";
                };
@@ -300,6 +312,14 @@
                        #size-cells = <0>;
                        clocks = <&clock_fsys FSYS_CLK_MMC1>, <&clock_top TOP_SCLK_MMC1>;
                        clock-names = "biu", "ciu";
+                       assigned-clocks =
+                               <&clock_top TOP_MOUT_SCLK_FSYS_MMC1_SDCLKIN_A>,
+                               <&clock_top TOP_MOUT_SCLK_FSYS_MMC1_SDCLKIN_B>,
+                               <&clock_top TOP_SCLK_MMC1>;
+                       assigned-clock-parents =
+                               <&clock_top TOP_MOUT_BUSTOP_PLL_USER>,
+                               <&clock_top TOP_MOUT_SCLK_FSYS_MMC1_SDCLKIN_A>;
+                       assigned-clock-rates = <0>, <0>, <800000000>;
                        fifo-depth = <64>;
                        status = "disabled";
                };
@@ -312,9 +332,69 @@
                        #size-cells = <0>;
                        clocks = <&clock_fsys FSYS_CLK_MMC2>, <&clock_top TOP_SCLK_MMC2>;
                        clock-names = "biu", "ciu";
+                       assigned-clocks =
+                               <&clock_top TOP_MOUT_SCLK_FSYS_MMC2_SDCLKIN_A>,
+                               <&clock_top TOP_MOUT_SCLK_FSYS_MMC2_SDCLKIN_B>,
+                               <&clock_top TOP_SCLK_MMC2>;
+                       assigned-clock-parents =
+                               <&clock_top TOP_MOUT_BUSTOP_PLL_USER>,
+                               <&clock_top TOP_MOUT_SCLK_FSYS_MMC2_SDCLKIN_A>;
+                       assigned-clock-rates = <0>, <0>, <800000000>;
                        fifo-depth = <64>;
                        status = "disabled";
                };
+
+               hsi2c_0: hsi2c@12da0000 {
+                       compatible = "samsung,exynos5260-hsi2c";
+                       reg = <0x12DA0000 0x1000>;
+                       interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       pinctrl-names = "default";
+                       pinctrl-0 = <&i2c0_hs_bus>;
+                       clocks = <&clock_peri PERI_CLK_HSIC0>;
+                       clock-names = "hsi2c";
+                       status = "disabled";
+               };
+
+               hsi2c_1: hsi2c@12db0000 {
+                       compatible = "samsung,exynos5260-hsi2c";
+                       reg = <0x12DB0000 0x1000>;
+                       interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       pinctrl-names = "default";
+                       pinctrl-0 = <&i2c1_hs_bus>;
+                       clocks = <&clock_peri PERI_CLK_HSIC1>;
+                       clock-names = "hsi2c";
+                       status = "disabled";
+               };
+
+               hsi2c_2: hsi2c@12dc0000 {
+                       compatible = "samsung,exynos5260-hsi2c";
+                       reg = <0x12DC0000 0x1000>;
+                       interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       pinctrl-names = "default";
+                       pinctrl-0 = <&i2c2_hs_bus>;
+                       clocks = <&clock_peri PERI_CLK_HSIC2>;
+                       clock-names = "hsi2c";
+                       status = "disabled";
+               };
+
+               hsi2c_3: hsi2c@12dd0000 {
+                       compatible = "samsung,exynos5260-hsi2c";
+                       reg = <0x12DD0000 0x1000>;
+                       interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       pinctrl-names = "default";
+                       pinctrl-0 = <&i2c3_hs_bus>;
+                       clocks = <&clock_peri PERI_CLK_HSIC3>;
+                       clock-names = "hsi2c";
+                       status = "disabled";
+               };
        };
 };
 

diff --git a/arch/arm/boot/dts/exynos5410-odroidxu.dts b/arch/arm/boot/dts/exynos5410-odroidxu.dts
index 434a759..8f9e08f 100644 (file)
--- a/arch/arm/boot/dts/exynos5410-odroidxu.dts
+++ b/arch/arm/boot/dts/exynos5410-odroidxu.dts
@@ -38,8 +38,6 @@
        fan0: pwm-fan {
                compatible = "pwm-fan";
                pwms = <&pwm 0 20972 0>;
-               cooling-min-state = <0>;
-               cooling-max-state = <3>;
                #cooling-cells = <2>;
                cooling-levels = <0 130 170 230>;
        };

diff --git a/arch/arm/boot/dts/exynos5410-smdk5410.dts b/arch/arm/boot/dts/exynos5410-smdk5410.dts
index 8fc8c84..dffa5e3 100644 (file)
--- a/arch/arm/boot/dts/exynos5410-smdk5410.dts
+++ b/arch/arm/boot/dts/exynos5410-smdk5410.dts
@@ -19,7 +19,7 @@
        };
 
        chosen {
-               bootargs = "console=ttySAC2,115200";
+               stdout-path = "serial2:115200n8";
        };
 
        fin_pll: xxti {

diff --git a/arch/arm/boot/dts/exynos5420-arndale-octa.dts b/arch/arm/boot/dts/exynos5420-arndale-octa.dts
index 3447160..dbf0306 100644 (file)
--- a/arch/arm/boot/dts/exynos5420-arndale-octa.dts
+++ b/arch/arm/boot/dts/exynos5420-arndale-octa.dts
@@ -24,7 +24,7 @@
        };
 
        chosen {
-               bootargs = "console=ttySAC3,115200";
+               stdout-path = "serial3:115200n8";
        };
 
        firmware@2073000 {
@@ -51,6 +51,15 @@
        };
 };
 
+&adc {
+       vdd-supply = <&ldo4_reg>;
+       status = "okay";
+};
+
+&cci {
+       status = "disabled";
+};
+
 &cpu0 {
        cpu-supply = <&buck2_reg>;
 };
@@ -59,12 +68,268 @@
        cpu-supply = <&buck6_reg>;
 };
 
-&usbdrd_dwc3_1 {
-       dr_mode = "host";
+&cpu0_thermal {
+       trips {
+               cpu0_alert0: cpu-alert-0 {
+                       temperature = <60000>; /* millicelsius */
+                       hysteresis = <5000>; /* millicelsius */
+                       type = "passive";
+               };
+               cpu0_alert1: cpu-alert-1 {
+                       temperature = <80000>; /* millicelsius */
+                       hysteresis = <10000>; /* millicelsius */
+                       type = "passive";
+               };
+               cpu0_alert2: cpu-alert-2 {
+                       temperature = <110000>; /* millicelsius */
+                       hysteresis = <10000>; /* millicelsius */
+                       type = "passive";
+               };
+               cpu0_crit0: cpu-crit-0 {
+                       temperature = <120000>; /* millicelsius */
+                       hysteresis = <0>; /* millicelsius */
+                       type = "critical";
+               };
+       };
+
+       cooling-maps {
+               /*
+                * Reduce the CPU speed by 2 steps, down to: 1600 MHz
+                * and 1100 MHz.
+                */
+               map0 {
+                       trip = <&cpu0_alert0>;
+                       cooling-device = <&cpu0 0 2>,
+                                        <&cpu1 0 2>,
+                                        <&cpu2 0 2>,
+                                        <&cpu3 0 2>,
+                                        <&cpu4 0 2>,
+                                        <&cpu5 0 2>,
+                                        <&cpu6 0 2>,
+                                        <&cpu7 0 2>;
+               };
+
+               /*
+                * Reduce the CPU speed down to 1200 MHz big (6 steps)
+                * and 800 MHz LITTLE (5 steps).
+                */
+               map1 {
+                       trip = <&cpu0_alert1>;
+                       cooling-device = <&cpu0 3 6>,
+                                        <&cpu1 3 6>,
+                                        <&cpu2 3 6>,
+                                        <&cpu3 3 6>,
+                                        <&cpu4 3 5>,
+                                        <&cpu5 3 5>,
+                                        <&cpu6 3 5>,
+                                        <&cpu7 3 5>;
+               };
+
+               /*
+                * Reduce the CPU speed as much as possible, down to 700 MHz
+                * big (11 steps) and 600 MHz LITTLE (7 steps).
+                */
+               map2 {
+                       trip = <&cpu0_alert2>;
+                       cooling-device = <&cpu0 6 11>,
+                                        <&cpu1 6 11>,
+                                        <&cpu2 6 11>,
+                                        <&cpu3 6 11>,
+                                        <&cpu4 5 7>,
+                                        <&cpu5 5 7>,
+                                        <&cpu6 5 7>,
+                                        <&cpu7 5 7>;
+               };
+       };
 };
 
-&cci {
-       status = "disabled";
+&cpu1_thermal {
+       trips {
+               cpu1_alert0: cpu-alert-0 {
+                       temperature = <60000>; /* millicelsius */
+                       hysteresis = <5000>; /* millicelsius */
+                       type = "passive";
+               };
+               cpu1_alert1: cpu-alert-1 {
+                       temperature = <80000>; /* millicelsius */
+                       hysteresis = <10000>; /* millicelsius */
+                       type = "passive";
+               };
+               cpu1_alert2: cpu-alert-2 {
+                       temperature = <110000>; /* millicelsius */
+                       hysteresis = <10000>; /* millicelsius */
+                       type = "passive";
+               };
+               cpu1_crit0: cpu-crit-0 {
+                       temperature = <120000>; /* millicelsius */
+                       hysteresis = <0>; /* millicelsius */
+                       type = "critical";
+               };
+       };
+
+       cooling-maps {
+               map0 {
+                       trip = <&cpu1_alert0>;
+                       cooling-device = <&cpu0 0 2>,
+                                        <&cpu1 0 2>,
+                                        <&cpu2 0 2>,
+                                        <&cpu3 0 2>,
+                                        <&cpu4 0 2>,
+                                        <&cpu5 0 2>,
+                                        <&cpu6 0 2>,
+                                        <&cpu7 0 2>;
+               };
+
+               map1 {
+                       trip = <&cpu1_alert1>;
+                       cooling-device = <&cpu0 3 6>,
+                                        <&cpu1 3 6>,
+                                        <&cpu2 3 6>,
+                                        <&cpu3 3 6>,
+                                        <&cpu4 3 5>,
+                                        <&cpu5 3 5>,
+                                        <&cpu6 3 5>,
+                                        <&cpu7 3 5>;
+               };
+
+               map2 {
+                       trip = <&cpu1_alert2>;
+                       cooling-device = <&cpu0 6 11>,
+                                        <&cpu1 6 11>,
+                                        <&cpu2 6 11>,
+                                        <&cpu3 6 11>,
+                                        <&cpu4 5 7>,
+                                        <&cpu5 5 7>,
+                                        <&cpu6 5 7>,
+                                        <&cpu7 5 7>;
+               };
+       };
+};
+
+&cpu2_thermal {
+       trips {
+               cpu2_alert0: cpu-alert-0 {
+                       temperature = <60000>; /* millicelsius */
+                       hysteresis = <5000>; /* millicelsius */
+                       type = "passive";
+               };
+               cpu2_alert1: cpu-alert-1 {
+                       temperature = <80000>; /* millicelsius */
+                       hysteresis = <10000>; /* millicelsius */
+                       type = "passive";
+               };
+               cpu2_alert2: cpu-alert-2 {
+                       temperature = <110000>; /* millicelsius */
+                       hysteresis = <10000>; /* millicelsius */
+                       type = "passive";
+               };
+               cpu2_crit0: cpu-crit-0 {
+                       temperature = <120000>; /* millicelsius */
+                       hysteresis = <0>; /* millicelsius */
+                       type = "critical";
+               };
+       };
+
+       cooling-maps {
+               map0 {
+                       trip = <&cpu2_alert0>;
+                       cooling-device = <&cpu0 0 2>,
+                                        <&cpu1 0 2>,
+                                        <&cpu2 0 2>,
+                                        <&cpu3 0 2>,
+                                        <&cpu4 0 2>,
+                                        <&cpu5 0 2>,
+                                        <&cpu6 0 2>,
+                                        <&cpu7 0 2>;
+               };
+
+               map1 {
+                       trip = <&cpu2_alert1>;
+                       cooling-device = <&cpu0 3 6>,
+                                        <&cpu1 3 6>,
+                                        <&cpu2 3 6>,
+                                        <&cpu3 3 6>,
+                                        <&cpu4 3 5>,
+                                        <&cpu5 3 5>,
+                                        <&cpu6 3 5>,
+                                        <&cpu7 3 5>;
+               };
+
+               map2 {
+                       trip = <&cpu2_alert2>;
+                       cooling-device = <&cpu0 6 11>,
+                                        <&cpu1 6 11>,
+                                        <&cpu2 6 11>,
+                                        <&cpu3 6 11>,
+                                        <&cpu4 6 7>,
+                                        <&cpu5 6 7>,
+                                        <&cpu6 6 7>,
+                                        <&cpu7 6 7>;
+               };
+       };
+};
+
+&cpu3_thermal {
+       trips {
+               cpu3_alert0: cpu-alert-0 {
+                       temperature = <60000>; /* millicelsius */
+                       hysteresis = <5000>; /* millicelsius */
+                       type = "passive";
+               };
+               cpu3_alert1: cpu-alert-1 {
+                       temperature = <80000>; /* millicelsius */
+                       hysteresis = <10000>; /* millicelsius */
+                       type = "passive";
+               };
+               cpu3_alert2: cpu-alert-2 {
+                       temperature = <110000>; /* millicelsius */
+                       hysteresis = <10000>; /* millicelsius */
+                       type = "passive";
+               };
+               cpu3_crit0: cpu-crit-0 {
+                       temperature = <120000>; /* millicelsius */
+                       hysteresis = <0>; /* millicelsius */
+                       type = "critical";
+               };
+       };
+
+       cooling-maps {
+               map0 {
+                       trip = <&cpu3_alert0>;
+                       cooling-device = <&cpu0 0 2>,
+                                        <&cpu1 0 2>,
+                                        <&cpu2 0 2>,
+                                        <&cpu3 0 2>,
+                                        <&cpu4 0 2>,
+                                        <&cpu5 0 2>,
+                                        <&cpu6 0 2>,
+                                        <&cpu7 0 2>;
+               };
+
+               map1 {
+                       trip = <&cpu3_alert1>;
+                       cooling-device = <&cpu0 3 6>,
+                                        <&cpu1 3 6>,
+                                        <&cpu2 3 6>,
+                                        <&cpu3 3 6>,
+                                        <&cpu4 3 5>,
+                                        <&cpu5 3 5>,
+                                        <&cpu6 3 5>,
+                                        <&cpu7 3 5>;
+               };
+
+               map2 {
+                       trip = <&cpu3_alert2>;
+                       cooling-device = <&cpu0 6 11>,
+                                        <&cpu1 6 11>,
+                                        <&cpu2 6 11>,
+                                        <&cpu3 6 11>,
+                                        <&cpu4 5 7>,
+                                        <&cpu5 5 7>,
+                                        <&cpu6 5 7>,
+                                        <&cpu7 5 7>;
+               };
+       };
 };
 
 &hdmi {
@@ -107,12 +372,19 @@
                                regulator-name = "PVDD_APIO_1V8";
                                regulator-min-microvolt = <1800000>;
                                regulator-max-microvolt = <1800000>;
+                               regulator-always-on;
                        };
 
                        ldo3_reg: LDO3 {
                                regulator-name = "PVDD_APIO_MMCON_1V8";
                                regulator-min-microvolt = <1800000>;
                                regulator-max-microvolt = <1800000>;
+                               /*
+                                * Must be always on, even though there is
+                                * a consumer (mmc_0).  Otherwise the board
+                                * does not reboot with vendor U-Boot
+                                * (Linaro for Arndale Octa, v2012.07).
+                                */
                                regulator-always-on;
                        };
 
@@ -145,6 +417,7 @@
                                regulator-name = "PVDD_ABB_1V8";
                                regulator-min-microvolt = <1800000>;
                                regulator-max-microvolt = <1800000>;
+                               regulator-always-on;
                        };
 
                        ldo9_reg: LDO9 {
@@ -176,10 +449,17 @@
 
                        ldo13_reg: LDO13 {
                                regulator-name = "PVDD_APIO_MMCOFF_2V8";
-                               regulator-min-microvolt = <2800000>;
+                               regulator-min-microvolt = <1800000>;
                                regulator-max-microvolt = <2800000>;
                        };
 
+                       ldo14_reg: LDO14 {
+                               /* Unused */
+                               regulator-name = "PVDD_LDO14";
+                               regulator-min-microvolt = <800000>;
+                               regulator-max-microvolt = <3950000>;
+                       };
+
                        ldo15_reg: LDO15 {
                                regulator-name = "PVDD_PERI_2V8";
                                regulator-min-microvolt = <3300000>;
@@ -192,6 +472,13 @@
                                regulator-max-microvolt = <2200000>;
                        };
 
+                       ldo17_reg: LDO17 {
+                               /* Unused */
+                               regulator-name = "PVDD_LDO17";
+                               regulator-min-microvolt = <800000>;
+                               regulator-max-microvolt = <3950000>;
+                       };
+
                        ldo18_reg: LDO18 {
                                regulator-name = "PVDD_EMMC_1V8";
                                regulator-min-microvolt = <1800000>;
@@ -216,10 +503,17 @@
                                regulator-max-microvolt = <1800000>;
                        };
 
+                       ldo22_reg: LDO22 {
+                               /* Unused */
+                               regulator-name = "PVDD_LDO22";
+                               regulator-min-microvolt = <800000>;
+                               regulator-max-microvolt = <2375000>;
+                       };
+
                        ldo23_reg: LDO23 {
                                regulator-name = "PVDD_MIFS_1V1";
-                               regulator-min-microvolt = <1200000>;
-                               regulator-max-microvolt = <1200000>;
+                               regulator-min-microvolt = <800000>;
+                               regulator-max-microvolt = <1100000>;
                                regulator-always-on;
                        };
 
@@ -229,6 +523,13 @@
                                regulator-max-microvolt = <2800000>;
                        };
 
+                       ldo25_reg: LDO25 {
+                               /* Unused */
+                               regulator-name = "PVDD_LDO25";
+                               regulator-min-microvolt = <800000>;
+                               regulator-max-microvolt = <3950000>;
+                       };
+
                        ldo26_reg: LDO26 {
                                regulator-name = "PVDD_CAM0_AF_2V8";
                                regulator-min-microvolt = <3000000>;
@@ -237,8 +538,8 @@
 
                        ldo27_reg: LDO27 {
                                regulator-name = "PVDD_G3DS_1V0";
-                               regulator-min-microvolt = <1200000>;
-                               regulator-max-microvolt = <1200000>;
+                               regulator-min-microvolt = <800000>;
+                               regulator-max-microvolt = <1100000>;
                        };
 
                        ldo28_reg: LDO28 {
@@ -253,6 +554,13 @@
                                regulator-max-microvolt = <1800000>;
                        };
 
+                       ldo30_reg: LDO30 {
+                               /* Unused */
+                               regulator-name = "PVDD_LDO30";
+                               regulator-min-microvolt = <800000>;
+                               regulator-max-microvolt = <3950000>;
+                       };
+
                        ldo31_reg: LDO31 {
                                regulator-name = "PVDD_PERI_1V8";
                                regulator-min-microvolt = <1800000>;
@@ -271,12 +579,33 @@
                                regulator-max-microvolt = <1800000>;
                        };
 
+                       ldo34_reg: LDO34 {
+                               /* Unused */
+                               regulator-name = "PVDD_LDO34";
+                               regulator-min-microvolt = <800000>;
+                               regulator-max-microvolt = <3950000>;
+                       };
+
                        ldo35_reg: LDO35 {
                                regulator-name = "PVDD_CAM0_DVDD_1V2";
                                regulator-min-microvolt = <1200000>;
                                regulator-max-microvolt = <1200000>;
                        };
 
+                       ldo36_reg: LDO36 {
+                               /* Unused */
+                               regulator-name = "PVDD_LDO36";
+                               regulator-min-microvolt = <800000>;
+                               regulator-max-microvolt = <3950000>;
+                       };
+
+                       ldo37_reg: LDO37 {
+                               /* Unused */
+                               regulator-name = "PVDD_LDO37";
+                               regulator-min-microvolt = <800000>;
+                               regulator-max-microvolt = <3950000>;
+                       };
+
                        ldo38_reg: LDO38 {
                                regulator-name = "PVDD_CAM0_AVDD_2V8";
                                regulator-min-microvolt = <2800000>;
@@ -364,7 +693,7 @@
 
 &mmc_0 {
        status = "okay";
-       broken-cd;
+       non-removable;
        card-detect-delay = <200>;
        samsung,dw-mshc-ciu-div = <3>;
        samsung,dw-mshc-sdr-timing = <0 4>;
@@ -372,22 +701,27 @@
        pinctrl-names = "default";
        pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8>;
        vmmc-supply = <&ldo10_reg>;
+       vqmmc-supply = <&ldo3_reg>;
        bus-width = <8>;
        cap-mmc-highspeed;
+       mmc-hs200-1_8v;
 };
 
 &mmc_2 {
        status = "okay";
        card-detect-delay = <200>;
        samsung,dw-mshc-ciu-div = <3>;
-       samsung,dw-mshc-sdr-timing = <2 3>;
-       samsung,dw-mshc-ddr-timing = <1 2>;
+       samsung,dw-mshc-sdr-timing = <0 4>;
+       samsung,dw-mshc-ddr-timing = <0 2>;
        pinctrl-names = "default";
        pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus1 &sd2_bus4>;
        vmmc-supply = <&ldo19_reg>;
        vqmmc-supply = <&ldo13_reg>;
        bus-width = <4>;
        cap-sd-highspeed;
+       sd-uhs-sdr50;
+       sd-uhs-sdr104;
+       sd-uhs-ddr50;
 };
 
 &pinctrl_0 {
@@ -404,3 +738,7 @@
        clocks = <&clock CLK_RTC>, <&s2mps11_osc S2MPS11_CLK_AP>;
        clock-names = "rtc", "rtc_src";
 };
+
+&usbdrd_dwc3_1 {
+       dr_mode = "host";
+};

diff --git a/arch/arm/boot/dts/exynos5420-smdk5420.dts b/arch/arm/boot/dts/exynos5420-smdk5420.dts
index 3cf9050..8240e51 100644 (file)
--- a/arch/arm/boot/dts/exynos5420-smdk5420.dts
+++ b/arch/arm/boot/dts/exynos5420-smdk5420.dts
@@ -21,7 +21,8 @@
        };
 
        chosen {
-               bootargs = "console=ttySAC2,115200 init=/linuxrc";
+               bootargs = "init=/linuxrc";
+               stdout-path = "serial2:115200n8";
        };
 
        fixed-rate-clocks {

diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
index aaff158..5fb2326 100644 (file)
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -5,7 +5,7 @@
  * Copyright (c) 2013 Samsung Electronics Co., Ltd.
  *             http://www.samsung.com
  *
- * SAMSUNG EXYNOS54200 SoC device nodes are listed in this file.
+ * SAMSUNG EXYNOS5420 SoC device nodes are listed in this file.
  * EXYNOS5420 based board files can include this file and provide
  * values for board specfic bindings.
  */

diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3-audio.dtsi b/arch/arm/boot/dts/exynos5422-odroidxu3-audio.dtsi
index 51a843b..c3c2d85 100644 (file)
--- a/arch/arm/boot/dts/exynos5422-odroidxu3-audio.dtsi
+++ b/arch/arm/boot/dts/exynos5422-odroidxu3-audio.dtsi
@@ -22,11 +22,12 @@
                        "Headphone Jack", "HPL",
                        "Headphone Jack", "HPR",
                        "Headphone Jack", "MICBIAS",
-                       "IN1", "Headphone Jack",
+                       "IN12", "Headphone Jack",
                        "Speakers", "SPKL",
                        "Speakers", "SPKR",
                        "I2S Playback", "Mixer DAI TX",
-                       "HiFi Playback", "Mixer DAI TX";
+                       "HiFi Playback", "Mixer DAI TX",
+                       "Mixer DAI RX", "HiFi Capture";
 
                assigned-clocks = <&clock CLK_MOUT_EPLL>,
                                <&clock CLK_MOUT_MAU_EPLL>,

diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi
index 5f195ad..93a48f2 100644 (file)
--- a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi
+++ b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi
@@ -44,8 +44,6 @@
        fan0: pwm-fan {
                compatible = "pwm-fan";
                pwms = <&pwm 0 20972 0>;
-               cooling-min-state = <0>;
-               cooling-max-state = <3>;
                #cooling-cells = <2>;
                cooling-levels = <0 130 170 230>;
        };

diff --git a/arch/arm/boot/dts/exynos54xx.dtsi b/arch/arm/boot/dts/exynos54xx.dtsi
index de26e5e..ae866bc 100644 (file)
--- a/arch/arm/boot/dts/exynos54xx.dtsi
+++ b/arch/arm/boot/dts/exynos54xx.dtsi
@@ -25,27 +25,27 @@
                usbdrdphy1 = &usbdrd_phy1;
        };
 
-       soc: soc {
-               arm_a7_pmu: arm-a7-pmu {
-                       compatible = "arm,cortex-a7-pmu";
-                       interrupt-parent = <&gic>;
-                       interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
-                                    <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
-                                    <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
-                                    <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
-                       status = "disabled";
-               };
+       arm_a7_pmu: arm-a7-pmu {
+               compatible = "arm,cortex-a7-pmu";
+               interrupt-parent = <&gic>;
+               interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
+               status = "disabled";
+       };
 
-               arm_a15_pmu: arm-a15-pmu {
-                       compatible = "arm,cortex-a15-pmu";
-                       interrupt-parent = <&combiner>;
-                       interrupts = <1 2>,
-                                    <7 0>,
-                                    <16 6>,
-                                    <19 2>;
-                       status = "disabled";
-               };
+       arm_a15_pmu: arm-a15-pmu {
+               compatible = "arm,cortex-a15-pmu";
+               interrupt-parent = <&combiner>;
+               interrupts = <1 2>,
+                            <7 0>,
+                            <16 6>,
+                            <19 2>;
+               status = "disabled";
+       };
 
+       soc: soc {
                sysram@2020000 {
                        compatible = "mmio-sram";
                        reg = <0x02020000 0x54000>;

diff --git a/arch/arm/boot/dts/gemini-dlink-dir-685.dts b/arch/arm/boot/dts/gemini-dlink-dir-685.dts
index 592111c..cfbfbc9 100644 (file)
--- a/arch/arm/boot/dts/gemini-dlink-dir-685.dts
+++ b/arch/arm/boot/dts/gemini-dlink-dir-685.dts
@@ -267,44 +267,50 @@
                        /* 32MB of flash */
                        reg = <0x30000000 0x02000000>;
 
-                       /*
-                        * This "RedBoot" is the Storlink derivative.
-                        */
-                       partition@0 {
-                               label = "RedBoot";
-                               reg = <0x00000000 0x00040000>;
-                               read-only;
-                       };
-                       /*
-                        * This firmware image contains the kernel catenated
-                        * with the squashfs root filesystem. For some reason
-                        * this is called "upgrade" on the vendor system.
-                        */
-                       partition@40000 {
-                               label = "upgrade";
-                               reg = <0x00040000 0x01f40000>;
-                               read-only;
-                       };
-                       /* RGDB, Residental Gateway Database? */
-                       partition@1f80000 {
-                               label = "rgdb";
-                               reg = <0x01f80000 0x00040000>;
-                               read-only;
-                       };
-                       /*
-                        * This partition contains MAC addresses for WAN,
-                        * WLAN and LAN, and the country code (for wireless
-                        * I guess).
-                        */
-                       partition@1fc0000 {
-                               label = "nvram";
-                               reg = <0x01fc0000 0x00020000>;
-                               read-only;
-                       };
-                       partition@1fe0000 {
-                               label = "LangPack";
-                               reg = <0x01fe0000 0x00020000>;
-                               read-only;
+                       partitions {
+                               compatible = "fixed-partitions";
+                               #address-cells = <1>;
+                               #size-cells = <1>;
+
+                               /*
+                                * This "RedBoot" is the Storlink derivative.
+                                */
+                               partition@0 {
+                                       label = "RedBoot";
+                                       reg = <0x00000000 0x00040000>;
+                                       read-only;
+                               };
+                               /*
+                                * This firmware image contains the kernel catenated
+                                * with the squashfs root filesystem. For some reason
+                                * this is called "upgrade" on the vendor system.
+                                */
+                               partition@40000 {
+                                       label = "upgrade";
+                                       reg = <0x00040000 0x01f40000>;
+                                       read-only;
+                               };
+                               /* RGDB, Residental Gateway Database? */
+                               partition@1f80000 {
+                                       label = "rgdb";
+                                       reg = <0x01f80000 0x00040000>;
+                                       read-only;
+                               };
+                               /*
+                                * This partition contains MAC addresses for WAN,
+                                * WLAN and LAN, and the country code (for wireless
+                                * I guess).
+                                */
+                               partition@1fc0000 {
+                                       label = "nvram";
+                                       reg = <0x01fc0000 0x00020000>;
+                                       read-only;
+                               };
+                               partition@1fe0000 {
+                                       label = "LangPack";
+                                       reg = <0x01fe0000 0x00020000>;
+                                       read-only;
+                               };
                        };
                };
 

diff --git a/arch/arm/boot/dts/imx35.dtsi b/arch/arm/boot/dts/imx35.dtsi
index 59cadee..9cbdc1a 100644 (file)
--- a/arch/arm/boot/dts/imx35.dtsi
+++ b/arch/arm/boot/dts/imx35.dtsi
@@ -21,6 +21,12 @@
                gpio0 = &gpio1;
                gpio1 = &gpio2;
                gpio2 = &gpio3;
+               i2c0 = &i2c1;
+               i2c1 = &i2c2;
+               i2c2 = &i2c3;
+               mmc0 = &esdhc1;
+               mmc1 = &esdhc2;
+               mmc2 = &esdhc3;
                serial0 = &uart1;
                serial1 = &uart2;
                serial2 = &uart3;

diff --git a/arch/arm/boot/dts/imx50-kobo-aura.dts b/arch/arm/boot/dts/imx50-kobo-aura.dts
new file mode 100644 (file)
index 0000000..a0eaf86
--- /dev/null
+++ b/arch/arm/boot/dts/imx50-kobo-aura.dts
@@ -0,0 +1,258 @@
+// SPDX-License-Identifier: GPL-2.0+
+// Copyright 2019 Jonathan Neuschäfer
+//
+// The Kobo Aura e-book reader, model N514. The mainboard is marked as E606F0B.
+
+/dts-v1/;
+#include "imx50.dtsi"
+#include <dt-bindings/input/input.h>
+
+/ {
+       model = "Kobo Aura (N514)";
+       compatible = "kobo,aura", "fsl,imx50";
+
+       chosen {
+               stdout-path = "serial1:115200n8";
+       };
+
+       memory@70000000 {
+               device_type = "memory";
+               reg = <0x70000000 0x10000000>;
+       };
+
+       gpio-leds {
+               compatible = "gpio-leds";
+               pinctrl-names = "default";
+               pinctrl-0 = <&pinctrl_leds>;
+
+               on {
+                       label = "kobo_aura:orange:on";
+                       gpios = <&gpio6 24 GPIO_ACTIVE_LOW>;
+                       panic-indicator;
+               };
+       };
+
+       gpio-keys {
+               compatible = "gpio-keys";
+               pinctrl-names = "default";
+               pinctrl-0 = <&pinctrl_gpiokeys>;
+
+               power {
+                       label = "Power Button";
+                       gpios = <&gpio4 10 GPIO_ACTIVE_LOW>;
+                       linux,code = <KEY_POWER>;
+               };
+
+               hallsensor {
+                       label = "Hallsensor";
+                       gpios = <&gpio5 15 GPIO_ACTIVE_LOW>;
+                       linux,code = <KEY_RESERVED>;
+                       linux,input-type = <EV_SW>;
+               };
+
+               frontlight {
+                       label = "Frontlight";
+                       gpios = <&gpio4 1 GPIO_ACTIVE_LOW>;
+                       linux,code = <KEY_DISPLAYTOGGLE>;
+               };
+       };
+
+       sd2_pwrseq: pwrseq {
+               compatible = "mmc-pwrseq-simple";
+               pinctrl-names = "default";
+               pinctrl-0 = <&pinctrl_sd2_reset>;
+               reset-gpios = <&gpio4 17 GPIO_ACTIVE_LOW>;
+       };
+
+       sd2_vmmc: gpio-regulator {
+               compatible = "regulator-gpio";
+               pinctrl-names = "default";
+               pinctrl-0 = <&pinctrl_sd2_vmmc>;
+               regulator-name = "vmmc";
+               states = <3300000 0>;
+               regulator-min-microvolt = <3300000>;
+               regulator-max-microvolt = <3300000>;
+               enable-gpio = <&gpio4 12 GPIO_ACTIVE_LOW>;
+               startup-delay-us = <100000>;
+       };
+};
+
+&esdhc1 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_sd1>;
+       max-frequency = <50000000>;
+       bus-width = <4>;
+       cd-gpios = <&gpio5 17 GPIO_ACTIVE_LOW>;
+       disable-wp;
+       status = "okay";
+
+       /* External µSD card */
+};
+
+&esdhc2 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_sd2>;
+       bus-width = <4>;
+       max-frequency = <50000000>;
+       disable-wp;
+       mmc-pwrseq = <&sd2_pwrseq>;
+       vmmc-supply = <&sd2_vmmc>;
+       status = "okay";
+
+       /* CyberTan WC121 SDIO WiFi (BCM43362) */
+};
+
+&esdhc3 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_sd3>;
+       bus-width = <8>;
+       non-removable;
+       max-frequency = <50000000>;
+       disable-wp;
+       status = "okay";
+
+       /* Internal eMMC */
+};
+
+&i2c1 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_i2c1>;
+       status = "okay";
+
+       /* TODO: ektf2132 touch controller at 0x15 */
+};
+
+&i2c2 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_i2c2>;
+       status = "okay";
+
+       /* TODO: TPS65185 PMIC for E Ink at 0x68 */
+};
+
+&i2c3 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_i2c3>;
+       status = "okay";
+
+       /* TODO: embedded controller at 0x43 */
+};
+
+&iomuxc {
+       pinctrl_gpiokeys: gpiokeys {
+               fsl,pins = <
+                       MX50_PAD_CSPI_MISO__GPIO4_10            0x0
+                       MX50_PAD_SD2_D7__GPIO5_15               0x0
+                       MX50_PAD_KEY_ROW0__GPIO4_1              0x0
+               >;
+       };
+
+       pinctrl_i2c1: i2c1 {
+               fsl,pins = <
+                       MX50_PAD_I2C1_SCL__I2C1_SCL             0x400001fd
+                       MX50_PAD_I2C1_SDA__I2C1_SDA             0x400001fd
+               >;
+       };
+
+       pinctrl_i2c2: i2c2 {
+               fsl,pins = <
+                       MX50_PAD_I2C2_SCL__I2C2_SCL             0x400001fd
+                       MX50_PAD_I2C2_SDA__I2C2_SDA             0x400001fd
+               >;
+       };
+
+       pinctrl_i2c3: i2c3 {
+               fsl,pins = <
+                       MX50_PAD_I2C3_SCL__I2C3_SCL             0x400001fd
+                       MX50_PAD_I2C3_SDA__I2C3_SDA             0x400001fd
+               >;
+       };
+
+       pinctrl_leds: leds {
+               fsl,pins = <
+                       MX50_PAD_PWM1__GPIO6_24                 0x0
+               >;
+       };
+
+       pinctrl_sd1: sd1 {
+               fsl,pins = <
+                       MX50_PAD_SD1_CMD__ESDHC1_CMD            0x1e4
+                       MX50_PAD_SD1_CLK__ESDHC1_CLK            0xd4
+                       MX50_PAD_SD1_D0__ESDHC1_DAT0            0x1d4
+                       MX50_PAD_SD1_D1__ESDHC1_DAT1            0x1d4
+                       MX50_PAD_SD1_D2__ESDHC1_DAT2            0x1d4
+                       MX50_PAD_SD1_D3__ESDHC1_DAT3            0x1d4
+
+                       MX50_PAD_SD2_CD__GPIO5_17               0x0
+               >;
+       };
+
+       pinctrl_sd2: sd2 {
+               fsl,pins = <
+                       MX50_PAD_SD2_CMD__ESDHC2_CMD            0x1e4
+                       MX50_PAD_SD2_CLK__ESDHC2_CLK            0xd4
+                       MX50_PAD_SD2_D0__ESDHC2_DAT0            0x1d4
+                       MX50_PAD_SD2_D1__ESDHC2_DAT1            0x1d4
+                       MX50_PAD_SD2_D2__ESDHC2_DAT2            0x1d4
+                       MX50_PAD_SD2_D3__ESDHC2_DAT3            0x1d4
+               >;
+       };
+
+       pinctrl_sd2_reset: sd2-reset {
+               fsl,pins = <
+                       MX50_PAD_ECSPI2_MOSI__GPIO4_17          0x0
+               >;
+       };
+
+       pinctrl_sd2_vmmc: sd2-vmmc {
+               fsl,pins = <
+                       MX50_PAD_ECSPI1_SCLK__GPIO4_12          0x0
+               >;
+       };
+
+       pinctrl_sd3: sd3 {
+               fsl,pins = <
+                       MX50_PAD_SD3_CMD__ESDHC3_CMD            0x1e4
+                       MX50_PAD_SD3_CLK__ESDHC3_CLK            0xd4
+                       MX50_PAD_SD3_D0__ESDHC3_DAT0            0x1d4
+                       MX50_PAD_SD3_D1__ESDHC3_DAT1            0x1d4
+                       MX50_PAD_SD3_D2__ESDHC3_DAT2            0x1d4
+                       MX50_PAD_SD3_D3__ESDHC3_DAT3            0x1d4
+                       MX50_PAD_SD3_D4__ESDHC3_DAT4            0x1d4
+                       MX50_PAD_SD3_D5__ESDHC3_DAT5            0x1d4
+                       MX50_PAD_SD3_D6__ESDHC3_DAT6            0x1d4
+                       MX50_PAD_SD3_D7__ESDHC3_DAT7            0x1d4
+               >;
+       };
+
+       pinctrl_uart2: uart2 {
+               fsl,pins = <
+                       MX50_PAD_UART2_TXD__UART2_TXD_MUX       0x1e4
+                       MX50_PAD_UART2_RXD__UART2_RXD_MUX       0x1e4
+               >;
+       };
+
+       pinctrl_usbphy: usbphy {
+               fsl,pins = <
+                       MX50_PAD_ECSPI2_SS0__GPIO4_19           0x0
+               >;
+       };
+};
+
+&uart2 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_uart2>;
+       status = "okay";
+};
+
+&usbotg {
+       phy_type = "utmi_wide";
+       dr_mode = "peripheral";
+       status = "okay";
+};
+
+&usbphy0 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_usbphy>;
+       vbus-detect-gpio = <&gpio4 19 GPIO_ACTIVE_LOW>;
+};

diff --git a/arch/arm/boot/dts/imx50.dtsi b/arch/arm/boot/dts/imx50.dtsi
index ee1e3e8..0bfe7c9 100644 (file)
--- a/arch/arm/boot/dts/imx50.dtsi
+++ b/arch/arm/boot/dts/imx50.dtsi
@@ -26,11 +26,21 @@
                gpio3 = &gpio4;
                gpio4 = &gpio5;
                gpio5 = &gpio6;
+               i2c0 = &i2c1;
+               i2c1 = &i2c2;
+               i2c2 = &i2c3;
+               mmc0 = &esdhc1;
+               mmc1 = &esdhc2;
+               mmc2 = &esdhc3;
+               mmc3 = &esdhc4;
                serial0 = &uart1;
                serial1 = &uart2;
                serial2 = &uart3;
                serial3 = &uart4;
                serial4 = &uart5;
+               spi0 = &ecspi1;
+               spi1 = &ecspi2;
+               spi2 = &cspi;
        };
 
        cpus {
@@ -76,6 +86,14 @@
                };
        };
 
+       usbphy0: usbphy-0 {
+               compatible = "usb-nop-xceiv";
+               clocks = <&clks IMX5_CLK_USB_PHY1_GATE>;
+               clock-names = "main_clk";
+               #phy-cells = <0>;
+               status = "okay";
+       };
+
        soc {
                #address-cells = <1>;
                #size-cells = <1>;
@@ -187,7 +205,8 @@
                                compatible = "fsl,imx50-usb", "fsl,imx27-usb";
                                reg = <0x53f80000 0x0200>;
                                interrupts = <18>;
-                               clocks = <&clks IMX5_CLK_USB_PHY1_GATE>;
+                               clocks = <&clks IMX5_CLK_USBOH3_GATE>;
+                               fsl,usbphy = <&usbphy0>;
                                status = "disabled";
                        };
 
@@ -411,7 +430,7 @@
                                reg = <0x63fb0000 0x4000>;
                                interrupts = <6>;
                                clocks = <&clks IMX5_CLK_SDMA_GATE>,
-                                        <&clks IMX5_CLK_SDMA_GATE>;
+                                        <&clks IMX5_CLK_AHB>;
                                clock-names = "ipg", "ahb";
                                #dma-cells = <3>;
                                fsl,sdma-ram-script-name = "imx/sdma/sdma-imx50.bin";

diff --git a/arch/arm/boot/dts/imx51-zii-rdu1.dts b/arch/arm/boot/dts/imx51-zii-rdu1.dts
index a8220f0..3596060 100644 (file)
--- a/arch/arm/boot/dts/imx51-zii-rdu1.dts
+++ b/arch/arm/boot/dts/imx51-zii-rdu1.dts
@@ -1,42 +1,6 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
 /*
  * Copyright (C) 2017 Zodiac Inflight Innovations
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- *  a) This file is free software; you can redistribute it and/or
- *     modify it under the terms of the GNU General Public License
- *     version 2 as published by the Free Software Foundation.
- *
- *     This file is distributed in the hope that it will be useful,
- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *     GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- *  b) Permission is hereby granted, free of charge, to any person
- *     obtaining a copy of this software and associated documentation
- *     files (the "Software"), to deal in the Software without
- *     restriction, including without limitation the rights to use,
- *     copy, modify, merge, publish, distribute, sublicense, and/or
- *     sell copies of the Software, and to permit persons to whom the
- *     Software is furnished to do so, subject to the following
- *     conditions:
- *
- *     The above copyright notice and this permission notice shall be
- *     included in all copies or substantial portions of the Software.
- *
- *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND,
- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- *     OTHER DEALINGS IN THE SOFTWARE.
  */
 
 /dts-v1/;

diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi
index a5ee25c..0a4b9a5 100644 (file)
--- a/arch/arm/boot/dts/imx51.dtsi
+++ b/arch/arm/boot/dts/imx51.dtsi
@@ -489,7 +489,7 @@
                                reg = <0x83fb0000 0x4000>;
                                interrupts = <6>;
                                clocks = <&clks IMX5_CLK_SDMA_GATE>,
-                                        <&clks IMX5_CLK_SDMA_GATE>;
+                                        <&clks IMX5_CLK_AHB>;
                                clock-names = "ipg", "ahb";
                                #dma-cells = <3>;
                                fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin";

diff --git a/arch/arm/boot/dts/imx53-m53.dtsi b/arch/arm/boot/dts/imx53-m53.dtsi
index db2e5bc..d1770e1 100644 (file)
--- a/arch/arm/boot/dts/imx53-m53.dtsi
+++ b/arch/arm/boot/dts/imx53-m53.dtsi
@@ -52,7 +52,7 @@
        clock-frequency = <400000>;
        status = "okay";
 
-       stmpe610@41 {
+       touchscreen@41 {
                compatible = "st,stmpe610";
                reg = <0x41>;
                id = <0>;

diff --git a/arch/arm/boot/dts/imx53-m53menlo.dts b/arch/arm/boot/dts/imx53-m53menlo.dts
new file mode 100644 (file)
index 0000000..f0a3fde
--- /dev/null
+++ b/arch/arm/boot/dts/imx53-m53menlo.dts
@@ -0,0 +1,311 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2019 Marek Vasut <marex@denx.de>
+ */
+
+/dts-v1/;
+#include "imx53-m53.dtsi"
+
+/ {
+       model = "MENLO M53 EMBEDDED DEVICE";
+       compatible = "menlo,m53menlo", "fsl,imx53";
+
+       leds {
+               compatible = "gpio-leds";
+               pinctrl-names = "default";
+               pinctrl-0 = <&pinctrl_led>;
+
+               user1 {
+                       label = "TestLed601";
+                       gpios = <&gpio6 1 GPIO_ACTIVE_HIGH>;
+                       linux,default-trigger = "mmc0";
+               };
+
+               user2 {
+                       label = "TestLed602";
+                       gpios = <&gpio6 2 GPIO_ACTIVE_HIGH>;
+                       linux,default-trigger = "heartbeat";
+               };
+
+               eth {
+                       label = "EthLedYe";
+                       gpios = <&gpio2 11 GPIO_ACTIVE_LOW>;
+                       linux,default-trigger = "none";
+               };
+       };
+
+       panel {
+               compatible = "edt,etm070080dh6";
+               enable-gpios = <&gpio6 0 GPIO_ACTIVE_HIGH>;
+
+               port {
+                       panel_in: endpoint {
+                               remote-endpoint = <&lvds0_out>;
+                       };
+               };
+       };
+
+       reg_usbh1_vbus: regulator-usbh1-vbus {
+               compatible = "regulator-fixed";
+               regulator-name = "vbus";
+               regulator-min-microvolt = <5000000>;
+               regulator-max-microvolt = <5000000>;
+               gpio = <&gpio1 2 GPIO_ACTIVE_LOW>;
+       };
+};
+
+&can1 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_can1>;
+       status = "okay";
+};
+
+&can2 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_can2>;
+       status = "okay";
+};
+
+&clks {
+       assigned-clocks = <&clks IMX5_CLK_CKO1_SEL>,
+                         <&clks IMX5_CLK_CKO1_PODF>,
+                         <&clks IMX5_CLK_CKO1>;
+       assigned-clock-parents = <&clks IMX5_CLK_AHB>;
+       assigned-clock-rates = <133333334>, <33333334>, <33333334>;
+};
+
+&esdhc1 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_esdhc1>;
+       cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
+       wp-gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>;
+       status = "okay";
+};
+
+&fec {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_fec>;
+       phy-mode = "rmii";
+       status = "okay";
+};
+
+&i2c1 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_i2c1>;
+       status = "okay";
+
+       touchscreen@38 {
+               compatible = "edt,edt-ft5x06";
+               reg = <0x38>;
+               pinctrl-names = "default";
+               pinctrl-0 = <&pinctrl_edt_ft5x06>;
+               interrupt-parent = <&gpio6>;
+               interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
+               reset-gpios = <&gpio2 9 GPIO_ACTIVE_LOW>;
+               wake-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>;
+       };
+
+       eeprom@50 {
+               compatible = "atmel,24c64";
+               reg = <0x50>;
+               pagesize = <32>;
+       };
+
+       dac@60 {
+               compatible = "microchip,mcp4725";
+               reg = <0x60>;
+       };
+};
+
+&i2c2 {
+       touchscreen@41 {
+               status = "disabled";
+       };
+};
+
+&i2c3 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_i2c3>;
+       status = "okay";
+};
+
+&iomuxc {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_hog>;
+
+       imx53-m53evk {
+               hoggrp {
+                       fsl,pins = <
+                               MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK       0x1c4
+                               MX53_PAD_EIM_EB3__GPIO2_31              0x1d5
+                               MX53_PAD_PATA_DA_0__GPIO7_6             0x1d5
+                               MX53_PAD_GPIO_19__CCM_CLKO              0x1d5
+                               MX53_PAD_CSI0_MCLK__CCM_CSI0_MCLK       0x1d5
+                               MX53_PAD_CSI0_DAT4__GPIO5_22            0x1d5
+                               MX53_PAD_CSI0_DAT5__GPIO5_23            0x1d5
+                               MX53_PAD_CSI0_DAT6__GPIO5_24            0x1d5
+                               MX53_PAD_CSI0_DAT7__GPIO5_25            0x1d5
+                               MX53_PAD_CSI0_DAT8__GPIO5_26            0x1d5
+                               MX53_PAD_CSI0_DAT9__GPIO5_27            0x1d5
+                               MX53_PAD_CSI0_DAT10__GPIO5_28           0x1d5
+                               MX53_PAD_CSI0_DAT11__GPIO5_29           0x1d5
+                               MX53_PAD_CSI0_DAT14__GPIO6_0            0x1d5
+                       >;
+               };
+
+               pinctrl_led: ledgrp {
+                       fsl,pins = <
+                               MX53_PAD_CSI0_DAT15__GPIO6_1            0x1d5
+                               MX53_PAD_CSI0_DAT16__GPIO6_2            0x1d5
+                       >;
+               };
+
+               pinctrl_can1: can1grp {
+                       fsl,pins = <
+                               MX53_PAD_GPIO_7__CAN1_TXCAN             0x1c4
+                               MX53_PAD_GPIO_8__CAN1_RXCAN             0x1c4
+                       >;
+               };
+
+               pinctrl_can2: can2grp {
+                       fsl,pins = <
+                               MX53_PAD_KEY_COL4__CAN2_TXCAN           0x1c4
+                               MX53_PAD_KEY_ROW4__CAN2_RXCAN           0x1c4
+                       >;
+               };
+
+               pinctrl_display_gpio: display-gpiogrp {
+                       fsl,pins = <
+                               MX53_PAD_CSI0_DAT12__GPIO5_30           0x1d5 /* Reset */
+                               MX53_PAD_CSI0_DAT13__GPIO5_31           0x1d5 /* Interrupt */
+                       >;
+               };
+
+               pinctrl_edt_ft5x06: edt-ft5x06grp {
+                       fsl,pins = <
+                               MX53_PAD_PATA_DATA9__GPIO2_9            0x1d5 /* Reset */
+                               MX53_PAD_CSI0_DAT19__GPIO6_5            0x1d5 /* Interrupt */
+                               MX53_PAD_PATA_DATA10__GPIO2_10          0x1d5 /* Wake */
+                       >;
+               };
+
+               pinctrl_esdhc1: esdhc1grp {
+                       fsl,pins = <
+                               MX53_PAD_SD1_DATA0__ESDHC1_DAT0         0x1d5
+                               MX53_PAD_SD1_DATA1__ESDHC1_DAT1         0x1d5
+                               MX53_PAD_SD1_DATA2__ESDHC1_DAT2         0x1d5
+                               MX53_PAD_SD1_DATA3__ESDHC1_DAT3         0x1d5
+                               MX53_PAD_SD1_CMD__ESDHC1_CMD            0x1d5
+                               MX53_PAD_SD1_CLK__ESDHC1_CLK            0x1d5
+                       >;
+               };
+
+               pinctrl_fec: fecgrp {
+                       fsl,pins = <
+                               MX53_PAD_FEC_MDC__FEC_MDC               0x4
+                               MX53_PAD_FEC_MDIO__FEC_MDIO             0x1fc
+                               MX53_PAD_FEC_REF_CLK__FEC_TX_CLK        0x180
+                               MX53_PAD_FEC_RX_ER__FEC_RX_ER           0x180
+                               MX53_PAD_FEC_CRS_DV__FEC_RX_DV          0x180
+                               MX53_PAD_FEC_RXD1__FEC_RDATA_1          0x180
+                               MX53_PAD_FEC_RXD0__FEC_RDATA_0          0x180
+                               MX53_PAD_FEC_TX_EN__FEC_TX_EN           0x4
+                               MX53_PAD_FEC_TXD1__FEC_TDATA_1          0x4
+                               MX53_PAD_FEC_TXD0__FEC_TDATA_0          0x4
+                       >;
+               };
+
+               pinctrl_i2c1: i2c1grp {
+                       fsl,pins = <
+                               MX53_PAD_EIM_D21__I2C1_SCL              0x400001e4
+                               MX53_PAD_EIM_D28__I2C1_SDA              0x400001e4
+                       >;
+               };
+
+               pinctrl_i2c3: i2c3grp {
+                       fsl,pins = <
+                               MX53_PAD_GPIO_6__I2C3_SDA               0x400001e4
+                               MX53_PAD_GPIO_5__I2C3_SCL               0x400001e4
+                       >;
+               };
+
+               pinctrl_lvds0: lvds0grp {
+                       /* LVDS pins only have pin mux configuration */
+                       fsl,pins = <
+                               MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK     0x80000000
+                               MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0     0x80000000
+                               MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1     0x80000000
+                               MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2     0x80000000
+                               MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3     0x80000000
+                       >;
+               };
+
+               pinctrl_uart1: uart1grp {
+                       fsl,pins = <
+                               MX53_PAD_PATA_DIOW__UART1_TXD_MUX       0x1e4
+                               MX53_PAD_PATA_DMACK__UART1_RXD_MUX      0x1e4
+                       >;
+               };
+
+               pinctrl_uart2: uart2grp {
+                       fsl,pins = <
+                               MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX  0x1e4
+                               MX53_PAD_PATA_DMARQ__UART2_TXD_MUX      0x1e4
+                       >;
+               };
+
+               pinctrl_usb: usbgrp {
+                       fsl,pins = <
+                               MX53_PAD_GPIO_2__GPIO1_2                0x1d5
+                               MX53_PAD_GPIO_3__USBOH3_USBH1_OC        0x1d5
+                       >;
+               };
+       };
+};
+
+&ldb {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_lvds0>;
+       status = "okay";
+
+       lvds0: lvds-channel@0 {
+               reg = <0>;
+               fsl,data-mapping = "spwg";
+               fsl,data-width = <18>;
+               status = "okay";
+
+               port@2 {
+                       reg = <2>;
+
+                       lvds0_out: endpoint {
+                               remote-endpoint = <&panel_in>;
+                       };
+               };
+       };
+};
+
+&uart1 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_uart1>;
+       status = "okay";
+};
+
+&uart2 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_uart2>;
+       status = "okay";
+};
+
+&usbh1 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_usb>;
+       vbus-supply = <&reg_usbh1_vbus>;
+       phy_type = "utmi";
+       dr_mode = "peripheral";
+       status = "okay";
+};
+
+&usbotg {
+       dr_mode = "peripheral";
+       status = "okay";
+};

diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi
index b330030..9b672ed 100644 (file)
--- a/arch/arm/boot/dts/imx53.dtsi
+++ b/arch/arm/boot/dts/imx53.dtsi
@@ -702,7 +702,7 @@
                                reg = <0x63fb0000 0x4000>;
                                interrupts = <6>;
                                clocks = <&clks IMX5_CLK_SDMA_GATE>,
-                                        <&clks IMX5_CLK_SDMA_GATE>;
+                                        <&clks IMX5_CLK_AHB>;
                                clock-names = "ipg", "ahb";
                                #dma-cells = <3>;
                                fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";

diff --git a/arch/arm/boot/dts/imx6-logicpd-baseboard.dtsi b/arch/arm/boot/dts/imx6-logicpd-baseboard.dtsi
index c40a7af..2a6ce87 100644 (file)
--- a/arch/arm/boot/dts/imx6-logicpd-baseboard.dtsi
+++ b/arch/arm/boot/dts/imx6-logicpd-baseboard.dtsi
@@ -249,9 +249,9 @@
                gpio-cfg = <
                        0x0000 /* 0:Default */
                        0x0000 /* 1:Default */
-                       0x0013 /* 2:FN_DMICCLK */
+                       0x0000 /* 2:FN_DMICCLK */
                        0x0000 /* 3:Default */
-                       0x8014 /* 4:FN_DMICCDAT */
+                       0x0000 /* 4:FN_DMICCDAT */
                        0x0000 /* 5:Default */
                >;
        };

diff --git a/arch/arm/boot/dts/imx6dl-eckelmann-ci4x10.dts b/arch/arm/boot/dts/imx6dl-eckelmann-ci4x10.dts
new file mode 100644 (file)
index 0000000..9eb2b73
--- /dev/null
+++ b/arch/arm/boot/dts/imx6dl-eckelmann-ci4x10.dts
@@ -0,0 +1,381 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2016 Eckelmann AG.
+ * Copyright (C) 2013 Freescale Semiconductor, Inc.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+
+#include "imx6dl.dtsi"
+
+/ {
+       model = "Eckelmann CI 4X10 Board";
+       compatible = "eckelmann,imx6dl-ci4x10", "fsl,imx6dl";
+
+       chosen {
+               stdout-path = &uart3;
+       };
+
+       memory@10000000 {
+               device_type = "memory";
+               reg = <0x10000000 0x40000000>;
+       };
+
+       rmii_clk: clock-rmii {
+               /* This clock is provided by the phy (KSZ8091RNB) */
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               clock-frequency = <50000000>;
+       };
+
+       reg_usb_h1_vbus: regulator-usb-h1-vbus {
+               pinctrl-names = "default";
+               pinctrl-0 = <&pinctrl_reg_usb_h1_vbus>;
+               compatible = "regulator-fixed";
+               regulator-name = "usb_h1_vbus";
+               regulator-min-microvolt = <5000000>;
+               regulator-max-microvolt = <5000000>;
+               gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>;
+               enable-active-high;
+       };
+
+       siox {
+               compatible = "eckelmann,siox-gpio";
+               pinctrl-names = "default";
+               pinctrl-0 = <&pinctrl_siox>;
+               din-gpios = <&gpio6 11 GPIO_ACTIVE_HIGH>;
+               dout-gpios = <&gpio6 8 GPIO_ACTIVE_HIGH>;
+               dclk-gpios = <&gpio6 9 GPIO_ACTIVE_HIGH>;
+               dld-gpios = <&gpio6 10 GPIO_ACTIVE_HIGH>;
+       };
+};
+
+&can1 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_flexcan1>;
+       status = "okay";
+};
+
+&can2 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_flexcan2>;
+       status = "okay";
+};
+
+&ecspi2 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_ecspi2>;
+       cs-gpios = <&gpio5 12 GPIO_ACTIVE_HIGH>;
+       status = "okay";
+
+       flash@0 {
+               compatible = "everspin,mr25h256";
+               reg = <0>;
+               spi-max-frequency = <15000000>;
+       };
+};
+
+&ecspi1 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_ecspi1>;
+       cs-gpios = <&gpio5 25 GPIO_ACTIVE_HIGH>;
+       status = "okay";
+
+       tpm@0 {
+               compatible = "infineon,slb9670", "tcg,tpm_tis-spi";
+               reg = <0>;
+               spi-max-frequency = <10000000>;
+       };
+};
+
+&gpio2 {
+       gpio-line-names = "buzzer", "", "", "", "", "", "", "",
+                         "", "", "", "", "", "", "", "",
+                         "", "", "", "", "", "", "", "",
+                         "", "", "", "", "", "", "", "";
+};
+
+&gpio4 {
+       gpio-line-names = "", "", "", "", "", "", "", "in2",
+                         "prio2", "prio1", "aux", "", "", "", "", "",
+                         "", "", "", "", "", "", "", "",
+                         "", "", "", "", "", "", "", "";
+};
+
+&gpio6 {
+       gpio-line-names = "", "", "", "", "", "", "", "",
+                         "", "", "", "", "", "", "", "in1",
+                         "", "", "", "", "", "", "", "",
+                         "", "", "", "", "", "", "", "";
+};
+
+&i2c1 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_i2c1>;
+       status = "okay";
+
+       temperature-sensor@49 {
+               compatible = "ad,ad7414";
+               reg = <0x49>;
+       };
+
+       rtc@51 {
+               compatible = "nxp,pcf2127";
+               reg = <0x51>;
+       };
+};
+
+&iomuxc {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_hog>;
+
+       pinctrl_hog: hog {
+               fsl,pins = <
+                       MX6QDL_PAD_NANDF_D0__GPIO2_IO00         0x00000018 /* buzzer */
+                       MX6QDL_PAD_KEY_COL1__GPIO4_IO08         0x00000018 /* OUT_1 */
+                       MX6QDL_PAD_KEY_ROW1__GPIO4_IO09         0x00000018 /* OUT_2 */
+                       MX6QDL_PAD_KEY_COL2__GPIO4_IO10         0x00000018 /* OUT_3 */
+                       MX6QDL_PAD_NANDF_CS2__GPIO6_IO15        0x00000000 /* In1 */
+                       MX6QDL_PAD_KEY_ROW0__GPIO4_IO07         0x00000000 /* In2 */
+                       MX6QDL_PAD_GPIO_9__GPIO1_IO09           0x00000018 /* unused watchdog pin */
+                       MX6QDL_PAD_SD1_DAT2__GPIO1_IO19         0x00000018 /* unused watchdog pin */
+
+               >;
+       };
+
+       pinctrl_ecspi1: ecspi1grp {
+               fsl,pins = <
+                       MX6QDL_PAD_CSI0_DAT4__ECSPI1_SCLK       0x000100a0
+                       MX6QDL_PAD_CSI0_DAT5__ECSPI1_MOSI       0x000100a0
+                       MX6QDL_PAD_CSI0_DAT6__ECSPI1_MISO       0x000100a0
+                       MX6QDL_PAD_CSI0_DAT7__GPIO5_IO25        0x000100a0
+               >;
+       };
+
+       pinctrl_ecspi2: ecspi2grp {
+               fsl,pins = <
+                       MX6QDL_PAD_DISP0_DAT19__ECSPI2_SCLK     0x000100b1
+                       MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI         0x000100b1
+                       MX6QDL_PAD_EIM_OE__ECSPI2_MISO          0x000100b1
+                       MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12      0x000100b1
+               >;
+       };
+
+       pinctrl_enet: enetgrp {
+               fsl,pins = <
+                       MX6QDL_PAD_GPIO_16__ENET_REF_CLK        0x4001b0a8
+                       MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x0001b098
+                       MX6QDL_PAD_ENET_MDC__ENET_MDC           0x0001b098
+                       MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0     0x0001b098
+                       MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1     0x0001b098
+                       MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN       0x0001b098
+                       MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER       0x0001b0b0
+                       MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0     0x0001b0b0
+                       MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1     0x0001b0b0
+                       MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN      0x0001b0b0
+                       MX6QDL_PAD_SD1_CMD__GPIO1_IO18          0x00000018
+               >;
+       };
+
+       pinctrl_flexcan1: flexcan1grp {
+               fsl,pins = <
+                       MX6QDL_PAD_GPIO_7__FLEXCAN1_TX          0x0001b020
+                       MX6QDL_PAD_GPIO_8__FLEXCAN1_RX          0x0001b0b0
+               >;
+       };
+
+       pinctrl_flexcan2: flexcan2grp {
+               fsl,pins = <
+                       MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX        0x0001b020
+                       MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX        0x0001b0b0
+               >;
+       };
+
+       pinctrl_i2c1: i2c1grp {
+               fsl,pins = <
+                       /* without SION i2c doesn't detect bus busy */
+                       MX6QDL_PAD_CSI0_DAT9__I2C1_SCL          0x4001b820
+                       MX6QDL_PAD_CSI0_DAT8__I2C1_SDA          0x4001b820
+               >;
+       };
+
+       pinctrl_pcie: pciegrp {
+               fsl,pins = <
+                       MX6QDL_PAD_SD1_CLK__GPIO1_IO20          0x00000018
+               >;
+       };
+
+       pinctrl_reg_usb_h1_vbus: reg_usb_h1_vbusgrp {
+               fsl,pins = <
+                       MX6QDL_PAD_EIM_D31__GPIO3_IO31          0x0001b0b0
+               >;
+       };
+
+       pinctrl_siox: sioxgrp {
+               fsl,pins = <
+                       MX6QDL_PAD_NANDF_CS0__GPIO6_IO11        0x0001b010      /* DIN */
+                       MX6QDL_PAD_NANDF_ALE__GPIO6_IO08        0x0001b010      /* DOUT */
+                       MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09       0x0001b010      /* DCLK */
+                       MX6QDL_PAD_NANDF_RB0__GPIO6_IO10        0x0001b010      /* DLD */
+               >;
+       };
+
+       pinctrl_uart1_dte: uart1grp {
+               fsl,pins = <
+                       MX6QDL_PAD_CSI0_DAT11__UART1_TX_DATA    0x0001b010
+                       MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA    0x0001b010
+                       MX6QDL_PAD_EIM_D19__UART1_RTS_B         0x0001b010
+                       MX6QDL_PAD_EIM_D20__UART1_CTS_B         0x0001b010
+                       MX6QDL_PAD_EIM_D23__GPIO3_IO23          0x0001b010      /* DCD */
+                       MX6QDL_PAD_EIM_D24__GPIO3_IO24          0x0001b010      /* DTR */
+                       MX6QDL_PAD_EIM_D25__GPIO3_IO25          0x0001b010      /* DSR */
+               >;
+       };
+
+       pinctrl_uart2_dte: uart2grp {
+               fsl,pins = <
+                       MX6QDL_PAD_EIM_D27__UART2_TX_DATA       0x0001b010
+                       MX6QDL_PAD_EIM_D26__UART2_RX_DATA       0x0001b010
+                       MX6QDL_PAD_EIM_D28__UART2_RTS_B         0x0001b010
+                       MX6QDL_PAD_EIM_D29__UART2_CTS_B         0x0001b010
+                       MX6QDL_PAD_NANDF_D1__GPIO2_IO01         0x0001b010      /* DCD */
+                       MX6QDL_PAD_GPIO_18__GPIO7_IO13          0x0001b010      /* DTR */
+                       MX6QDL_PAD_NANDF_CS3__GPIO6_IO16        0x0001b010      /* DSR */
+               >;
+       };
+
+       pinctrl_uart3_dce: uart3grp {
+               fsl,pins = <
+                       MX6QDL_PAD_SD4_CLK__UART3_RX_DATA       0x0001b010
+                       MX6QDL_PAD_SD4_CMD__UART3_TX_DATA       0x0001b010
+               >;
+       };
+
+       pinctrl_uart4_dce: uart4grp {
+               fsl,pins = <
+                       MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA    0x0001b010
+                       MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA    0x0001b010
+                       MX6QDL_PAD_CSI0_DAT17__GPIO6_IO03       0x0001b010
+               >;
+       };
+
+       pinctrl_uart5_dce: uart5grp {
+               fsl,pins = <
+                       MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA    0x0001b010
+                       MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA    0x0001b010
+                       MX6QDL_PAD_CSI0_DAT19__GPIO6_IO05       0x0001b010      /* RTS */
+               >;
+       };
+
+       pinctrl_usbh1: usbh1grp {
+               fsl,pins = <
+                       MX6QDL_PAD_EIM_D30__USB_H1_OC           0x0001b0b0
+               >;
+       };
+
+       pinctrl_usdhc3: usdhc3grp {
+               fsl,pins = <
+                       MX6QDL_PAD_SD3_CMD__SD3_CMD             0x00017059
+                       MX6QDL_PAD_SD3_CLK__SD3_CLK             0x00010059
+                       MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x00017059
+                       MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x00017059
+                       MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x00017059
+                       MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x00017059
+                       MX6QDL_PAD_SD3_DAT4__SD3_DATA4          0x00017059
+                       MX6QDL_PAD_SD3_DAT5__SD3_DATA5          0x00017059
+                       MX6QDL_PAD_SD3_DAT6__SD3_DATA6          0x00017059
+                       MX6QDL_PAD_SD3_DAT7__SD3_DATA7          0x00017059
+               >;
+       };
+};
+
+&fec {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_enet>;
+       phy-mode = "rmii";
+       phy-reset-gpios = <&gpio1 18 GPIO_ACTIVE_LOW>;
+       phy-handle = <&phy>;
+       clocks = <&clks IMX6QDL_CLK_ENET>, <&clks IMX6QDL_CLK_ENET>, <&rmii_clk>;
+       status = "okay";
+
+       mdio {
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               phy: ethernet-phy@1 {
+                       compatible = "ethernet-phy-ieee802.3-c22";
+                       reg = <1>;
+               };
+       };
+};
+
+&pcie {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_pcie>;
+       reset-gpio = <&gpio1 20 GPIO_ACTIVE_LOW>;
+       status = "okay";
+};
+
+&uart1 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_uart1_dte>;
+       uart-has-rtscts;
+       fsl,dte-mode;
+       dcd-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
+       dtr-gpios = <&gpio3 24 GPIO_ACTIVE_LOW>;
+       dsr-gpios = <&gpio3 25 GPIO_ACTIVE_LOW>;
+       status = "okay";
+};
+
+&uart2 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_uart2_dte>;
+       uart-has-rtscts;
+       fsl,dte-mode;
+       dcd-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
+       dtr-gpios = <&gpio7 13 GPIO_ACTIVE_LOW>;
+       dsr-gpios = <&gpio6 16 GPIO_ACTIVE_LOW>;
+       status = "okay";
+};
+
+&uart3 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_uart3_dce>;
+       status = "okay";
+};
+
+&uart4 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_uart4_dce>;
+       rts-gpios = <&gpio6 3 GPIO_ACTIVE_HIGH>;
+       status = "okay";
+};
+
+&uart5 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_uart5_dce>;
+       rts-gpios = <&gpio6 5 GPIO_ACTIVE_HIGH>;
+       status = "okay";
+};
+
+&usbh1 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_usbh1>;
+       vbus-supply = <&reg_usb_h1_vbus>;
+       status = "okay";
+};
+
+&usbotg {
+       dr_mode = "peripheral";
+       status = "okay";
+};
+
+&usdhc3 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_usdhc3>;
+       bus-width = <8>;
+       non-removable;
+       status = "okay";
+};

diff --git a/arch/arm/boot/dts/imx6dl-sabreauto.dts b/arch/arm/boot/dts/imx6dl-sabreauto.dts
index 660d52a..ff3283c 100644 (file)
--- a/arch/arm/boot/dts/imx6dl-sabreauto.dts
+++ b/arch/arm/boot/dts/imx6dl-sabreauto.dts
@@ -11,3 +11,18 @@
        model = "Freescale i.MX6 DualLite/Solo SABRE Automotive Board";
        compatible = "fsl,imx6dl-sabreauto", "fsl,imx6dl";
 };
+
+&cpu0 {
+       operating-points = <
+               /* kHz    uV */
+               996000  1275000
+               792000  1175000
+               396000  1150000
+       >;
+       fsl,soc-operating-points = <
+               /* ARM kHz  SOC-PU uV */
+               996000  1200000
+               792000  1175000
+               396000  1175000
+       >;
+};

diff --git a/arch/arm/boot/dts/imx6q-gw54xx.dts b/arch/arm/boot/dts/imx6q-gw54xx.dts
index 56e5b50..cb0a5f7 100644 (file)
--- a/arch/arm/boot/dts/imx6q-gw54xx.dts
+++ b/arch/arm/boot/dts/imx6q-gw54xx.dts
@@ -12,10 +12,30 @@
 /dts-v1/;
 #include "imx6q.dtsi"
 #include "imx6qdl-gw54xx.dtsi"
+#include <dt-bindings/media/tda1997x.h>
 
 / {
        model = "Gateworks Ventana i.MX6 Dual/Quad GW54XX";
        compatible = "gw,imx6q-gw54xx", "gw,ventana", "fsl,imx6q";
+
+       sound-digital {
+               compatible = "simple-audio-card";
+               simple-audio-card,name = "tda1997x-audio";
+
+               simple-audio-card,dai-link@0 {
+                       format = "i2s";
+
+                       cpu {
+                               sound-dai = <&ssi2>;
+                       };
+
+                       codec {
+                               bitclock-master;
+                               frame-master;
+                               sound-dai = <&hdmi_receiver>;
+                       };
+               };
+       };
 };
 
 &i2c3 {
@@ -35,6 +55,61 @@
                        };
                };
        };
+
+       hdmi_receiver: hdmi-receiver@48 {
+               compatible = "nxp,tda19971";
+               pinctrl-names = "default";
+               pinctrl-0 = <&pinctrl_tda1997x>;
+               reg = <0x48>;
+               interrupt-parent = <&gpio1>;
+               interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
+               DOVDD-supply = <&reg_3p3v>;
+               AVDD-supply = <&sw4_reg>;
+               DVDD-supply = <&sw4_reg>;
+               #sound-dai-cells = <0>;
+               nxp,audout-format = "i2s";
+               nxp,audout-layout = <0>;
+               nxp,audout-width = <16>;
+               nxp,audout-mclk-fs = <128>;
+               /*
+                * The 8bpp YUV422 semi-planar mode outputs CbCr[11:4]
+                * and Y[11:4] across 16bits in the same cycle
+                * which we map to VP[15:08]<->CSI_DATA[19:12]
+                */
+               nxp,vidout-portcfg =
+                       /*G_Y_11_8<->VP[15:12]<->CSI_DATA[19:16]*/
+                       < TDA1997X_VP24_V15_12 TDA1997X_G_Y_11_8 >,
+                       /*G_Y_7_4<->VP[11:08]<->CSI_DATA[15:12]*/
+                       < TDA1997X_VP24_V11_08 TDA1997X_G_Y_7_4 >,
+                       /*R_CR_CBCR_11_8<->VP[07:04]<->CSI_DATA[11:08]*/
+                       < TDA1997X_VP24_V07_04 TDA1997X_R_CR_CBCR_11_8 >,
+                       /*R_CR_CBCR_7_4<->VP[03:00]<->CSI_DATA[07:04]*/
+                       < TDA1997X_VP24_V03_00 TDA1997X_R_CR_CBCR_7_4 >;
+
+               port {
+                       tda1997x_to_ipu1_csi0_mux: endpoint {
+                               remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>;
+                               bus-width = <16>;
+                               hsync-active = <1>;
+                               vsync-active = <1>;
+                               data-active = <1>;
+                       };
+               };
+       };
+};
+
+&ipu1_csi0_from_ipu1_csi0_mux {
+       bus-width = <16>;
+};
+
+&ipu1_csi0_mux_from_parallel_sensor {
+       remote-endpoint = <&tda1997x_to_ipu1_csi0_mux>;
+       bus-width = <16>;
+};
+
+&ipu1_csi0 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_ipu1_csi0>;
 };
 
 &ipu2_csi1_from_ipu2_csi1_mux {
@@ -63,6 +138,30 @@
                >;
        };
 
+       pinctrl_ipu1_csi0: ipu1_csi0grp {
+               fsl,pins = <
+                       MX6QDL_PAD_CSI0_DAT4__IPU1_CSI0_DATA04          0x1b0b0
+                       MX6QDL_PAD_CSI0_DAT5__IPU1_CSI0_DATA05          0x1b0b0
+                       MX6QDL_PAD_CSI0_DAT6__IPU1_CSI0_DATA06          0x1b0b0
+                       MX6QDL_PAD_CSI0_DAT7__IPU1_CSI0_DATA07          0x1b0b0
+                       MX6QDL_PAD_CSI0_DAT8__IPU1_CSI0_DATA08          0x1b0b0
+                       MX6QDL_PAD_CSI0_DAT9__IPU1_CSI0_DATA09          0x1b0b0
+                       MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10         0x1b0b0
+                       MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11         0x1b0b0
+                       MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12         0x1b0b0
+                       MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13         0x1b0b0
+                       MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14         0x1b0b0
+                       MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15         0x1b0b0
+                       MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16         0x1b0b0
+                       MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17         0x1b0b0
+                       MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18         0x1b0b0
+                       MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19         0x1b0b0
+                       MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC           0x1b0b0
+                       MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK        0x1b0b0
+                       MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC          0x1b0b0
+               >;
+       };
+
        pinctrl_ipu2_csi1: ipu2_csi1grp {
                fsl,pins = <
                        MX6QDL_PAD_EIM_EB2__IPU2_CSI1_DATA19    0x1b0b0
@@ -78,4 +177,10 @@
                        MX6QDL_PAD_EIM_A16__IPU2_CSI1_PIXCLK    0x1b0b0
                >;
        };
+
+       pinctrl_tda1997x: tda1997xgrp {
+               fsl,pins = <
+                       MX6QDL_PAD_GPIO_7__GPIO1_IO07   0x1b0b0
+               >;
+       };
 };

diff --git a/arch/arm/boot/dts/imx6q-logicpd.dts b/arch/arm/boot/dts/imx6q-logicpd.dts
index 45eb0b7..d96ae54 100644 (file)
--- a/arch/arm/boot/dts/imx6q-logicpd.dts
+++ b/arch/arm/boot/dts/imx6q-logicpd.dts
@@ -21,6 +21,8 @@
 
        panel-lvds0 {
                compatible = "okaya,rs800480t-7x0gp";
+               power-supply = <&reg_lcd_reset>;
+               backlight = <&backlight>;
 
                port {
                        panel_in_lvds0: endpoint {
@@ -38,7 +40,6 @@
                regulator-max-microvolt = <3300000>;
                gpio = <&gpio4 17 GPIO_ACTIVE_HIGH>;
                enable-active-high;
-               regulator-always-on;
                vin-supply = <&reg_3v3>;
                startup-delay-us = <500000>;
        };
@@ -52,7 +53,6 @@
                regulator-max-microvolt = <3300000>;
                gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>;
                enable-active-high;
-               regulator-always-on;
                vin-supply = <&reg_lcd>;
        };
 };

diff --git a/arch/arm/boot/dts/imx6q-zii-rdu2.dts b/arch/arm/boot/dts/imx6q-zii-rdu2.dts
index 0f0743d..a1c5e69 100644 (file)
--- a/arch/arm/boot/dts/imx6q-zii-rdu2.dts
+++ b/arch/arm/boot/dts/imx6q-zii-rdu2.dts
@@ -1,42 +1,6 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
 /*
  * Copyright (C) 2016-2017 Zodiac Inflight Innovations
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- *  a) This file is free software; you can redistribute it and/or
- *     modify it under the terms of the GNU General Public License
- *     version 2 as published by the Free Software Foundation.
- *
- *     This file is distributed in the hope that it will be useful,
- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *     GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- *  b) Permission is hereby granted, free of charge, to any person
- *     obtaining a copy of this software and associated documentation
- *     files (the "Software"), to deal in the Software without
- *     restriction, including without limitation the rights to use,
- *     copy, modify, merge, publish, distribute, sublicense, and/or
- *     sell copies of the Software, and to permit persons to whom the
- *     Software is furnished to do so, subject to the following
- *     conditions:
- *
- *     The above copyright notice and this permission notice shall be
- *     included in all copies or substantial portions of the Software.
- *
- *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND,
- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- *     OTHER DEALINGS IN THE SOFTWARE.
  */
 
 /dts-v1/;

diff --git a/arch/arm/boot/dts/imx6qdl-emcon.dtsi b/arch/arm/boot/dts/imx6qdl-emcon.dtsi
index 397e205..70d2661 100644 (file)
--- a/arch/arm/boot/dts/imx6qdl-emcon.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-emcon.dtsi
@@ -77,8 +77,6 @@
 
        pwm_fan: pwm-fan {
                compatible = "pwm-fan";
-               cooling-min-state = <0>;
-               cooling-max-state = <4>;
                #cooling-cells = <2>;
                pwms = <&pwm4 0 50000>;
                cooling-levels = <0 64 127 191 255>;

diff --git a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi
index 81b2fcf..e4d1c52 100644 (file)
--- a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi
@@ -10,6 +10,7 @@
  */
 
 #include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/sound/fsl-imx-audmux.h>
 
 / {
        /* these are used by bootloader for disabling nodes */
@@ -115,12 +116,12 @@
                };
        };
 
-       sound {
+       sound-analog {
                compatible = "fsl,imx6q-ventana-sgtl5000",
                             "fsl,imx-audio-sgtl5000";
                model = "sgtl5000-audio";
                ssi-controller = <&ssi1>;
-               audio-codec = <&codec>;
+               audio-codec = <&sgtl5000>;
                audio-routing =
                        "MIC_IN", "Mic Jack",
                        "Mic Jack", "Mic Bias",
@@ -134,6 +135,25 @@
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_audmux>; /* AUD4<->sgtl5000 */
        status = "okay";
+
+       ssi2 {
+               fsl,audmux-port = <1>;
+               fsl,port-config = <
+                       (IMX_AUDMUX_V2_PTCR_TFSDIR |
+                       IMX_AUDMUX_V2_PTCR_TFSEL(4+8) | /* RXFS */
+                       IMX_AUDMUX_V2_PTCR_TCLKDIR |
+                       IMX_AUDMUX_V2_PTCR_TCSEL(4+8) | /* RXC */
+                       IMX_AUDMUX_V2_PTCR_SYN)
+                       IMX_AUDMUX_V2_PDCR_RXDSEL(4)
+               >;
+       };
+
+       aud5 {
+               fsl,audmux-port = <4>;
+               fsl,port-config = <
+                       IMX_AUDMUX_V2_PTCR_SYN
+                       IMX_AUDMUX_V2_PDCR_RXDSEL(1)>;
+       };
 };
 
 &can1 {
@@ -332,7 +352,7 @@
        pinctrl-0 = <&pinctrl_i2c3>;
        status = "okay";
 
-       codec: sgtl5000@a {
+       sgtl5000: audio-codec@a {
                compatible = "fsl,sgtl5000";
                reg = <0x0a>;
                clocks = <&clks IMX6QDL_CLK_CKO>;
@@ -476,6 +496,9 @@
                        MX6QDL_PAD_SD2_DAT2__AUD4_TXD           0x110b0
                        MX6QDL_PAD_SD2_DAT1__AUD4_TXFS          0x130b0
                        MX6QDL_PAD_GPIO_0__CCM_CLKO1            0x130b0 /* AUD4_MCK */
+                       MX6QDL_PAD_EIM_D25__AUD5_RXC            0x130b0
+                       MX6QDL_PAD_DISP0_DAT19__AUD5_RXD        0x130b0
+                       MX6QDL_PAD_EIM_D24__AUD5_RXFS           0x130b0
                >;
        };
 

diff --git a/arch/arm/boot/dts/imx6qdl-gw551x.dtsi b/arch/arm/boot/dts/imx6qdl-gw551x.dtsi
index 8e46a80..c23ba22 100644 (file)
--- a/arch/arm/boot/dts/imx6qdl-gw551x.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw551x.dtsi
@@ -46,6 +46,8 @@
  */
 
 #include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/media/tda1997x.h>
+#include <dt-bindings/sound/fsl-imx-audmux.h>
 
 / {
        /* these are used by bootloader for disabling nodes */
@@ -99,6 +101,50 @@
                regulator-min-microvolt = <5000000>;
                regulator-max-microvolt = <5000000>;
        };
+
+       sound-digital {
+               compatible = "simple-audio-card";
+               simple-audio-card,name = "tda1997x-audio";
+
+               simple-audio-card,dai-link@0 {
+                       format = "i2s";
+
+                       cpu {
+                               sound-dai = <&ssi2>;
+                       };
+
+                       codec {
+                               bitclock-master;
+                               frame-master;
+                               sound-dai = <&hdmi_receiver>;
+                       };
+               };
+       };
+};
+
+&audmux {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_audmux>; /* AUD5<->tda1997x */
+       status = "okay";
+
+       ssi1 {
+               fsl,audmux-port = <0>;
+               fsl,port-config = <
+                       (IMX_AUDMUX_V2_PTCR_TFSDIR |
+                       IMX_AUDMUX_V2_PTCR_TFSEL(4+8) | /* RXFS */
+                       IMX_AUDMUX_V2_PTCR_TCLKDIR |
+                       IMX_AUDMUX_V2_PTCR_TCSEL(4+8) | /* RXC */
+                       IMX_AUDMUX_V2_PTCR_SYN)
+                       IMX_AUDMUX_V2_PDCR_RXDSEL(4)
+               >;
+       };
+
+       aud5 {
+               fsl,audmux-port = <4>;
+               fsl,port-config = <
+                       IMX_AUDMUX_V2_PTCR_SYN
+                       IMX_AUDMUX_V2_PDCR_RXDSEL(0)>;
+       };
 };
 
 &can1 {
@@ -264,6 +310,60 @@
                #gpio-cells = <2>;
        };
 
+       hdmi_receiver: hdmi-receiver@48 {
+               compatible = "nxp,tda19971";
+               pinctrl-names = "default";
+               pinctrl-0 = <&pinctrl_tda1997x>;
+               reg = <0x48>;
+               interrupt-parent = <&gpio1>;
+               interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
+               DOVDD-supply = <&reg_3p3>;
+               AVDD-supply = <&reg_1p8b>;
+               DVDD-supply = <&reg_1p8a>;
+               #sound-dai-cells = <0>;
+               nxp,audout-format = "i2s";
+               nxp,audout-layout = <0>;
+               nxp,audout-width = <16>;
+               nxp,audout-mclk-fs = <128>;
+               /*
+                * The 8bpp YUV422 semi-planar mode outputs CbCr[11:4]
+                * and Y[11:4] across 16bits in the same cycle
+                * which we map to VP[15:08]<->CSI_DATA[19:12]
+                */
+               nxp,vidout-portcfg =
+                       /*G_Y_11_8<->VP[15:12]<->CSI_DATA[19:16]*/
+                       < TDA1997X_VP24_V15_12 TDA1997X_G_Y_11_8 >,
+                       /*G_Y_7_4<->VP[11:08]<->CSI_DATA[15:12]*/
+                       < TDA1997X_VP24_V11_08 TDA1997X_G_Y_7_4 >,
+                       /*R_CR_CBCR_11_8<->VP[07:04]<->CSI_DATA[11:08]*/
+                       < TDA1997X_VP24_V07_04 TDA1997X_R_CR_CBCR_11_8 >,
+                       /*R_CR_CBCR_7_4<->VP[03:00]<->CSI_DATA[07:04]*/
+                       < TDA1997X_VP24_V03_00 TDA1997X_R_CR_CBCR_7_4 >;
+
+               port {
+                       tda1997x_to_ipu1_csi0_mux: endpoint {
+                               remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>;
+                               bus-width = <16>;
+                               hsync-active = <1>;
+                               vsync-active = <1>;
+                               data-active = <1>;
+                       };
+               };
+       };
+};
+
+&ipu1_csi0_from_ipu1_csi0_mux {
+       bus-width = <16>;
+};
+
+&ipu1_csi0_mux_from_parallel_sensor {
+       remote-endpoint = <&tda1997x_to_ipu1_csi0_mux>;
+       bus-width = <16>;
+};
+
+&ipu1_csi0 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_ipu1_csi0>;
 };
 
 &pcie {
@@ -321,6 +421,14 @@
 };
 
 &iomuxc {
+       pinctrl_audmux: audmuxgrp {
+               fsl,pins = <
+                       MX6QDL_PAD_DISP0_DAT19__AUD5_RXD        0x130b0
+                       MX6QDL_PAD_DISP0_DAT14__AUD5_RXC        0x130b0
+                       MX6QDL_PAD_DISP0_DAT13__AUD5_RXFS       0x130b0
+               >;
+       };
+
        pinctrl_flexcan1: flexcan1grp {
                fsl,pins = <
                        MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX        0x1b0b1
@@ -376,6 +484,30 @@
                >;
        };
 
+       pinctrl_ipu1_csi0: ipu1_csi0grp {
+               fsl,pins = <
+                       MX6QDL_PAD_CSI0_DAT4__IPU1_CSI0_DATA04          0x1b0b0
+                       MX6QDL_PAD_CSI0_DAT5__IPU1_CSI0_DATA05          0x1b0b0
+                       MX6QDL_PAD_CSI0_DAT6__IPU1_CSI0_DATA06          0x1b0b0
+                       MX6QDL_PAD_CSI0_DAT7__IPU1_CSI0_DATA07          0x1b0b0
+                       MX6QDL_PAD_CSI0_DAT8__IPU1_CSI0_DATA08          0x1b0b0
+                       MX6QDL_PAD_CSI0_DAT9__IPU1_CSI0_DATA09          0x1b0b0
+                       MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10         0x1b0b0
+                       MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11         0x1b0b0
+                       MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12         0x1b0b0
+                       MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13         0x1b0b0
+                       MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14         0x1b0b0
+                       MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15         0x1b0b0
+                       MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16         0x1b0b0
+                       MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17         0x1b0b0
+                       MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18         0x1b0b0
+                       MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19         0x1b0b0
+                       MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC           0x1b0b0
+                       MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK        0x1b0b0
+                       MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC          0x1b0b0
+               >;
+       };
+
        pinctrl_pcie: pciegrp {
                fsl,pins = <
                        MX6QDL_PAD_GPIO_0__GPIO1_IO00           0x1b0b0 /* PCIE RST */
@@ -400,6 +532,12 @@
                >;
        };
 
+       pinctrl_tda1997x: tda1997xgrp {
+               fsl,pins = <
+                       MX6QDL_PAD_GPIO_7__GPIO1_IO07           0x1b0b0
+               >;
+       };
+
        pinctrl_uart2: uart2grp {
                fsl,pins = <
                        MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA      0x1b0b1

diff --git a/arch/arm/boot/dts/imx6qdl-gw5903.dtsi b/arch/arm/boot/dts/imx6qdl-gw5903.dtsi
index 9cb9a74..aee9221 100644 (file)
--- a/arch/arm/boot/dts/imx6qdl-gw5903.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw5903.dtsi
@@ -311,7 +311,7 @@
        tlv320aic3105: codec@18 {
                compatible = "ti,tlv320aic3x";
                reg = <0x18>;
-               gpio-reset = <&gpio5 17 GPIO_ACTIVE_LOW>;
+               reset-gpios = <&gpio5 17 GPIO_ACTIVE_LOW>;
                clocks = <&clks IMX6QDL_CLK_CKO>;
                ai3x-micbias-vg = <2>; /* MICBIAS_2_5V */
                /* Regulators */

diff --git a/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi b/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi
index 027df06..7e53ac6 100644 (file)
--- a/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi
@@ -79,7 +79,7 @@
        status = "okay";
        cs-gpios = <&gpio4 24 0>;
 
-       flash@0 {
+       som_flash: flash@0 {
                compatible = "m25p80", "jedec,spi-nor";
                spi-max-frequency = <20000000>;
                reg = <0>;
@@ -121,7 +121,7 @@
        pinctrl-0 = <&pinctrl_i2c1>;
        status = "okay";
 
-       eeprom@50 {
+       som_eeprom: eeprom@50 {
                compatible = "atmel,24c32";
                reg = <0x50>;
        };

diff --git a/arch/arm/boot/dts/imx6qdl-var-dart.dtsi b/arch/arm/boot/dts/imx6qdl-var-dart.dtsi
index 8752a49..c41cac5 100644 (file)
--- a/arch/arm/boot/dts/imx6qdl-var-dart.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-var-dart.dtsi
@@ -183,7 +183,7 @@
                IOVDD-supply = <&reg_3p3v>;
                DVDD-supply = <&reg_3p3v>;
                ai3x-ocmv = <0>;
-               gpio-reset = <&gpio5 5 GPIO_ACTIVE_LOW>;
+               reset-gpios = <&gpio5 5 GPIO_ACTIVE_LOW>;
        };
 };
 

diff --git a/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi b/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi
index 69942c7..93be00a 100644 (file)
--- a/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi
@@ -1,42 +1,6 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
 /*
  * Copyright (C) 2016-2017 Zodiac Inflight Innovations
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- *  a) This file is free software; you can redistribute it and/or
- *     modify it under the terms of the GNU General Public License
- *     version 2 as published by the Free Software Foundation.
- *
- *     This file is distributed in the hope that it will be useful,
- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *     GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- *  b) Permission is hereby granted, free of charge, to any person
- *     obtaining a copy of this software and associated documentation
- *     files (the "Software"), to deal in the Software without
- *     restriction, including without limitation the rights to use,
- *     copy, modify, merge, publish, distribute, sublicense, and/or
- *     sell copies of the Software, and to permit persons to whom the
- *     Software is furnished to do so, subject to the following
- *     conditions:
- *
- *     The above copyright notice and this permission notice shall be
- *     included in all copies or substantial portions of the Software.
- *
- *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND,
- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- *     OTHER DEALINGS IN THE SOFTWARE.
  */
 
 #include <dt-bindings/gpio/gpio.h>
@@ -210,6 +174,7 @@
 
        panel {
                power-supply = <&reg_3p3v_display>;
+               backlight = <&sp_backlight>;
                status = "disabled";
 
                port {
@@ -327,7 +292,7 @@
                        compatible = "zii,rave-sp-watchdog";
                };
 
-               backlight {
+               sp_backlight: backlight {
                        compatible = "zii,rave-sp-backlight";
                };
 
@@ -384,7 +349,7 @@
                AVDD-supply = <&reg_3p3v>;
                IOVDD-supply = <&reg_3p3v>;
                DVDD-supply = <&vgen4_reg>;
-               gpio-reset = <&gpio1 2 GPIO_ACTIVE_HIGH>;
+               reset-gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
        };
 
        accel@1c {
@@ -528,6 +493,11 @@
                };
        };
 
+       watchdog@38 {
+               compatible = "zii,rave-wdt";
+               reg = <0x38>;
+       };
+
        temp-sense@48 {
                compatible = "national,lm75";
                reg = <0x48>;
@@ -572,7 +542,7 @@
                AVDD-supply = <&reg_3p3v>;
                IOVDD-supply = <&reg_3p3v>;
                DVDD-supply = <&vgen4_reg>;
-               gpio-reset = <&gpio1 0 GPIO_ACTIVE_HIGH>;
+               reset-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
        };
 
        touchscreen@20 {

diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index fe17a34..b3a77bc 100644 (file)
--- a/arch/arm/boot/dts/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -4,6 +4,7 @@
 // Copyright 2011 Linaro Ltd.
 
 #include <dt-bindings/clock/imx6qdl-clock.h>
+#include <dt-bindings/input/input.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 
 / {
@@ -279,6 +280,7 @@
                        ranges = <0x81000000 0 0          0x01f80000 0 0x00010000 /* downstream I/O */
                                  0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */
                        num-lanes = <1>;
+                       num-viewport = <4>;
                        interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
                        interrupt-names = "msi";
                        #interrupt-cells = <1>;
@@ -833,6 +835,14 @@
                                        status = "disabled";
                                };
 
+                               snvs_pwrkey: snvs-powerkey {
+                                       compatible = "fsl,sec-v4.0-pwrkey";
+                                       regmap = <&snvs>;
+                                       interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+                                       linux,keycode = <KEY_POWER>;
+                                       wakeup-source;
+                               };
+
                                snvs_lpgpr: snvs-lpgpr {
                                        compatible = "fsl,imx6q-snvs-lpgpr";
                                };
@@ -918,7 +928,7 @@
                                compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma";
                                reg = <0x020ec000 0x4000>;
                                interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>;
-                               clocks = <&clks IMX6QDL_CLK_SDMA>,
+                               clocks = <&clks IMX6QDL_CLK_IPG>,
                                         <&clks IMX6QDL_CLK_SDMA>;
                                clock-names = "ipg", "ahb";
                                #dma-cells = <3>;
@@ -1129,14 +1139,16 @@
                                reg = <0x021ac000 0x4000>;
                        };
 
-                       mmdc0: mmdc@21b0000 { /* MMDC0 */
+                       mmdc0: memory-controller@21b0000 { /* MMDC0 */
                                compatible = "fsl,imx6q-mmdc";
                                reg = <0x021b0000 0x4000>;
                                clocks = <&clks IMX6QDL_CLK_MMDC_P0_IPG>;
                        };
 
-                       mmdc1: mmdc@21b4000 { /* MMDC1 */
+                       mmdc1: memory-controller@21b4000 { /* MMDC1 */
+                               compatible = "fsl,imx6q-mmdc";
                                reg = <0x021b4000 0x4000>;
+                               status = "disabled";
                        };
 
                        weim: weim@21b8000 {

diff --git a/arch/arm/boot/dts/imx6qp-zii-rdu2.dts b/arch/arm/boot/dts/imx6qp-zii-rdu2.dts
index 98bf7a6..57de447 100644 (file)
--- a/arch/arm/boot/dts/imx6qp-zii-rdu2.dts
+++ b/arch/arm/boot/dts/imx6qp-zii-rdu2.dts
@@ -1,42 +1,6 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
 /*
  * Copyright (C) 2016-2017 Zodiac Inflight Innovations
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- *  a) This file is free software; you can redistribute it and/or
- *     modify it under the terms of the GNU General Public License
- *     version 2 as published by the Free Software Foundation.
- *
- *     This file is distributed in the hope that it will be useful,
- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *     GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- *  b) Permission is hereby granted, free of charge, to any person
- *     obtaining a copy of this software and associated documentation
- *     files (the "Software"), to deal in the Software without
- *     restriction, including without limitation the rights to use,
- *     copy, modify, merge, publish, distribute, sublicense, and/or
- *     sell copies of the Software, and to permit persons to whom the
- *     Software is furnished to do so, subject to the following
- *     conditions:
- *
- *     The above copyright notice and this permission notice shall be
- *     included in all copies or substantial portions of the Software.
- *
- *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND,
- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- *     OTHER DEALINGS IN THE SOFTWARE.
  */
 
 /dts-v1/;

diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi
index 4b4813f..9ddbeea 100644 (file)
--- a/arch/arm/boot/dts/imx6sl.dtsi
+++ b/arch/arm/boot/dts/imx6sl.dtsi
@@ -23,6 +23,13 @@
                gpio2 = &gpio3;
                gpio3 = &gpio4;
                gpio4 = &gpio5;
+               i2c0 = &i2c1;
+               i2c1 = &i2c2;
+               i2c2 = &i2c3;
+               mmc0 = &usdhc1;
+               mmc1 = &usdhc2;
+               mmc2 = &usdhc3;
+               mmc3 = &usdhc4;
                serial0 = &uart1;
                serial1 = &uart2;
                serial2 = &uart3;
@@ -741,7 +748,7 @@
                                reg = <0x020ec000 0x4000>;
                                interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&clks IMX6SL_CLK_SDMA>,
-                                        <&clks IMX6SL_CLK_SDMA>;
+                                        <&clks IMX6SL_CLK_AHB>;
                                clock-names = "ipg", "ahb";
                                #dma-cells = <3>;
                                /* imx6sl reuses imx6q sdma firmware */
@@ -922,7 +929,7 @@
                                status = "disabled";
                        };
 
-                       mmdc: mmdc@21b0000 {
+                       memory-controller@21b0000 {
                                compatible = "fsl,imx6sl-mmdc", "fsl,imx6q-mmdc";
                                reg = <0x021b0000 0x4000>;
                                clocks = <&clks IMX6SL_CLK_MMDC_P0_IPG>;

diff --git a/arch/arm/boot/dts/imx6sll.dtsi b/arch/arm/boot/dts/imx6sll.dtsi
index 62847c6..1b4899f 100644 (file)
--- a/arch/arm/boot/dts/imx6sll.dtsi
+++ b/arch/arm/boot/dts/imx6sll.dtsi
@@ -64,6 +64,7 @@
                                198000          1175000
                        >;
                        clock-latency = <61036>; /* two CLK32 periods */
+                       #cooling-cells = <2>;
                        clocks = <&clks IMX6SLL_CLK_ARM>,
                                 <&clks IMX6SLL_CLK_PLL2_PFD2>,
                                 <&clks IMX6SLL_CLK_STEP>,
@@ -621,7 +622,7 @@
                                compatible = "fsl,imx6sll-sdma", "fsl,imx35-sdma";
                                reg = <0x020ec000 0x4000>;
                                interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
-                               clocks = <&clks IMX6SLL_CLK_SDMA>,
+                               clocks = <&clks IMX6SLL_CLK_IPG>,
                                         <&clks IMX6SLL_CLK_SDMA>;
                                clock-names = "ipg", "ahb";
                                #dma-cells = <3>;

diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi
index 5b16e65..b16a123 100644 (file)
--- a/arch/arm/boot/dts/imx6sx.dtsi
+++ b/arch/arm/boot/dts/imx6sx.dtsi
@@ -820,7 +820,7 @@
                                compatible = "fsl,imx6sx-sdma", "fsl,imx6q-sdma";
                                reg = <0x020ec000 0x4000>;
                                interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
-                               clocks = <&clks IMX6SX_CLK_SDMA>,
+                               clocks = <&clks IMX6SX_CLK_IPG>,
                                         <&clks IMX6SX_CLK_SDMA>;
                                clock-names = "ipg", "ahb";
                                #dma-cells = <3>;
@@ -1017,7 +1017,7 @@
                                status = "disabled";
                        };
 
-                       mmdc: mmdc@21b0000 {
+                       memory-controller@21b0000 {
                                compatible = "fsl,imx6sx-mmdc", "fsl,imx6q-mmdc";
                                reg = <0x021b0000 0x4000>;
                                clocks = <&clks IMX6SX_CLK_MMDC_P0_IPG>;

diff --git a/arch/arm/boot/dts/imx6ul.dtsi b/arch/arm/boot/dts/imx6ul.dtsi
index 62ed30c..bbf010c 100644 (file)
--- a/arch/arm/boot/dts/imx6ul.dtsi
+++ b/arch/arm/boot/dts/imx6ul.dtsi
@@ -708,7 +708,7 @@
                                             "fsl,imx35-sdma";
                                reg = <0x020ec000 0x4000>;
                                interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
-                               clocks = <&clks IMX6UL_CLK_SDMA>,
+                               clocks = <&clks IMX6UL_CLK_IPG>,
                                         <&clks IMX6UL_CLK_SDMA>;
                                clock-names = "ipg", "ahb";
                                #dma-cells = <3>;
@@ -914,7 +914,7 @@
                                status = "disabled";
                        };
 
-                       mmdc: mmdc@21b0000 {
+                       memory-controller@21b0000 {
                                compatible = "fsl,imx6ul-mmdc", "fsl,imx6q-mmdc";
                                reg = <0x021b0000 0x4000>;
                                clocks = <&clks IMX6UL_CLK_MMDC_P0_IPG>;

diff --git a/arch/arm/boot/dts/imx7-mba7.dtsi b/arch/arm/boot/dts/imx7-mba7.dtsi
new file mode 100644 (file)
index 0000000..50abf18
--- /dev/null
+++ b/arch/arm/boot/dts/imx7-mba7.dtsi
@@ -0,0 +1,550 @@
+// SPDX-License-Identifier: GPL-2.0 OR X11
+/*
+ * Device Tree Include file for TQ Systems MBa7 carrier board.
+ *
+ * Copyright (C) 2016 TQ Systems GmbH
+ * Author: Markus Niebel <Markus.Niebel@tq-group.com>
+ * Copyright (C) 2019 Bruno Thomsen <bruno.thomsen@gmail.com>
+ *
+ * Note: This file does not include nodes for all peripheral devices.
+ * As device driver coverage increases additional nodes can be added.
+ */
+
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/net/ti-dp83867.h>
+
+/ {
+       beeper {
+               compatible = "gpio-beeper";
+               gpios = <&pca9555 0 GPIO_ACTIVE_HIGH>;
+       };
+
+       chosen {
+               stdout-path = &uart6;
+       };
+
+       gpio_buttons: gpio-keys {
+               compatible = "gpio-keys";
+
+               button-0 {
+                       /* #SWITCH_A */
+                       label = "S11";
+                       linux,code = <KEY_1>;
+                       gpios = <&pca9555 13 GPIO_ACTIVE_LOW>;
+               };
+
+               button-1 {
+                       /* #SWITCH_B */
+                       label = "S12";
+                       linux,code = <KEY_2>;
+                       gpios = <&pca9555 14 GPIO_ACTIVE_LOW>;
+               };
+
+               button-2 {
+                       /* #SWITCH_C */
+                       label = "S13";
+                       linux,code = <KEY_3>;
+                       gpios = <&pca9555 15 GPIO_ACTIVE_LOW>;
+               };
+       };
+
+       gpio-leds {
+               compatible = "gpio-leds";
+
+               led1 {
+                       label = "led1";
+                       gpios = <&pca9555 8 GPIO_ACTIVE_HIGH>;
+                       linux,default-trigger = "default-on";
+               };
+
+               led2 {
+                       label = "led2";
+                       gpios = <&pca9555 9 GPIO_ACTIVE_HIGH>;
+                       linux,default-trigger = "heartbeat";
+               };
+       };
+
+       reg_sd1_vmmc: regulator-sd1-vmmc {
+               compatible = "regulator-fixed";
+               regulator-name = "VCC3V3_SD1";
+               regulator-min-microvolt = <3300000>;
+               regulator-max-microvolt = <3300000>;
+               regulator-always-on;
+       };
+
+       reg_fec1_pwdn: regulator-fec1-pwdn {
+               compatible = "regulator-fixed";
+               regulator-name = "PWDN_FEC1";
+               regulator-min-microvolt = <3300000>;
+               regulator-max-microvolt = <3300000>;
+               regulator-always-on;
+               gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
+               enable-active-high;
+       };
+
+       reg_fec2_pwdn: regulator-fec2-pwdn {
+               compatible = "regulator-fixed";
+               regulator-name = "PWDN_FEC2";
+               regulator-min-microvolt = <3300000>;
+               regulator-max-microvolt = <3300000>;
+               regulator-always-on;
+               gpio = <&gpio2 31 GPIO_ACTIVE_HIGH>;
+               enable-active-high;
+       };
+
+       reg_usb_otg1_vbus: regulator-usb-otg1-vbus {
+               compatible = "regulator-fixed";
+               regulator-name = "VBUS_USBOTG1";
+               regulator-min-microvolt = <5000000>;
+               regulator-max-microvolt = <5000000>;
+               gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
+               enable-active-high;
+       };
+
+       reg_usb_otg2_vbus: regulator-usb-otg2-vbus {
+               compatible = "regulator-fixed";
+               regulator-name = "VBUS_USBOTG2";
+               regulator-min-microvolt = <5000000>;
+               regulator-max-microvolt = <5000000>;
+               gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
+               enable-active-high;
+       };
+
+       reg_mpcie_1v5: regulator-mpcie-1v5 {
+               compatible = "regulator-fixed";
+               regulator-name = "VCC1V5_MPCIE";
+               regulator-min-microvolt = <1500000>;
+               regulator-max-microvolt = <1500000>;
+               gpio = <&pca9555 12 GPIO_ACTIVE_HIGH>;
+               enable-active-high;
+               regulator-always-on;
+       };
+
+       reg_mpcie_3v3: regulator-mpcie-3v3 {
+               compatible = "regulator-fixed";
+               regulator-name = "VCC3V3_MPCIE";
+               regulator-min-microvolt = <3300000>;
+               regulator-max-microvolt = <3300000>;
+               gpio = <&pca9555 10 GPIO_ACTIVE_HIGH>;
+               enable-active-high;
+               regulator-always-on;
+       };
+
+       reg_mba_12v0: regulator-mba-12v0 {
+               compatible = "regulator-fixed";
+               regulator-name = "VCC12V0_MBA7";
+               regulator-min-microvolt = <12000000>;
+               regulator-max-microvolt = <12000000>;
+               gpio = <&pca9555 11 GPIO_ACTIVE_HIGH>;
+               enable-active-high;
+       };
+
+       reg_lvds_transmitter: regulator-lvds-transmitter {
+               compatible = "regulator-fixed";
+               regulator-name = "#SHTDN_LVDS";
+               regulator-min-microvolt = <3300000>;
+               regulator-max-microvolt = <3300000>;
+               gpio = <&pca9555 1 GPIO_ACTIVE_HIGH>;
+               enable-active-high;
+       };
+
+       reg_vref_1v8: regulator-vref-1v8 {
+               compatible = "regulator-fixed";
+               regulator-name = "VCC1V8_REF";
+               regulator-min-microvolt = <1800000>;
+               regulator-max-microvolt = <1800000>;
+               regulator-always-on;
+               vin-supply = <&sw2_reg>;
+       };
+
+       reg_audio_3v3: regulator-audio-3v3 {
+               compatible = "regulator-fixed";
+               regulator-name = "VCC3V3_AUDIO";
+               regulator-min-microvolt = <3300000>;
+               regulator-max-microvolt = <3300000>;
+               regulator-always-on;
+       };
+};
+
+&adc1 {
+       vref-supply = <&reg_vref_1v8>;
+       status = "okay";
+};
+
+&adc2 {
+       vref-supply = <&reg_vref_1v8>;
+       status = "okay";
+};
+
+&ecspi1 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_ecspi1>;
+       num-chipselects = <3>;
+       cs-gpios = <&gpio4 0 GPIO_ACTIVE_LOW>, <&gpio4 1 GPIO_ACTIVE_LOW>,
+                  <&gpio4 2 GPIO_ACTIVE_LOW>;
+       status = "okay";
+};
+
+&ecspi2 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_ecspi2>;
+       num-chipselects = <1>;
+       status = "okay";
+};
+
+&fec1 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_enet1>;
+       phy-mode = "rgmii-id";
+       phy-reset-gpios = <&gpio7 15 GPIO_ACTIVE_LOW>;
+       phy-reset-duration = <1>;
+       phy-reset-delay = <1>;
+       phy-supply = <&reg_fec1_pwdn>;
+       phy-handle = <&ethphy1_0>;
+       fsl,magic-packet;
+       status = "okay";
+
+       mdio {
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               ethphy1_0: ethernet-phy@0 {
+                       compatible = "ethernet-phy-ieee802.3-c22";
+                       reg = <0>;
+                       ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_50_NS>;
+                       ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_50_NS>;
+                       ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+                       /* LED1: Link/Activity, LED2: Error */
+                       ti,led-function = <0x0db0>;
+                       /* Active low, LED1 and LED2 driven by phy */
+                       ti,led-ctrl = <0x1001>;
+               };
+       };
+};
+
+&flexcan1 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_flexcan1>;
+       status = "okay";
+};
+
+&flexcan2 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_flexcan2>;
+       status = "okay";
+};
+
+&i2c1 {
+       lm75: temperature-sensor@49 {
+               compatible = "national,lm75";
+               reg = <0x49>;
+       };
+};
+
+&i2c2 {
+       clock-frequency = <100000>;
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_i2c2>;
+       status = "okay";
+
+       tlv320aic32x4: audio-codec@18 {
+               compatible = "ti,tlv320aic32x4";
+               reg = <0x18>;
+               clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>;
+               clock-names = "mclk";
+               ldoin-supply = <&reg_audio_3v3>;
+               iov-supply = <&reg_audio_3v3>;
+       };
+
+       pca9555: gpio-expander@20 {
+               compatible = "nxp,pca9555";
+               reg = <0x20>;
+               pinctrl-names = "default";
+               pinctrl-0 = <&pinctrl_pca9555>;
+               gpio-controller;
+               #gpio-cells = <2>;
+               interrupt-parent = <&gpio7>;
+               interrupts = <12 IRQ_TYPE_EDGE_FALLING>;
+               interrupt-controller;
+               #interrupt-cells = <2>;
+       };
+};
+
+&i2c3 {
+       clock-frequency = <100000>;
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_i2c3>;
+       status = "okay";
+};
+
+&iomuxc {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_hog_mba7_1>;
+
+       pinctrl_ecspi1: ecspi1grp {
+               fsl,pins = <
+                       MX7D_PAD_ECSPI1_MISO__ECSPI1_MISO               0x7c
+                       MX7D_PAD_ECSPI1_MOSI__ECSPI1_MOSI               0x74
+                       MX7D_PAD_ECSPI1_SCLK__ECSPI1_SCLK               0x74
+                       MX7D_PAD_UART1_RX_DATA__GPIO4_IO0               0x74
+                       MX7D_PAD_UART1_TX_DATA__GPIO4_IO1               0x74
+                       MX7D_PAD_UART2_RX_DATA__GPIO4_IO2               0x74
+               >;
+       };
+
+       pinctrl_ecspi2: ecspi2grp {
+               fsl,pins = <
+                       MX7D_PAD_ECSPI2_MISO__ECSPI2_MISO               0x7c
+                       MX7D_PAD_ECSPI2_MOSI__ECSPI2_MOSI               0x74
+                       MX7D_PAD_ECSPI2_SCLK__ECSPI2_SCLK               0x74
+                       MX7D_PAD_ECSPI2_SS0__ECSPI2_SS0                 0x74
+               >;
+       };
+
+       pinctrl_enet1: enet1grp {
+               fsl,pins = <
+                       MX7D_PAD_GPIO1_IO10__ENET1_MDIO                 0x02
+                       MX7D_PAD_GPIO1_IO11__ENET1_MDC                  0x00
+                       MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC       0x71
+                       MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0       0x71
+                       MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1       0x71
+                       MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2       0x71
+                       MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3       0x71
+                       MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x71
+                       MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC       0x79
+                       MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0       0x79
+                       MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1       0x79
+                       MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2       0x79
+                       MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3       0x79
+                       MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x79
+                       /* Reset: SION, 100kPU, SRE_FAST, DSE_X1 */
+                       MX7D_PAD_ENET1_COL__GPIO7_IO15          0x40000070
+                       /* INT/PWDN: SION, 100kPU, HYS, SRE_FAST, DSE_X1 */
+                       MX7D_PAD_GPIO1_IO09__GPIO1_IO9          0x40000078
+               >;
+       };
+
+       pinctrl_flexcan1: flexcan1grp {
+               fsl,pins = <
+                       MX7D_PAD_GPIO1_IO12__FLEXCAN1_RX        0x5a
+                       MX7D_PAD_GPIO1_IO13__FLEXCAN1_TX        0x52
+               >;
+       };
+
+       pinctrl_flexcan2: flexcan2grp {
+               fsl,pins = <
+                       MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX        0x5a
+                       MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX        0x52
+               >;
+       };
+
+       pinctrl_hog_mba7_1: hogmba71grp {
+               fsl,pins = <
+                       /* Limitation: WDOG2_B / WDOG2_RESET not usable */
+                       MX7D_PAD_ENET1_RX_CLK__GPIO7_IO13       0x4000007c
+                       MX7D_PAD_ENET1_CRS__GPIO7_IO14          0x40000074
+                       /* #BOOT_EN */
+                       MX7D_PAD_UART2_TX_DATA__GPIO4_IO3       0x40000010
+               >;
+       };
+
+       pinctrl_i2c2: i2c2grp {
+               fsl,pins = <
+                       MX7D_PAD_I2C2_SCL__I2C2_SCL             0x40000078
+                       MX7D_PAD_I2C2_SDA__I2C2_SDA             0x40000078
+               >;
+       };
+
+       pinctrl_i2c3: i2c3grp {
+               fsl,pins = <
+                       MX7D_PAD_I2C3_SCL__I2C3_SCL             0x40000078
+                       MX7D_PAD_I2C3_SDA__I2C3_SDA             0x40000078
+               >;
+       };
+
+
+       pinctrl_pca9555: pca95550grp {
+               fsl,pins = <
+                       MX7D_PAD_ENET1_TX_CLK__GPIO7_IO12       0x78
+               >;
+       };
+
+       pinctrl_uart3: uart3grp {
+               fsl,pins = <
+                       MX7D_PAD_UART3_RX_DATA__UART3_DCE_RX    0x7e
+                       MX7D_PAD_UART3_TX_DATA__UART3_DCE_TX    0x76
+                       MX7D_PAD_UART3_CTS_B__UART3_DCE_CTS     0x76
+                       MX7D_PAD_UART3_RTS_B__UART3_DCE_RTS     0x7e
+               >;
+       };
+
+       pinctrl_uart4: uart4grp {
+               fsl,pins = <
+                       MX7D_PAD_SAI2_TX_SYNC__UART4_DCE_RX     0x7e
+                       MX7D_PAD_SAI2_TX_BCLK__UART4_DCE_TX     0x76
+                       MX7D_PAD_SAI2_RX_DATA__UART4_DCE_CTS    0x76
+                       MX7D_PAD_SAI2_TX_DATA__UART4_DCE_RTS    0x7e
+               >;
+       };
+
+       pinctrl_uart5: uart5grp {
+               fsl,pins = <
+                       MX7D_PAD_I2C4_SCL__UART5_DCE_RX         0x7e
+                       MX7D_PAD_I2C4_SDA__UART5_DCE_TX         0x76
+               >;
+       };
+
+       pinctrl_uart6: uart6grp {
+               fsl,pins = <
+                       MX7D_PAD_EPDC_DATA08__UART6_DCE_RX      0x7d
+                       MX7D_PAD_EPDC_DATA09__UART6_DCE_TX      0x75
+                       MX7D_PAD_EPDC_DATA11__UART6_DCE_CTS     0x75
+                       MX7D_PAD_EPDC_DATA10__UART6_DCE_RTS     0x7d
+               >;
+       };
+
+       pinctrl_uart7: uart7grp {
+               fsl,pins = <
+                       MX7D_PAD_EPDC_DATA12__UART7_DCE_RX      0x7e
+                       MX7D_PAD_EPDC_DATA13__UART7_DCE_TX      0x76
+                       MX7D_PAD_EPDC_DATA15__UART7_DCE_CTS     0x76
+                       /* Limitation: RTS is not connected */
+                       MX7D_PAD_EPDC_DATA14__UART7_DCE_RTS     0x7e
+               >;
+       };
+
+       pinctrl_usdhc1_gpio: usdhc1grp_gpio {
+               fsl,pins = <
+                       /* WP */
+                       MX7D_PAD_SD1_WP__GPIO5_IO1              0x7c
+                       /* CD */
+                       MX7D_PAD_SD1_CD_B__GPIO5_IO0            0x7c
+                       /* VSELECT */
+                       MX7D_PAD_GPIO1_IO08__SD1_VSELECT        0x59
+               >;
+       };
+
+       pinctrl_usdhc1: usdhc1grp {
+               fsl,pins = <
+                       MX7D_PAD_SD1_CMD__SD1_CMD               0x5e
+                       MX7D_PAD_SD1_CLK__SD1_CLK               0x57
+                       MX7D_PAD_SD1_DATA0__SD1_DATA0           0x5e
+                       MX7D_PAD_SD1_DATA1__SD1_DATA1           0x5e
+                       MX7D_PAD_SD1_DATA2__SD1_DATA2           0x5e
+                       MX7D_PAD_SD1_DATA3__SD1_DATA3           0x5e
+               >;
+       };
+
+       pinctrl_usdhc1_100mhz: usdhc1grp_100mhz {
+               fsl,pins = <
+                       MX7D_PAD_SD1_CMD__SD1_CMD               0x5a
+                       MX7D_PAD_SD1_CLK__SD1_CLK               0x57
+                       MX7D_PAD_SD1_DATA0__SD1_DATA0           0x5a
+                       MX7D_PAD_SD1_DATA1__SD1_DATA1           0x5a
+                       MX7D_PAD_SD1_DATA2__SD1_DATA2           0x5a
+                       MX7D_PAD_SD1_DATA3__SD1_DATA3           0x5a
+               >;
+       };
+
+       pinctrl_usdhc1_200mhz: usdhc1grp_200mhz {
+               fsl,pins = <
+                       MX7D_PAD_SD1_CMD__SD1_CMD               0x5b
+                       MX7D_PAD_SD1_CLK__SD1_CLK               0x57
+                       MX7D_PAD_SD1_DATA0__SD1_DATA0           0x5b
+                       MX7D_PAD_SD1_DATA1__SD1_DATA1           0x5b
+                       MX7D_PAD_SD1_DATA2__SD1_DATA2           0x5b
+                       MX7D_PAD_SD1_DATA3__SD1_DATA3           0x5b
+               >;
+       };
+};
+
+&iomuxc_lpsr {
+       pinctrl_pwm1: pwm1grp {
+               fsl,pins = <
+                       /* LCD_CONTRAST */
+                       MX7D_PAD_LPSR_GPIO1_IO01__PWM1_OUT      0x50
+               >;
+       };
+
+       pinctrl_usbotg1: usbotg1grp {
+               fsl,pins = <
+                       MX7D_PAD_LPSR_GPIO1_IO04__USB_OTG1_OC   0x5c
+                       MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5     0x59
+               >;
+       };
+};
+
+&pwm1 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_pwm1>;
+       status = "okay";
+};
+
+&uart3 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_uart3>;
+       assigned-clocks = <&clks IMX7D_UART3_ROOT_SRC>;
+       assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
+       status = "okay";
+};
+
+&uart4 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_uart4>;
+       assigned-clocks = <&clks IMX7D_UART4_ROOT_SRC>;
+       assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
+       status = "okay";
+};
+
+&uart5 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_uart5>;
+       assigned-clocks = <&clks IMX7D_UART5_ROOT_SRC>;
+       assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
+       status = "okay";
+};
+
+&uart6 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_uart6>;
+       assigned-clocks = <&clks IMX7D_UART6_ROOT_SRC>;
+       assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
+       status = "okay";
+};
+
+&uart7 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_uart7>;
+       assigned-clocks = <&clks IMX7D_UART7_ROOT_SRC>;
+       assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
+       uart-has-rtscts;
+       status = "okay";
+};
+
+&usbh {
+       status = "okay";
+};
+
+&usbotg1 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_usbotg1>;
+       vbus-supply = <&reg_usb_otg1_vbus>;
+       srp-disable;
+       hnp-disable;
+       adp-disable;
+       dr_mode = "host";
+       status = "okay";
+};
+
+&usdhc1 {
+       pinctrl-names = "default", "state_100mhz", "state_200mhz";
+       pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>;
+       pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_usdhc1_gpio>;
+       pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_usdhc1_gpio>;
+       cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
+       wp-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
+       vmmc-supply = <&reg_sd1_vmmc>;
+       bus-width = <4>;
+       no-1-8-v;
+       status = "okay";
+};

diff --git a/arch/arm/boot/dts/imx7-tqma7.dtsi b/arch/arm/boot/dts/imx7-tqma7.dtsi
new file mode 100644 (file)
index 0000000..9aaed85
--- /dev/null
+++ b/arch/arm/boot/dts/imx7-tqma7.dtsi
@@ -0,0 +1,249 @@
+// SPDX-License-Identifier: GPL-2.0 OR X11
+/*
+ * Device Tree Include file for TQ Systems TQMa7x boards with full mounted PCB.
+ *
+ * Copyright (C) 2016 TQ Systems GmbH
+ * Author: Markus Niebel <Markus.Niebel@tq-group.com>
+ * Copyright (C) 2019 Bruno Thomsen <bruno.thomsen@gmail.com>
+ */
+
+/ {
+       memory@80000000 {
+               device_type = "memory";
+               /* 512 MB - default configuration */
+               reg = <0x80000000 0x20000000>;
+       };
+};
+
+&cpu0 {
+       arm-supply = <&sw1a_reg>;
+};
+
+&i2c1 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_i2c1>;
+       clock-frequency = <100000>;
+       status = "okay";
+
+       pfuze3000: pmic@8 {
+               pinctrl-names = "default";
+               pinctrl-0 = <&pinctrl_pmic1>;
+               compatible = "fsl,pfuze3000";
+               reg = <0x08>;
+
+               regulators {
+                       sw1a_reg: sw1a {
+                               regulator-min-microvolt = <700000>;
+                               regulator-max-microvolt = <3300000>;
+                               regulator-boot-on;
+                               regulator-always-on;
+                               regulator-ramp-delay = <6250>;
+                       };
+
+                       /* use sw1c_reg to align with pfuze100/pfuze200 */
+                       sw1c_reg: sw1b {
+                               regulator-min-microvolt = <700000>;
+                               regulator-max-microvolt = <1475000>;
+                               regulator-boot-on;
+                               regulator-always-on;
+                               regulator-ramp-delay = <6250>;
+                       };
+
+                       sw2_reg: sw2 {
+                               regulator-min-microvolt = <1500000>;
+                               regulator-max-microvolt = <1850000>;
+                               regulator-boot-on;
+                               regulator-always-on;
+                       };
+
+                       sw3a_reg: sw3 {
+                               regulator-min-microvolt = <900000>;
+                               regulator-max-microvolt = <1650000>;
+                               regulator-boot-on;
+                               regulator-always-on;
+                       };
+
+                       swbst_reg: swbst {
+                               regulator-min-microvolt = <5000000>;
+                               regulator-max-microvolt = <5150000>;
+                       };
+
+                       snvs_reg: vsnvs {
+                               regulator-min-microvolt = <1000000>;
+                               regulator-max-microvolt = <3000000>;
+                               regulator-boot-on;
+                               regulator-always-on;
+                       };
+
+                       vref_reg: vrefddr {
+                               regulator-boot-on;
+                               regulator-always-on;
+                       };
+
+                       vgen1_reg: vldo1 {
+                               regulator-min-microvolt = <1800000>;
+                               regulator-max-microvolt = <3300000>;
+                               regulator-always-on;
+                       };
+
+                       vgen2_reg: vldo2 {
+                               regulator-min-microvolt = <800000>;
+                               regulator-max-microvolt = <1550000>;
+                               regulator-always-on;
+                       };
+
+                       vgen3_reg: vccsd {
+                               regulator-min-microvolt = <2850000>;
+                               regulator-max-microvolt = <3300000>;
+                               regulator-always-on;
+                       };
+
+                       vgen4_reg: v33 {
+                               regulator-min-microvolt = <2850000>;
+                               regulator-max-microvolt = <3300000>;
+                               regulator-always-on;
+                       };
+
+                       vgen5_reg: vldo3 {
+                               regulator-min-microvolt = <1800000>;
+                               regulator-max-microvolt = <3300000>;
+                               regulator-always-on;
+                       };
+
+                       vgen6_reg: vldo4 {
+                               regulator-min-microvolt = <1800000>;
+                               regulator-max-microvolt = <3300000>;
+                               regulator-always-on;
+                       };
+               };
+       };
+
+       /* NXP SE97BTP with temperature sensor + eeprom */
+       se97b: temperature-sensor-eeprom@1e {
+               compatible = "nxp,se97b", "jedec,jc-42.4-temp";
+               reg = <0x1e>;
+               status = "okay";
+       };
+
+       /* ST M24C64 */
+       m24c64: eeprom@50 {
+               compatible = "atmel,24c64";
+               reg = <0x50>;
+               pagesize = <32>;
+               status = "okay";
+       };
+
+       at24c02: eeprom@56 {
+               compatible = "atmel,24c02";
+               reg = <0x56>;
+               pagesize = <16>;
+               status = "okay";
+       };
+
+       ds1339: rtc@68 {
+               compatible = "dallas,ds1339";
+               reg = <0x68>;
+       };
+};
+
+&iomuxc {
+       pinctrl_i2c1: i2c1grp {
+               fsl,pins = <
+                       MX7D_PAD_I2C1_SDA__I2C1_SDA     0x40000078
+                       MX7D_PAD_I2C1_SCL__I2C1_SCL     0x40000078
+               >;
+       };
+
+       pinctrl_pmic1: pmic1grp {
+               fsl,pins = <
+                       MX7D_PAD_SD2_RESET_B__GPIO5_IO11        0x4000005C
+               >;
+       };
+
+       pinctrl_usdhc3: usdhc3grp {
+               fsl,pins = <
+                       MX7D_PAD_SD3_CMD__SD3_CMD               0x59
+                       MX7D_PAD_SD3_CLK__SD3_CLK               0x56
+                       MX7D_PAD_SD3_DATA0__SD3_DATA0           0x59
+                       MX7D_PAD_SD3_DATA1__SD3_DATA1           0x59
+                       MX7D_PAD_SD3_DATA2__SD3_DATA2           0x59
+                       MX7D_PAD_SD3_DATA3__SD3_DATA3           0x59
+                       MX7D_PAD_SD3_DATA4__SD3_DATA4           0x59
+                       MX7D_PAD_SD3_DATA5__SD3_DATA5           0x59
+                       MX7D_PAD_SD3_DATA6__SD3_DATA6           0x59
+                       MX7D_PAD_SD3_DATA7__SD3_DATA7           0x59
+                       MX7D_PAD_SD3_STROBE__SD3_STROBE         0x19
+               >;
+       };
+
+       pinctrl_usdhc3_100mhz: usdhc3grp_100mhz {
+               fsl,pins = <
+                       MX7D_PAD_SD3_CMD__SD3_CMD               0x5a
+                       MX7D_PAD_SD3_CLK__SD3_CLK               0x51
+                       MX7D_PAD_SD3_DATA0__SD3_DATA0           0x5a
+                       MX7D_PAD_SD3_DATA1__SD3_DATA1           0x5a
+                       MX7D_PAD_SD3_DATA2__SD3_DATA2           0x5a
+                       MX7D_PAD_SD3_DATA3__SD3_DATA3           0x5a
+                       MX7D_PAD_SD3_DATA4__SD3_DATA4           0x5a
+                       MX7D_PAD_SD3_DATA5__SD3_DATA5           0x5a
+                       MX7D_PAD_SD3_DATA6__SD3_DATA6           0x5a
+                       MX7D_PAD_SD3_DATA7__SD3_DATA7           0x5a
+                       MX7D_PAD_SD3_STROBE__SD3_STROBE         0x1a
+               >;
+       };
+
+       pinctrl_usdhc3_200mhz: usdhc3grp_200mhz {
+               fsl,pins = <
+                       MX7D_PAD_SD3_CMD__SD3_CMD               0x5b
+                       MX7D_PAD_SD3_CLK__SD3_CLK               0x51
+                       MX7D_PAD_SD3_DATA0__SD3_DATA0           0x5b
+                       MX7D_PAD_SD3_DATA1__SD3_DATA1           0x5b
+                       MX7D_PAD_SD3_DATA2__SD3_DATA2           0x5b
+                       MX7D_PAD_SD3_DATA3__SD3_DATA3           0x5b
+                       MX7D_PAD_SD3_DATA4__SD3_DATA4           0x5b
+                       MX7D_PAD_SD3_DATA5__SD3_DATA5           0x5b
+                       MX7D_PAD_SD3_DATA6__SD3_DATA6           0x5b
+                       MX7D_PAD_SD3_DATA7__SD3_DATA7           0x5b
+                       MX7D_PAD_SD3_STROBE__SD3_STROBE         0x1b
+               >;
+       };
+};
+
+&iomuxc_lpsr {
+       pinctrl_wdog1: wdog1grp {
+               fsl,pins = <
+                       MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B  0x30
+               >;
+       };
+};
+
+&sdma {
+       status = "okay";
+};
+
+&usdhc3 {
+       pinctrl-names = "default", "state_100mhz", "state_200mhz";
+       pinctrl-0 = <&pinctrl_usdhc3>;
+       pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
+       pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
+       assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>;
+       assigned-clock-rates = <400000000>;
+       bus-width = <8>;
+       non-removable;
+       vmmc-supply = <&vgen4_reg>;
+       vqmmc-supply = <&sw2_reg>;
+       status = "okay";
+};
+
+&wdog1 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_wdog1>;
+       /*
+        * Errata e10574:
+        * WDOG reset needs to run with WDOG_RESET_B signal enabled.
+        * X1-51 (WDOG1#) signal needs carrier board handling to reset
+        * TQMa7 on X1-22 (RESET_IN#).
+        */
+       fsl,ext-reset-output;
+       status = "okay";
+};

diff --git a/arch/arm/boot/dts/imx7d-mba7.dts b/arch/arm/boot/dts/imx7d-mba7.dts
new file mode 100644 (file)
index 0000000..221274c
--- /dev/null
+++ b/arch/arm/boot/dts/imx7d-mba7.dts
@@ -0,0 +1,119 @@
+// SPDX-License-Identifier: GPL-2.0 OR X11
+/*
+ * Device Tree Source for TQ Systems TQMa7D board on MBa7 carrier board.
+ *
+ * Copyright (C) 2016 TQ Systems GmbH
+ * Author: Markus Niebel <Markus.Niebel@tq-group.com>
+ * Copyright (C) 2019 Bruno Thomsen <bruno.thomsen@gmail.com>
+ */
+
+/dts-v1/;
+
+#include "imx7d-tqma7.dtsi"
+#include "imx7-mba7.dtsi"
+
+/ {
+       model = "TQ Systems TQMa7D board on MBa7 carrier board";
+       compatible = "tq,imx7d-mba7", "fsl,imx7d";
+};
+
+&fec2 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_enet2>;
+       phy-mode = "rgmii-id";
+       phy-reset-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>;
+       phy-reset-duration = <1>;
+       phy-reset-delay = <1>;
+       phy-supply = <&reg_fec2_pwdn>;
+       phy-handle = <&ethphy2_0>;
+       fsl,magic-packet;
+       status = "okay";
+
+       mdio {
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               ethphy2_0: ethernet-phy@0 {
+                       compatible = "ethernet-phy-ieee802.3-c22";
+                       reg = <0>;
+                       ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_50_NS>;
+                       ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_50_NS>;
+                       ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+                       /* LED1: Link/Activity, LED2: error */
+                       ti,led-function = <0x0db0>;
+                       /* active low, LED1/2 driven by phy */
+                       ti,led-ctrl = <0x1001>;
+               };
+       };
+};
+
+&iomuxc {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_hog_mba7_1>;
+
+       pinctrl_enet2: enet2grp {
+               fsl,pins = <
+                       MX7D_PAD_SD2_CD_B__ENET2_MDIO                   0x02
+                       MX7D_PAD_SD2_WP__ENET2_MDC                      0x00
+                       MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC             0x71
+                       MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0            0x71
+                       MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1            0x71
+                       MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2            0x71
+                       MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3             0x71
+                       MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL          0x71
+                       MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC            0x79
+                       MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0            0x79
+                       MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1             0x79
+                       MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2             0x79
+                       MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3            0x79
+                       MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL         0x79
+                       /* Reset: SION, 100kPU, SRE_FAST, DSE_X1 */
+                       MX7D_PAD_EPDC_BDR0__GPIO2_IO28          0x40000070
+                       /* INT/PWDN: SION, 100kPU, HYS, SRE_FAST, DSE_X1 */
+                       MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31      0x40000078
+               >;
+       };
+
+       pinctrl_pcie: pciegrp {
+               fsl,pins = <
+                       /* #pcie_wake */
+                       MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30               0x70
+                       /* #pcie_rst */
+                       MX7D_PAD_SD2_CLK__GPIO5_IO12                    0x70
+                       /* #pcie_dis */
+                       MX7D_PAD_EPDC_BDR1__GPIO2_IO29                  0x70
+               >;
+       };
+};
+
+&iomuxc_lpsr {
+       pinctrl_usbotg2: usbotg2grp {
+               fsl,pins = <
+                       MX7D_PAD_LPSR_GPIO1_IO06__USB_OTG2_OC   0x5c
+                       MX7D_PAD_LPSR_GPIO1_IO07__GPIO1_IO7     0x59
+               >;
+       };
+};
+
+&pcie {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_pcie>;
+       /* 1.5V logically from 3.3V */
+       /* probe deferral not supported */
+       /* pcie-bus-supply = <&reg_mpcie_1v5>; */
+       reset-gpio = <&gpio5 12 GPIO_ACTIVE_LOW>;
+       disable-gpio = <&gpio2 29 GPIO_ACTIVE_LOW>;
+       power-on-gpio = <&gpio2 30 GPIO_ACTIVE_LOW>;
+       status = "okay";
+};
+
+&usbotg2 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_usbotg2>;
+       vbus-supply = <&reg_usb_otg2_vbus>;
+       srp-disable;
+       hnp-disable;
+       adp-disable;
+       dr_mode = "host";
+       status = "okay";
+};

diff --git a/arch/arm/boot/dts/imx7d-tqma7.dtsi b/arch/arm/boot/dts/imx7d-tqma7.dtsi
new file mode 100644 (file)
index 0000000..8ad3048
--- /dev/null
+++ b/arch/arm/boot/dts/imx7d-tqma7.dtsi
@@ -0,0 +1,11 @@
+// SPDX-License-Identifier: GPL-2.0 OR X11
+/*
+ * Device Tree Include file for TQ Systems TQMa7D board with NXP i.MX7Dual SoC.
+ *
+ * Copyright (C) 2016 TQ Systems GmbH
+ * Author: Markus Niebel <Markus.Niebel@tq-group.com>
+ * Copyright (C) 2019 Bruno Thomsen <bruno.thomsen@gmail.com>
+ */
+
+#include "imx7d.dtsi"
+#include "imx7-tqma7.dtsi"

diff --git a/arch/arm/boot/dts/imx7d-zii-rpu2.dts b/arch/arm/boot/dts/imx7d-zii-rpu2.dts
new file mode 100644 (file)
index 0000000..3e467a9
--- /dev/null
+++ b/arch/arm/boot/dts/imx7d-zii-rpu2.dts
@@ -0,0 +1,941 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Device tree file for ZII's RPU2 board
+ *
+ * RPU - Remote Peripheral Unit
+ *
+ * Copyright (C) 2019 Zodiac Inflight Innovations
+ */
+
+/dts-v1/;
+#include <dt-bindings/thermal/thermal.h>
+#include "imx7d.dtsi"
+
+/ {
+       model = "ZII RPU2 Board";
+       compatible = "zii,imx7d-rpu2", "fsl,imx7d";
+
+       chosen {
+               stdout-path = &uart1;
+       };
+
+       cs2000_ref: oscillator {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               clock-frequency = <24576000>;
+       };
+
+       cs2000_in_dummy: dummy-oscillator {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               clock-frequency = <0>;
+       };
+
+       gpio-leds {
+               compatible = "gpio-leds";
+               pinctrl-0 = <&pinctrl_leds_debug>;
+               pinctrl-names = "default";
+
+               debug {
+                       label = "zii:green:debug1";
+                       gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>;
+                       linux,default-trigger = "heartbeat";
+               };
+       };
+
+       iio-hwmon {
+               compatible = "iio-hwmon";
+               io-channels = <&adc1 0>, <&adc1 1>, <&adc1 2>, <&adc1 3>,
+                             <&adc2 1>;
+       };
+
+       reg_can1_stby: regulator-can1-stby {
+               compatible = "regulator-fixed";
+               pinctrl-names = "default";
+               pinctrl-0 = <&pinctrl_flexcan1_stby>;
+               regulator-name = "can1-3v3";
+               regulator-min-microvolt = <3300000>;
+               regulator-max-microvolt = <3300000>;
+               gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
+               enable-active-high;
+       };
+
+       reg_can2_stby: regulator-can2-stby {
+               compatible = "regulator-fixed";
+               pinctrl-names = "default";
+               pinctrl-0 = <&pinctrl_flexcan2_stby>;
+               regulator-name = "can2-3v3";
+               regulator-min-microvolt = <3300000>;
+               regulator-max-microvolt = <3300000>;
+               gpio = <&gpio1 8 GPIO_ACTIVE_HIGH>;
+               enable-active-high;
+       };
+
+       reg_vref_1v8: regulator-vref-1v8 {
+               compatible = "regulator-fixed";
+               regulator-name = "vref-1v8";
+               regulator-min-microvolt = <1800000>;
+               regulator-max-microvolt = <1800000>;
+               regulator-always-on;
+       };
+
+       reg_3p3v: regulator-3p3v {
+               compatible = "regulator-fixed";
+               regulator-name = "GEN_3V3";
+               regulator-min-microvolt = <3300000>;
+               regulator-max-microvolt = <3300000>;
+               regulator-always-on;
+       };
+
+       reg_5p0v_main: regulator-5p0v-main {
+               compatible = "regulator-fixed";
+               regulator-name = "5V_MAIN";
+               regulator-min-microvolt = <5000000>;
+               regulator-max-microvolt = <5000000>;
+               regulator-always-on;
+       };
+
+       sound1 {
+               compatible = "simple-audio-card";
+               simple-audio-card,name = "Audio Output 1";
+               simple-audio-card,format = "i2s";
+               simple-audio-card,bitclock-master = <&sound1_codec>;
+               simple-audio-card,frame-master = <&sound1_codec>;
+               simple-audio-card,widgets =
+                       "Headphone", "Headphone Jack";
+               simple-audio-card,routing =
+                       "Headphone Jack", "HPLEFT",
+                       "Headphone Jack", "HPRIGHT",
+                       "LEFTIN", "HPL",
+                       "RIGHTIN", "HPR";
+               simple-audio-card,aux-devs = <&hpa1>;
+
+               simple-audio-card,cpu {
+                       sound-dai = <&sai1>;
+               };
+
+               sound1_codec: simple-audio-card,codec {
+                       sound-dai = <&codec1>;
+                       clocks = <&cs2000>;
+               };
+       };
+
+       sound2 {
+               compatible = "simple-audio-card";
+               simple-audio-card,name = "Audio Output 2";
+               simple-audio-card,format = "i2s";
+               simple-audio-card,bitclock-master = <&sound2_codec>;
+               simple-audio-card,frame-master = <&sound2_codec>;
+               simple-audio-card,widgets =
+                       "Headphone", "Headphone Jack";
+               simple-audio-card,routing =
+                       "Headphone Jack", "HPLEFT",
+                       "Headphone Jack", "HPRIGHT",
+                       "LEFTIN", "HPL",
+                       "RIGHTIN", "HPR";
+               simple-audio-card,aux-devs = <&hpa2>;
+
+               simple-audio-card,cpu {
+                       sound-dai = <&sai2>;
+               };
+
+               sound2_codec: simple-audio-card,codec {
+                       sound-dai = <&codec2>;
+                       clocks = <&cs2000>;
+               };
+       };
+
+       sound3 {
+               compatible = "simple-audio-card";
+               simple-audio-card,name = "Audio Output 3";
+               simple-audio-card,format = "i2s";
+               simple-audio-card,bitclock-master = <&sound3_codec>;
+               simple-audio-card,frame-master = <&sound3_codec>;
+               simple-audio-card,widgets =
+                       "Headphone", "Headphone Jack";
+               simple-audio-card,routing =
+                       "Headphone Jack", "HPLEFT",
+                       "Headphone Jack", "HPRIGHT",
+                       "LEFTIN", "HPL",
+                       "RIGHTIN", "HPR";
+               simple-audio-card,aux-devs = <&hpa3>;
+
+               simple-audio-card,cpu {
+                       sound-dai = <&sai3>;
+               };
+
+               sound3_codec: simple-audio-card,codec {
+                       sound-dai = <&codec3>;
+                       clocks = <&cs2000>;
+               };
+       };
+};
+
+&adc1 {
+       vref-supply = <&reg_vref_1v8>;
+       status = "okay";
+};
+
+&adc2 {
+       vref-supply = <&reg_vref_1v8>;
+       status = "okay";
+};
+
+&cpu0 {
+       arm-supply = <&sw1a_reg>;
+};
+
+&clks {
+       assigned-clocks = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
+       assigned-clock-rates = <884736000>;
+};
+
+&ecspi1 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_ecspi1>;
+       cs-gpios = <&gpio4 19 GPIO_ACTIVE_HIGH>;
+       status = "okay";
+
+       flash@0 {
+               compatible = "jedec,spi-nor";
+               spi-max-frequency = <20000000>;
+               reg = <0>;
+               #address-cells = <1>;
+               #size-cells = <1>;
+       };
+};
+
+&fec1 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_enet1>;
+       assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
+                         <&clks IMX7D_ENET1_TIME_ROOT_CLK>;
+       assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
+       assigned-clock-rates = <0>, <100000000>;
+       phy-mode = "rgmii";
+       status = "okay";
+
+       fixed-link {
+               speed = <1000>;
+               full-duplex;
+       };
+
+       mdio1: mdio {
+               #address-cells = <1>;
+               #size-cells = <0>;
+               status = "okay";
+
+               switch: switch@0 {
+                       compatible = "marvell,mv88e6085";
+                       pinctrl-names = "default";
+                       pinctrl-0 = <&pinctrl_switch>;
+                       reg = <0>;
+                       eeprom-length = <512>;
+                       interrupt-parent = <&gpio1>;
+                       interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+
+                       ports {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+
+                               port@0 {
+                                       reg = <0>;
+                                       label = "eth_cu_1000_1";
+                               };
+
+                               port@1 {
+                                       reg = <1>;
+                                       label = "eth_cu_1000_2";
+                               };
+
+                               port@2 {
+                                       reg = <2>;
+                                       label = "pic";
+
+                                       fixed-link {
+                                               speed = <100>;
+                                               full-duplex;
+                                       };
+                               };
+
+                               port@5 {
+                                       reg = <5>;
+                                       label = "cpu";
+                                       ethernet = <&fec1>;
+                                       phy-mode = "rgmii-id";
+
+                                       fixed-link {
+                                               speed = <1000>;
+                                               full-duplex;
+                                       };
+                               };
+
+                               port@6 {
+                                       reg = <6>;
+                                       label = "gigabit_proc";
+                                       ethernet = <&fec2>;
+                                       phy-mode = "rgmii-id";
+
+                                       fixed-link {
+                                               speed = <1000>;
+                                               full-duplex;
+                                       };
+                               };
+                       };
+               };
+       };
+};
+
+&fec2 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_enet2>;
+       assigned-clocks = <&clks IMX7D_ENET2_TIME_ROOT_SRC>,
+                         <&clks IMX7D_ENET2_TIME_ROOT_CLK>;
+       assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
+       assigned-clock-rates = <0>, <100000000>;
+       phy-mode = "rgmii";
+       fsl,magic-packet;
+       status = "okay";
+
+       fixed-link {
+               speed = <1000>;
+               full-duplex;
+       };
+};
+
+&flexcan1 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_flexcan1>;
+       xceiver-supply = <&reg_can1_stby>;
+       status = "okay";
+};
+
+&flexcan2 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_flexcan2>;
+       xceiver-supply = <&reg_can2_stby>;
+       status = "okay";
+};
+
+&gpio1 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_gpio1>;
+
+       gpio-line-names = "", "", "", "", "", "", "", "",
+                         "", "",
+                         "usb_1_en_b",
+                         "usb_2_en_b",
+                         "", "", "", "", "", "", "", "",
+                         "", "", "", "", "", "", "", "",
+                         "", "", "", "";
+};
+
+&gpio2 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_gpio2>;
+
+       gpio-line-names = "12v_out_en_1",
+                         "12v_out_en_2",
+                         "12v_out_en_3",
+                         "28v_out_en_5",
+                         "28v_out_en_1",
+                         "28v_out_en_2",
+                         "28v_out_en_3",
+                         "28v_out_en_4",
+                         "", "",
+                         "usb_3_en_b",
+                         "usb_4_en_b",
+                         "", "", "", "", "", "", "", "",
+                         "", "", "", "", "", "", "", "",
+                         "", "", "", "";
+};
+
+&i2c1 {
+       clock-frequency = <100000>;
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_i2c1>;
+       status = "okay";
+
+       pmic: pmic@8 {
+               compatible = "fsl,pfuze3000";
+               reg = <0x08>;
+
+               regulators {
+                       sw1a_reg: sw1a {
+                               regulator-min-microvolt = <700000>;
+                               regulator-max-microvolt = <3300000>;
+                               regulator-boot-on;
+                               regulator-always-on;
+                               regulator-ramp-delay = <6250>;
+                       };
+
+                       sw1c_reg: sw1b {
+                               regulator-min-microvolt = <700000>;
+                               regulator-max-microvolt = <1475000>;
+                               regulator-boot-on;
+                               regulator-always-on;
+                               regulator-ramp-delay = <6250>;
+                       };
+
+                       sw2_reg: sw2 {
+                               regulator-min-microvolt = <1500000>;
+                               regulator-max-microvolt = <1850000>;
+                               regulator-boot-on;
+                               regulator-always-on;
+                       };
+
+                       sw3a_reg: sw3 {
+                               regulator-min-microvolt = <900000>;
+                               regulator-max-microvolt = <1650000>;
+                               regulator-boot-on;
+                               regulator-always-on;
+                       };
+
+                       swbst_reg: swbst {
+                               regulator-min-microvolt = <5000000>;
+                               regulator-max-microvolt = <5150000>;
+                       };
+
+                       snvs_reg: vsnvs {
+                               regulator-min-microvolt = <1000000>;
+                               regulator-max-microvolt = <3000000>;
+                               regulator-boot-on;
+                               regulator-always-on;
+                       };
+
+                       vref_reg: vrefddr {
+                               regulator-boot-on;
+                               regulator-always-on;
+                       };
+
+                       vgen1_reg: vldo1 {
+                               regulator-min-microvolt = <1800000>;
+                               regulator-max-microvolt = <3300000>;
+                               regulator-always-on;
+                       };
+
+                       vgen2_reg: vldo2 {
+                               regulator-min-microvolt = <800000>;
+                               regulator-max-microvolt = <1550000>;
+                               regulator-always-on;
+                       };
+
+                       vgen3_reg: vccsd {
+                               regulator-min-microvolt = <2850000>;
+                               regulator-max-microvolt = <3300000>;
+                               regulator-always-on;
+                       };
+
+                       vgen4_reg: v33 {
+                               regulator-min-microvolt = <2850000>;
+                               regulator-max-microvolt = <3300000>;
+                               regulator-always-on;
+                       };
+
+                       vgen5_reg: vldo3 {
+                               regulator-min-microvolt = <1800000>;
+                               regulator-max-microvolt = <3300000>;
+                               regulator-always-on;
+                       };
+
+                       vgen6_reg: vldo4 {
+                               regulator-min-microvolt = <1800000>;
+                               regulator-max-microvolt = <3300000>;
+                               regulator-always-on;
+                       };
+               };
+       };
+
+       cs2000: clkgen@4e {
+               compatible = "cirrus,cs2000-cp";
+               reg = <0x4e>;
+               #clock-cells = <0>;
+               clock-names = "clk_in", "ref_clk";
+               clocks = <&cs2000_in_dummy>, <&cs2000_ref>;
+               assigned-clocks = <&cs2000>;
+               assigned-clock-rates = <24000000>;
+       };
+
+       eeprom@50 {
+               compatible = "atmel,24c04";
+               reg = <0x50>;
+       };
+
+       eeprom@52 {
+               compatible = "atmel,24c04";
+               reg = <0x52>;
+       };
+};
+
+&i2c2 {
+       clock-frequency = <100000>;
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_i2c2>;
+       status = "okay";
+
+       codec2: codec@18 {
+               compatible = "ti,tlv320dac3100";
+               pinctrl-names = "default";
+               pinctrl-0 = <&pinctrl_codec2>;
+               reg = <0x18>;
+               #sound-dai-cells = <0>;
+               HPVDD-supply = <&reg_3p3v>;
+               SPRVDD-supply = <&reg_3p3v>;
+               SPLVDD-supply = <&reg_3p3v>;
+               AVDD-supply = <&reg_3p3v>;
+               IOVDD-supply = <&reg_3p3v>;
+               DVDD-supply = <&vgen4_reg>;
+               gpio-reset = <&gpio1 6 GPIO_ACTIVE_LOW>;
+       };
+
+       hpa2: amp@60 {
+               compatible = "ti,tpa6130a2";
+               pinctrl-names = "default";
+               pinctrl-0 = <&pinctrl_tpa2>;
+               reg = <0x60>;
+               power-gpio = <&gpio3 27 GPIO_ACTIVE_HIGH>;
+               Vdd-supply = <&reg_5p0v_main>;
+       };
+};
+
+&i2c3 {
+       clock-frequency = <100000>;
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_i2c3>;
+       status = "okay";
+
+       codec3: codec@18 {
+               compatible = "ti,tlv320dac3100";
+               pinctrl-names = "default";
+               pinctrl-0 = <&pinctrl_codec3>;
+               reg = <0x18>;
+               #sound-dai-cells = <0>;
+               HPVDD-supply = <&reg_3p3v>;
+               SPRVDD-supply = <&reg_3p3v>;
+               SPLVDD-supply = <&reg_3p3v>;
+               AVDD-supply = <&reg_3p3v>;
+               IOVDD-supply = <&reg_3p3v>;
+               DVDD-supply = <&vgen4_reg>;
+               gpio-reset = <&gpio1 7 GPIO_ACTIVE_LOW>;
+       };
+
+       hpa3: amp@60 {
+               compatible = "ti,tpa6130a2";
+               pinctrl-names = "default";
+               pinctrl-0 = <&pinctrl_tpa3>;
+               reg = <0x60>;
+               power-gpio = <&gpio3 28 GPIO_ACTIVE_HIGH>;
+               Vdd-supply = <&reg_5p0v_main>;
+       };
+};
+
+&i2c4 {
+       clock-frequency = <100000>;
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_i2c4>;
+       status = "okay";
+
+       codec1: codec@18 {
+               compatible = "ti,tlv320dac3100";
+               pinctrl-names = "default";
+               pinctrl-0 = <&pinctrl_codec1>;
+               reg = <0x18>;
+               #sound-dai-cells = <0>;
+               HPVDD-supply = <&reg_3p3v>;
+               SPRVDD-supply = <&reg_3p3v>;
+               SPLVDD-supply = <&reg_3p3v>;
+               AVDD-supply = <&reg_3p3v>;
+               IOVDD-supply = <&reg_3p3v>;
+               DVDD-supply = <&vgen4_reg>;
+               gpio-reset = <&gpio1 5 GPIO_ACTIVE_LOW>;
+       };
+
+       hpa1: amp@60 {
+               compatible = "ti,tpa6130a2";
+               pinctrl-names = "default";
+               pinctrl-0 = <&pinctrl_tpa1>;
+               reg = <0x60>;
+               power-gpio = <&gpio3 26 GPIO_ACTIVE_HIGH>;
+               Vdd-supply = <&reg_5p0v_main>;
+       };
+};
+
+&sai1 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_sai1>;
+       assigned-clocks = <&clks IMX7D_SAI1_ROOT_SRC>,
+                         <&clks IMX7D_SAI1_ROOT_CLK>;
+       assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
+       assigned-clock-rates = <0>, <36864000>;
+       status = "okay";
+};
+
+&sai2 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_sai2>;
+       assigned-clocks = <&clks IMX7D_SAI2_ROOT_SRC>,
+                         <&clks IMX7D_SAI2_ROOT_CLK>;
+       assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
+       assigned-clock-rates = <0>, <36864000>;
+       status = "okay";
+};
+
+&sai3 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_sai3>;
+       assigned-clocks = <&clks IMX7D_SAI3_ROOT_SRC>,
+                         <&clks IMX7D_SAI3_ROOT_CLK>;
+       assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
+       assigned-clock-rates = <0>, <36864000>;
+       status = "okay";
+};
+
+&uart2 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_uart2>;
+       assigned-clocks = <&clks IMX7D_UART2_ROOT_SRC>;
+       assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
+       status = "okay";
+};
+
+&uart4 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_uart4>;
+       assigned-clocks = <&clks IMX7D_UART4_ROOT_SRC>;
+       assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
+       status = "okay";
+
+       rave-sp {
+               compatible = "zii,rave-sp-rdu2";
+               current-speed = <1000000>;
+               #address-cells = <1>;
+               #size-cells = <1>;
+
+               watchdog {
+                       compatible = "zii,rave-sp-watchdog";
+               };
+
+               eeprom@a3 {
+                       compatible = "zii,rave-sp-eeprom";
+                       reg = <0xa3 0x4000>;
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       zii,eeprom-name = "main-eeprom";
+               };
+       };
+};
+
+&usbotg1 {
+       dr_mode = "host";
+       disable-over-current;
+       status = "okay";
+};
+
+&usbotg2 {
+       dr_mode = "host";
+       disable-over-current;
+       status = "okay";
+};
+
+&usdhc1 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_usdhc1>;
+       bus-width = <4>;
+       no-1-8-v;
+       no-sdio;
+       keep-power-in-suspend;
+       status = "okay";
+};
+
+&usdhc3 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_usdhc3>;
+       bus-width = <8>;
+       no-1-8-v;
+       non-removable;
+       no-sdio;
+       no-sd;
+       keep-power-in-suspend;
+       status = "okay";
+};
+
+&wdog1 {
+       status = "disabled";
+};
+
+&snvs_rtc {
+       status = "disabled";
+};
+
+&snvs_pwrkey {
+       status = "disabled";
+};
+
+&iomuxc {
+       pinctrl_ecspi1: ecspi1grp {
+               fsl,pins = <
+                       MX7D_PAD_ECSPI1_SCLK__ECSPI1_SCLK       0x2
+                       MX7D_PAD_ECSPI1_MOSI__ECSPI1_MOSI       0x2
+                       MX7D_PAD_ECSPI1_MISO__ECSPI1_MISO       0x2
+                       MX7D_PAD_ECSPI1_SS0__GPIO4_IO19         0x59
+               >;
+       };
+
+       pinctrl_enet1: enet1grp {
+               fsl,pins = <
+                       MX7D_PAD_SD2_CD_B__ENET1_MDIO                           0x3
+                       MX7D_PAD_SD2_WP__ENET1_MDC                              0x3
+                       MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC               0x1
+                       MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0               0x1
+                       MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1               0x1
+                       MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2               0x1
+                       MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3               0x1
+                       MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL         0x1
+                       MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC               0x1
+                       MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0               0x1
+                       MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1               0x1
+                       MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2               0x1
+                       MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3               0x1
+                       MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL         0x1
+               >;
+       };
+
+       pinctrl_enet2: enet2grp {
+               fsl,pins = <
+                       MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC                     0x1
+                       MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0                    0x1
+                       MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1                    0x1
+                       MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2                    0x1
+                       MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3                     0x1
+                       MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL                  0x1
+                       MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC                    0x1
+                       MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0                    0x1
+                       MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1                     0x1
+                       MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2                     0x1
+                       MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3                    0x1
+                       MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL                 0x1
+                       MX7D_PAD_UART1_TX_DATA__ENET2_1588_EVENT0_OUT           0x1
+               >;
+       };
+
+       pinctrl_flexcan1: flexcan1grp {
+               fsl,pins = <
+                       MX7D_PAD_GPIO1_IO12__FLEXCAN1_RX        0x59
+                       MX7D_PAD_GPIO1_IO13__FLEXCAN1_TX        0x59
+               >;
+       };
+
+       pinctrl_flexcan1_stby: flexcan1stbygrp {
+               fsl,pins = <
+                       MX7D_PAD_GPIO1_IO08__GPIO1_IO8          0x59
+               >;
+       };
+
+       pinctrl_flexcan2: flexcan2grp {
+               fsl,pins = <
+                       MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX        0x59
+                       MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX        0x59
+               >;
+       };
+
+       pinctrl_flexcan2_stby: flexcan2stbygrp {
+               fsl,pins = <
+                       MX7D_PAD_GPIO1_IO09__GPIO1_IO9          0x59
+               >;
+       };
+
+       pinctrl_gpio1: gpio1grp {
+               fsl,pins = <
+                       MX7D_PAD_GPIO1_IO10__GPIO1_IO10         0x00
+                       MX7D_PAD_GPIO1_IO11__GPIO1_IO11         0x00
+               >;
+       };
+
+       pinctrl_gpio2: gpio2grp {
+               fsl,pins = <
+                       MX7D_PAD_EPDC_DATA00__GPIO2_IO0         0x00
+                       MX7D_PAD_EPDC_DATA01__GPIO2_IO1         0x00
+                       MX7D_PAD_EPDC_DATA02__GPIO2_IO2         0x00
+                       MX7D_PAD_EPDC_DATA03__GPIO2_IO3         0x03
+                       MX7D_PAD_EPDC_DATA04__GPIO2_IO4         0x03
+                       MX7D_PAD_EPDC_DATA05__GPIO2_IO5         0x03
+                       MX7D_PAD_EPDC_DATA06__GPIO2_IO6         0x03
+                       MX7D_PAD_EPDC_DATA07__GPIO2_IO7         0x03
+                       MX7D_PAD_EPDC_DATA10__GPIO2_IO10        0x00
+                       MX7D_PAD_EPDC_DATA11__GPIO2_IO11        0x00
+               >;
+       };
+
+       pinctrl_i2c1: i2c1grp {
+               fsl,pins = <
+                       MX7D_PAD_I2C1_SDA__I2C1_SDA             0x4000007f
+                       MX7D_PAD_I2C1_SCL__I2C1_SCL             0x4000007f
+               >;
+       };
+
+       pinctrl_i2c1_gpio: i2c1gpiogrp {
+               fsl,pins = <
+                       MX7D_PAD_I2C1_SDA__GPIO4_IO9            0x4000007f
+                       MX7D_PAD_I2C1_SCL__GPIO4_IO8            0x4000007f
+               >;
+       };
+
+       pinctrl_i2c2: i2c2grp {
+               fsl,pins = <
+                       MX7D_PAD_I2C2_SDA__I2C2_SDA             0x4000007f
+                       MX7D_PAD_I2C2_SCL__I2C2_SCL             0x4000007f
+               >;
+       };
+
+       pinctrl_i2c2_gpio: i2c2gpiogrp {
+               fsl,pins = <
+                       MX7D_PAD_I2C2_SDA__GPIO4_IO11           0x4000007f
+                       MX7D_PAD_I2C2_SCL__GPIO4_IO10           0x4000007f
+               >;
+       };
+
+       pinctrl_i2c3: i2c3grp {
+               fsl,pins = <
+                       MX7D_PAD_I2C3_SDA__I2C3_SDA             0x4000007f
+                       MX7D_PAD_I2C3_SCL__I2C3_SCL             0x4000007f
+               >;
+       };
+
+       pinctrl_i2c3_gpio: i2c3gpiogrp {
+               fsl,pins = <
+                       MX7D_PAD_I2C3_SDA__GPIO4_IO13           0x4000007f
+                       MX7D_PAD_I2C3_SCL__GPIO4_IO12           0x4000007f
+               >;
+       };
+
+       pinctrl_i2c4: i2c4grp {
+               fsl,pins = <
+                       MX7D_PAD_I2C4_SDA__I2C4_SDA             0x4000007f
+                       MX7D_PAD_I2C4_SCL__I2C4_SCL             0x4000007f
+               >;
+       };
+
+       pinctrl_i2c4_gpio: i2c4gpiogrp {
+               fsl,pins = <
+                       MX7D_PAD_SAI1_RX_BCLK__GPIO6_IO17       0x4000007f
+                       MX7D_PAD_SAI1_RX_SYNC__GPIO6_IO16       0x4000007f
+               >;
+       };
+
+       pinctrl_leds_debug: debuggrp {
+               fsl,pins = <
+                       MX7D_PAD_EPDC_DATA08__GPIO2_IO8         0x59
+               >;
+       };
+
+       pinctrl_sai1: sai1grp {
+               fsl,pins = <
+                       MX7D_PAD_SAI1_TX_BCLK__SAI1_TX_BCLK     0x1f
+                       MX7D_PAD_SAI1_TX_SYNC__SAI1_TX_SYNC     0x1f
+                       MX7D_PAD_SAI1_TX_DATA__SAI1_TX_DATA0    0x30
+               >;
+       };
+
+       pinctrl_sai2: sai2grp {
+               fsl,pins = <
+                       MX7D_PAD_SAI2_TX_BCLK__SAI2_TX_BCLK     0x1f
+                       MX7D_PAD_SAI2_TX_SYNC__SAI2_TX_SYNC     0x1f
+                       MX7D_PAD_SAI2_TX_DATA__SAI2_TX_DATA0    0x30
+               >;
+       };
+
+       pinctrl_sai3: sai3grp {
+               fsl,pins = <
+                       MX7D_PAD_UART3_TX_DATA__SAI3_TX_BCLK    0x1f
+                       MX7D_PAD_UART3_CTS_B__SAI3_TX_SYNC      0x1f
+                       MX7D_PAD_UART3_RTS_B__SAI3_TX_DATA0     0x30
+               >;
+       };
+
+       pinctrl_tpa1: tpa6130-1grp {
+               fsl,pins = <
+                       MX7D_PAD_LCD_DATA21__GPIO3_IO26         0x40000038
+               >;
+       };
+
+       pinctrl_tpa2: tpa6130-2grp {
+               fsl,pins = <
+                       MX7D_PAD_LCD_DATA22__GPIO3_IO27         0x40000038
+               >;
+       };
+
+       pinctrl_tpa3: tpa6130-3grp {
+               fsl,pins = <
+                       MX7D_PAD_LCD_DATA23__GPIO3_IO28         0x40000038
+               >;
+       };
+
+       pinctrl_uart2: uart2grp {
+               fsl,pins = <
+                       MX7D_PAD_UART2_RX_DATA__UART2_DCE_RX    0x79
+                       MX7D_PAD_UART2_TX_DATA__UART2_DCE_TX    0x79
+               >;
+       };
+
+       pinctrl_uart4: uart4grp {
+               fsl,pins = <
+                       MX7D_PAD_SD2_DATA0__UART4_DCE_RX        0x79
+                       MX7D_PAD_SD2_DATA1__UART4_DCE_TX        0x79
+               >;
+       };
+
+       pinctrl_usdhc1: usdhc1grp {
+               fsl,pins = <
+                       MX7D_PAD_SD1_CMD__SD1_CMD               0x59
+                       MX7D_PAD_SD1_CLK__SD1_CLK               0x19
+                       MX7D_PAD_SD1_DATA0__SD1_DATA0           0x59
+                       MX7D_PAD_SD1_DATA1__SD1_DATA1           0x59
+                       MX7D_PAD_SD1_DATA2__SD1_DATA2           0x59
+                       MX7D_PAD_SD1_DATA3__SD1_DATA3           0x59
+               >;
+       };
+
+       pinctrl_usdhc3: usdhc3grp {
+               fsl,pins = <
+                       MX7D_PAD_SD3_CMD__SD3_CMD               0x59
+                       MX7D_PAD_SD3_CLK__SD3_CLK               0x19
+                       MX7D_PAD_SD3_DATA0__SD3_DATA0           0x59
+                       MX7D_PAD_SD3_DATA1__SD3_DATA1           0x59
+                       MX7D_PAD_SD3_DATA2__SD3_DATA2           0x59
+                       MX7D_PAD_SD3_DATA3__SD3_DATA3           0x59
+                       MX7D_PAD_SD3_DATA4__SD3_DATA4           0x59
+                       MX7D_PAD_SD3_DATA5__SD3_DATA5           0x59
+                       MX7D_PAD_SD3_DATA6__SD3_DATA6           0x59
+                       MX7D_PAD_SD3_DATA7__SD3_DATA7           0x59
+                       MX7D_PAD_SD3_RESET_B__SD3_RESET_B       0x59
+               >;
+       };
+};
+
+&iomuxc_lpsr {
+       pinctrl_codec1: dac1grp {
+               fsl,pins = <
+                       MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5     0x40000038
+               >;
+       };
+
+       pinctrl_codec2: dac2grp {
+               fsl,pins = <
+                       MX7D_PAD_LPSR_GPIO1_IO06__GPIO1_IO6     0x40000038
+               >;
+       };
+
+       pinctrl_codec3: dac3grp {
+               fsl,pins = <
+                       MX7D_PAD_LPSR_GPIO1_IO07__GPIO1_IO7     0x40000038
+               >;
+       };
+
+       pinctrl_switch: switchgrp {
+               fsl,pins = <
+                       MX7D_PAD_LPSR_GPIO1_IO02__GPIO1_IO2     0x08
+               >;
+       };
+};

diff --git a/arch/arm/boot/dts/imx7d.dtsi b/arch/arm/boot/dts/imx7d.dtsi
index 6eb98e7..f33b560 100644 (file)
--- a/arch/arm/boot/dts/imx7d.dtsi
+++ b/arch/arm/boot/dts/imx7d.dtsi
@@ -154,6 +154,7 @@
                ranges = <0x81000000 0 0          0x4ff80000 0 0x00010000   /* downstream I/O */
                          0x82000000 0 0x40000000 0x40000000 0 0x0ff00000>; /* non-prefetchable memory */
                num-lanes = <1>;
+               num-viewport = <4>;
                interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
                interrupt-names = "msi";
                #interrupt-cells = <1>;

diff --git a/arch/arm/boot/dts/imx7s-mba7.dts b/arch/arm/boot/dts/imx7s-mba7.dts
new file mode 100644 (file)
index 0000000..a143d56
--- /dev/null
+++ b/arch/arm/boot/dts/imx7s-mba7.dts
@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: GPL-2.0 OR X11
+/*
+ * Device Tree Source for TQ Systems TQMa7S board on MBa7 carrier board.
+ *
+ * Copyright (C) 2016 TQ Systems GmbH
+ * Author: Markus Niebel <Markus.Niebel@tq-group.com>
+ * Copyright (C) 2019 Bruno Thomsen <bruno.thomsen@gmail.com>
+ */
+
+/dts-v1/;
+
+#include "imx7s-tqma7.dtsi"
+#include "imx7-mba7.dtsi"
+
+/ {
+       model = "TQ Systems TQMa7S board on MBa7 carrier board";
+       compatible = "tq,imx7s-mba7", "fsl,imx7s";
+};

diff --git a/arch/arm/boot/dts/imx7s-tqma7.dtsi b/arch/arm/boot/dts/imx7s-tqma7.dtsi
new file mode 100644 (file)
index 0000000..5f5433e
--- /dev/null
+++ b/arch/arm/boot/dts/imx7s-tqma7.dtsi
@@ -0,0 +1,11 @@
+// SPDX-License-Identifier: GPL-2.0 OR X11
+/*
+ * Device Tree Include file for TQ Systems TQMa7S board with NXP i.MX7Solo SoC.
+ *
+ * Copyright (C) 2016 TQ Systems GmbH
+ * Author: Markus Niebel <Markus.Niebel@tq-group.com>
+ * Copyright (C) 2019 Bruno Thomsen <bruno.thomsen@gmail.com>
+ */
+
+#include "imx7s.dtsi"
+#include "imx7-tqma7.dtsi"

diff --git a/arch/arm/boot/dts/imx7s-warp.dts b/arch/arm/boot/dts/imx7s-warp.dts
index 23431fa..d6b4888 100644 (file)
--- a/arch/arm/boot/dts/imx7s-warp.dts
+++ b/arch/arm/boot/dts/imx7s-warp.dts
@@ -55,6 +55,14 @@
                regulator-always-on;
        };
 
+       reg_peri_3p15v: regulator-peri-3p15v {
+               compatible = "regulator-fixed";
+               regulator-name = "peri_3p15v_reg";
+               regulator-min-microvolt = <3150000>;
+               regulator-max-microvolt = <3150000>;
+               regulator-always-on;
+       };
+
        sound {
                compatible = "simple-audio-card";
                simple-audio-card,name = "imx7-sgtl5000";
@@ -77,6 +85,10 @@
        assigned-clock-rates = <884736000>;
 };
 
+&csi {
+       status = "okay";
+};
+
 &i2c1 {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_i2c1>;
@@ -121,6 +133,8 @@
                        swbst_reg: swbst {
                                regulator-min-microvolt = <5000000>;
                                regulator-max-microvolt = <5150000>;
+                               regulator-boot-on;
+                               regulator-always-on;
                        };
 
                        snvs_reg: vsnvs {
@@ -178,6 +192,27 @@
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_i2c2>;
        status = "okay";
+
+       ov2680: camera@36 {
+               compatible = "ovti,ov2680";
+               pinctrl-names = "default";
+               pinctrl-0 = <&pinctrl_ov2680>;
+               reg = <0x36>;
+               clocks = <&osc>;
+               clock-names = "xvclk";
+               reset-gpios = <&gpio1 3 GPIO_ACTIVE_LOW>;
+               DOVDD-supply = <&sw2_reg>;
+               DVDD-supply = <&sw2_reg>;
+               AVDD-supply = <&reg_peri_3p15v>;
+
+               port {
+                       ov2680_to_mipi: endpoint {
+                               remote-endpoint = <&mipi_from_sensor>;
+                               clock-lanes = <0>;
+                               data-lanes = <1>;
+                       };
+               };
+       };
 };
 
 &i2c3 {
@@ -211,6 +246,22 @@
        };
 };
 
+&mipi_csi {
+       clock-frequency = <166000000>;
+       fsl,csis-hs-settle = <3>;
+       status = "okay";
+
+       port@0 {
+               reg = <0>;
+
+               mipi_from_sensor: endpoint {
+                       remote-endpoint = <&ov2680_to_mipi>;
+                       data-lanes = <1>;
+               };
+
+       };
+};
+
 &sai1 {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_sai1>;
@@ -277,6 +328,10 @@
        status = "okay";
 };
 
+&video_mux {
+       status = "okay";
+};
+
 &wdog1 {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_wdog>;
@@ -331,6 +386,12 @@
                >;
        };
 
+       pinctrl_ov2680: ov2660grp {
+               fsl,pins = <
+                       MX7D_PAD_LPSR_GPIO1_IO03__GPIO1_IO3     0x14
+               >;
+       };
+
        pinctrl_sai1: sai1grp {
                fsl,pins = <
                        MX7D_PAD_SAI1_RX_DATA__SAI1_RX_DATA0    0x1f

diff --git a/arch/arm/boot/dts/imx7s.dtsi b/arch/arm/boot/dts/imx7s.dtsi
index e88f53a..106711d 100644 (file)
--- a/arch/arm/boot/dts/imx7s.dtsi
+++ b/arch/arm/boot/dts/imx7s.dtsi
@@ -8,6 +8,7 @@
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/reset/imx7-reset.h>
 #include "imx7d-pinfunc.h"
 
 / {
@@ -497,8 +498,43 @@
 
                        gpr: iomuxc-gpr@30340000 {
                                compatible = "fsl,imx7d-iomuxc-gpr",
-                                       "fsl,imx6q-iomuxc-gpr", "syscon";
+                                       "fsl,imx6q-iomuxc-gpr", "syscon",
+                                       "simple-mfd";
                                reg = <0x30340000 0x10000>;
+
+                               mux: mux-controller {
+                                       compatible = "mmio-mux";
+                                       #mux-control-cells = <0>;
+                                       mux-reg-masks = <0x14 0x00000010>;
+                               };
+
+                               video_mux: csi-mux {
+                                       compatible = "video-mux";
+                                       mux-controls = <&mux 0>;
+                                       #address-cells = <1>;
+                                       #size-cells = <0>;
+                                       status = "disabled";
+
+                                       port@0 {
+                                               reg = <0>;
+                                       };
+
+                                       port@1 {
+                                               reg = <1>;
+
+                                               csi_mux_from_mipi_vc0: endpoint {
+                                                       remote-endpoint = <&mipi_vc0_to_csi_mux>;
+                                               };
+                                       };
+
+                                       port@2 {
+                                               reg = <2>;
+
+                                               csi_mux_to_csi: endpoint {
+                                                       remote-endpoint = <&csi_from_csi_mux>;
+                                               };
+                                       };
+                               };
                        };
 
                        ocotp: ocotp-ctrl@30350000 {
@@ -606,7 +642,13 @@
                                        #address-cells = <1>;
                                        #size-cells = <0>;
 
-                                       pgc_pcie_phy: pgc-power-domain@1 {
+                                       pgc_mipi_phy: power-domain@0 {
+                                               #power-domain-cells = <0>;
+                                               reg = <0>;
+                                               power-supply = <&reg_1p0d>;
+                                       };
+
+                                       pgc_pcie_phy: power-domain@1 {
                                                #power-domain-cells = <0>;
                                                reg = <1>;
                                                power-supply = <&reg_1p0d>;
@@ -628,6 +670,7 @@
                                interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&clks IMX7D_ADC_ROOT_CLK>;
                                clock-names = "adc";
+                               #io-channel-cells = <1>;
                                status = "disabled";
                        };
 
@@ -637,6 +680,7 @@
                                interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&clks IMX7D_ADC_ROOT_CLK>;
                                clock-names = "adc";
+                               #io-channel-cells = <1>;
                                status = "disabled";
                        };
 
@@ -696,6 +740,23 @@
                                status = "disabled";
                        };
 
+                       csi: csi@30710000 {
+                               compatible = "fsl,imx7-csi";
+                               reg = <0x30710000 0x10000>;
+                               interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+                               clocks = <&clks IMX7D_CLK_DUMMY>,
+                                        <&clks IMX7D_CSI_MCLK_ROOT_CLK>,
+                                        <&clks IMX7D_CLK_DUMMY>;
+                               clock-names = "axi", "mclk", "dcic";
+                               status = "disabled";
+
+                               port {
+                                       csi_from_csi_mux: endpoint {
+                                               remote-endpoint = <&csi_mux_to_csi>;
+                                       };
+                               };
+                       };
+
                        lcdif: lcdif@30730000 {
                                compatible = "fsl,imx7d-lcdif", "fsl,imx28-lcdif";
                                reg = <0x30730000 0x10000>;
@@ -705,6 +766,35 @@
                                clock-names = "pix", "axi";
                                status = "disabled";
                        };
+
+                       mipi_csi: mipi-csi@30750000 {
+                               compatible = "fsl,imx7-mipi-csi2";
+                               reg = <0x30750000 0x10000>;
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                               interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+                               clocks = <&clks IMX7D_IPG_ROOT_CLK>,
+                                        <&clks IMX7D_MIPI_CSI_ROOT_CLK>,
+                                        <&clks IMX7D_MIPI_DPHY_ROOT_CLK>;
+                               clock-names = "pclk", "wrap", "phy";
+                               power-domains = <&pgc_mipi_phy>;
+                               phy-supply = <&reg_1p0d>;
+                               resets = <&src IMX7_RESET_MIPI_PHY_MRST>;
+                               reset-names = "mrst";
+                               status = "disabled";
+
+                               port@0 {
+                                       reg = <0>;
+                               };
+
+                               port@1 {
+                                       reg = <1>;
+
+                                       mipi_vc0_to_csi_mux: endpoint {
+                                               remote-endpoint = <&csi_mux_from_mipi_vc0>;
+                                       };
+                               };
+                       };
                };
 
                aips3: aips-bus@30800000 {
@@ -1067,8 +1157,8 @@
                                compatible = "fsl,imx7d-sdma", "fsl,imx35-sdma";
                                reg = <0x30bd0000 0x10000>;
                                interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
-                               clocks = <&clks IMX7D_SDMA_CORE_CLK>,
-                                        <&clks IMX7D_AHB_CHANNEL_ROOT_CLK>;
+                               clocks = <&clks IMX7D_IPG_ROOT_CLK>,
+                                        <&clks IMX7D_SDMA_CORE_CLK>;
                                clock-names = "ipg", "ahb";
                                #dma-cells = <3>;
                                fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";

diff --git a/arch/arm/boot/dts/imx7ulp.dtsi b/arch/arm/boot/dts/imx7ulp.dtsi
index fca6e50..d6b7110 100644 (file)
--- a/arch/arm/boot/dts/imx7ulp.dtsi
+++ b/arch/arm/boot/dts/imx7ulp.dtsi
@@ -286,6 +286,12 @@
                        status = "disabled";
                };
 
+               memory-controller@40ab0000 {
+                       compatible = "fsl,imx7ulp-mmdc", "fsl,imx6q-mmdc";
+                       reg = <0x40ab0000 0x1000>;
+                       clocks = <&pcc3 IMX7ULP_CLK_MMDC>;
+               };
+
                iomuxc1: pinctrl@40ac0000 {
                        compatible = "fsl,imx7ulp-iomuxc1";
                        reg = <0x40ac0000 0x1000>;
@@ -359,5 +365,11 @@
                        compatible = "fsl,imx7ulp-sim", "syscon";
                        reg = <0x410a3000 0x1000>;
                };
+
+               ocotp: ocotp-ctrl@410a6000 {
+                       compatible = "fsl,imx7ulp-ocotp", "syscon";
+                       reg = <0x410a6000 0x4000>;
+                       clocks = <&scg1 IMX7ULP_CLK_DUMMY>;
+               };
        };
 };

diff --git a/arch/arm/boot/dts/lpc3250-ea3250.dts b/arch/arm/boot/dts/lpc3250-ea3250.dts
index f46a118..4adf4c9 100644 (file)
--- a/arch/arm/boot/dts/lpc3250-ea3250.dts
+++ b/arch/arm/boot/dts/lpc3250-ea3250.dts
@@ -201,6 +201,7 @@
 &mac {
        phy-mode = "rmii";
        use-iram;
+       status = "okay";
 };
 
 /* Here, choose exactly one from: ohci, usbd */

diff --git a/arch/arm/boot/dts/lpc3250-phy3250.dts b/arch/arm/boot/dts/lpc3250-phy3250.dts
index ebd1925..1b15f79 100644 (file)
--- a/arch/arm/boot/dts/lpc3250-phy3250.dts
+++ b/arch/arm/boot/dts/lpc3250-phy3250.dts
@@ -134,6 +134,7 @@
 &mac {
        phy-mode = "rmii";
        use-iram;
+       status = "okay";
 };
 
 /* Here, choose exactly one from: ohci, usbd */
@@ -201,8 +202,6 @@
 };
 
 &ssp0 {
-       #address-cells = <1>;
-       #size-cells = <0>;
        num-cs = <1>;
        cs-gpios = <&gpio 3 5 0>;
        status = "okay";

diff --git a/arch/arm/boot/dts/lpc32xx.dtsi b/arch/arm/boot/dts/lpc32xx.dtsi
index 20b38f4..7b7ec7b 100644 (file)
--- a/arch/arm/boot/dts/lpc32xx.dtsi
+++ b/arch/arm/boot/dts/lpc32xx.dtsi
@@ -1,14 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * NXP LPC32xx SoC
  *
+ * Copyright (C) 2015-2019 Vladimir Zapolskiy <vz@mleia.com>
  * Copyright 2012 Roland Stigge <stigge@antcom.de>
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
  */
 
 #include <dt-bindings/clock/lpc32xx-clock.h>
@@ -152,6 +147,7 @@
                        reg = <0x31060000 0x1000>;
                        interrupts = <29 IRQ_TYPE_LEVEL_HIGH>;
                        clocks = <&clk LPC32XX_CLK_MAC>;
+                       status = "disabled";
                };
 
                emc: memory-controller@31080000 {
@@ -185,6 +181,8 @@
                                interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&clk LPC32XX_CLK_SSP0>;
                                clock-names = "apb_pclk";
+                               #address-cells = <1>;
+                               #size-cells = <0>;
                                status = "disabled";
                        };
 
@@ -192,6 +190,8 @@
                                compatible = "nxp,lpc3220-spi";
                                reg = <0x20088000 0x1000>;
                                clocks = <&clk LPC32XX_CLK_SPI1>;
+                               #address-cells = <1>;
+                               #size-cells = <0>;
                                status = "disabled";
                        };
 
@@ -205,6 +205,8 @@
                                interrupts = <21 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&clk LPC32XX_CLK_SSP1>;
                                clock-names = "apb_pclk";
+                               #address-cells = <1>;
+                               #size-cells = <0>;
                                status = "disabled";
                        };
 
@@ -212,12 +214,15 @@
                                compatible = "nxp,lpc3220-spi";
                                reg = <0x20090000 0x1000>;
                                clocks = <&clk LPC32XX_CLK_SPI2>;
+                               #address-cells = <1>;
+                               #size-cells = <0>;
                                status = "disabled";
                        };
 
                        i2s0: i2s@20094000 {
                                compatible = "nxp,lpc3220-i2s";
                                reg = <0x20094000 0x1000>;
+                               status = "disabled";
                        };
 
                        sd: sd@20098000 {
@@ -232,7 +237,8 @@
 
                        i2s1: i2s@2009c000 {
                                compatible = "nxp,lpc3220-i2s";
-                               reg = <0x2009C000 0x1000>;
+                               reg = <0x2009c000 0x1000>;
+                               status = "disabled";
                        };
 
                        /* UART5 first since it is the default console, ttyS0 */
@@ -275,7 +281,7 @@
 
                        i2c1: i2c@400a0000 {
                                compatible = "nxp,pnx-i2c";
-                               reg = <0x400A0000 0x100>;
+                               reg = <0x400a0000 0x100>;
                                interrupt-parent = <&sic1>;
                                interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
                                #address-cells = <1>;
@@ -286,7 +292,7 @@
 
                        i2c2: i2c@400a8000 {
                                compatible = "nxp,pnx-i2c";
-                               reg = <0x400A8000 0x100>;
+                               reg = <0x400a8000 0x100>;
                                interrupt-parent = <&sic1>;
                                interrupts = <18 IRQ_TYPE_LEVEL_LOW>;
                                #address-cells = <1>;
@@ -297,7 +303,7 @@
 
                        mpwm: mpwm@400e8000 {
                                compatible = "nxp,lpc3220-motor-pwm";
-                               reg = <0x400E8000 0x78>;
+                               reg = <0x400e8000 0x78>;
                                status = "disabled";
                                #pwm-cells = <2>;
                        };
@@ -396,7 +402,7 @@
 
                        timer4: timer@4002c000 {
                                compatible = "nxp,lpc3220-timer";
-                               reg = <0x4002C000 0x1000>;
+                               reg = <0x4002c000 0x1000>;
                                interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
                                clocks = <&clk LPC32XX_CLK_TIMER4>;
                                clock-names = "timerclk";
@@ -414,7 +420,7 @@
 
                        watchdog: watchdog@4003c000 {
                                compatible = "nxp,pnx4008-wdt";
-                               reg = <0x4003C000 0x1000>;
+                               reg = <0x4003c000 0x1000>;
                                clocks = <&clk LPC32XX_CLK_WDOG>;
                        };
 
@@ -453,7 +459,7 @@
 
                        timer1: timer@4004c000 {
                                compatible = "nxp,lpc3220-timer";
-                               reg = <0x4004C000 0x1000>;
+                               reg = <0x4004c000 0x1000>;
                                interrupts = <17 IRQ_TYPE_LEVEL_LOW>;
                                clocks = <&clk LPC32XX_CLK_TIMER1>;
                                clock-names = "timerclk";
@@ -479,7 +485,7 @@
 
                        pwm1: pwm@4005c000 {
                                compatible = "nxp,lpc3220-pwm";
-                               reg = <0x4005C000 0x4>;
+                               reg = <0x4005c000 0x4>;
                                clocks = <&clk LPC32XX_CLK_PWM1>;
                                assigned-clocks = <&clk LPC32XX_CLK_PWM1>;
                                assigned-clock-parents = <&clk LPC32XX_CLK_PERIPH>;
@@ -488,7 +494,7 @@
 
                        pwm2: pwm@4005c004 {
                                compatible = "nxp,lpc3220-pwm";
-                               reg = <0x4005C004 0x4>;
+                               reg = <0x4005c004 0x4>;
                                clocks = <&clk LPC32XX_CLK_PWM2>;
                                assigned-clocks = <&clk LPC32XX_CLK_PWM2>;
                                assigned-clock-parents = <&clk LPC32XX_CLK_PERIPH>;

diff --git a/arch/arm/boot/dts/ls1021a-moxa-uc-8410a.dts b/arch/arm/boot/dts/ls1021a-moxa-uc-8410a.dts
index ba1ddd9..dcb1d9b 100644 (file)
--- a/arch/arm/boot/dts/ls1021a-moxa-uc-8410a.dts
+++ b/arch/arm/boot/dts/ls1021a-moxa-uc-8410a.dts
@@ -204,7 +204,6 @@
 };
 
 &qspi {
-       fsl,qspi-has-second-chip;
        status = "okay";
 
        flash: flash@0 {

diff --git a/arch/arm/boot/dts/ls1021a-qds.dts b/arch/arm/boot/dts/ls1021a-qds.dts
index ca60730..74a6760 100644 (file)
--- a/arch/arm/boot/dts/ls1021a-qds.dts
+++ b/arch/arm/boot/dts/ls1021a-qds.dts
@@ -146,6 +146,10 @@
        status = "okay";
 };
 
+&esdhc {
+       status = "okay";
+};
+
 &i2c0 {
        status = "okay";
 

diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi
index fe6eecf..464df42 100644 (file)
--- a/arch/arm/boot/dts/ls1021a.dtsi
+++ b/arch/arm/boot/dts/ls1021a.dtsi
@@ -186,7 +186,6 @@
                        interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
                        clock-names = "qspi_en", "qspi";
                        clocks = <&clockgen 4 1>, <&clockgen 4 1>;
-                       big-endian;
                        status = "disabled";
                };
 

diff --git a/arch/arm/boot/dts/meson.dtsi b/arch/arm/boot/dts/meson.dtsi
index 6f54a88..8841783 100644 (file)
--- a/arch/arm/boot/dts/meson.dtsi
+++ b/arch/arm/boot/dts/meson.dtsi
@@ -252,6 +252,15 @@
                                #size-cells = <0>;
                                status = "disabled";
                        };
+
+                       rtc: rtc@740 {
+                               compatible = "amlogic,meson6-rtc";
+                               reg = <0x740 0x14>;
+                               interrupts = <GIC_SPI 72 IRQ_TYPE_EDGE_RISING>;
+                               #address-cells = <1>;
+                               #size-cells = <1>;
+                               status = "disabled";
+                       };
                };
 
                usb0: usb@c9040000 {

diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi
index a978124..7ef4424 100644 (file)
--- a/arch/arm/boot/dts/meson8.dtsi
+++ b/arch/arm/boot/dts/meson8.dtsi
@@ -345,6 +345,11 @@
                status = "disabled";
        };
 
+       clock-measure@8758 {
+               compatible = "amlogic,meson8-clk-measure";
+               reg = <0x8758 0x1c>;
+       };
+
        pinctrl_cbus: pinctrl@9880 {
                compatible = "amlogic,meson8-cbus-pinctrl";
                reg = <0x9880 0x10>;
@@ -536,6 +541,11 @@
        compatible = "amlogic,meson8-pwm", "amlogic,meson8b-pwm";
 };
 
+&rtc {
+       compatible = "amlogic,meson8-rtc";
+       resets = <&reset RESET_RTC>;
+};
+
 &saradc {
        compatible = "amlogic,meson8-saradc", "amlogic,meson-saradc";
        clocks = <&clkc CLKID_XTAL>,

diff --git a/arch/arm/boot/dts/meson8b-ec100.dts b/arch/arm/boot/dts/meson8b-ec100.dts
index 3ca9638..9bf4249 100644 (file)
--- a/arch/arm/boot/dts/meson8b-ec100.dts
+++ b/arch/arm/boot/dts/meson8b-ec100.dts
@@ -88,6 +88,14 @@
                };
        };
 
+       rtc32k_xtal: rtc32k-xtal-clk {
+               /* X2 in the schematics */
+               compatible = "fixed-clock";
+               clock-frequency = <32768>;
+               clock-output-names = "RTC32K";
+               #clock-cells = <0>;
+       };
+
        usb_vbus: regulator-usb-vbus {
                /*
                 * Silergy SY6288CCAC-GP 2A Power Distribution Switch.
@@ -347,6 +355,12 @@
        clock-names = "clkin0";
 };
 
+&rtc {
+       status = "okay";
+       clocks = <&rtc32k_xtal>;
+       vdd-supply = <&vcc_rtc>;
+};
+
 /* exposed through the pin headers labeled "URDUG1" on the top of the PCB */
 &uart_AO {
        status = "okay";

diff --git a/arch/arm/boot/dts/meson8b-odroidc1.dts b/arch/arm/boot/dts/meson8b-odroidc1.dts
index 3b0e0f8..f3ad939 100644 (file)
--- a/arch/arm/boot/dts/meson8b-odroidc1.dts
+++ b/arch/arm/boot/dts/meson8b-odroidc1.dts
@@ -124,6 +124,14 @@
                io-channels = <&saradc 8>;
        };
 
+       rtc32k_xtal: rtc32k-xtal-clk {
+               /* X3 in the schematics */
+               compatible = "fixed-clock";
+               clock-frequency = <32768>;
+               clock-output-names = "RTC32K";
+               #clock-cells = <0>;
+       };
+
        vcc_1v8: regulator-vcc-1v8 {
                /*
                 * RICHTEK RT9179 configured for a fixed output voltage of
@@ -234,7 +242,59 @@
        };
 };
 
+&gpio {
+       gpio-line-names = /* Bank GPIOX */
+                         "J2 Header Pin 35", "J2 Header Pin 36",
+                         "J2 Header Pin 32", "J2 Header Pin 31",
+                         "J2 Header Pin 29", "J2 Header Pin 18",
+                         "J2 Header Pin 22", "J2 Header Pin 16",
+                         "J2 Header Pin 23", "J2 Header Pin 21",
+                         "J2 Header Pin 19", "J2 Header Pin 33",
+                         "J2 Header Pin 8", "J2 Header Pin 10",
+                         "J2 Header Pin 15", "J2 Header Pin 13",
+                         "J2 Header Pin 24", "J2 Header Pin 26",
+                         /* Bank GPIOY */
+                         "Revision (upper)", "Revision (lower)",
+                         "J2 Header Pin 7", "", "J2 Header Pin 12",
+                         "J2 Header Pin 11", "", "", "",
+                         "TFLASH_VDD_EN", "", "",
+                         /* Bank GPIODV */
+                         "VCCK_PWM (PWM_C)", "I2CA_SDA", "I2CA_SCL",
+                         "I2CB_SDA", "I2CB_SCL", "VDDEE_PWM (PWM_D)",
+                         "",
+                         /* Bank GPIOH */
+                         "HDMI_HPD", "HDMI_I2C_SDA", "HDMI_I2C_SCL",
+                         "ETH_PHY_INTR", "ETH_PHY_NRST", "ETH_TXD1",
+                         "ETH_TXD0", "ETH_TXD3", "ETH_TXD2",
+                         "ETH_RGMII_TX_CLK",
+                         /* Bank CARD */
+                         "SD_DATA1 (SDB_D1)", "SD_DATA0 (SDB_D0)",
+                         "SD_CLK",  "SD_CMD", "SD_DATA3 (SDB_D3)",
+                         "SD_DATA2 (SDB_D2)", "SD_CDN (SD_DET_N)",
+                         /* Bank BOOT */
+                         "SDC_D0 (EMMC)", "SDC_D1 (EMMC)",
+                         "SDC_D2 (EMMC)", "SDC_D3 (EMMC)",
+                         "SDC_D4 (EMMC)", "SDC_D5 (EMMC)",
+                         "SDC_D6 (EMMC)", "SDC_D7 (EMMC)",
+                         "SDC_CLK (EMMC)", "SDC_RSTn (EMMC)",
+                         "SDC_CMD (EMMC)", "BOOT_SEL", "", "", "",
+                         "", "", "", "",
+                         /* Bank DIF */
+                         "ETH_RXD1", "ETH_RXD0", "ETH_RX_DV",
+                         "RGMII_RX_CLK", "ETH_RXD3", "ETH_RXD2",
+                         "ETH_TXEN", "ETH_PHY_REF_CLK_25MOUT",
+                         "ETH_MDC", "ETH_MDIO";
+};
+
 &gpio_ao {
+       gpio-line-names = "UART TX", "UART RX", "",
+                         "TF_3V3N_1V8_EN", "USB_HUB_RST_N",
+                         "USB_OTG_PWREN", "J7 Header Pin 2",
+                         "IR_IN", "J7 Header Pin 4",
+                         "J7 Header Pin 6", "J7 Header Pin 5",
+                         "J7 Header Pin 7", "HDMI_CEC",
+                         "SYS_LED", "", "";
+
        /*
         * WARNING: The USB Hub on the Odroid-C1/C1+ needs a reset signal
         * to be turned high in order to be detected by the USB Controller.
@@ -293,6 +353,12 @@
        clock-names = "clkin0";
 };
 
+&rtc {
+       /* needs to be enabled manually when a battery is connected */
+       clocks = <&rtc32k_xtal>;
+       vdd-supply = <&vdd_rtc>;
+};
+
 &uart_AO {
        status = "okay";
        pinctrl-0 = <&uart_ao_a_pins>;

diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/meson8b.dtsi
index fe84a8c..800cd65 100644 (file)
--- a/arch/arm/boot/dts/meson8b.dtsi
+++ b/arch/arm/boot/dts/meson8b.dtsi
@@ -294,6 +294,11 @@
                status = "disabled";
        };
 
+       clock-measure@8758 {
+               compatible = "amlogic,meson8b-clk-measure";
+               reg = <0x8758 0x1c>;
+       };
+
        pinctrl_cbus: pinctrl@9880 {
                compatible = "amlogic,meson8b-cbus-pinctrl";
                reg = <0x9880 0x10>;
@@ -505,6 +510,11 @@
        compatible = "amlogic,meson8b-pwm";
 };
 
+&rtc {
+       compatible = "amlogic,meson8b-rtc";
+       resets = <&reset RESET_RTC>;
+};
+
 &saradc {
        compatible = "amlogic,meson8b-saradc", "amlogic,meson-saradc";
        clocks = <&clkc CLKID_XTAL>,

diff --git a/arch/arm/boot/dts/omap2420-n810.dts b/arch/arm/boot/dts/omap2420-n810.dts
index 96b9913..09c1dbc 100644 (file)
--- a/arch/arm/boot/dts/omap2420-n810.dts
+++ b/arch/arm/boot/dts/omap2420-n810.dts
@@ -48,7 +48,7 @@
                pinctrl-names = "default";
                pinctrl-0 = <&aic33_pins>;
 
-               gpio-reset = <&gpio4 22 GPIO_ACTIVE_LOW>; /* gpio118 */
+               reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; /* gpio118 */
 
                ai3x-gpio-func = <
                        10 /* AIC3X_GPIO1_FUNC_DIGITAL_MIC_MODCLK */

diff --git a/arch/arm/boot/dts/omap4-duovero.dtsi b/arch/arm/boot/dts/omap4-duovero.dtsi
index 5e81691..a1dacb8 100644 (file)
--- a/arch/arm/boot/dts/omap4-duovero.dtsi
+++ b/arch/arm/boot/dts/omap4-duovero.dtsi
@@ -7,6 +7,7 @@
  */
 
 #include "omap443x.dtsi"
+#include "omap4-mcpdm.dtsi"
 
 / {
        model = "Gumstix Duovero";
@@ -82,16 +83,6 @@
                >;
        };
 
-       mcpdm_pins: pinmux_mcpdm_pins {
-               pinctrl-single,pins = <
-                       OMAP4_IOPAD(0x106, PIN_INPUT_PULLDOWN | MUX_MODE0)      /* abe_pdm_ul_data.abe_pdm_ul_data */
-                       OMAP4_IOPAD(0x108, PIN_INPUT_PULLDOWN | MUX_MODE0)      /* abe_pdm_dl_data.abe_pdm_dl_data */
-                       OMAP4_IOPAD(0x10a, PIN_INPUT_PULLUP   | MUX_MODE0)      /* abe_pdm_frame.abe_pdm_frame */
-                       OMAP4_IOPAD(0x10c, PIN_INPUT_PULLDOWN | MUX_MODE0)      /* abe_pdm_lb_clk.abe_pdm_lb_clk */
-                       OMAP4_IOPAD(0x10e, PIN_INPUT_PULLDOWN | MUX_MODE0)      /* abe_clks.abe_clks */
-               >;
-       };
-
        mcbsp1_pins: pinmux_mcbsp1_pins {
                pinctrl-single,pins = <
                        OMAP4_IOPAD(0x0fe, PIN_INPUT | MUX_MODE0)               /* abe_mcbsp1_clkx.abe_mcbsp1_clkx */
@@ -210,16 +201,6 @@
        status = "okay";
 };
 
-&mcpdm {
-       pinctrl-names = "default";
-       pinctrl-0 = <&mcpdm_pins>;
-
-       clocks = <&twl6040>;
-       clock-names = "pdmclk";
-
-       status = "okay";
-};
-
 &mmc1 {
        pinctrl-names = "default";
        pinctrl-0 = <&mmc1_pins>;

diff --git a/arch/arm/boot/dts/omap4-l4-abe.dtsi b/arch/arm/boot/dts/omap4-l4-abe.dtsi
new file mode 100644 (file)
index 0000000..67072df
--- /dev/null
+++ b/arch/arm/boot/dts/omap4-l4-abe.dtsi
@@ -0,0 +1,501 @@
+&l4_abe {                                              /* 0x40100000 */
+       compatible = "ti,omap4-l4-abe", "simple-bus";
+       reg = <0x40100000 0x400>,
+             <0x40100400 0x400>;
+       reg-names = "la", "ap";
+       #address-cells = <1>;
+       #size-cells = <1>;
+       ranges = <0x00000000 0x40100000 0x100000>,      /* segment 0 */
+                <0x49000000 0x49000000 0x100000>;
+       segment@0 {                                     /* 0x40100000 */
+               compatible = "simple-bus";
+               #address-cells = <1>;
+               #size-cells = <1>;
+               ranges =
+                        /* CPU to L4 ABE mapping */
+                        <0x00000000 0x00000000 0x000400>,      /* ap 0 */
+                        <0x00000400 0x00000400 0x000400>,      /* ap 1 */
+                        <0x00022000 0x00022000 0x001000>,      /* ap 2 */
+                        <0x00023000 0x00023000 0x001000>,      /* ap 3 */
+                        <0x00024000 0x00024000 0x001000>,      /* ap 4 */
+                        <0x00025000 0x00025000 0x001000>,      /* ap 5 */
+                        <0x00026000 0x00026000 0x001000>,      /* ap 6 */
+                        <0x00027000 0x00027000 0x001000>,      /* ap 7 */
+                        <0x00028000 0x00028000 0x001000>,      /* ap 8 */
+                        <0x00029000 0x00029000 0x001000>,      /* ap 9 */
+                        <0x0002a000 0x0002a000 0x001000>,      /* ap 10 */
+                        <0x0002b000 0x0002b000 0x001000>,      /* ap 11 */
+                        <0x0002e000 0x0002e000 0x001000>,      /* ap 12 */
+                        <0x0002f000 0x0002f000 0x001000>,      /* ap 13 */
+                        <0x00030000 0x00030000 0x001000>,      /* ap 14 */
+                        <0x00031000 0x00031000 0x001000>,      /* ap 15 */
+                        <0x00032000 0x00032000 0x001000>,      /* ap 16 */
+                        <0x00033000 0x00033000 0x001000>,      /* ap 17 */
+                        <0x00038000 0x00038000 0x001000>,      /* ap 18 */
+                        <0x00039000 0x00039000 0x001000>,      /* ap 19 */
+                        <0x0003a000 0x0003a000 0x001000>,      /* ap 20 */
+                        <0x0003b000 0x0003b000 0x001000>,      /* ap 21 */
+                        <0x0003c000 0x0003c000 0x001000>,      /* ap 22 */
+                        <0x0003d000 0x0003d000 0x001000>,      /* ap 23 */
+                        <0x0003e000 0x0003e000 0x001000>,      /* ap 24 */
+                        <0x0003f000 0x0003f000 0x001000>,      /* ap 25 */
+                        <0x00080000 0x00080000 0x010000>,      /* ap 26 */
+                        <0x00080000 0x00080000 0x001000>,      /* ap 27 */
+                        <0x000a0000 0x000a0000 0x010000>,      /* ap 28 */
+                        <0x000a0000 0x000a0000 0x001000>,      /* ap 29 */
+                        <0x000c0000 0x000c0000 0x010000>,      /* ap 30 */
+                        <0x000c0000 0x000c0000 0x001000>,      /* ap 31 */
+                        <0x000f1000 0x000f1000 0x001000>,      /* ap 32 */
+                        <0x000f2000 0x000f2000 0x001000>,      /* ap 33 */
+
+                        /* L3 to L4 ABE mapping */
+                        <0x49000000 0x49000000 0x000400>,      /* ap 0 */
+                        <0x49000400 0x49000400 0x000400>,      /* ap 1 */
+                        <0x49022000 0x49022000 0x001000>,      /* ap 2 */
+                        <0x49023000 0x49023000 0x001000>,      /* ap 3 */
+                        <0x49024000 0x49024000 0x001000>,      /* ap 4 */
+                        <0x49025000 0x49025000 0x001000>,      /* ap 5 */
+                        <0x49026000 0x49026000 0x001000>,      /* ap 6 */
+                        <0x49027000 0x49027000 0x001000>,      /* ap 7 */
+                        <0x49028000 0x49028000 0x001000>,      /* ap 8 */
+                        <0x49029000 0x49029000 0x001000>,      /* ap 9 */
+                        <0x4902a000 0x4902a000 0x001000>,      /* ap 10 */
+                        <0x4902b000 0x4902b000 0x001000>,      /* ap 11 */
+                        <0x4902e000 0x4902e000 0x001000>,      /* ap 12 */
+                        <0x4902f000 0x4902f000 0x001000>,      /* ap 13 */
+                        <0x49030000 0x49030000 0x001000>,      /* ap 14 */
+                        <0x49031000 0x49031000 0x001000>,      /* ap 15 */
+                        <0x49032000 0x49032000 0x001000>,      /* ap 16 */
+                        <0x49033000 0x49033000 0x001000>,      /* ap 17 */
+                        <0x49038000 0x49038000 0x001000>,      /* ap 18 */
+                        <0x49039000 0x49039000 0x001000>,      /* ap 19 */
+                        <0x4903a000 0x4903a000 0x001000>,      /* ap 20 */
+                        <0x4903b000 0x4903b000 0x001000>,      /* ap 21 */
+                        <0x4903c000 0x4903c000 0x001000>,      /* ap 22 */
+                        <0x4903d000 0x4903d000 0x001000>,      /* ap 23 */
+                        <0x4903e000 0x4903e000 0x001000>,      /* ap 24 */
+                        <0x4903f000 0x4903f000 0x001000>,      /* ap 25 */
+                        <0x49080000 0x49080000 0x010000>,      /* ap 26 */
+                        <0x49080000 0x49080000 0x001000>,      /* ap 27 */
+                        <0x490a0000 0x490a0000 0x010000>,      /* ap 28 */
+                        <0x490a0000 0x490a0000 0x001000>,      /* ap 29 */
+                        <0x490c0000 0x490c0000 0x010000>,      /* ap 30 */
+                        <0x490c0000 0x490c0000 0x001000>,      /* ap 31 */
+                        <0x490f1000 0x490f1000 0x001000>,      /* ap 32 */
+                        <0x490f2000 0x490f2000 0x001000>;      /* ap 33 */
+
+               target-module@22000 {                   /* 0x40122000, ap 2 02.0 */
+                       compatible = "ti,sysc-omap2", "ti,sysc";
+                       ti,hwmods = "mcbsp1";
+                       reg = <0x2208c 0x4>;
+                       reg-names = "sysc";
+                       ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+                                        SYSC_OMAP2_ENAWAKEUP |
+                                        SYSC_OMAP2_SOFTRESET)>;
+                       ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+                                       <SYSC_IDLE_NO>,
+                                       <SYSC_IDLE_SMART>;
+                       /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
+                       clocks = <&abe_clkctrl OMAP4_MCBSP1_CLKCTRL 0>;
+                       clock-names = "fck";
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       ranges = <0x0 0x22000 0x1000>,
+                                <0x49022000 0x49022000 0x1000>;
+
+                       mcbsp1: mcbsp@0 {
+                               compatible = "ti,omap4-mcbsp";
+                               reg = <0x0 0xff>, /* MPU private access */
+                                     <0x49022000 0xff>; /* L3 Interconnect */
+                               reg-names = "mpu", "dma";
+                               interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+                               interrupt-names = "common";
+                               ti,buffer-size = <128>;
+                               dmas = <&sdma 33>,
+                                      <&sdma 34>;
+                               dma-names = "tx", "rx";
+                               status = "disabled";
+                       };
+               };
+
+               target-module@24000 {                   /* 0x40124000, ap 4 04.0 */
+                       compatible = "ti,sysc-omap2", "ti,sysc";
+                       ti,hwmods = "mcbsp2";
+                       reg = <0x2408c 0x4>;
+                       reg-names = "sysc";
+                       ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+                                        SYSC_OMAP2_ENAWAKEUP |
+                                        SYSC_OMAP2_SOFTRESET)>;
+                       ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+                                       <SYSC_IDLE_NO>,
+                                       <SYSC_IDLE_SMART>;
+                       /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
+                       clocks = <&abe_clkctrl OMAP4_MCBSP2_CLKCTRL 0>;
+                       clock-names = "fck";
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       ranges = <0x0 0x24000 0x1000>,
+                                <0x49024000 0x49024000 0x1000>;
+
+                       mcbsp2: mcbsp@0 {
+                               compatible = "ti,omap4-mcbsp";
+                               reg = <0x0 0xff>, /* MPU private access */
+                                     <0x49024000 0xff>; /* L3 Interconnect */
+                               reg-names = "mpu", "dma";
+                               interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
+                               interrupt-names = "common";
+                               ti,buffer-size = <128>;
+                               dmas = <&sdma 17>,
+                                      <&sdma 18>;
+                               dma-names = "tx", "rx";
+                               status = "disabled";
+                       };
+               };
+
+               target-module@26000 {                   /* 0x40126000, ap 6 06.0 */
+                       compatible = "ti,sysc-omap2", "ti,sysc";
+                       ti,hwmods = "mcbsp3";
+                       reg = <0x2608c 0x4>;
+                       reg-names = "sysc";
+                       ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+                                        SYSC_OMAP2_ENAWAKEUP |
+                                        SYSC_OMAP2_SOFTRESET)>;
+                       ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+                                       <SYSC_IDLE_NO>,
+                                       <SYSC_IDLE_SMART>;
+                       /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
+                       clocks = <&abe_clkctrl OMAP4_MCBSP3_CLKCTRL 0>;
+                       clock-names = "fck";
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       ranges = <0x0 0x26000 0x1000>,
+                                <0x49026000 0x49026000 0x1000>;
+
+                       mcbsp3: mcbsp@0 {
+                               compatible = "ti,omap4-mcbsp";
+                               reg = <0x0 0xff>, /* MPU private access */
+                                     <0x49026000 0xff>; /* L3 Interconnect */
+                               reg-names = "mpu", "dma";
+                               interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+                               interrupt-names = "common";
+                               ti,buffer-size = <128>;
+                               dmas = <&sdma 19>,
+                                      <&sdma 20>;
+                               dma-names = "tx", "rx";
+                               status = "disabled";
+                       };
+               };
+
+               target-module@28000 {                   /* 0x40128000, ap 8 08.0 */
+                       compatible = "ti,sysc-mcasp", "ti,sysc";
+                       ti,hwmods = "mcasp";
+                       reg = <0x28000 0x4>,
+                             <0x28004 0x4>;
+                       reg-names = "rev", "sysc";
+                       ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+                                       <SYSC_IDLE_NO>,
+                                       <SYSC_IDLE_SMART>,
+                                       <SYSC_IDLE_SMART_WKUP>;
+                       /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
+                       clocks = <&abe_clkctrl OMAP4_MCASP_CLKCTRL 0>;
+                       clock-names = "fck";
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       ranges = <0x0 0x28000 0x1000>,
+                                <0x49028000 0x49028000 0x1000>;
+
+                       /*
+                        * Child device unsupported by davinci-mcasp. At least
+                        * RX path is disabled for omap4, and only DIT mode
+                        * works with no I2S. See also old Android kernel
+                        * omap-mcasp driver for more information.
+                        */
+               };
+
+               target-module@2a000 {                   /* 0x4012a000, ap 10 0a.0 */
+                       compatible = "ti,sysc";
+                       status = "disabled";
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       ranges = <0x0 0x2a000 0x1000>,
+                                <0x4902a000 0x4902a000 0x1000>;
+               };
+
+               target-module@2e000 {                   /* 0x4012e000, ap 12 0c.0 */
+                       compatible = "ti,sysc-omap4", "ti,sysc";
+                       ti,hwmods = "dmic";
+                       reg = <0x2e000 0x4>,
+                             <0x2e010 0x4>;
+                       reg-names = "rev", "sysc";
+                       ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
+                                        SYSC_OMAP4_SOFTRESET)>;
+                       ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+                                       <SYSC_IDLE_NO>,
+                                       <SYSC_IDLE_SMART>,
+                                       <SYSC_IDLE_SMART_WKUP>;
+                       /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
+                       clocks = <&abe_clkctrl OMAP4_DMIC_CLKCTRL 0>;
+                       clock-names = "fck";
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       ranges = <0x0 0x2e000 0x1000>,
+                                <0x4902e000 0x4902e000 0x1000>;
+
+                       dmic: dmic@0 {
+                               compatible = "ti,omap4-dmic";
+                               reg = <0x0 0x7f>, /* MPU private access */
+                                     <0x4902e000 0x7f>; /* L3 Interconnect */
+                               reg-names = "mpu", "dma";
+                               interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
+                               dmas = <&sdma 67>;
+                               dma-names = "up_link";
+                               status = "disabled";
+                       };
+               };
+
+               target-module@30000 {                   /* 0x40130000, ap 14 0e.0 */
+                       compatible = "ti,sysc-omap2", "ti,sysc";
+                       ti,hwmods = "wd_timer3";
+                       reg = <0x30000 0x4>,
+                             <0x30010 0x4>,
+                             <0x30014 0x4>;
+                       reg-names = "rev", "sysc", "syss";
+                       ti,sysc-mask = <(SYSC_OMAP2_EMUFREE |
+                                        SYSC_OMAP2_SOFTRESET)>;
+                       ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+                                       <SYSC_IDLE_NO>,
+                                       <SYSC_IDLE_SMART>,
+                                       <SYSC_IDLE_SMART_WKUP>;
+                       ti,syss-mask = <1>;
+                       /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
+                       clocks = <&abe_clkctrl OMAP4_WD_TIMER3_CLKCTRL 0>;
+                       clock-names = "fck";
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       ranges = <0x0 0x30000 0x1000>,
+                                <0x49030000 0x49030000 0x1000>;
+
+                       wdt3: wdt@0 {
+                               compatible = "ti,omap4-wdt", "ti,omap3-wdt";
+                               reg = <0x0 0x80>;
+                               interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
+                       };
+               };
+
+               mcpdm_module: target-module@32000 {     /* 0x40132000, ap 16 10.0 */
+                       compatible = "ti,sysc-omap4", "ti,sysc";
+                       ti,hwmods = "mcpdm";
+                       reg = <0x32000 0x4>,
+                             <0x32010 0x4>;
+                       reg-names = "rev", "sysc";
+                       ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
+                                        SYSC_OMAP4_SOFTRESET)>;
+                       ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+                                       <SYSC_IDLE_NO>,
+                                       <SYSC_IDLE_SMART>,
+                                       <SYSC_IDLE_SMART_WKUP>;
+                       /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
+                       clocks = <&abe_clkctrl OMAP4_MCPDM_CLKCTRL 0>;
+                       clock-names = "fck";
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       ranges = <0x0 0x32000 0x1000>,
+                                <0x49032000 0x49032000 0x1000>;
+
+                       /* Must be only enabled for boards with pdmclk wired */
+                       status = "disabled";
+
+                       mcpdm: mcpdm@0 {
+                               compatible = "ti,omap4-mcpdm";
+                               reg = <0x0 0x7f>, /* MPU private access */
+                                     <0x49032000 0x7f>; /* L3 Interconnect */
+                               reg-names = "mpu", "dma";
+                               interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
+                               dmas = <&sdma 65>,
+                                      <&sdma 66>;
+                               dma-names = "up_link", "dn_link";
+                       };
+               };
+
+               target-module@38000 {                   /* 0x40138000, ap 18 12.0 */
+                       compatible = "ti,sysc-omap4-timer", "ti,sysc";
+                       ti,hwmods = "timer5";
+                       reg = <0x38000 0x4>,
+                             <0x38010 0x4>;
+                       reg-names = "rev", "sysc";
+                       ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
+                                        SYSC_OMAP4_SOFTRESET)>;
+                       ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+                                       <SYSC_IDLE_NO>,
+                                       <SYSC_IDLE_SMART>,
+                                       <SYSC_IDLE_SMART_WKUP>;
+                       /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
+                       clocks = <&abe_clkctrl OMAP4_TIMER5_CLKCTRL 0>;
+                       clock-names = "fck";
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       ranges = <0x0 0x38000 0x1000>,
+                                <0x49038000 0x49038000 0x1000>;
+
+                       timer5: timer@0 {
+                               compatible = "ti,omap4430-timer";
+                               reg = <0x00000000 0x80>,
+                                     <0x49038000 0x80>;
+                               clocks = <&abe_clkctrl OMAP4_TIMER5_CLKCTRL 24>;
+                               clock-names = "fck";
+                               interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
+                               ti,timer-dsp;
+                       };
+               };
+
+               target-module@3a000 {                   /* 0x4013a000, ap 20 14.0 */
+                       compatible = "ti,sysc-omap4-timer", "ti,sysc";
+                       ti,hwmods = "timer6";
+                       reg = <0x3a000 0x4>,
+                             <0x3a010 0x4>;
+                       reg-names = "rev", "sysc";
+                       ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
+                                        SYSC_OMAP4_SOFTRESET)>;
+                       ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+                                       <SYSC_IDLE_NO>,
+                                       <SYSC_IDLE_SMART>,
+                                       <SYSC_IDLE_SMART_WKUP>;
+                       /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
+                       clocks = <&abe_clkctrl OMAP4_TIMER6_CLKCTRL 0>;
+                       clock-names = "fck";
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       ranges = <0x0 0x3a000 0x1000>,
+                                <0x4903a000 0x4903a000 0x1000>;
+
+                       timer6: timer@0 {
+                               compatible = "ti,omap4430-timer";
+                               reg = <0x00000000 0x80>,
+                                     <0x4903a000 0x80>;
+                               clocks = <&abe_clkctrl OMAP4_TIMER6_CLKCTRL 24>;
+                               clock-names = "fck";
+                               interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
+                               ti,timer-dsp;
+                       };
+               };
+
+               target-module@3c000 {                   /* 0x4013c000, ap 22 16.0 */
+                       compatible = "ti,sysc-omap4-timer", "ti,sysc";
+                       ti,hwmods = "timer7";
+                       reg = <0x3c000 0x4>,
+                             <0x3c010 0x4>;
+                       reg-names = "rev", "sysc";
+                       ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
+                                        SYSC_OMAP4_SOFTRESET)>;
+                       ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+                                       <SYSC_IDLE_NO>,
+                                       <SYSC_IDLE_SMART>,
+                                       <SYSC_IDLE_SMART_WKUP>;
+                       /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
+                       clocks = <&abe_clkctrl OMAP4_TIMER7_CLKCTRL 0>;
+                       clock-names = "fck";
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       ranges = <0x0 0x3c000 0x1000>,
+                                <0x4903c000 0x4903c000 0x1000>;
+
+                       timer7: timer@0 {
+                               compatible = "ti,omap4430-timer";
+                               reg = <0x00000000 0x80>,
+                                     <0x4903c000 0x80>;
+                               clocks = <&abe_clkctrl OMAP4_TIMER7_CLKCTRL 24>;
+                               clock-names = "fck";
+                               interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
+                               ti,timer-dsp;
+                       };
+               };
+
+               target-module@3e000 {                   /* 0x4013e000, ap 24 18.0 */
+                       compatible = "ti,sysc-omap4-timer", "ti,sysc";
+                       ti,hwmods = "timer8";
+                       reg = <0x3e000 0x4>,
+                             <0x3e010 0x4>;
+                       reg-names = "rev", "sysc";
+                       ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
+                                        SYSC_OMAP4_SOFTRESET)>;
+                       ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+                                       <SYSC_IDLE_NO>,
+                                       <SYSC_IDLE_SMART>,
+                                       <SYSC_IDLE_SMART_WKUP>;
+                       /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
+                       clocks = <&abe_clkctrl OMAP4_TIMER8_CLKCTRL 0>;
+                       clock-names = "fck";
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       ranges = <0x0 0x3e000 0x1000>,
+                                <0x4903e000 0x4903e000 0x1000>;
+
+                       timer8: timer@0 {
+                               compatible = "ti,omap4430-timer";
+                               reg = <0x00000000 0x80>,
+                                     <0x4903e000 0x80>;
+                               clocks = <&abe_clkctrl OMAP4_TIMER8_CLKCTRL 24>;
+                               clock-names = "fck";
+                               interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
+                               ti,timer-pwm;
+                               ti,timer-dsp;
+                       };
+               };
+
+               target-module@80000 {                   /* 0x40180000, ap 26 1a.0 */
+                       compatible = "ti,sysc";
+                       status = "disabled";
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       ranges = <0x0 0x80000 0x10000>,
+                                <0x49080000 0x49080000 0x10000>;
+               };
+
+               target-module@a0000 {                   /* 0x401a0000, ap 28 1c.0 */
+                       compatible = "ti,sysc";
+                       status = "disabled";
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       ranges = <0x0 0xa0000 0x10000>,
+                                <0x490a0000 0x490a0000 0x10000>;
+               };
+
+               target-module@c0000 {                   /* 0x401c0000, ap 30 1e.0 */
+                       compatible = "ti,sysc";
+                       status = "disabled";
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       ranges = <0x0 0xc0000 0x10000>,
+                                <0x490c0000 0x490c0000 0x10000>;
+               };
+
+               target-module@f1000 {                   /* 0x401f1000, ap 32 20.0 */
+                       compatible = "ti,sysc-omap4", "ti,sysc";
+                       ti,hwmods = "aess";
+                       reg = <0xf1000 0x4>,
+                             <0xf1010 0x4>;
+                       reg-names = "rev", "sysc";
+                       ti,sysc-midle = <SYSC_IDLE_FORCE>,
+                                       <SYSC_IDLE_NO>,
+                                       <SYSC_IDLE_SMART>,
+                                       <SYSC_IDLE_SMART_WKUP>;
+                       ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+                                       <SYSC_IDLE_NO>,
+                                       <SYSC_IDLE_SMART>;
+                       /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
+                       clocks = <&abe_clkctrl OMAP4_AESS_CLKCTRL 0>;
+                       clock-names = "fck";
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       ranges = <0x0 0xf1000 0x1000>,
+                                <0x490f1000 0x490f1000 0x1000>;
+
+                       /*
+                        * No child device binding or driver in mainline.
+                        * See Android tree and related upstreaming efforts
+                        * for the old driver.
+                        */
+               };
+       };
+};
+

diff --git a/arch/arm/boot/dts/omap4-mcpdm.dtsi b/arch/arm/boot/dts/omap4-mcpdm.dtsi
new file mode 100644 (file)
index 0000000..915a9b3
--- /dev/null
+++ b/arch/arm/boot/dts/omap4-mcpdm.dtsi
@@ -0,0 +1,44 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Common omap4 mcpdm configuration
+ *
+ * Only include this file if your board has pdmclk wired from the
+ * pmic to ABE as mcpdm uses an external clock for the module.
+ */
+
+&omap4_pmx_core {
+       mcpdm_pins: pinmux_mcpdm_pins {
+               pinctrl-single,pins = <
+               /* 0x4a100106 abe_pdm_ul_data.abe_pdm_ul_data ag25 */
+               OMAP4_IOPAD(0x106, PIN_INPUT_PULLDOWN | MUX_MODE0)
+
+               /* 0x4a100108 abe_pdm_dl_data.abe_pdm_dl_data af25 */
+               OMAP4_IOPAD(0x108, PIN_INPUT_PULLDOWN | MUX_MODE0)
+
+               /* 0x4a10010a abe_pdm_frame.abe_pdm_frame ae25 */
+               OMAP4_IOPAD(0x10a, PIN_INPUT_PULLUP   | MUX_MODE0)
+
+               /* 0x4a10010c abe_pdm_lb_clk.abe_pdm_lb_clk af26 */
+               OMAP4_IOPAD(0x10c, PIN_INPUT_PULLDOWN | MUX_MODE0)
+
+               /* 0x4a10010e abe_clks.abe_clks ah26 */
+               OMAP4_IOPAD(0x10e, PIN_INPUT_PULLDOWN | MUX_MODE0)
+               >;
+       };
+};
+
+&mcpdm_module {
+       /*
+        * McPDM pads must be muxed at the interconnect target module
+        * level as the module on the SoC needs external clock from
+        * the PMIC
+        */
+       pinctrl-names = "default";
+       pinctrl-0 = <&mcpdm_pins>;
+       status = "okay";
+};
+
+&mcpdm {
+       clocks = <&twl6040>;
+       clock-names = "pdmclk";
+};

diff --git a/arch/arm/boot/dts/omap4-panda-common.dtsi b/arch/arm/boot/dts/omap4-panda-common.dtsi
index 926f018..68e1894 100644 (file)
--- a/arch/arm/boot/dts/omap4-panda-common.dtsi
+++ b/arch/arm/boot/dts/omap4-panda-common.dtsi
@@ -7,6 +7,7 @@
  */
 #include <dt-bindings/input/input.h>
 #include "elpida_ecb240abacn.dtsi"
+#include "omap4-mcpdm.dtsi"
 
 / {
        memory@80000000 {
@@ -226,16 +227,6 @@
                >;
        };
 
-       mcpdm_pins: pinmux_mcpdm_pins {
-               pinctrl-single,pins = <
-                       OMAP4_IOPAD(0x106, PIN_INPUT_PULLDOWN | MUX_MODE0)      /* abe_pdm_ul_data.abe_pdm_ul_data */
-                       OMAP4_IOPAD(0x108, PIN_INPUT_PULLDOWN | MUX_MODE0)      /* abe_pdm_dl_data.abe_pdm_dl_data */
-                       OMAP4_IOPAD(0x10a, PIN_INPUT_PULLUP   | MUX_MODE0)      /* abe_pdm_frame.abe_pdm_frame */
-                       OMAP4_IOPAD(0x10c, PIN_INPUT_PULLDOWN | MUX_MODE0)      /* abe_pdm_lb_clk.abe_pdm_lb_clk */
-                       OMAP4_IOPAD(0x10e, PIN_INPUT_PULLDOWN | MUX_MODE0)      /* abe_clks.abe_clks */
-               >;
-       };
-
        mcbsp1_pins: pinmux_mcbsp1_pins {
                pinctrl-single,pins = <
                        OMAP4_IOPAD(0x0fe, PIN_INPUT | MUX_MODE0)               /* abe_mcbsp1_clkx.abe_mcbsp1_clkx */
@@ -509,16 +500,6 @@
        status = "okay";
 };
 
-&mcpdm {
-       pinctrl-names = "default";
-       pinctrl-0 = <&mcpdm_pins>;
-
-       clocks = <&twl6040>;
-       clock-names = "pdmclk";
-
-       status = "okay";
-};
-
 &twl_usb_comparator {
        usb-supply = <&vusb>;
 };

diff --git a/arch/arm/boot/dts/omap4-sdp.dts b/arch/arm/boot/dts/omap4-sdp.dts
index c88817b..fb51a4b 100644 (file)
--- a/arch/arm/boot/dts/omap4-sdp.dts
+++ b/arch/arm/boot/dts/omap4-sdp.dts
@@ -9,6 +9,7 @@
 
 #include "omap443x.dtsi"
 #include "elpida_ecb240abacn.dtsi"
+#include "omap4-mcpdm.dtsi"
 
 / {
        model = "TI OMAP4 SDP board";
@@ -246,16 +247,6 @@
                >;
        };
 
-       mcpdm_pins: pinmux_mcpdm_pins {
-               pinctrl-single,pins = <
-                       OMAP4_IOPAD(0x106, PIN_INPUT_PULLDOWN | MUX_MODE0)      /* abe_pdm_ul_data.abe_pdm_ul_data */
-                       OMAP4_IOPAD(0x108, PIN_INPUT_PULLDOWN | MUX_MODE0)      /* abe_pdm_dl_data.abe_pdm_dl_data */
-                       OMAP4_IOPAD(0x10a, PIN_INPUT_PULLUP | MUX_MODE0)        /* abe_pdm_frame.abe_pdm_frame */
-                       OMAP4_IOPAD(0x10c, PIN_INPUT_PULLDOWN | MUX_MODE0)      /* abe_pdm_lb_clk.abe_pdm_lb_clk */
-                       OMAP4_IOPAD(0x10e, PIN_INPUT_PULLDOWN | MUX_MODE0)      /* abe_clks.abe_clks */
-               >;
-       };
-
        dmic_pins: pinmux_dmic_pins {
                pinctrl-single,pins = <
                        OMAP4_IOPAD(0x110, PIN_OUTPUT | MUX_MODE0)              /* abe_dmic_clk1.abe_dmic_clk1 */
@@ -649,16 +640,6 @@
        status = "okay";
 };
 
-&mcpdm {
-       pinctrl-names = "default";
-       pinctrl-0 = <&mcpdm_pins>;
-
-       clocks = <&twl6040>;
-       clock-names = "pdmclk";
-
-       status = "okay";
-};
-
 &twl_usb_comparator {
        usb-supply = <&vusb>;
 };

diff --git a/arch/arm/boot/dts/omap4-var-som-om44.dtsi b/arch/arm/boot/dts/omap4-var-som-om44.dtsi
index 10fce28..9562d37 100644 (file)
--- a/arch/arm/boot/dts/omap4-var-som-om44.dtsi
+++ b/arch/arm/boot/dts/omap4-var-som-om44.dtsi
@@ -7,6 +7,7 @@
  * published by the Free Software Foundation.
  */
 #include "omap4460.dtsi"
+#include "omap4-mcpdm.dtsi"
 
 / {
        model = "Variscite VAR-SOM-OM44";
@@ -74,16 +75,6 @@
                >;
        };
 
-       mcpdm_pins: pinmux_mcpdm_pins {
-               pinctrl-single,pins = <
-                       OMAP4_IOPAD(0x106, PIN_INPUT_PULLDOWN | MUX_MODE0)      /* abe_pdm_ul_data.abe_pdm_ul_data */
-                       OMAP4_IOPAD(0x108, PIN_INPUT_PULLDOWN | MUX_MODE0)      /* abe_pdm_dl_data.abe_pdm_dl_data */
-                       OMAP4_IOPAD(0x10a, PIN_INPUT_PULLUP | MUX_MODE0)        /* abe_pdm_frame.abe_pdm_frame */
-                       OMAP4_IOPAD(0x10c, PIN_INPUT_PULLDOWN | MUX_MODE0)      /* abe_pdm_lb_clk.abe_pdm_lb_clk */
-                       OMAP4_IOPAD(0x10e, PIN_INPUT_PULLDOWN | MUX_MODE0)      /* abe_clks.abe_clks */
-               >;
-       };
-
        tsc2004_pins: pinmux_tsc2004_pins {
                pinctrl-single,pins = <
                        OMAP4_IOPAD(0x090, PIN_INPUT | MUX_MODE3)               /* gpmc_ncs4.gpio_101 (irq) */
@@ -251,16 +242,6 @@
        status = "disabled";
 };
 
-&mcpdm {
-       pinctrl-names = "default";
-       pinctrl-0 = <&mcpdm_pins>;
-
-       clocks = <&twl6040>;
-       clock-names = "pdmclk";
-
-       status = "okay";
-};
-
 &gpmc {
        status = "disabled";
 };

diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
index 1a96d43..442a737 100644 (file)
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -148,6 +148,9 @@
                l4_per: interconnect@48000000 {
                };
 
+               l4_abe: interconnect@40100000 {
+               };
+
                ocmcram: ocmcram@40304000 {
                        compatible = "mmio-sram";
                        reg = <0x40304000 0xa000>; /* 40k */
@@ -214,130 +217,6 @@
                        #iommu-cells = <0>;
                        ti,iommu-bus-err-back;
                };
-               target-module@40130000 {
-                       compatible = "ti,sysc-omap2", "ti,sysc";
-                       ti,hwmods = "wd_timer3";
-                       reg = <0x40130000 0x4>,
-                             <0x40130010 0x4>,
-                             <0x40130014 0x4>;
-                       reg-names = "rev", "sysc", "syss";
-                       ti,sysc-mask = <(SYSC_OMAP2_EMUFREE |
-                                        SYSC_OMAP2_SOFTRESET)>;
-                       ti,sysc-sidle = <SYSC_IDLE_FORCE>,
-                                       <SYSC_IDLE_NO>,
-                                       <SYSC_IDLE_SMART>,
-                                       <SYSC_IDLE_SMART_WKUP>;
-                       ti,syss-mask = <1>;
-                       /* Domains (V, P, C): abe, abe_pwrdm, abe_clkdm */
-                       clocks = <&abe_clkctrl OMAP4_WD_TIMER3_CLKCTRL 0>;
-                       clock-names = "fck";
-                       #address-cells = <1>;
-                       #size-cells = <1>;
-                       ranges = <0x00000000 0x40130000 0x1000>, /* MPU private access */
-                                <0x49030000 0x49030000 0x0080>; /* L3 Interconnect */
-
-                       wdt3: wdt@0 {
-                               compatible = "ti,omap4-wdt", "ti,omap3-wdt";
-                               reg = <0x0 0x80>;
-                               interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
-                       };
-               };
-
-               mcpdm: mcpdm@40132000 {
-                       compatible = "ti,omap4-mcpdm";
-                       reg = <0x40132000 0x7f>, /* MPU private access */
-                             <0x49032000 0x7f>; /* L3 Interconnect */
-                       reg-names = "mpu", "dma";
-                       interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
-                       ti,hwmods = "mcpdm";
-                       dmas = <&sdma 65>,
-                              <&sdma 66>;
-                       dma-names = "up_link", "dn_link";
-                       status = "disabled";
-               };
-
-               dmic: dmic@4012e000 {
-                       compatible = "ti,omap4-dmic";
-                       reg = <0x4012e000 0x7f>, /* MPU private access */
-                             <0x4902e000 0x7f>; /* L3 Interconnect */
-                       reg-names = "mpu", "dma";
-                       interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
-                       ti,hwmods = "dmic";
-                       dmas = <&sdma 67>;
-                       dma-names = "up_link";
-                       status = "disabled";
-               };
-
-               mcbsp1: mcbsp@40122000 {
-                       compatible = "ti,omap4-mcbsp";
-                       reg = <0x40122000 0xff>, /* MPU private access */
-                             <0x49022000 0xff>; /* L3 Interconnect */
-                       reg-names = "mpu", "dma";
-                       interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
-                       interrupt-names = "common";
-                       ti,buffer-size = <128>;
-                       ti,hwmods = "mcbsp1";
-                       dmas = <&sdma 33>,
-                              <&sdma 34>;
-                       dma-names = "tx", "rx";
-                       status = "disabled";
-               };
-
-               mcbsp2: mcbsp@40124000 {
-                       compatible = "ti,omap4-mcbsp";
-                       reg = <0x40124000 0xff>, /* MPU private access */
-                             <0x49024000 0xff>; /* L3 Interconnect */
-                       reg-names = "mpu", "dma";
-                       interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
-                       interrupt-names = "common";
-                       ti,buffer-size = <128>;
-                       ti,hwmods = "mcbsp2";
-                       dmas = <&sdma 17>,
-                              <&sdma 18>;
-                       dma-names = "tx", "rx";
-                       status = "disabled";
-               };
-
-               mcbsp3: mcbsp@40126000 {
-                       compatible = "ti,omap4-mcbsp";
-                       reg = <0x40126000 0xff>, /* MPU private access */
-                             <0x49026000 0xff>; /* L3 Interconnect */
-                       reg-names = "mpu", "dma";
-                       interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
-                       interrupt-names = "common";
-                       ti,buffer-size = <128>;
-                       ti,hwmods = "mcbsp3";
-                       dmas = <&sdma 19>,
-                              <&sdma 20>;
-                       dma-names = "tx", "rx";
-                       status = "disabled";
-               };
-
-               target-module@40128000 {
-                       compatible = "ti,sysc-mcasp", "ti,sysc";
-                       ti,hwmods = "mcasp";
-                       reg = <0x40128000 0x4>,
-                             <0x40128004 0x4>;
-                       reg-names = "rev", "sysc";
-                       ti,sysc-sidle = <SYSC_IDLE_FORCE>,
-                                       <SYSC_IDLE_NO>,
-                                       <SYSC_IDLE_SMART>,
-                                       <SYSC_IDLE_SMART_WKUP>;
-                       clocks = <&abe_clkctrl OMAP4_MCASP_CLKCTRL 0>;
-                       clock-names = "fck";
-                       #address-cells = <1>;
-                       #size-cells = <1>;
-                       ranges = <0x00000000 0x40128000 0x1000>, /* MPU */
-                                <0x49028000 0x49028000 0x1000>; /* L3 */
-
-                       /*
-                        * Child device unsupported by davinci-mcasp. At least
-                        * RX path is disabled for omap4, and only DIT mode
-                        * works with no I2S. See also old Android kernel
-                        * omap-mcasp driver for more information.
-                        */
-               };
-
                target-module@4012c000 {
                        compatible = "ti,sysc-omap4", "ti,sysc";
                        ti,hwmods = "slimbus1";
@@ -359,33 +238,6 @@
                        /* No child device binding or driver in mainline */
                };
 
-               target-module@401f1000 {
-                       compatible = "ti,sysc-omap4", "ti,sysc";
-                       ti,hwmods = "aess";
-                       reg = <0x401f1000 0x4>,
-                             <0x401f1010 0x4>;
-                       reg-names = "rev", "sysc";
-                       ti,sysc-midle = <SYSC_IDLE_FORCE>,
-                                       <SYSC_IDLE_NO>,
-                                       <SYSC_IDLE_SMART>,
-                                       <SYSC_IDLE_SMART_WKUP>;
-                       ti,sysc-sidle = <SYSC_IDLE_FORCE>,
-                                       <SYSC_IDLE_NO>,
-                                       <SYSC_IDLE_SMART>;
-                       clocks = <&abe_clkctrl OMAP4_AESS_CLKCTRL 0>;
-                       clock-names = "fck";
-                       #address-cells = <1>;
-                       #size-cells = <1>;
-                       ranges = <0x00000000 0x401f1000 0x1000>, /* MPU */
-                                <0x490f1000 0x490f1000 0x1000>; /* L3 */
-
-                       /*
-                        * No child device binding or driver in mainline.
-                        * See Android tree and related upstreaming efforts
-                        * for the old driver.
-                        */
-               };
-
                dmm@4e000000 {
                        compatible = "ti,omap4-dmm";
                        reg = <0x4e000000 0x800>;
@@ -417,43 +269,6 @@
                        hw-caps-temp-alert;
                };
 
-               timer5: timer@40138000 {
-                       compatible = "ti,omap4430-timer";
-                       reg = <0x40138000 0x80>,
-                             <0x49038000 0x80>;
-                       interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
-                       ti,hwmods = "timer5";
-                       ti,timer-dsp;
-               };
-
-               timer6: timer@4013a000 {
-                       compatible = "ti,omap4430-timer";
-                       reg = <0x4013a000 0x80>,
-                             <0x4903a000 0x80>;
-                       interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
-                       ti,hwmods = "timer6";
-                       ti,timer-dsp;
-               };
-
-               timer7: timer@4013c000 {
-                       compatible = "ti,omap4430-timer";
-                       reg = <0x4013c000 0x80>,
-                             <0x4903c000 0x80>;
-                       interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
-                       ti,hwmods = "timer7";
-                       ti,timer-dsp;
-               };
-
-               timer8: timer@4013e000 {
-                       compatible = "ti,omap4430-timer";
-                       reg = <0x4013e000 0x80>,
-                             <0x4903e000 0x80>;
-                       interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
-                       ti,hwmods = "timer8";
-                       ti,timer-pwm;
-                       ti,timer-dsp;
-               };
-
                aes1: aes@4b501000 {
                        compatible = "ti,omap4-aes";
                        ti,hwmods = "aes1";
@@ -629,4 +444,5 @@
 };
 
 #include "omap4-l4.dtsi"
+#include "omap4-l4-abe.dtsi"
 #include "omap44xx-clocks.dtsi"

diff --git a/arch/arm/boot/dts/omap5-board-common.dtsi b/arch/arm/boot/dts/omap5-board-common.dtsi
index 61a06f6..2dc3e19 100644 (file)
--- a/arch/arm/boot/dts/omap5-board-common.dtsi
+++ b/arch/arm/boot/dts/omap5-board-common.dtsi
@@ -667,14 +667,16 @@
        };
 };
 
-&mcpdm {
+&mcpdm_module {
+       /* Module on the SoC needs external clock from the PMIC */
        pinctrl-names = "default";
        pinctrl-0 = <&mcpdm_pins>;
+       status = "okay";
+};
 
+&mcpdm {
        clocks = <&twl6040>;
        clock-names = "pdmclk";
-
-       status = "okay";
 };
 
 &mcbsp1 {

diff --git a/arch/arm/boot/dts/omap5-l4-abe.dtsi b/arch/arm/boot/dts/omap5-l4-abe.dtsi
new file mode 100644 (file)
index 0000000..dc9d053
--- /dev/null
+++ b/arch/arm/boot/dts/omap5-l4-abe.dtsi
@@ -0,0 +1,447 @@
+&l4_abe {                                              /* 0x40100000 */
+       compatible = "ti,omap5-l4-abe", "simple-bus";
+       reg = <0x40100000 0x400>,
+             <0x40100400 0x400>;
+       reg-names = "la", "ap";
+       #address-cells = <1>;
+       #size-cells = <1>;
+       ranges = <0x00000000 0x40100000 0x100000>,      /* segment 0 */
+                <0x49000000 0x49000000 0x100000>;
+       segment@0 {                                     /* 0x40100000 */
+               compatible = "simple-bus";
+               #address-cells = <1>;
+               #size-cells = <1>;
+               ranges =
+                        /* CPU to L4 ABE mapping */
+                        <0x00000000 0x00000000 0x000400>,      /* ap 0 */
+                        <0x00000400 0x00000400 0x000400>,      /* ap 1 */
+                        <0x00022000 0x00022000 0x001000>,      /* ap 2 */
+                        <0x00023000 0x00023000 0x001000>,      /* ap 3 */
+                        <0x00024000 0x00024000 0x001000>,      /* ap 4 */
+                        <0x00025000 0x00025000 0x001000>,      /* ap 5 */
+                        <0x00026000 0x00026000 0x001000>,      /* ap 6 */
+                        <0x00027000 0x00027000 0x001000>,      /* ap 7 */
+                        <0x00028000 0x00028000 0x001000>,      /* ap 8 */
+                        <0x00029000 0x00029000 0x001000>,      /* ap 9 */
+                        <0x0002a000 0x0002a000 0x001000>,      /* ap 10 */
+                        <0x0002b000 0x0002b000 0x001000>,      /* ap 11 */
+                        <0x0002e000 0x0002e000 0x001000>,      /* ap 12 */
+                        <0x0002f000 0x0002f000 0x001000>,      /* ap 13 */
+                        <0x00030000 0x00030000 0x001000>,      /* ap 14 */
+                        <0x00031000 0x00031000 0x001000>,      /* ap 15 */
+                        <0x00032000 0x00032000 0x001000>,      /* ap 16 */
+                        <0x00033000 0x00033000 0x001000>,      /* ap 17 */
+                        <0x00038000 0x00038000 0x001000>,      /* ap 18 */
+                        <0x00039000 0x00039000 0x001000>,      /* ap 19 */
+                        <0x0003a000 0x0003a000 0x001000>,      /* ap 20 */
+                        <0x0003b000 0x0003b000 0x001000>,      /* ap 21 */
+                        <0x0003c000 0x0003c000 0x001000>,      /* ap 22 */
+                        <0x0003d000 0x0003d000 0x001000>,      /* ap 23 */
+                        <0x0003e000 0x0003e000 0x001000>,      /* ap 24 */
+                        <0x0003f000 0x0003f000 0x001000>,      /* ap 25 */
+                        <0x00080000 0x00080000 0x010000>,      /* ap 26 */
+                        <0x00080000 0x00080000 0x001000>,      /* ap 27 */
+                        <0x000a0000 0x000a0000 0x010000>,      /* ap 28 */
+                        <0x000a0000 0x000a0000 0x001000>,      /* ap 29 */
+                        <0x000c0000 0x000c0000 0x010000>,      /* ap 30 */
+                        <0x000c0000 0x000c0000 0x001000>,      /* ap 31 */
+                        <0x000f1000 0x000f1000 0x001000>,      /* ap 32 */
+                        <0x000f2000 0x000f2000 0x001000>,      /* ap 33 */
+
+                        /* L3 to L4 ABE mapping */
+                        <0x49000000 0x49000000 0x000400>,      /* ap 0 */
+                        <0x49000400 0x49000400 0x000400>,      /* ap 1 */
+                        <0x49022000 0x49022000 0x001000>,      /* ap 2 */
+                        <0x49023000 0x49023000 0x001000>,      /* ap 3 */
+                        <0x49024000 0x49024000 0x001000>,      /* ap 4 */
+                        <0x49025000 0x49025000 0x001000>,      /* ap 5 */
+                        <0x49026000 0x49026000 0x001000>,      /* ap 6 */
+                        <0x49027000 0x49027000 0x001000>,      /* ap 7 */
+                        <0x49028000 0x49028000 0x001000>,      /* ap 8 */
+                        <0x49029000 0x49029000 0x001000>,      /* ap 9 */
+                        <0x4902a000 0x4902a000 0x001000>,      /* ap 10 */
+                        <0x4902b000 0x4902b000 0x001000>,      /* ap 11 */
+                        <0x4902e000 0x4902e000 0x001000>,      /* ap 12 */
+                        <0x4902f000 0x4902f000 0x001000>,      /* ap 13 */
+                        <0x49030000 0x49030000 0x001000>,      /* ap 14 */
+                        <0x49031000 0x49031000 0x001000>,      /* ap 15 */
+                        <0x49032000 0x49032000 0x001000>,      /* ap 16 */
+                        <0x49033000 0x49033000 0x001000>,      /* ap 17 */
+                        <0x49038000 0x49038000 0x001000>,      /* ap 18 */
+                        <0x49039000 0x49039000 0x001000>,      /* ap 19 */
+                        <0x4903a000 0x4903a000 0x001000>,      /* ap 20 */
+                        <0x4903b000 0x4903b000 0x001000>,      /* ap 21 */
+                        <0x4903c000 0x4903c000 0x001000>,      /* ap 22 */
+                        <0x4903d000 0x4903d000 0x001000>,      /* ap 23 */
+                        <0x4903e000 0x4903e000 0x001000>,      /* ap 24 */
+                        <0x4903f000 0x4903f000 0x001000>,      /* ap 25 */
+                        <0x49080000 0x49080000 0x010000>,      /* ap 26 */
+                        <0x49080000 0x49080000 0x001000>,      /* ap 27 */
+                        <0x490a0000 0x490a0000 0x010000>,      /* ap 28 */
+                        <0x490a0000 0x490a0000 0x001000>,      /* ap 29 */
+                        <0x490c0000 0x490c0000 0x010000>,      /* ap 30 */
+                        <0x490c0000 0x490c0000 0x001000>,      /* ap 31 */
+                        <0x490f1000 0x490f1000 0x001000>,      /* ap 32 */
+                        <0x490f2000 0x490f2000 0x001000>;      /* ap 33 */
+
+               target-module@22000 {                   /* 0x40122000, ap 2 02.0 */
+                       compatible = "ti,sysc-omap2", "ti,sysc";
+                       ti,hwmods = "mcbsp1";
+                       reg = <0x2208c 0x4>;
+                       reg-names = "sysc";
+                       ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+                                        SYSC_OMAP2_ENAWAKEUP |
+                                        SYSC_OMAP2_SOFTRESET)>;
+                       ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+                                       <SYSC_IDLE_NO>,
+                                       <SYSC_IDLE_SMART>;
+                       /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */
+                       clocks = <&abe_clkctrl OMAP5_MCBSP1_CLKCTRL 0>;
+                       clock-names = "fck";
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       ranges = <0x0 0x22000 0x1000>,
+                                <0x49022000 0x49022000 0x1000>;
+
+                       mcbsp1: mcbsp@0 {
+                               compatible = "ti,omap4-mcbsp";
+                               reg = <0x0 0xff>, /* MPU private access */
+                                     <0x49022000 0xff>; /* L3 Interconnect */
+                               reg-names = "mpu", "dma";
+                               interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+                               interrupt-names = "common";
+                               ti,buffer-size = <128>;
+                               dmas = <&sdma 33>,
+                                      <&sdma 34>;
+                               dma-names = "tx", "rx";
+                               status = "disabled";
+                       };
+               };
+
+               target-module@24000 {                   /* 0x40124000, ap 4 04.0 */
+                       compatible = "ti,sysc-omap2", "ti,sysc";
+                       ti,hwmods = "mcbsp2";
+                       reg = <0x2408c 0x4>;
+                       reg-names = "sysc";
+                       ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+                                        SYSC_OMAP2_ENAWAKEUP |
+                                        SYSC_OMAP2_SOFTRESET)>;
+                       ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+                                       <SYSC_IDLE_NO>,
+                                       <SYSC_IDLE_SMART>;
+                       /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */
+                       clocks = <&abe_clkctrl OMAP5_MCBSP2_CLKCTRL 0>;
+                       clock-names = "fck";
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       ranges = <0x0 0x24000 0x1000>,
+                                <0x49024000 0x49024000 0x1000>;
+
+                       mcbsp2: mcbsp@0 {
+                               compatible = "ti,omap4-mcbsp";
+                               reg = <0x0 0xff>, /* MPU private access */
+                                     <0x49024000 0xff>; /* L3 Interconnect */
+                               reg-names = "mpu", "dma";
+                               interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
+                               interrupt-names = "common";
+                               ti,buffer-size = <128>;
+                               dmas = <&sdma 17>,
+                                      <&sdma 18>;
+                               dma-names = "tx", "rx";
+                               status = "disabled";
+                       };
+               };
+
+               target-module@26000 {                   /* 0x40126000, ap 6 06.0 */
+                       compatible = "ti,sysc-omap2", "ti,sysc";
+                       ti,hwmods = "mcbsp3";
+                       reg = <0x2608c 0x4>;
+                       reg-names = "sysc";
+                       ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+                                        SYSC_OMAP2_ENAWAKEUP |
+                                        SYSC_OMAP2_SOFTRESET)>;
+                       ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+                                       <SYSC_IDLE_NO>,
+                                       <SYSC_IDLE_SMART>;
+                       /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */
+                       clocks = <&abe_clkctrl OMAP5_MCBSP3_CLKCTRL 0>;
+                       clock-names = "fck";
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       ranges = <0x0 0x26000 0x1000>,
+                                <0x49026000 0x49026000 0x1000>;
+
+                       mcbsp3: mcbsp@0 {
+                               compatible = "ti,omap4-mcbsp";
+                               reg = <0x0 0xff>, /* MPU private access */
+                                     <0x49026000 0xff>; /* L3 Interconnect */
+                               reg-names = "mpu", "dma";
+                               interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+                               interrupt-names = "common";
+                               ti,buffer-size = <128>;
+                               dmas = <&sdma 19>,
+                                      <&sdma 20>;
+                               dma-names = "tx", "rx";
+                               status = "disabled";
+                       };
+               };
+
+               target-module@28000 {                   /* 0x40128000, ap 8 08.0 */
+                       compatible = "ti,sysc";
+                       status = "disabled";
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       ranges = <0x0 0x28000 0x1000>,
+                                <0x49028000 0x49028000 0x1000>;
+               };
+
+               target-module@2a000 {                   /* 0x4012a000, ap 10 0a.0 */
+                       compatible = "ti,sysc";
+                       status = "disabled";
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       ranges = <0x0 0x2a000 0x1000>,
+                                <0x4902a000 0x4902a000 0x1000>;
+               };
+
+               target-module@2e000 {                   /* 0x4012e000, ap 12 0c.0 */
+                       compatible = "ti,sysc-omap4", "ti,sysc";
+                       ti,hwmods = "dmic";
+                       reg = <0x2e000 0x4>,
+                             <0x2e010 0x4>;
+                       reg-names = "rev", "sysc";
+                       ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
+                                        SYSC_OMAP4_SOFTRESET)>;
+                       ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+                                       <SYSC_IDLE_NO>,
+                                       <SYSC_IDLE_SMART>,
+                                       <SYSC_IDLE_SMART_WKUP>;
+                       /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */
+                       clocks = <&abe_clkctrl OMAP5_DMIC_CLKCTRL 0>;
+                       clock-names = "fck";
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       ranges = <0x0 0x2e000 0x1000>,
+                                <0x4902e000 0x4902e000 0x1000>;
+
+                       dmic: dmic@0 {
+                               compatible = "ti,omap4-dmic";
+                               reg = <0x0 0x7f>, /* MPU private access */
+                                     <0x4902e000 0x7f>; /* L3 Interconnect */
+                               reg-names = "mpu", "dma";
+                               interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
+                               dmas = <&sdma 67>;
+                               dma-names = "up_link";
+                               status = "disabled";
+                       };
+               };
+
+               target-module@30000 {                   /* 0x40130000, ap 14 0e.0 */
+                       compatible = "ti,sysc";
+                       status = "disabled";
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       ranges = <0x0 0x30000 0x1000>,
+                                <0x49030000 0x49030000 0x1000>;
+               };
+
+               mcpdm_module: target-module@32000 {     /* 0x40132000, ap 16 10.0 */
+                       compatible = "ti,sysc-omap4", "ti,sysc";
+                       ti,hwmods = "mcpdm";
+                       reg = <0x32000 0x4>,
+                             <0x32010 0x4>;
+                       reg-names = "rev", "sysc";
+                       ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
+                                        SYSC_OMAP4_SOFTRESET)>;
+                       ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+                                       <SYSC_IDLE_NO>,
+                                       <SYSC_IDLE_SMART>,
+                                       <SYSC_IDLE_SMART_WKUP>;
+                       /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */
+                       clocks = <&abe_clkctrl OMAP5_MCPDM_CLKCTRL 0>;
+                       clock-names = "fck";
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       ranges = <0x0 0x32000 0x1000>,
+                                <0x49032000 0x49032000 0x1000>;
+
+                       /* Must be only enabled for boards with pdmclk wired */
+                       status = "disabled";
+
+                       mcpdm: mcpdm@0 {
+                               compatible = "ti,omap4-mcpdm";
+                               reg = <0x0 0x7f>, /* MPU private access */
+                                     <0x49032000 0x7f>; /* L3 Interconnect */
+                               reg-names = "mpu", "dma";
+                               interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
+                               dmas = <&sdma 65>,
+                                      <&sdma 66>;
+                               dma-names = "up_link", "dn_link";
+                       };
+               };
+
+               target-module@38000 {                   /* 0x40138000, ap 18 12.0 */
+                       compatible = "ti,sysc-omap4-timer", "ti,sysc";
+                       ti,hwmods = "timer5";
+                       reg = <0x38000 0x4>,
+                             <0x38010 0x4>;
+                       reg-names = "rev", "sysc";
+                       ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
+                                        SYSC_OMAP4_SOFTRESET)>;
+                       ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+                                       <SYSC_IDLE_NO>,
+                                       <SYSC_IDLE_SMART>,
+                                       <SYSC_IDLE_SMART_WKUP>;
+                       /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */
+                       clocks = <&abe_clkctrl OMAP5_TIMER5_CLKCTRL 0>;
+                       clock-names = "fck";
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       ranges = <0x0 0x38000 0x1000>,
+                                <0x49038000 0x49038000 0x1000>;
+
+                       timer5: timer@0 {
+                               compatible = "ti,omap5430-timer";
+                               reg = <0x0 0x80>,
+                                     <0x49038000 0x80>;
+                               clocks = <&abe_clkctrl OMAP5_TIMER5_CLKCTRL 24>;
+                               clock-names = "fck";
+                               interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
+                               ti,timer-dsp;
+                               ti,timer-pwm;
+                       };
+               };
+
+               target-module@3a000 {                   /* 0x4013a000, ap 20 14.0 */
+                       compatible = "ti,sysc-omap4-timer", "ti,sysc";
+                       ti,hwmods = "timer6";
+                       reg = <0x3a000 0x4>,
+                             <0x3a010 0x4>;
+                       reg-names = "rev", "sysc";
+                       ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
+                                        SYSC_OMAP4_SOFTRESET)>;
+                       ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+                                       <SYSC_IDLE_NO>,
+                                       <SYSC_IDLE_SMART>,
+                                       <SYSC_IDLE_SMART_WKUP>;
+                       /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */
+                       clocks = <&abe_clkctrl OMAP5_TIMER6_CLKCTRL 0>;
+                       clock-names = "fck";
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       ranges = <0x0 0x3a000 0x1000>,
+                                <0x4903a000 0x4903a000 0x1000>;
+
+                       timer6: timer@0 {
+                               compatible = "ti,omap5430-timer";
+                               reg = <0x0 0x80>,
+                                     <0x4903a000 0x80>;
+                               clocks = <&abe_clkctrl OMAP5_TIMER6_CLKCTRL 24>;
+                               clock-names = "fck";
+                               interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
+                               ti,timer-dsp;
+                               ti,timer-pwm;
+                       };
+               };
+
+               target-module@3c000 {                   /* 0x4013c000, ap 22 16.0 */
+                       compatible = "ti,sysc-omap4-timer", "ti,sysc";
+                       ti,hwmods = "timer7";
+                       reg = <0x3c000 0x4>,
+                             <0x3c010 0x4>;
+                       reg-names = "rev", "sysc";
+                       ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
+                                        SYSC_OMAP4_SOFTRESET)>;
+                       ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+                                       <SYSC_IDLE_NO>,
+                                       <SYSC_IDLE_SMART>,
+                                       <SYSC_IDLE_SMART_WKUP>;
+                       /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */
+                       clocks = <&abe_clkctrl OMAP5_TIMER7_CLKCTRL 0>;
+                       clock-names = "fck";
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       ranges = <0x0 0x3c000 0x1000>,
+                                <0x4903c000 0x4903c000 0x1000>;
+
+                       timer7: timer@0 {
+                               compatible = "ti,omap5430-timer";
+                               reg = <0x0 0x80>,
+                                     <0x4903c000 0x80>;
+                               clocks = <&abe_clkctrl OMAP5_TIMER7_CLKCTRL 24>;
+                               clock-names = "fck";
+                               interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
+                               ti,timer-dsp;
+                       };
+               };
+
+               target-module@3e000 {                   /* 0x4013e000, ap 24 18.0 */
+                       compatible = "ti,sysc-omap4-timer", "ti,sysc";
+                       ti,hwmods = "timer8";
+                       reg = <0x3e000 0x4>,
+                             <0x3e010 0x4>;
+                       reg-names = "rev", "sysc";
+                       ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
+                                        SYSC_OMAP4_SOFTRESET)>;
+                       ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+                                       <SYSC_IDLE_NO>,
+                                       <SYSC_IDLE_SMART>,
+                                       <SYSC_IDLE_SMART_WKUP>;
+                       /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */
+                       clocks = <&abe_clkctrl OMAP5_TIMER8_CLKCTRL 0>;
+                       clock-names = "fck";
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       ranges = <0x0 0x3e000 0x1000>,
+                                <0x4903e000 0x4903e000 0x1000>;
+
+                       timer8: timer@0 {
+                               compatible = "ti,omap5430-timer";
+                               reg = <0x0 0x80>,
+                                     <0x4903e000 0x80>;
+                               clocks = <&abe_clkctrl OMAP5_TIMER8_CLKCTRL 24>;
+                               clock-names = "fck";
+                               interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
+                               ti,timer-dsp;
+                               ti,timer-pwm;
+                       };
+               };
+
+               target-module@80000 {                   /* 0x40180000, ap 26 1a.0 */
+                       compatible = "ti,sysc";
+                       status = "disabled";
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       ranges = <0x0 0x80000 0x10000>,
+                                <0x49080000 0x49080000 0x10000>;
+               };
+
+               target-module@a0000 {                   /* 0x401a0000, ap 28 1c.0 */
+                       compatible = "ti,sysc";
+                       status = "disabled";
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       ranges = <0x0 0xa0000 0x10000>,
+                                <0x490a0000 0x490a0000 0x10000>;
+               };
+
+               target-module@c0000 {                   /* 0x401c0000, ap 30 1e.0 */
+                       compatible = "ti,sysc";
+                       status = "disabled";
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       ranges = <0x0 0xc0000 0x10000>,
+                                <0x490c0000 0x490c0000 0x10000>;
+               };
+
+               target-module@f1000 {                   /* 0x401f1000, ap 32 20.0 */
+                       compatible = "ti,sysc";
+                       status = "disabled";
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       ranges = <0x0 0xf1000 0x1000>,
+                                <0x490f1000 0x490f1000 0x1000>;
+               };
+       };
+};
+

diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index 2fefaaf..4b40e47 100644 (file)
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -161,6 +161,9 @@
                l4_per: interconnect@48000000 {
                };
 
+               l4_abe: interconnect@40100000 {
+               };
+
                ocmcram: ocmcram@40300000 {
                        compatible = "mmio-sram";
                        reg = <0x40300000 0x20000>; /* 128k */
@@ -202,115 +205,6 @@
                        ti,iommu-bus-err-back;
                };
 
-               mcpdm: mcpdm@40132000 {
-                       compatible = "ti,omap4-mcpdm";
-                       reg = <0x40132000 0x7f>, /* MPU private access */
-                             <0x49032000 0x7f>; /* L3 Interconnect */
-                       reg-names = "mpu", "dma";
-                       interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
-                       ti,hwmods = "mcpdm";
-                       dmas = <&sdma 65>,
-                              <&sdma 66>;
-                       dma-names = "up_link", "dn_link";
-                       status = "disabled";
-               };
-
-               dmic: dmic@4012e000 {
-                       compatible = "ti,omap4-dmic";
-                       reg = <0x4012e000 0x7f>, /* MPU private access */
-                             <0x4902e000 0x7f>; /* L3 Interconnect */
-                       reg-names = "mpu", "dma";
-                       interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
-                       ti,hwmods = "dmic";
-                       dmas = <&sdma 67>;
-                       dma-names = "up_link";
-                       status = "disabled";
-               };
-
-               mcbsp1: mcbsp@40122000 {
-                       compatible = "ti,omap4-mcbsp";
-                       reg = <0x40122000 0xff>, /* MPU private access */
-                             <0x49022000 0xff>; /* L3 Interconnect */
-                       reg-names = "mpu", "dma";
-                       interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
-                       interrupt-names = "common";
-                       ti,buffer-size = <128>;
-                       ti,hwmods = "mcbsp1";
-                       dmas = <&sdma 33>,
-                              <&sdma 34>;
-                       dma-names = "tx", "rx";
-                       status = "disabled";
-               };
-
-               mcbsp2: mcbsp@40124000 {
-                       compatible = "ti,omap4-mcbsp";
-                       reg = <0x40124000 0xff>, /* MPU private access */
-                             <0x49024000 0xff>; /* L3 Interconnect */
-                       reg-names = "mpu", "dma";
-                       interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
-                       interrupt-names = "common";
-                       ti,buffer-size = <128>;
-                       ti,hwmods = "mcbsp2";
-                       dmas = <&sdma 17>,
-                              <&sdma 18>;
-                       dma-names = "tx", "rx";
-                       status = "disabled";
-               };
-
-               mcbsp3: mcbsp@40126000 {
-                       compatible = "ti,omap4-mcbsp";
-                       reg = <0x40126000 0xff>, /* MPU private access */
-                             <0x49026000 0xff>; /* L3 Interconnect */
-                       reg-names = "mpu", "dma";
-                       interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
-                       interrupt-names = "common";
-                       ti,buffer-size = <128>;
-                       ti,hwmods = "mcbsp3";
-                       dmas = <&sdma 19>,
-                              <&sdma 20>;
-                       dma-names = "tx", "rx";
-                       status = "disabled";
-               };
-
-               timer5: timer@40138000 {
-                       compatible = "ti,omap5430-timer";
-                       reg = <0x40138000 0x80>,
-                             <0x49038000 0x80>;
-                       interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
-                       ti,hwmods = "timer5";
-                       ti,timer-dsp;
-                       ti,timer-pwm;
-               };
-
-               timer6: timer@4013a000 {
-                       compatible = "ti,omap5430-timer";
-                       reg = <0x4013a000 0x80>,
-                             <0x4903a000 0x80>;
-                       interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
-                       ti,hwmods = "timer6";
-                       ti,timer-dsp;
-                       ti,timer-pwm;
-               };
-
-               timer7: timer@4013c000 {
-                       compatible = "ti,omap5430-timer";
-                       reg = <0x4013c000 0x80>,
-                             <0x4903c000 0x80>;
-                       interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
-                       ti,hwmods = "timer7";
-                       ti,timer-dsp;
-               };
-
-               timer8: timer@4013e000 {
-                       compatible = "ti,omap5430-timer";
-                       reg = <0x4013e000 0x80>,
-                             <0x4903e000 0x80>;
-                       interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
-                       ti,hwmods = "timer8";
-                       ti,timer-dsp;
-                       ti,timer-pwm;
-               };
-
                dmm@4e000000 {
                        compatible = "ti,omap5-dmm";
                        reg = <0x4e000000 0x800>;
@@ -517,3 +411,6 @@
 &core_thermal {
        coefficients = <0 2000>;
 };
+
+#include "omap5-l4-abe.dtsi"
+#include "omap54xx-clocks.dtsi"

diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi
index bd6907d..65975df 100644 (file)
--- a/arch/arm/boot/dts/qcom-apq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-apq8064.dtsi
@@ -714,6 +714,7 @@
                                        interrupt-controller;
                                        #interrupt-cells = <2>;
                                        gpio-controller;
+                                       gpio-ranges = <&pm8921_gpio 0 0 44>;
                                        #gpio-cells = <2>;
 
                                };
@@ -1302,8 +1303,9 @@
                                <0x04700300 0x200>,
                                <0x04700500 0x5c>;
                        reg-names = "dsi_pll", "dsi_phy", "dsi_phy_regulator";
-                       clock-names = "iface_clk";
-                       clocks = <&mmcc DSI_M_AHB_CLK>;
+                       clock-names = "iface_clk", "ref";
+                       clocks = <&mmcc DSI_M_AHB_CLK>,
+                                <&cxo_board>;
                };
 
 

diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi
index 9e75f97..1008dfb 100644 (file)
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
@@ -400,8 +400,8 @@
                        #address-cells = <3>;
                        #size-cells = <2>;
 
-                       ranges = <0x81000000 0 0x40200000 0x40200000 0 0x00100000
-                                 0x82000000 0 0x40300000 0x40300000 0 0x400000>;
+                       ranges = <0x81000000 0 0x40200000 0x40200000 0 0x00100000>,
+                                <0x82000000 0 0x40300000 0x40300000 0 0x00d00000>;
 
                        interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
                        interrupt-names = "msi";

diff --git a/arch/arm/boot/dts/qcom-mdm9615.dtsi b/arch/arm/boot/dts/qcom-mdm9615.dtsi
index 02afc6a..356e953 100644 (file)
--- a/arch/arm/boot/dts/qcom-mdm9615.dtsi
+++ b/arch/arm/boot/dts/qcom-mdm9615.dtsi
@@ -326,6 +326,7 @@
                                        interrupt-controller;
                                        #interrupt-cells = <2>;
                                        gpio-controller;
+                                       gpio-ranges = <&pmicgpio 0 0 6>;
                                        #gpio-cells = <2>;
                                };
                        };

diff --git a/arch/arm/boot/dts/qcom-msm8660.dtsi b/arch/arm/boot/dts/qcom-msm8660.dtsi
index 65a994f..ec5cbc4 100644 (file)
--- a/arch/arm/boot/dts/qcom-msm8660.dtsi
+++ b/arch/arm/boot/dts/qcom-msm8660.dtsi
@@ -295,6 +295,7 @@
                                        interrupt-controller;
                                        #interrupt-cells = <2>;
                                        gpio-controller;
+                                       gpio-ranges = <&pm8058_gpio 0 0 44>;
                                        #gpio-cells = <2>;
 
                                };

diff --git a/arch/arm/boot/dts/qcom-pma8084.dtsi b/arch/arm/boot/dts/qcom-pma8084.dtsi
index 8f5ea7a..ea1ca16 100644 (file)
--- a/arch/arm/boot/dts/qcom-pma8084.dtsi
+++ b/arch/arm/boot/dts/qcom-pma8084.dtsi
@@ -31,6 +31,7 @@
                        compatible = "qcom,pma8084-gpio", "qcom,spmi-gpio";
                        reg = <0xc000>;
                        gpio-controller;
+                       gpio-ranges = <&pma8084_gpios 0 0 22>;
                        #gpio-cells = <2>;
                        interrupt-controller;
                        #interrupt-cells = <2>;

diff --git a/arch/arm/boot/dts/r7s72100-rskrza1.dts b/arch/arm/boot/dts/r7s72100-rskrza1.dts
index 8ee44a1..ff24301 100644 (file)
--- a/arch/arm/boot/dts/r7s72100-rskrza1.dts
+++ b/arch/arm/boot/dts/r7s72100-rskrza1.dts
@@ -34,12 +34,23 @@
        };
 
        leds {
-               status = "okay";
                compatible = "gpio-leds";
 
                led0 {
                        gpios = <&port7 1 GPIO_ACTIVE_LOW>;
                };
+
+               led1 {
+                       gpios = <&io_expander1 0 GPIO_ACTIVE_LOW>;
+               };
+
+               led2 {
+                       gpios = <&io_expander1 1 GPIO_ACTIVE_LOW>;
+               };
+
+               led3 {
+                       gpios = <&io_expander1 2 GPIO_ACTIVE_LOW>;
+               };
        };
 };
 
@@ -47,6 +58,34 @@
        clock-frequency = <13330000>;
 };
 
+&i2c3 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&i2c3_pins>;
+       status = "okay";
+
+       clock-frequency = <400000>;
+
+       io_expander1: gpio@20 {
+               compatible = "onnn,cat9554";
+               reg = <0x20>;
+               gpio-controller;
+               #gpio-cells = <2>;
+       };
+
+       io_expander2: gpio@21 {
+               compatible = "onnn,cat9554";
+               reg = <0x21>;
+               gpio-controller;
+               #gpio-cells = <2>;
+       };
+
+       eeprom@50 {
+               compatible = "renesas,r1ex24016", "atmel,24c16";
+               reg = <0x50>;
+               pagesize = <16>;
+       };
+};
+
 &usb_x1_clk {
        clock-frequency = <48000000>;
 };
@@ -56,6 +95,11 @@
 };
 
 &pinctrl {
+       /* RIIC ch3 (Port Expander, EEPROM (MAC Addr), Audio Codec) */
+       i2c3_pins: i2c3 {
+               pinmux = <RZA1_PINMUX(1, 6, 1)>,        /* RIIC3SCL */
+                        <RZA1_PINMUX(1, 7, 1)>;        /* RIIC3SDA */
+       };
 
        /* Serial Console */
        scif2_pins: serial2 {

diff --git a/arch/arm/boot/dts/r8a73a4-ape6evm.dts b/arch/arm/boot/dts/r8a73a4-ape6evm.dts
index d530f45..f70f4a3 100644 (file)
--- a/arch/arm/boot/dts/r8a73a4-ape6evm.dts
+++ b/arch/arm/boot/dts/r8a73a4-ape6evm.dts
@@ -19,7 +19,7 @@
        };
 
        chosen {
-               bootargs = "ignore_loglevel root=/dev/nfs ip=dhcp rw";
+               bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
                stdout-path = "serial0:115200n8";
        };
 
@@ -166,6 +166,33 @@
 };
 
 &bsc {
+       flash@0 {
+               compatible = "cfi-flash", "mtd-rom";
+               reg = <0x0 0x08000000>;
+               bank-width = <2>;
+
+               partitions {
+                       compatible = "fixed-partitions";
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+
+                       partition@0 {
+                               label = "uboot";
+                               reg = <0x00000000 0x00040000>;
+                               read-only;
+                       };
+                       partition@40000 {
+                               label = "uboot-env";
+                               reg = <0x00040000 0x00040000>;
+                               read-only;
+                       };
+                       partition@80000 {
+                               label = "flash";
+                               reg = <0x00080000 0x07f80000>;
+                       };
+               };
+       };
+
        ethernet@8000000 {
                compatible = "smsc,lan9220", "smsc,lan9115";
                reg = <0x08000000 0x1000>;

diff --git a/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts b/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts
index 77d1824..2840eb0 100644 (file)
--- a/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts
+++ b/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts
@@ -22,6 +22,17 @@
                stdout-path = "serial1:115200n8";
        };
 
+       hdmi-out {
+               compatible = "hdmi-connector";
+               type = "a";
+
+               port {
+                       hdmi_con: endpoint {
+                               remote-endpoint = <&bridge_out>;
+                       };
+               };
+       };
+
        memory@40000000 {
                device_type = "memory";
                reg = <0 0x40000000 0 0x20000000>;
@@ -80,10 +91,42 @@
        status = "okay";
 };
 
+&du {
+       pinctrl-0 = <&du0_pins>;
+       pinctrl-names = "default";
+
+       status = "okay";
+
+       ports {
+               port@0 {
+                       endpoint {
+                               remote-endpoint = <&bridge_in>;
+                       };
+               };
+       };
+};
+
+&ehci1 {
+       status = "okay";
+};
+
 &extal_clk {
        clock-frequency = <20000000>;
 };
 
+&gpio2 {
+       interrupt-fixup {
+               gpio-hog;
+               gpios = <29 GPIO_ACTIVE_HIGH>;
+               line-name = "hdmi-hpd-int";
+               input;
+       };
+};
+
+&hsusb0 {
+       status = "okay";
+};
+
 &i2c3 {
        pinctrl-0 = <&i2c3_pins>;
        pinctrl-names = "default";
@@ -97,12 +140,60 @@
        };
 };
 
+&i2c4 {
+       pinctrl-0 = <&i2c4_pins>;
+       pinctrl-names = "default";
+
+       status = "okay";
+       clock-frequency = <100000>;
+
+       hdmi@39 {
+               compatible = "sil,sii9022";
+               reg = <0x39>;
+               interrupt-parent = <&gpio2>;
+               interrupts = <29 IRQ_TYPE_LEVEL_LOW>;
+
+               ports {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+
+                       port@0 {
+                               reg = <0>;
+                               bridge_in: endpoint {
+                                       remote-endpoint = <&du_out_rgb0>;
+                               };
+                       };
+
+                       port@1 {
+                               reg = <1>;
+                               bridge_out: endpoint {
+                                       remote-endpoint = <&hdmi_con>;
+                               };
+                       };
+               };
+       };
+};
+
+&ohci1 {
+       status = "okay";
+};
+
 &pfc {
        avb_pins: avb {
                groups = "avb_mdio", "avb_gmii_tx_rx";
                function = "avb";
        };
 
+       du0_pins: du0 {
+               groups = "du0_rgb888", "du0_sync", "du0_disp", "du0_clk0_out";
+               function = "du0";
+       };
+
+       i2c4_pins: i2c4 {
+               groups = "i2c4_e";
+               function = "i2c4";
+       };
+
        i2c3_pins: i2c3 {
                groups = "i2c3_c";
                function = "i2c3";
@@ -135,6 +226,16 @@
                function = "sdhi2";
                power-source = <1800>;
        };
+
+       usb0_pins: usb0 {
+               groups = "usb0";
+               function = "usb0";
+       };
+
+       usb1_pins: usb1 {
+               groups = "usb1";
+               function = "usb1";
+       };
 };
 
 &qspi0 {
@@ -195,3 +296,25 @@
        sd-uhs-sdr50;
        status = "okay";
 };
+
+&usb2_phy0 {
+       status = "okay";
+};
+
+&usb2_phy1 {
+       status = "okay";
+};
+
+&usbphy0 {
+       pinctrl-0 = <&usb0_pins>;
+       pinctrl-names = "default";
+
+       status = "okay";
+};
+
+&usbphy1 {
+       pinctrl-0 = <&usb1_pins>;
+       pinctrl-names = "default";
+
+       status = "okay";
+};

diff --git a/arch/arm/boot/dts/r8a77470.dtsi b/arch/arm/boot/dts/r8a77470.dtsi
index f4e232b..56cb10b 100644 (file)
--- a/arch/arm/boot/dts/r8a77470.dtsi
+++ b/arch/arm/boot/dts/r8a77470.dtsi
@@ -325,6 +325,77 @@
                        status = "disabled";
                };
 
+               hsusb0: hsusb@e6590000 {
+                       compatible = "renesas,usbhs-r8a77470",
+                                    "renesas,rcar-gen2-usbhs";
+                       reg = <0 0xe6590000 0 0x100>;
+                       interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 704>;
+                       dmas = <&usb_dmac00 0>, <&usb_dmac00 1>,
+                              <&usb_dmac10 0>, <&usb_dmac10 1>;
+                       dma-names = "ch0", "ch1", "ch2", "ch3";
+                       renesas,buswait = <4>;
+                       phys = <&usb0 1>;
+                       phy-names = "usb";
+                       power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
+                       resets = <&cpg 704>;
+                       status = "disabled";
+               };
+
+               usbphy0: usb-phy@e6590100 {
+                       compatible = "renesas,usb-phy-r8a77470",
+                                    "renesas,rcar-gen2-usb-phy";
+                       reg = <0 0xe6590100 0 0x100>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       clocks = <&cpg CPG_MOD 704>;
+                       clock-names = "usbhs";
+                       power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
+                       resets = <&cpg 704>;
+                       status = "disabled";
+
+                       usb0: usb-channel@0 {
+                               reg = <0>;
+                               #phy-cells = <1>;
+                       };
+               };
+
+               hsusb1: hsusb@e6598000 {
+                       compatible = "renesas,usbhs-r8a77470",
+                                    "renesas,rcar-gen2-usbhs";
+                       reg = <0 0xe6598000 0 0x100>;
+                       interrupts = <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 706>;
+                       dmas = <&usb_dmac01 0>, <&usb_dmac01 1>,
+                              <&usb_dmac11 0>, <&usb_dmac11 1>;
+                       dma-names = "ch0", "ch1", "ch2", "ch3";
+                       renesas,buswait = <4>;
+                       /* We need to turn on usbphy0 to make usbphy1 to work */
+                       phys = <&usb1 1>;
+                       phy-names = "usb";
+                       power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
+                       resets = <&cpg 706>;
+                       status = "disabled";
+               };
+
+               usbphy1: usb-phy@e6598100 {
+                       compatible = "renesas,usb-phy-r8a77470",
+                                    "renesas,rcar-gen2-usb-phy";
+                       reg = <0 0xe6598100 0 0x100>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       clocks = <&cpg CPG_MOD 706>;
+                       clock-names = "usbhs";
+                       power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
+                       resets = <&cpg 706>;
+                       status = "disabled";
+
+                       usb1: usb-channel@0 {
+                               reg = <0>;
+                               #phy-cells = <1>;
+                       };
+               };
+
                usb_dmac00: dma-controller@e65a0000 {
                        compatible = "renesas,r8a77470-usb-dmac",
                                     "renesas,usb-dmac";
@@ -588,6 +659,216 @@
                        status = "disabled";
                };
 
+               hscif0: serial@e62c0000 {
+                       compatible = "renesas,hscif-r8a77470",
+                                    "renesas,rcar-gen2-hscif", "renesas,hscif";
+                       reg = <0 0xe62c0000 0 0x60>;
+                       interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 717>,
+                                <&cpg CPG_CORE R8A77470_CLK_ZS>, <&scif_clk>;
+                       clock-names = "fck", "brg_int", "scif_clk";
+                       dmas = <&dmac0 0x39>, <&dmac0 0x3a>,
+                              <&dmac1 0x39>, <&dmac1 0x3a>;
+                       dma-names = "tx", "rx", "tx", "rx";
+                       power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
+                       resets = <&cpg 717>;
+                       status = "disabled";
+               };
+
+               hscif1: serial@e62c8000 {
+                       compatible = "renesas,hscif-r8a77470",
+                                    "renesas,rcar-gen2-hscif", "renesas,hscif";
+                       reg = <0 0xe62c8000 0 0x60>;
+                       interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 716>,
+                                <&cpg CPG_CORE R8A77470_CLK_ZS>, <&scif_clk>;
+                       clock-names = "fck", "brg_int", "scif_clk";
+                       dmas = <&dmac0 0x4d>, <&dmac0 0x4e>,
+                              <&dmac1 0x4d>, <&dmac1 0x4e>;
+                       dma-names = "tx", "rx", "tx", "rx";
+                       power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
+                       resets = <&cpg 716>;
+                       status = "disabled";
+               };
+
+               hscif2: serial@e62d0000 {
+                       compatible = "renesas,hscif-r8a77470",
+                                    "renesas,rcar-gen2-hscif", "renesas,hscif";
+                       reg = <0 0xe62d0000 0 0x60>;
+                       interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 713>,
+                                <&cpg CPG_CORE R8A77470_CLK_ZS>, <&scif_clk>;
+                       clock-names = "fck", "brg_int", "scif_clk";
+                       dmas = <&dmac0 0x3b>, <&dmac0 0x3c>,
+                              <&dmac1 0x3b>, <&dmac1 0x3c>;
+                       dma-names = "tx", "rx", "tx", "rx";
+                       power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
+                       resets = <&cpg 713>;
+                       status = "disabled";
+               };
+
+               pwm0: pwm@e6e30000 {
+                       compatible = "renesas,pwm-r8a77470", "renesas,pwm-rcar";
+                       reg = <0 0xe6e30000 0 0x8>;
+                       clocks = <&cpg CPG_MOD 523>;
+                       power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
+                       resets = <&cpg 523>;
+                       #pwm-cells = <2>;
+                       status = "disabled";
+               };
+
+               pwm1: pwm@e6e31000 {
+                       compatible = "renesas,pwm-r8a77470", "renesas,pwm-rcar";
+                       reg = <0 0xe6e31000 0 0x8>;
+                       clocks = <&cpg CPG_MOD 523>;
+                       power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
+                       resets = <&cpg 523>;
+                       #pwm-cells = <2>;
+                       status = "disabled";
+               };
+
+               pwm2: pwm@e6e32000 {
+                       compatible = "renesas,pwm-r8a77470", "renesas,pwm-rcar";
+                       reg = <0 0xe6e32000 0 0x8>;
+                       clocks = <&cpg CPG_MOD 523>;
+                       power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
+                       resets = <&cpg 523>;
+                       #pwm-cells = <2>;
+                       status = "disabled";
+               };
+
+               pwm3: pwm@e6e33000 {
+                       compatible = "renesas,pwm-r8a77470", "renesas,pwm-rcar";
+                       reg = <0 0xe6e33000 0 0x8>;
+                       clocks = <&cpg CPG_MOD 523>;
+                       power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
+                       resets = <&cpg 523>;
+                       #pwm-cells = <2>;
+                       status = "disabled";
+               };
+
+               pwm4: pwm@e6e34000 {
+                       compatible = "renesas,pwm-r8a77470", "renesas,pwm-rcar";
+                       reg = <0 0xe6e34000 0 0x8>;
+                       clocks = <&cpg CPG_MOD 523>;
+                       power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
+                       resets = <&cpg 523>;
+                       #pwm-cells = <2>;
+                       status = "disabled";
+               };
+
+               pwm5: pwm@e6e35000 {
+                       compatible = "renesas,pwm-r8a77470", "renesas,pwm-rcar";
+                       reg = <0 0xe6e35000 0 0x8>;
+                       clocks = <&cpg CPG_MOD 523>;
+                       power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
+                       resets = <&cpg 523>;
+                       #pwm-cells = <2>;
+                       status = "disabled";
+               };
+
+               pwm6: pwm@e6e36000 {
+                       compatible = "renesas,pwm-r8a77470", "renesas,pwm-rcar";
+                       reg = <0 0xe6e36000 0 0x8>;
+                       clocks = <&cpg CPG_MOD 523>;
+                       power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
+                       resets = <&cpg 523>;
+                       #pwm-cells = <2>;
+                       status = "disabled";
+               };
+
+               vin0: video@e6ef0000 {
+                       compatible = "renesas,vin-r8a77470",
+                                    "renesas,rcar-gen2-vin";
+                       reg = <0 0xe6ef0000 0 0x1000>;
+                       interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 811>;
+                       power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
+                       resets = <&cpg 811>;
+                       status = "disabled";
+               };
+
+               vin1: video@e6ef1000 {
+                       compatible = "renesas,vin-r8a77470",
+                                    "renesas,rcar-gen2-vin";
+                       reg = <0 0xe6ef1000 0 0x1000>;
+                       interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 810>;
+                       power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
+                       resets = <&cpg 810>;
+                       status = "disabled";
+               };
+
+               ohci0: usb@ee080000 {
+                       compatible = "generic-ohci";
+                       reg = <0 0xee080000 0 0x100>;
+                       interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 703>;
+                       phys = <&usb0 0>, <&usb2_phy0>;
+                       phy-names = "usb";
+                       power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
+                       resets = <&cpg 703>;
+                       status = "disabled";
+               };
+
+               ehci0: usb@ee080100 {
+                       compatible = "generic-ehci";
+                       reg = <0 0xee080100 0 0x100>;
+                       interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 703>;
+                       phys = <&usb0 0>, <&usb2_phy0>;
+                       phy-names = "usb";
+                       companion = <&ohci0>;
+                       power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
+                       resets = <&cpg 703>;
+                       status = "disabled";
+               };
+
+               usb2_phy0: usb-phy@ee080200 {
+                       compatible = "renesas,usb2-phy-r8a77470";
+                       reg = <0 0xee080200 0 0x700>;
+                       clocks = <&cpg CPG_MOD 703>;
+                       power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
+                       resets = <&cpg 703>;
+                       #phy-cells = <0>;
+                       status = "disabled";
+               };
+
+               ohci1: usb@ee0c0000 {
+                       compatible = "generic-ohci";
+                       reg = <0 0xee0c0000 0 0x100>;
+                       interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 705>;
+                       phys = <&usb0 1>, <&usb2_phy1>, <&usb1 0>;
+                       phy-names = "usb";
+                       power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
+                       resets = <&cpg 705>;
+                       status = "disabled";
+               };
+
+               ehci1: usb@ee0c0100 {
+                       compatible = "generic-ehci";
+                       reg = <0 0xee0c0100 0 0x100>;
+                       interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 705>;
+                       phys = <&usb0 1>, <&usb2_phy1>, <&usb1 0>;
+                       phy-names = "usb";
+                       companion = <&ohci1>;
+                       power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
+                       resets = <&cpg 705>;
+                       status = "disabled";
+               };
+
+               usb2_phy1: usb-phy@ee0c0200 {
+                       compatible = "renesas,usb2-phy-r8a77470";
+                       reg = <0 0xee0c0200 0 0x700>;
+                       clocks = <&cpg CPG_MOD 705>;
+                       power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
+                       resets = <&cpg 705>;
+                       #phy-cells = <0>;
+                       status = "disabled";
+               };
+
                sdhi0: sd@ee100000 {
                        compatible = "renesas,sdhi-r8a77470",
                                     "renesas,rcar-gen2-sdhi";
@@ -643,6 +924,38 @@
                        resets = <&cpg 408>;
                };
 
+               du: display@feb00000 {
+                       compatible = "renesas,du-r8a77470";
+                       reg = <0 0xfeb00000 0 0x40000>;
+                       interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 724>,
+                                <&cpg CPG_MOD 723>;
+                       clock-names = "du.0", "du.1";
+                       status = "disabled";
+
+                       ports {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+
+                               port@0 {
+                                       reg = <0>;
+                                       du_out_rgb0: endpoint {
+                                       };
+                               };
+                               port@1 {
+                                       reg = <1>;
+                                       du_out_rgb1: endpoint {
+                                       };
+                               };
+                               port@2 {
+                                       reg = <2>;
+                                       du_out_lvds0: endpoint {
+                                       };
+                               };
+                       };
+               };
+
                prr: chipid@ff000044 {
                        compatible = "renesas,prr";
                        reg = <0 0xff000044 0 4>;

diff --git a/arch/arm/boot/dts/r8a7778-bockw.dts b/arch/arm/boot/dts/r8a7778-bockw.dts
index cecb229..0b49956 100644 (file)
--- a/arch/arm/boot/dts/r8a7778-bockw.dts
+++ b/arch/arm/boot/dts/r8a7778-bockw.dts
@@ -25,7 +25,7 @@
        };
 
        chosen {
-               bootargs = "ignore_loglevel ip=dhcp root=/dev/nfs rw";
+               bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
                stdout-path = "serial0:115200n8";
        };
 

diff --git a/arch/arm/boot/dts/r8a7779-marzen.dts b/arch/arm/boot/dts/r8a7779-marzen.dts
index abc14e7..d4bee1e 100644 (file)
--- a/arch/arm/boot/dts/r8a7779-marzen.dts
+++ b/arch/arm/boot/dts/r8a7779-marzen.dts
@@ -21,7 +21,7 @@
        };
 
        chosen {
-               bootargs = "ignore_loglevel root=/dev/nfs ip=on";
+               bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
                stdout-path = "serial0:115200n8";
        };
 

diff --git a/arch/arm/boot/dts/r8a7792-blanche.dts b/arch/arm/boot/dts/r8a7792-blanche.dts
index f923012..b6fa80c 100644 (file)
--- a/arch/arm/boot/dts/r8a7792-blanche.dts
+++ b/arch/arm/boot/dts/r8a7792-blanche.dts
@@ -308,6 +308,26 @@
        };
 };
 
+&iic3 {
+       status = "okay";
+
+       pmic@58 {
+               compatible = "dlg,da9063";
+               reg = <0x58>;
+               interrupt-parent = <&irqc>;
+               interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
+               interrupt-controller;
+
+               rtc {
+                       compatible = "dlg,da9063-rtc";
+               };
+
+               wdt {
+                       compatible = "dlg,da9063-watchdog";
+               };
+       };
+};
+
 &du {
        pinctrl-0 = <&du0_pins &du1_pins>;
        pinctrl-names = "default";

diff --git a/arch/arm/boot/dts/r8a7792.dtsi b/arch/arm/boot/dts/r8a7792.dtsi
index 8e9eb4b..38fb43d 100644 (file)
--- a/arch/arm/boot/dts/r8a7792.dtsi
+++ b/arch/arm/boot/dts/r8a7792.dtsi
@@ -22,6 +22,7 @@
                i2c3 = &i2c3;
                i2c4 = &i2c4;
                i2c5 = &i2c5;
+               i2c6 = &iic3;
                spi0 = &qspi;
                spi1 = &msiof0;
                spi2 = &msiof1;
@@ -444,6 +445,23 @@
                        status = "disabled";
                };
 
+               iic3: i2c@e60b0000 {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       compatible = "renesas,iic-r8a7792",
+                                    "renesas,rcar-gen2-iic",
+                                    "renesas,rmobile-iic";
+                       reg = <0 0xe60b0000 0 0x425>;
+                       interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 926>;
+                       dmas = <&dmac0 0x77>, <&dmac0 0x78>,
+                              <&dmac1 0x77>, <&dmac1 0x78>;
+                       dma-names = "tx", "rx", "tx", "rx";
+                       power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+                       resets = <&cpg 926>;
+                       status = "disabled";
+               };
+
                dmac0: dma-controller@e6700000 {
                        compatible = "renesas,dmac-r8a7792",
                                     "renesas,rcar-dmac";

diff --git a/arch/arm/boot/dts/r8a7794-alt.dts b/arch/arm/boot/dts/r8a7794-alt.dts
index ef7e2a8..0ab3d8d 100644 (file)
--- a/arch/arm/boot/dts/r8a7794-alt.dts
+++ b/arch/arm/boot/dts/r8a7794-alt.dts
@@ -199,6 +199,22 @@
        };
 };
 
+&pci0 {
+       status = "okay";
+       pinctrl-0 = <&usb0_pins>;
+       pinctrl-names = "default";
+};
+
+&pci1 {
+       status = "okay";
+       pinctrl-0 = <&usb1_pins>;
+       pinctrl-names = "default";
+};
+
+&usbphy {
+       status = "okay";
+};
+
 &du {
        pinctrl-0 = <&du_pins>;
        pinctrl-names = "default";
@@ -293,6 +309,16 @@
                function = "sdhi1";
                power-source = <1800>;
        };
+
+       usb0_pins: usb0 {
+               groups = "usb0";
+               function = "usb0";
+       };
+
+       usb1_pins: usb1 {
+               groups = "usb1";
+               function = "usb1";
+       };
 };
 
 &cmt0 {
@@ -377,6 +403,27 @@
        pinctrl-names = "i2c-exio4";
 };
 
+&i2c7 {
+       status = "okay";
+       clock-frequency = <100000>;
+
+       pmic@58 {
+               compatible = "dlg,da9063";
+               reg = <0x58>;
+               interrupt-parent = <&gpio3>;
+               interrupts = <31 IRQ_TYPE_LEVEL_LOW>;
+               interrupt-controller;
+
+               rtc {
+                       compatible = "dlg,da9063-rtc";
+               };
+
+               wdt {
+                       compatible = "dlg,da9063-watchdog";
+               };
+       };
+};
+
 &vin0 {
        status = "okay";
        pinctrl-0 = <&vin0_pins>;

diff --git a/arch/arm/boot/dts/rk3036-kylin.dts b/arch/arm/boot/dts/rk3036-kylin.dts
index 0173eb1..fb3cf00 100644 (file)
--- a/arch/arm/boot/dts/rk3036-kylin.dts
+++ b/arch/arm/boot/dts/rk3036-kylin.dts
@@ -368,31 +368,31 @@
 &pinctrl {
        leds {
                led_ctl: led-ctl {
-                       rockchip,pins = <2 30 RK_FUNC_GPIO &pcfg_pull_none>;
+                       rockchip,pins = <2 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
                };
        };
 
        pmic {
                pmic_int: pmic-int {
-                       rockchip,pins = <2 2 RK_FUNC_GPIO &pcfg_pull_default>;
+                       rockchip,pins = <2 RK_PA2 RK_FUNC_GPIO &pcfg_pull_default>;
                };
        };
 
        sdio {
                bt_wake_h: bt-wake-h {
-                       rockchip,pins = <2 8 RK_FUNC_GPIO &pcfg_pull_default>;
+                       rockchip,pins = <2 RK_PB0 RK_FUNC_GPIO &pcfg_pull_default>;
                };
        };
 
        sdmmc {
                sdmmc_pwr: sdmmc-pwr {
-                       rockchip,pins = <2 28 RK_FUNC_GPIO &pcfg_pull_none>;
+                       rockchip,pins = <2 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
                };
        };
 
        sleep {
                global_pwroff: global-pwroff {
-                       rockchip,pins = <2 7 RK_FUNC_1 &pcfg_pull_none>;
+                       rockchip,pins = <2 RK_PA7 1 &pcfg_pull_none>;
                };
        };
 };

diff --git a/arch/arm/boot/dts/rk3036.dtsi b/arch/arm/boot/dts/rk3036.dtsi
index 59c9086..0290ea4 100644 (file)
--- a/arch/arm/boot/dts/rk3036.dtsi
+++ b/arch/arm/boot/dts/rk3036.dtsi
@@ -551,71 +551,71 @@
 
                pwm0 {
                        pwm0_pin: pwm0-pin {
-                               rockchip,pins = <0 0 RK_FUNC_2 &pcfg_pull_none>;
+                               rockchip,pins = <0 RK_PA0 2 &pcfg_pull_none>;
                        };
                };
 
                pwm1 {
                        pwm1_pin: pwm1-pin {
-                               rockchip,pins = <0 1 RK_FUNC_2 &pcfg_pull_none>;
+                               rockchip,pins = <0 RK_PA1 2 &pcfg_pull_none>;
                        };
                };
 
                pwm2 {
                        pwm2_pin: pwm2-pin {
-                               rockchip,pins = <0 1 2 &pcfg_pull_none>;
+                               rockchip,pins = <0 RK_PA1 2 &pcfg_pull_none>;
                        };
                };
 
                pwm3 {
                        pwm3_pin: pwm3-pin {
-                               rockchip,pins = <0 27 1 &pcfg_pull_none>;
+                               rockchip,pins = <0 RK_PD3 1 &pcfg_pull_none>;
                        };
                };
 
                sdmmc {
                        sdmmc_clk: sdmmc-clk {
-                               rockchip,pins = <1 16 RK_FUNC_1 &pcfg_pull_none>;
+                               rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none>;
                        };
 
                        sdmmc_cmd: sdmmc-cmd {
-                               rockchip,pins = <1 15 RK_FUNC_1 &pcfg_pull_default>;
+                               rockchip,pins = <1 RK_PB7 1 &pcfg_pull_default>;
                        };
 
                        sdmmc_cd: sdmmc-cd {
-                               rockchip,pins = <1 17 RK_FUNC_1 &pcfg_pull_default>;
+                               rockchip,pins = <1 RK_PC1 1 &pcfg_pull_default>;
                        };
 
                        sdmmc_bus1: sdmmc-bus1 {
-                               rockchip,pins = <1 18 RK_FUNC_1 &pcfg_pull_default>;
+                               rockchip,pins = <1 RK_PC2 1 &pcfg_pull_default>;
                        };
 
                        sdmmc_bus4: sdmmc-bus4 {
-                               rockchip,pins = <1 18 RK_FUNC_1 &pcfg_pull_default>,
-                                               <1 19 RK_FUNC_1 &pcfg_pull_default>,
-                                               <1 20 RK_FUNC_1 &pcfg_pull_default>,
-                                               <1 21 RK_FUNC_1 &pcfg_pull_default>;
+                               rockchip,pins = <1 RK_PC2 1 &pcfg_pull_default>,
+                                               <1 RK_PC3 1 &pcfg_pull_default>,
+                                               <1 RK_PC4 1 &pcfg_pull_default>,
+                                               <1 RK_PC5 1 &pcfg_pull_default>;
                        };
                };
 
                sdio {
                        sdio_bus1: sdio-bus1 {
-                               rockchip,pins = <0 11 RK_FUNC_1 &pcfg_pull_default>;
+                               rockchip,pins = <0 RK_PB3 1 &pcfg_pull_default>;
                        };
 
                        sdio_bus4: sdio-bus4 {
-                               rockchip,pins = <0 11 RK_FUNC_1 &pcfg_pull_default>,
-                                               <0 12 RK_FUNC_1 &pcfg_pull_default>,
-                                               <0 13 RK_FUNC_1 &pcfg_pull_default>,
-                                               <0 14 RK_FUNC_1 &pcfg_pull_default>;
+                               rockchip,pins = <0 RK_PB3 1 &pcfg_pull_default>,
+                                               <0 RK_PB4 1 &pcfg_pull_default>,
+                                               <0 RK_PB5 1 &pcfg_pull_default>,
+                                               <0 RK_PB6 1 &pcfg_pull_default>;
                        };
 
                        sdio_cmd: sdio-cmd {
-                               rockchip,pins = <0 8 RK_FUNC_1 &pcfg_pull_default>;
+                               rockchip,pins = <0 RK_PB0 1 &pcfg_pull_default>;
                        };
 
                        sdio_clk: sdio-clk {
-                               rockchip,pins = <0 9 RK_FUNC_1 &pcfg_pull_none>;
+                               rockchip,pins = <0 RK_PB1 1 &pcfg_pull_none>;
                        };
                };
 
@@ -625,135 +625,135 @@
                         * We also have external pulls, so disable the internal ones.
                         */
                        emmc_clk: emmc-clk {
-                               rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>;
+                               rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>;
                        };
 
                        emmc_cmd: emmc-cmd {
-                               rockchip,pins = <2 1 RK_FUNC_2 &pcfg_pull_default>;
+                               rockchip,pins = <2 RK_PA1 2 &pcfg_pull_default>;
                        };
 
                        emmc_bus8: emmc-bus8 {
-                               rockchip,pins = <1 24 RK_FUNC_2 &pcfg_pull_default>,
-                                               <1 25 RK_FUNC_2 &pcfg_pull_default>,
-                                               <1 26 RK_FUNC_2 &pcfg_pull_default>,
-                                               <1 27 RK_FUNC_2 &pcfg_pull_default>,
-                                               <1 28 RK_FUNC_2 &pcfg_pull_default>,
-                                               <1 29 RK_FUNC_2 &pcfg_pull_default>,
-                                               <1 30 RK_FUNC_2 &pcfg_pull_default>,
-                                               <1 31 RK_FUNC_2 &pcfg_pull_default>;
+                               rockchip,pins = <1 RK_PD0 2 &pcfg_pull_default>,
+                                               <1 RK_PD1 2 &pcfg_pull_default>,
+                                               <1 RK_PD2 2 &pcfg_pull_default>,
+                                               <1 RK_PD3 2 &pcfg_pull_default>,
+                                               <1 RK_PD4 2 &pcfg_pull_default>,
+                                               <1 RK_PD5 2 &pcfg_pull_default>,
+                                               <1 RK_PD6 2 &pcfg_pull_default>,
+                                               <1 RK_PD7 2 &pcfg_pull_default>;
                        };
                };
 
                emac {
                        emac_xfer: emac-xfer {
-                               rockchip,pins = <2 10 RK_FUNC_1 &pcfg_pull_default>, /* crs_dvalid */
-                                               <2 13 RK_FUNC_1 &pcfg_pull_default>, /* tx_en */
-                                               <2 14 RK_FUNC_1 &pcfg_pull_default>, /* mac_clk */
-                                               <2 15 RK_FUNC_1 &pcfg_pull_default>, /* rx_err */
-                                               <2 16 RK_FUNC_1 &pcfg_pull_default>, /* rxd1 */
-                                               <2 17 RK_FUNC_1 &pcfg_pull_default>, /* rxd0 */
-                                               <2 18 RK_FUNC_1 &pcfg_pull_default>, /* txd1 */
-                                               <2 19 RK_FUNC_1 &pcfg_pull_default>; /* txd0 */
+                               rockchip,pins = <2 RK_PB2 1 &pcfg_pull_default>, /* crs_dvalid */
+                                               <2 RK_PB5 1 &pcfg_pull_default>, /* tx_en */
+                                               <2 RK_PB6 1 &pcfg_pull_default>, /* mac_clk */
+                                               <2 RK_PB7 1 &pcfg_pull_default>, /* rx_err */
+                                               <2 RK_PC0 1 &pcfg_pull_default>, /* rxd1 */
+                                               <2 RK_PC1 1 &pcfg_pull_default>, /* rxd0 */
+                                               <2 RK_PC2 1 &pcfg_pull_default>, /* txd1 */
+                                               <2 RK_PC3 1 &pcfg_pull_default>; /* txd0 */
                        };
 
                        emac_mdio: emac-mdio {
-                               rockchip,pins = <2 12 RK_FUNC_1 &pcfg_pull_default>, /* mac_md */
-                                               <2 25 RK_FUNC_1 &pcfg_pull_default>; /* mac_mdclk */
+                               rockchip,pins = <2 RK_PB4 1 &pcfg_pull_default>, /* mac_md */
+                                               <2 RK_PD1 1 &pcfg_pull_default>; /* mac_mdclk */
                        };
                };
 
                i2c0 {
                        i2c0_xfer: i2c0-xfer {
-                               rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>,
-                                               <0 1 RK_FUNC_1 &pcfg_pull_none>;
+                               rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>,
+                                               <0 RK_PA1 1 &pcfg_pull_none>;
                        };
                };
 
                i2c1 {
                        i2c1_xfer: i2c1-xfer {
-                               rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_none>,
-                                               <0 3 RK_FUNC_1 &pcfg_pull_none>;
+                               rockchip,pins = <0 RK_PA2 1 &pcfg_pull_none>,
+                                               <0 RK_PA3 1 &pcfg_pull_none>;
                        };
                };
 
                i2c2 {
                        i2c2_xfer: i2c2-xfer {
-                               rockchip,pins = <2 20 RK_FUNC_1 &pcfg_pull_none>,
-                                               <2 21 RK_FUNC_1 &pcfg_pull_none>;
+                               rockchip,pins = <2 RK_PC4 1 &pcfg_pull_none>,
+                                               <2 RK_PC5 1 &pcfg_pull_none>;
                        };
                };
 
                i2s {
                        i2s_bus: i2s-bus {
-                               rockchip,pins = <1 0 RK_FUNC_1 &pcfg_pull_default>,
-                                               <1 1 RK_FUNC_1 &pcfg_pull_default>,
-                                               <1 2 RK_FUNC_1 &pcfg_pull_default>,
-                                               <1 3 RK_FUNC_1 &pcfg_pull_default>,
-                                               <1 4 RK_FUNC_1 &pcfg_pull_default>,
-                                               <1 5 RK_FUNC_1 &pcfg_pull_default>;
+                               rockchip,pins = <1 RK_PA0 1 &pcfg_pull_default>,
+                                               <1 RK_PA1 1 &pcfg_pull_default>,
+                                               <1 RK_PA2 1 &pcfg_pull_default>,
+                                               <1 RK_PA3 1 &pcfg_pull_default>,
+                                               <1 RK_PA4 1 &pcfg_pull_default>,
+                                               <1 RK_PA5 1 &pcfg_pull_default>;
                        };
                };
 
                hdmi {
                        hdmi_ctl: hdmi-ctl {
-                               rockchip,pins = <1 8  RK_FUNC_1 &pcfg_pull_none>,
-                                               <1 9  RK_FUNC_1 &pcfg_pull_none>,
-                                               <1 10 RK_FUNC_1 &pcfg_pull_none>,
-                                               <1 11 RK_FUNC_1 &pcfg_pull_none>;
+                               rockchip,pins = <1 RK_PB0  1 &pcfg_pull_none>,
+                                               <1 RK_PB1  1 &pcfg_pull_none>,
+                                               <1 RK_PB2 1 &pcfg_pull_none>,
+                                               <1 RK_PB3 1 &pcfg_pull_none>;
                        };
                };
 
                uart0 {
                        uart0_xfer: uart0-xfer {
-                               rockchip,pins = <0 16 RK_FUNC_1 &pcfg_pull_default>,
-                                               <0 17 RK_FUNC_1 &pcfg_pull_none>;
+                               rockchip,pins = <0 RK_PC0 1 &pcfg_pull_default>,
+                                               <0 RK_PC1 1 &pcfg_pull_none>;
                        };
 
                        uart0_cts: uart0-cts {
-                               rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_default>;
+                               rockchip,pins = <0 RK_PC2 1 &pcfg_pull_default>;
                        };
 
                        uart0_rts: uart0-rts {
-                               rockchip,pins = <0 19 RK_FUNC_1 &pcfg_pull_none>;
+                               rockchip,pins = <0 RK_PC3 1 &pcfg_pull_none>;
                        };
                };
 
                uart1 {
                        uart1_xfer: uart1-xfer {
-                               rockchip,pins = <2 22 RK_FUNC_1 &pcfg_pull_default>,
-                                               <2 23 RK_FUNC_1 &pcfg_pull_none>;
+                               rockchip,pins = <2 RK_PC6 1 &pcfg_pull_default>,
+                                               <2 RK_PC7 1 &pcfg_pull_none>;
                        };
                        /* no rts / cts for uart1 */
                };
 
                uart2 {
                        uart2_xfer: uart2-xfer {
-                               rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_default>,
-                                               <1 19 RK_FUNC_2 &pcfg_pull_none>;
+                               rockchip,pins = <1 RK_PC2 2 &pcfg_pull_default>,
+                                               <1 RK_PC3 2 &pcfg_pull_none>;
                        };
                        /* no rts / cts for uart2 */
                };
 
                spi-pins {
                        spi_txd:spi-txd {
-                               rockchip,pins = <1 29 RK_FUNC_3 &pcfg_pull_default>;
+                               rockchip,pins = <1 RK_PD5 3 &pcfg_pull_default>;
                        };
 
                        spi_rxd:spi-rxd {
-                               rockchip,pins = <1 28 RK_FUNC_3 &pcfg_pull_default>;
+                               rockchip,pins = <1 RK_PD4 3 &pcfg_pull_default>;
                        };
 
                        spi_clk:spi-clk {
-                               rockchip,pins = <2 0 RK_FUNC_2 &pcfg_pull_default>;
+                               rockchip,pins = <2 RK_PA0 2 &pcfg_pull_default>;
                        };
 
                        spi_cs0:spi-cs0 {
-                               rockchip,pins = <1 30 RK_FUNC_3 &pcfg_pull_default>;
+                               rockchip,pins = <1 RK_PD6 3 &pcfg_pull_default>;
 
                        };
 
                        spi_cs1:spi-cs1 {
-                               rockchip,pins = <1 31 RK_FUNC_3 &pcfg_pull_default>;
+                               rockchip,pins = <1 RK_PD7 3 &pcfg_pull_default>;
 
                        };
                };

diff --git a/arch/arm/boot/dts/rk3066a-marsboard.dts b/arch/arm/boot/dts/rk3066a-marsboard.dts
index ce525b9..7e01f64 100644 (file)
--- a/arch/arm/boot/dts/rk3066a-marsboard.dts
+++ b/arch/arm/boot/dts/rk3066a-marsboard.dts
@@ -168,7 +168,7 @@
 &pinctrl {
        lan8720a {
                phy_int: phy-int {
-                       rockchip,pins = <RK_GPIO1 26 RK_FUNC_GPIO &pcfg_pull_none>;
+                       rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
                };
        };
 };

diff --git a/arch/arm/boot/dts/rk3066a-mk808.dts b/arch/arm/boot/dts/rk3066a-mk808.dts
index 9d2216d..365eff6 100644 (file)
--- a/arch/arm/boot/dts/rk3066a-mk808.dts
+++ b/arch/arm/boot/dts/rk3066a-mk808.dts
@@ -30,6 +30,17 @@
                };
        };
 
+       hdmi_con {
+               compatible = "hdmi-connector";
+               type = "c";
+
+               port {
+                       hdmi_con_in: endpoint {
+                               remote-endpoint = <&hdmi_out_con>;
+                       };
+               };
+       };
+
        vcc_io: vcc-io {
                compatible = "regulator-fixed";
                regulator-name = "vcc_io";
@@ -91,6 +102,20 @@
        };
 };
 
+&hdmi {
+       status = "okay";
+};
+
+&hdmi_in_vop1 {
+       status = "disabled";
+};
+
+&hdmi_out {
+       hdmi_out_con: endpoint {
+               remote-endpoint = <&hdmi_con_in>;
+       };
+};
+
 &mmc0 {
        bus-width = <4>;
        cap-mmc-highspeed;
@@ -111,25 +136,25 @@
 &pinctrl {
        usb-host {
                host_drv: host-drv {
-                       rockchip,pins = <RK_GPIO0 6 RK_FUNC_GPIO &pcfg_pull_default>;
+                       rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_default>;
                };
        };
 
        usb-otg {
                otg_drv: otg-drv {
-                       rockchip,pins = <RK_GPIO0 5 RK_FUNC_GPIO &pcfg_pull_default>;
+                       rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_default>;
                };
        };
 
        sdmmc {
                sdmmc_pwr: sdmmc-pwr {
-                       rockchip,pins = <RK_GPIO3 7 RK_FUNC_GPIO &pcfg_pull_default>;
+                       rockchip,pins = <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_default>;
                };
        };
 
        sdio {
                wifi_pwr: wifi-pwr {
-                       rockchip,pins = <RK_GPIO3 24 RK_FUNC_GPIO &pcfg_pull_none>;
+                       rockchip,pins = <3 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
                };
        };
 };
@@ -150,6 +175,10 @@
        status = "okay";
 };
 
+&vop0 {
+       status = "okay";
+};
+
 &wdt {
        status = "okay";
 };

diff --git a/arch/arm/boot/dts/rk3066a-rayeager.dts b/arch/arm/boot/dts/rk3066a-rayeager.dts
index 949fa80..f9db6bb 100644 (file)
--- a/arch/arm/boot/dts/rk3066a-rayeager.dts
+++ b/arch/arm/boot/dts/rk3066a-rayeager.dts
@@ -322,71 +322,71 @@
 
        ak8963 {
                comp_int: comp-int {
-                       rockchip,pins = <4 17 RK_FUNC_GPIO &pcfg_pull_default>;
+                       rockchip,pins = <4 RK_PC1 RK_FUNC_GPIO &pcfg_pull_default>;
                };
        };
 
        emac {
                rmii_rst: rmii-rst {
-                       rockchip,pins = <1 30 RK_FUNC_GPIO &pcfg_output_high>;
+                       rockchip,pins = <1 RK_PD6 RK_FUNC_GPIO &pcfg_output_high>;
                };
        };
 
        ir {
                ir_int: ir-int {
-                       rockchip,pins = <6 1 RK_FUNC_GPIO &pcfg_pull_default>;
+                       rockchip,pins = <6 RK_PA1 RK_FUNC_GPIO &pcfg_pull_default>;
                };
        };
 
        keys {
                pwr_key: pwr-key {
-                       rockchip,pins = <6 2 RK_FUNC_GPIO &pcfg_pull_default>;
+                       rockchip,pins = <6 RK_PA2 RK_FUNC_GPIO &pcfg_pull_default>;
                };
        };
 
        mma8452 {
                gsensor_int: gsensor-int {
-                       rockchip,pins = <4 16 RK_FUNC_GPIO &pcfg_pull_default>;
+                       rockchip,pins = <4 RK_PC0 RK_FUNC_GPIO &pcfg_pull_default>;
                };
        };
 
        mmc {
                sdmmc_pwr: sdmmc-pwr {
-                       rockchip,pins = <3 7 RK_FUNC_GPIO &pcfg_pull_default>;
+                       rockchip,pins = <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_default>;
                };
        };
 
        usb_host {
                host_drv: host-drv {
-                       rockchip,pins = <0 6 RK_FUNC_GPIO &pcfg_pull_default>;
+                       rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_default>;
                };
 
                hub_rst: hub-rst {
-                       rockchip,pins = <1 31 RK_FUNC_GPIO &pcfg_output_high>;
+                       rockchip,pins = <1 RK_PD7 RK_FUNC_GPIO &pcfg_output_high>;
                };
 
                sata_pwr: sata-pwr {
-                       rockchip,pins = <4 22 RK_FUNC_GPIO &pcfg_pull_default>;
+                       rockchip,pins = <4 RK_PC6 RK_FUNC_GPIO &pcfg_pull_default>;
                };
 
                sata_reset: sata-reset {
-                       rockchip,pins = <0 13 RK_FUNC_GPIO &pcfg_output_high>;
+                       rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_output_high>;
                };
        };
 
        usb_otg {
                otg_drv: otg-drv {
-                       rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_default>;
+                       rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_default>;
                };
        };
 
        tps {
                pmic_int: pmic-int {
-                       rockchip,pins = <6 4 RK_FUNC_GPIO &pcfg_pull_default>;
+                       rockchip,pins = <6 RK_PA4 RK_FUNC_GPIO &pcfg_pull_default>;
                };
 
                pwr_hold: pwr-hold {
-                       rockchip,pins = <6 8 RK_FUNC_GPIO &pcfg_output_high>;
+                       rockchip,pins = <6 RK_PB0 RK_FUNC_GPIO &pcfg_output_high>;
                };
        };
 };

diff --git a/arch/arm/boot/dts/rk3066a.dtsi b/arch/arm/boot/dts/rk3066a.dtsi
index 653127a..3d1b02f 100644 (file)
--- a/arch/arm/boot/dts/rk3066a.dtsi
+++ b/arch/arm/boot/dts/rk3066a.dtsi
@@ -80,6 +80,11 @@
                vop0_out: port {
                        #address-cells = <1>;
                        #size-cells = <0>;
+
+                       vop0_out_hdmi: endpoint@0 {
+                               reg = <0>;
+                               remote-endpoint = <&hdmi_in_vop0>;
+                       };
                };
        };
 
@@ -101,6 +106,49 @@
                vop1_out: port {
                        #address-cells = <1>;
                        #size-cells = <0>;
+
+                       vop1_out_hdmi: endpoint@0 {
+                               reg = <0>;
+                               remote-endpoint = <&hdmi_in_vop1>;
+                       };
+               };
+       };
+
+       hdmi: hdmi@10116000 {
+               compatible = "rockchip,rk3066-hdmi";
+               reg = <0x10116000 0x2000>;
+               interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&cru HCLK_HDMI>;
+               clock-names = "hclk";
+               pinctrl-names = "default";
+               pinctrl-0 = <&hdmii2c_xfer>, <&hdmi_hpd>;
+               power-domains = <&power RK3066_PD_VIO>;
+               rockchip,grf = <&grf>;
+               status = "disabled";
+
+               ports {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+
+                       hdmi_in: port@0 {
+                               reg = <0>;
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+
+                               hdmi_in_vop0: endpoint@0 {
+                                       reg = <0>;
+                                       remote-endpoint = <&vop0_out_hdmi>;
+                               };
+
+                               hdmi_in_vop1: endpoint@1 {
+                                       reg = <1>;
+                                       remote-endpoint = <&vop1_out_hdmi>;
+                               };
+                       };
+
+                       hdmi_out: port@1 {
+                               reg = <1>;
+                       };
                };
        };
 
@@ -343,33 +391,33 @@
 
                emac {
                        emac_xfer: emac-xfer {
-                               rockchip,pins = <RK_GPIO1 16 RK_FUNC_2 &pcfg_pull_none>, /* mac_clk */
-                                               <RK_GPIO1 17 RK_FUNC_2 &pcfg_pull_none>, /* tx_en */
-                                               <RK_GPIO1 18 RK_FUNC_2 &pcfg_pull_none>, /* txd1 */
-                                               <RK_GPIO1 19 RK_FUNC_2 &pcfg_pull_none>, /* txd0 */
-                                               <RK_GPIO1 20 RK_FUNC_2 &pcfg_pull_none>, /* rx_err */
-                                               <RK_GPIO1 21 RK_FUNC_2 &pcfg_pull_none>, /* crs_dvalid */
-                                               <RK_GPIO1 22 RK_FUNC_2 &pcfg_pull_none>, /* rxd1 */
-                                               <RK_GPIO1 23 RK_FUNC_2 &pcfg_pull_none>; /* rxd0 */
+                               rockchip,pins = <1 RK_PC0 2 &pcfg_pull_none>, /* mac_clk */
+                                               <1 RK_PC1 2 &pcfg_pull_none>, /* tx_en */
+                                               <1 RK_PC2 2 &pcfg_pull_none>, /* txd1 */
+                                               <1 RK_PC3 2 &pcfg_pull_none>, /* txd0 */
+                                               <1 RK_PC4 2 &pcfg_pull_none>, /* rx_err */
+                                               <1 RK_PC5 2 &pcfg_pull_none>, /* crs_dvalid */
+                                               <1 RK_PC6 2 &pcfg_pull_none>, /* rxd1 */
+                                               <1 RK_PC7 2 &pcfg_pull_none>; /* rxd0 */
                        };
 
                        emac_mdio: emac-mdio {
-                               rockchip,pins = <RK_GPIO1 24 RK_FUNC_2 &pcfg_pull_none>, /* mac_md */
-                                               <RK_GPIO1 25 RK_FUNC_2 &pcfg_pull_none>; /* mac_mdclk */
+                               rockchip,pins = <1 RK_PD0 2 &pcfg_pull_none>, /* mac_md */
+                                               <1 RK_PD1 2 &pcfg_pull_none>; /* mac_mdclk */
                        };
                };
 
                emmc {
                        emmc_clk: emmc-clk {
-                               rockchip,pins = <RK_GPIO3 31 RK_FUNC_2 &pcfg_pull_default>;
+                               rockchip,pins = <3 RK_PD7 2 &pcfg_pull_default>;
                        };
 
                        emmc_cmd: emmc-cmd {
-                               rockchip,pins = <RK_GPIO4 9 RK_FUNC_2 &pcfg_pull_default>;
+                               rockchip,pins = <4 RK_PB1 2 &pcfg_pull_default>;
                        };
 
                        emmc_rst: emmc-rst {
-                               rockchip,pins = <RK_GPIO4 10 RK_FUNC_2 &pcfg_pull_default>;
+                               rockchip,pins = <4 RK_PB2 2 &pcfg_pull_default>;
                        };
 
                        /*
@@ -380,245 +428,256 @@
                         */
                };
 
+               hdmi {
+                       hdmi_hpd: hdmi-hpd {
+                               rockchip,pins = <0 RK_PA0 1 &pcfg_pull_default>;
+                       };
+
+                       hdmii2c_xfer: hdmii2c-xfer {
+                               rockchip,pins = <0 RK_PA1 1 &pcfg_pull_none>,
+                                               <0 RK_PA2 1 &pcfg_pull_none>;
+                       };
+               };
+
                i2c0 {
                        i2c0_xfer: i2c0-xfer {
-                               rockchip,pins = <RK_GPIO2 28 RK_FUNC_1 &pcfg_pull_none>,
-                                               <RK_GPIO2 29 RK_FUNC_1 &pcfg_pull_none>;
+                               rockchip,pins = <2 RK_PD4 1 &pcfg_pull_none>,
+                                               <2 RK_PD5 1 &pcfg_pull_none>;
                        };
                };
 
                i2c1 {
                        i2c1_xfer: i2c1-xfer {
-                               rockchip,pins = <RK_GPIO2 30 RK_FUNC_1 &pcfg_pull_none>,
-                                               <RK_GPIO2 31 RK_FUNC_1 &pcfg_pull_none>;
+                               rockchip,pins = <2 RK_PD6 1 &pcfg_pull_none>,
+                                               <2 RK_PD7 1 &pcfg_pull_none>;
                        };
                };
 
                i2c2 {
                        i2c2_xfer: i2c2-xfer {
-                               rockchip,pins = <RK_GPIO3 0 RK_FUNC_1 &pcfg_pull_none>,
-                                               <RK_GPIO3 1 RK_FUNC_1 &pcfg_pull_none>;
+                               rockchip,pins = <3 RK_PA0 1 &pcfg_pull_none>,
+                                               <3 RK_PA1 1 &pcfg_pull_none>;
                        };
                };
 
                i2c3 {
                        i2c3_xfer: i2c3-xfer {
-                               rockchip,pins = <RK_GPIO3 2 RK_FUNC_2 &pcfg_pull_none>,
-                                               <RK_GPIO3 3 RK_FUNC_2 &pcfg_pull_none>;
+                               rockchip,pins = <3 RK_PA2 2 &pcfg_pull_none>,
+                                               <3 RK_PA3 2 &pcfg_pull_none>;
                        };
                };
 
                i2c4 {
                        i2c4_xfer: i2c4-xfer {
-                               rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>,
-                                               <RK_GPIO3 5 RK_FUNC_1 &pcfg_pull_none>;
+                               rockchip,pins = <3 RK_PA4 1 &pcfg_pull_none>,
+                                               <3 RK_PA5 1 &pcfg_pull_none>;
                        };
                };
 
                pwm0 {
                        pwm0_out: pwm0-out {
-                               rockchip,pins = <RK_GPIO0 3 RK_FUNC_1 &pcfg_pull_none>;
+                               rockchip,pins = <0 RK_PA3 1 &pcfg_pull_none>;
                        };
                };
 
                pwm1 {
                        pwm1_out: pwm1-out {
-                               rockchip,pins = <RK_GPIO0 4 RK_FUNC_1 &pcfg_pull_none>;
+                               rockchip,pins = <0 RK_PA4 1 &pcfg_pull_none>;
                        };
                };
 
                pwm2 {
                        pwm2_out: pwm2-out {
-                               rockchip,pins = <RK_GPIO0 30 RK_FUNC_1 &pcfg_pull_none>;
+                               rockchip,pins = <0 RK_PD6 1 &pcfg_pull_none>;
                        };
                };
 
                pwm3 {
                        pwm3_out: pwm3-out {
-                               rockchip,pins = <RK_GPIO0 31 RK_FUNC_1 &pcfg_pull_none>;
+                               rockchip,pins = <0 RK_PD7 1 &pcfg_pull_none>;
                        };
                };
 
                spi0 {
                        spi0_clk: spi0-clk {
-                               rockchip,pins = <RK_GPIO1 5 RK_FUNC_2 &pcfg_pull_default>;
+                               rockchip,pins = <1 RK_PA5 2 &pcfg_pull_default>;
                        };
                        spi0_cs0: spi0-cs0 {
-                               rockchip,pins = <RK_GPIO1 4 RK_FUNC_2 &pcfg_pull_default>;
+                               rockchip,pins = <1 RK_PA4 2 &pcfg_pull_default>;
                        };
                        spi0_tx: spi0-tx {
-                               rockchip,pins = <RK_GPIO1 7 RK_FUNC_2 &pcfg_pull_default>;
+                               rockchip,pins = <1 RK_PA7 2 &pcfg_pull_default>;
                        };
                        spi0_rx: spi0-rx {
-                               rockchip,pins = <RK_GPIO1 6 RK_FUNC_2 &pcfg_pull_default>;
+                               rockchip,pins = <1 RK_PA6 2 &pcfg_pull_default>;
                        };
                        spi0_cs1: spi0-cs1 {
-                               rockchip,pins = <RK_GPIO4 15 RK_FUNC_1 &pcfg_pull_default>;
+                               rockchip,pins = <4 RK_PB7 1 &pcfg_pull_default>;
                        };
                };
 
                spi1 {
                        spi1_clk: spi1-clk {
-                               rockchip,pins = <RK_GPIO2 19 RK_FUNC_2 &pcfg_pull_default>;
+                               rockchip,pins = <2 RK_PC3 2 &pcfg_pull_default>;
                        };
                        spi1_cs0: spi1-cs0 {
-                               rockchip,pins = <RK_GPIO2 20 RK_FUNC_2 &pcfg_pull_default>;
+                               rockchip,pins = <2 RK_PC4 2 &pcfg_pull_default>;
                        };
                        spi1_rx: spi1-rx {
-                               rockchip,pins = <RK_GPIO2 22 RK_FUNC_2 &pcfg_pull_default>;
+                               rockchip,pins = <2 RK_PC6 2 &pcfg_pull_default>;
                        };
                        spi1_tx: spi1-tx {
-                               rockchip,pins = <RK_GPIO2 21 RK_FUNC_2 &pcfg_pull_default>;
+                               rockchip,pins = <2 RK_PC5 2 &pcfg_pull_default>;
                        };
                        spi1_cs1: spi1-cs1 {
-                               rockchip,pins = <RK_GPIO2 23 RK_FUNC_2 &pcfg_pull_default>;
+                               rockchip,pins = <2 RK_PC7 2 &pcfg_pull_default>;
                        };
                };
 
                uart0 {
                        uart0_xfer: uart0-xfer {
-                               rockchip,pins = <RK_GPIO1 0 RK_FUNC_1 &pcfg_pull_default>,
-                                               <RK_GPIO1 1 RK_FUNC_1 &pcfg_pull_default>;
+                               rockchip,pins = <1 RK_PA0 1 &pcfg_pull_default>,
+                                               <1 RK_PA1 1 &pcfg_pull_default>;
                        };
 
                        uart0_cts: uart0-cts {
-                               rockchip,pins = <RK_GPIO1 2 RK_FUNC_1 &pcfg_pull_default>;
+                               rockchip,pins = <1 RK_PA2 1 &pcfg_pull_default>;
                        };
 
                        uart0_rts: uart0-rts {
-                               rockchip,pins = <RK_GPIO1 3 RK_FUNC_1 &pcfg_pull_default>;
+                               rockchip,pins = <1 RK_PA3 1 &pcfg_pull_default>;
                        };
                };
 
                uart1 {
                        uart1_xfer: uart1-xfer {
-                               rockchip,pins = <RK_GPIO1 4 RK_FUNC_1 &pcfg_pull_default>,
-                                               <RK_GPIO1 5 RK_FUNC_1 &pcfg_pull_default>;
+                               rockchip,pins = <1 RK_PA4 1 &pcfg_pull_default>,
+                                               <1 RK_PA5 1 &pcfg_pull_default>;
                        };
 
                        uart1_cts: uart1-cts {
-                               rockchip,pins = <RK_GPIO1 6 RK_FUNC_1 &pcfg_pull_default>;
+                               rockchip,pins = <1 RK_PA6 1 &pcfg_pull_default>;
                        };
 
                        uart1_rts: uart1-rts {
-                               rockchip,pins = <RK_GPIO1 7 RK_FUNC_1 &pcfg_pull_default>;
+                               rockchip,pins = <1 RK_PA7 1 &pcfg_pull_default>;
                        };
                };
 
                uart2 {
                        uart2_xfer: uart2-xfer {
-                               rockchip,pins = <RK_GPIO1 8 RK_FUNC_1 &pcfg_pull_default>,
-                                               <RK_GPIO1 9 RK_FUNC_1 &pcfg_pull_default>;
+                               rockchip,pins = <1 RK_PB0 1 &pcfg_pull_default>,
+                                               <1 RK_PB1 1 &pcfg_pull_default>;
                        };
                        /* no rts / cts for uart2 */
                };
 
                uart3 {
                        uart3_xfer: uart3-xfer {
-                               rockchip,pins = <RK_GPIO3 27 RK_FUNC_1 &pcfg_pull_default>,
-                                               <RK_GPIO3 28 RK_FUNC_1 &pcfg_pull_default>;
+                               rockchip,pins = <3 RK_PD3 1 &pcfg_pull_default>,
+                                               <3 RK_PD4 1 &pcfg_pull_default>;
                        };
 
                        uart3_cts: uart3-cts {
-                               rockchip,pins = <RK_GPIO3 29 RK_FUNC_1 &pcfg_pull_default>;
+                               rockchip,pins = <3 RK_PD5 1 &pcfg_pull_default>;
                        };
 
                        uart3_rts: uart3-rts {
-                               rockchip,pins = <RK_GPIO3 30 RK_FUNC_1 &pcfg_pull_default>;
+                               rockchip,pins = <3 RK_PD6 1 &pcfg_pull_default>;
                        };
                };
 
                sd0 {
                        sd0_clk: sd0-clk {
-                               rockchip,pins = <RK_GPIO3 8 RK_FUNC_1 &pcfg_pull_default>;
+                               rockchip,pins = <3 RK_PB0 1 &pcfg_pull_default>;
                        };
 
                        sd0_cmd: sd0-cmd {
-                               rockchip,pins = <RK_GPIO3 9 RK_FUNC_1 &pcfg_pull_default>;
+                               rockchip,pins = <3 RK_PB1 1 &pcfg_pull_default>;
                        };
 
                        sd0_cd: sd0-cd {
-                               rockchip,pins = <RK_GPIO3 14 RK_FUNC_1 &pcfg_pull_default>;
+                               rockchip,pins = <3 RK_PB6 1 &pcfg_pull_default>;
                        };
 
                        sd0_wp: sd0-wp {
-                               rockchip,pins = <RK_GPIO3 15 RK_FUNC_1 &pcfg_pull_default>;
+                               rockchip,pins = <3 RK_PB7 1 &pcfg_pull_default>;
                        };
 
                        sd0_bus1: sd0-bus-width1 {
-                               rockchip,pins = <RK_GPIO3 10 RK_FUNC_1 &pcfg_pull_default>;
+                               rockchip,pins = <3 RK_PB2 1 &pcfg_pull_default>;
                        };
 
                        sd0_bus4: sd0-bus-width4 {
-                               rockchip,pins = <RK_GPIO3 10 RK_FUNC_1 &pcfg_pull_default>,
-                                               <RK_GPIO3 11 RK_FUNC_1 &pcfg_pull_default>,
-                                               <RK_GPIO3 12 RK_FUNC_1 &pcfg_pull_default>,
-                                               <RK_GPIO3 13 RK_FUNC_1 &pcfg_pull_default>;
+                               rockchip,pins = <3 RK_PB2 1 &pcfg_pull_default>,
+                                               <3 RK_PB3 1 &pcfg_pull_default>,
+                                               <3 RK_PB4 1 &pcfg_pull_default>,
+                                               <3 RK_PB5 1 &pcfg_pull_default>;
                        };
                };
 
                sd1 {
                        sd1_clk: sd1-clk {
-                               rockchip,pins = <RK_GPIO3 21 RK_FUNC_1 &pcfg_pull_default>;
+                               rockchip,pins = <3 RK_PC5 1 &pcfg_pull_default>;
                        };
 
                        sd1_cmd: sd1-cmd {
-                               rockchip,pins = <RK_GPIO3 16 RK_FUNC_1 &pcfg_pull_default>;
+                               rockchip,pins = <3 RK_PC0 1 &pcfg_pull_default>;
                        };
 
                        sd1_cd: sd1-cd {
-                               rockchip,pins = <RK_GPIO3 22 RK_FUNC_1 &pcfg_pull_default>;
+                               rockchip,pins = <3 RK_PC6 1 &pcfg_pull_default>;
                        };
 
                        sd1_wp: sd1-wp {
-                               rockchip,pins = <RK_GPIO3 23 RK_FUNC_1 &pcfg_pull_default>;
+                               rockchip,pins = <3 RK_PC7 1 &pcfg_pull_default>;
                        };
 
                        sd1_bus1: sd1-bus-width1 {
-                               rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_default>;
+                               rockchip,pins = <3 RK_PC1 1 &pcfg_pull_default>;
                        };
 
                        sd1_bus4: sd1-bus-width4 {
-                               rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_default>,
-                                               <RK_GPIO3 18 RK_FUNC_1 &pcfg_pull_default>,
-                                               <RK_GPIO3 19 RK_FUNC_1 &pcfg_pull_default>,
-                                               <RK_GPIO3 20 RK_FUNC_1 &pcfg_pull_default>;
+                               rockchip,pins = <3 RK_PC1 1 &pcfg_pull_default>,
+                                               <3 RK_PC2 1 &pcfg_pull_default>,
+                                               <3 RK_PC3 1 &pcfg_pull_default>,
+                                               <3 RK_PC4 1 &pcfg_pull_default>;
                        };
                };
 
                i2s0 {
                        i2s0_bus: i2s0-bus {
-                               rockchip,pins = <RK_GPIO0 7 RK_FUNC_1 &pcfg_pull_default>,
-                                               <RK_GPIO0 8 RK_FUNC_1 &pcfg_pull_default>,
-                                               <RK_GPIO0 9 RK_FUNC_1 &pcfg_pull_default>,
-                                               <RK_GPIO0 10 RK_FUNC_1 &pcfg_pull_default>,
-                                               <RK_GPIO0 11 RK_FUNC_1 &pcfg_pull_default>,
-                                               <RK_GPIO0 12 RK_FUNC_1 &pcfg_pull_default>,
-                                               <RK_GPIO0 13 RK_FUNC_1 &pcfg_pull_default>,
-                                               <RK_GPIO0 14 RK_FUNC_1 &pcfg_pull_default>,
-                                               <RK_GPIO0 15 RK_FUNC_1 &pcfg_pull_default>;
+                               rockchip,pins = <0 RK_PA7 1 &pcfg_pull_default>,
+                                               <0 RK_PB0 1 &pcfg_pull_default>,
+                                               <0 RK_PB1 1 &pcfg_pull_default>,
+                                               <0 RK_PB2 1 &pcfg_pull_default>,
+                                               <0 RK_PB3 1 &pcfg_pull_default>,
+                                               <0 RK_PB4 1 &pcfg_pull_default>,
+                                               <0 RK_PB5 1 &pcfg_pull_default>,
+                                               <0 RK_PB6 1 &pcfg_pull_default>,
+                                               <0 RK_PB7 1 &pcfg_pull_default>;
                        };
                };
 
                i2s1 {
                        i2s1_bus: i2s1-bus {
-                               rockchip,pins = <RK_GPIO0 16 RK_FUNC_1 &pcfg_pull_default>,
-                                               <RK_GPIO0 17 RK_FUNC_1 &pcfg_pull_default>,
-                                               <RK_GPIO0 18 RK_FUNC_1 &pcfg_pull_default>,
-                                               <RK_GPIO0 19 RK_FUNC_1 &pcfg_pull_default>,
-                                               <RK_GPIO0 20 RK_FUNC_1 &pcfg_pull_default>,
-                                               <RK_GPIO0 21 RK_FUNC_1 &pcfg_pull_default>;
+                               rockchip,pins = <0 RK_PC0 1 &pcfg_pull_default>,
+                                               <0 RK_PC1 1 &pcfg_pull_default>,
+                                               <0 RK_PC2 1 &pcfg_pull_default>,
+                                               <0 RK_PC3 1 &pcfg_pull_default>,
+                                               <0 RK_PC4 1 &pcfg_pull_default>,
+                                               <0 RK_PC5 1 &pcfg_pull_default>;
                        };
                };
 
                i2s2 {
                        i2s2_bus: i2s2-bus {
-                               rockchip,pins = <RK_GPIO0 24 RK_FUNC_1 &pcfg_pull_default>,
-                                               <RK_GPIO0 25 RK_FUNC_1 &pcfg_pull_default>,
-                                               <RK_GPIO0 26 RK_FUNC_1 &pcfg_pull_default>,
-                                               <RK_GPIO0 27 RK_FUNC_1 &pcfg_pull_default>,
-                                               <RK_GPIO0 28 RK_FUNC_1 &pcfg_pull_default>,
-                                               <RK_GPIO0 29 RK_FUNC_1 &pcfg_pull_default>;
+                               rockchip,pins = <0 RK_PD0 1 &pcfg_pull_default>,
+                                               <0 RK_PD1 1 &pcfg_pull_default>,
+                                               <0 RK_PD2 1 &pcfg_pull_default>,
+                                               <0 RK_PD3 1 &pcfg_pull_default>,
+                                               <0 RK_PD4 1 &pcfg_pull_default>,
+                                               <0 RK_PD5 1 &pcfg_pull_default>;
                        };
                };
        };

diff --git a/arch/arm/boot/dts/rk3188-px3-evb.dts b/arch/arm/boot/dts/rk3188-px3-evb.dts
index c0eaa9c..c32e1d4 100644 (file)
--- a/arch/arm/boot/dts/rk3188-px3-evb.dts
+++ b/arch/arm/boot/dts/rk3188-px3-evb.dts
@@ -247,10 +247,10 @@
 
        usb {
                host_vbus_drv: host-vbus-drv {
-                       rockchip,pins = <0 3 RK_FUNC_GPIO &pcfg_pull_none>;
+                       rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
                };
                otg_vbus_drv: otg-vbus-drv {
-                       rockchip,pins = <2 31 RK_FUNC_GPIO &pcfg_pull_none>;
+                       rockchip,pins = <2 RK_PD7 RK_FUNC_GPIO &pcfg_pull_none>;
                };
        };
 };

diff --git a/arch/arm/boot/dts/rk3188-radxarock.dts b/arch/arm/boot/dts/rk3188-radxarock.dts
index 94bc81c..c9a7f54 100644 (file)
--- a/arch/arm/boot/dts/rk3188-radxarock.dts
+++ b/arch/arm/boot/dts/rk3188-radxarock.dts
@@ -307,40 +307,40 @@
 
        act8846 {
                act8846_dvs0_ctl: act8846-dvs0-ctl {
-                       rockchip,pins = <RK_GPIO3 27 RK_FUNC_GPIO &pcfg_output_low>;
+                       rockchip,pins = <3 RK_PD3 RK_FUNC_GPIO &pcfg_output_low>;
                };
        };
 
        hym8563 {
                rtc_int: rtc-int {
-                       rockchip,pins = <RK_GPIO0 0 RK_FUNC_GPIO &pcfg_pull_up>;
+                       rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>;
                };
        };
 
        lan8720a  {
                phy_int: phy-int {
-                       rockchip,pins = <RK_GPIO3 26 RK_FUNC_GPIO &pcfg_pull_up>;
+                       rockchip,pins = <3 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up>;
                };
        };
 
        ir-receiver {
                ir_recv_pin: ir-recv-pin {
-                       rockchip,pins = <RK_GPIO0 10 RK_FUNC_GPIO &pcfg_pull_none>;
+                       rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
                };
        };
 
        sd0 {
                sdmmc_pwr: sdmmc-pwr {
-                       rockchip,pins = <RK_GPIO3 1 RK_FUNC_GPIO &pcfg_pull_none>;
+                       rockchip,pins = <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>;
                };
        };
 
        usb {
                host_vbus_drv: host-vbus-drv {
-                       rockchip,pins = <0 3 RK_FUNC_GPIO &pcfg_pull_none>;
+                       rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
                };
                otg_vbus_drv: otg-vbus-drv {
-                       rockchip,pins = <2 31 RK_FUNC_GPIO &pcfg_pull_none>;
+                       rockchip,pins = <2 RK_PD7 RK_FUNC_GPIO &pcfg_pull_none>;
                };
        };
 };

diff --git a/arch/arm/boot/dts/rk3188.dtsi b/arch/arm/boot/dts/rk3188.dtsi
index 3ed4989..10ede65 100644 (file)
--- a/arch/arm/boot/dts/rk3188.dtsi
+++ b/arch/arm/boot/dts/rk3188.dtsi
@@ -315,15 +315,15 @@
 
                emmc {
                        emmc_clk: emmc-clk {
-                               rockchip,pins = <RK_GPIO0 24 RK_FUNC_2 &pcfg_pull_none>;
+                               rockchip,pins = <0 RK_PD0 2 &pcfg_pull_none>;
                        };
 
                        emmc_cmd: emmc-cmd {
-                               rockchip,pins = <RK_GPIO0 26 RK_FUNC_2 &pcfg_pull_up>;
+                               rockchip,pins = <0 RK_PD2 2 &pcfg_pull_up>;
                        };
 
                        emmc_rst: emmc-rst {
-                               rockchip,pins = <RK_GPIO0 27 RK_FUNC_2 &pcfg_pull_none>;
+                               rockchip,pins = <0 RK_PD3 2 &pcfg_pull_none>;
                        };
 
                        /*
@@ -336,291 +336,291 @@
 
                emac {
                        emac_xfer: emac-xfer {
-                               rockchip,pins = <RK_GPIO3 16 RK_FUNC_2 &pcfg_pull_none>, /* tx_en */
-                                               <RK_GPIO3 17 RK_FUNC_2 &pcfg_pull_none>, /* txd1 */
-                                               <RK_GPIO3 18 RK_FUNC_2 &pcfg_pull_none>, /* txd0 */
-                                               <RK_GPIO3 19 RK_FUNC_2 &pcfg_pull_none>, /* rxd0 */
-                                               <RK_GPIO3 20 RK_FUNC_2 &pcfg_pull_none>, /* rxd1 */
-                                               <RK_GPIO3 21 RK_FUNC_2 &pcfg_pull_none>, /* mac_clk */
-                                               <RK_GPIO3 22 RK_FUNC_2 &pcfg_pull_none>, /* rx_err */
-                                               <RK_GPIO3 23 RK_FUNC_2 &pcfg_pull_none>; /* crs_dvalid */
+                               rockchip,pins = <3 RK_PC0 2 &pcfg_pull_none>, /* tx_en */
+                                               <3 RK_PC1 2 &pcfg_pull_none>, /* txd1 */
+                                               <3 RK_PC2 2 &pcfg_pull_none>, /* txd0 */
+                                               <3 RK_PC3 2 &pcfg_pull_none>, /* rxd0 */
+                                               <3 RK_PC4 2 &pcfg_pull_none>, /* rxd1 */
+                                               <3 RK_PC5 2 &pcfg_pull_none>, /* mac_clk */
+                                               <3 RK_PC6 2 &pcfg_pull_none>, /* rx_err */
+                                               <3 RK_PC7 2 &pcfg_pull_none>; /* crs_dvalid */
                        };
 
                        emac_mdio: emac-mdio {
-                               rockchip,pins = <RK_GPIO3 24 RK_FUNC_2 &pcfg_pull_none>,
-                                               <RK_GPIO3 25 RK_FUNC_2 &pcfg_pull_none>;
+                               rockchip,pins = <3 RK_PD0 2 &pcfg_pull_none>,
+                                               <3 RK_PD1 2 &pcfg_pull_none>;
                        };
                };
 
                i2c0 {
                        i2c0_xfer: i2c0-xfer {
-                               rockchip,pins = <RK_GPIO1 24 RK_FUNC_1 &pcfg_pull_none>,
-                                               <RK_GPIO1 25 RK_FUNC_1 &pcfg_pull_none>;
+                               rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>,
+                                               <1 RK_PD1 1 &pcfg_pull_none>;
                        };
                };
 
                i2c1 {
                        i2c1_xfer: i2c1-xfer {
-                               rockchip,pins = <RK_GPIO1 26 RK_FUNC_1 &pcfg_pull_none>,
-                                               <RK_GPIO1 27 RK_FUNC_1 &pcfg_pull_none>;
+                               rockchip,pins = <1 RK_PD2 1 &pcfg_pull_none>,
+                                               <1 RK_PD3 1 &pcfg_pull_none>;
                        };
                };
 
                i2c2 {
                        i2c2_xfer: i2c2-xfer {
-                               rockchip,pins = <RK_GPIO1 28 RK_FUNC_1 &pcfg_pull_none>,
-                                               <RK_GPIO1 29 RK_FUNC_1 &pcfg_pull_none>;
+                               rockchip,pins = <1 RK_PD4 1 &pcfg_pull_none>,
+                                               <1 RK_PD5 1 &pcfg_pull_none>;
                        };
                };
 
                i2c3 {
                        i2c3_xfer: i2c3-xfer {
-                               rockchip,pins = <RK_GPIO3 14 RK_FUNC_2 &pcfg_pull_none>,
-                                               <RK_GPIO3 15 RK_FUNC_2 &pcfg_pull_none>;
+                               rockchip,pins = <3 RK_PB6 2 &pcfg_pull_none>,
+                                               <3 RK_PB7 2 &pcfg_pull_none>;
                        };
                };
 
                i2c4 {
                        i2c4_xfer: i2c4-xfer {
-                               rockchip,pins = <RK_GPIO1 30 RK_FUNC_1 &pcfg_pull_none>,
-                                               <RK_GPIO1 31 RK_FUNC_1 &pcfg_pull_none>;
+                               rockchip,pins = <1 RK_PD6 1 &pcfg_pull_none>,
+                                               <1 RK_PD7 1 &pcfg_pull_none>;
                        };
                };
 
                lcdc1 {
                        lcdc1_dclk: lcdc1-dclk {
-                               rockchip,pins = <2 RK_PD0 RK_FUNC_1 &pcfg_pull_none>;
+                               rockchip,pins = <2 RK_PD0 1 &pcfg_pull_none>;
                        };
 
                        lcdc1_den: lcdc1-den {
-                               rockchip,pins = <2 RK_PD1 RK_FUNC_1 &pcfg_pull_none>;
+                               rockchip,pins = <2 RK_PD1 1 &pcfg_pull_none>;
                        };
 
                        lcdc1_hsync: lcdc1-hsync {
-                               rockchip,pins = <2 RK_PD2 RK_FUNC_1 &pcfg_pull_none>;
+                               rockchip,pins = <2 RK_PD2 1 &pcfg_pull_none>;
                        };
 
                        lcdc1_vsync: lcdc1-vsync {
-                               rockchip,pins = <2 RK_PD3 RK_FUNC_1 &pcfg_pull_none>;
+                               rockchip,pins = <2 RK_PD3 1 &pcfg_pull_none>;
                        };
 
                        lcdc1_rgb24: ldcd1-rgb24 {
-                               rockchip,pins = <2 RK_PA0 RK_FUNC_1 &pcfg_pull_none>,
-                                               <2 RK_PA1 RK_FUNC_1 &pcfg_pull_none>,
-                                               <2 RK_PA2 RK_FUNC_1 &pcfg_pull_none>,
-                                               <2 RK_PA3 RK_FUNC_1 &pcfg_pull_none>,
-                                               <2 RK_PA4 RK_FUNC_1 &pcfg_pull_none>,
-                                               <2 RK_PA5 RK_FUNC_1 &pcfg_pull_none>,
-                                               <2 RK_PA6 RK_FUNC_1 &pcfg_pull_none>,
-                                               <2 RK_PA7 RK_FUNC_1 &pcfg_pull_none>,
-                                               <2 RK_PB0 RK_FUNC_1 &pcfg_pull_none>,
-                                               <2 RK_PB1 RK_FUNC_1 &pcfg_pull_none>,
-                                               <2 RK_PB2 RK_FUNC_1 &pcfg_pull_none>,
-                                               <2 RK_PB3 RK_FUNC_1 &pcfg_pull_none>,
-                                               <2 RK_PB4 RK_FUNC_1 &pcfg_pull_none>,
-                                               <2 RK_PB5 RK_FUNC_1 &pcfg_pull_none>,
-                                               <2 RK_PB6 RK_FUNC_1 &pcfg_pull_none>,
-                                               <2 RK_PB7 RK_FUNC_1 &pcfg_pull_none>,
-                                               <2 RK_PC0 RK_FUNC_1 &pcfg_pull_none>,
-                                               <2 RK_PC1 RK_FUNC_1 &pcfg_pull_none>,
-                                               <2 RK_PC2 RK_FUNC_1 &pcfg_pull_none>,
-                                               <2 RK_PC3 RK_FUNC_1 &pcfg_pull_none>,
-                                               <2 RK_PC4 RK_FUNC_1 &pcfg_pull_none>,
-                                               <2 RK_PC5 RK_FUNC_1 &pcfg_pull_none>,
-                                               <2 RK_PC6 RK_FUNC_1 &pcfg_pull_none>,
-                                               <2 RK_PC7 RK_FUNC_1 &pcfg_pull_none>;
+                               rockchip,pins = <2 RK_PA0 1 &pcfg_pull_none>,
+                                               <2 RK_PA1 1 &pcfg_pull_none>,
+                                               <2 RK_PA2 1 &pcfg_pull_none>,
+                                               <2 RK_PA3 1 &pcfg_pull_none>,
+                                               <2 RK_PA4 1 &pcfg_pull_none>,
+                                               <2 RK_PA5 1 &pcfg_pull_none>,
+                                               <2 RK_PA6 1 &pcfg_pull_none>,
+                                               <2 RK_PA7 1 &pcfg_pull_none>,
+                                               <2 RK_PB0 1 &pcfg_pull_none>,
+                                               <2 RK_PB1 1 &pcfg_pull_none>,
+                                               <2 RK_PB2 1 &pcfg_pull_none>,
+                                               <2 RK_PB3 1 &pcfg_pull_none>,
+                                               <2 RK_PB4 1 &pcfg_pull_none>,
+                                               <2 RK_PB5 1 &pcfg_pull_none>,
+                                               <2 RK_PB6 1 &pcfg_pull_none>,
+                                               <2 RK_PB7 1 &pcfg_pull_none>,
+                                               <2 RK_PC0 1 &pcfg_pull_none>,
+                                               <2 RK_PC1 1 &pcfg_pull_none>,
+                                               <2 RK_PC2 1 &pcfg_pull_none>,
+                                               <2 RK_PC3 1 &pcfg_pull_none>,
+                                               <2 RK_PC4 1 &pcfg_pull_none>,
+                                               <2 RK_PC5 1 &pcfg_pull_none>,
+                                               <2 RK_PC6 1 &pcfg_pull_none>,
+                                               <2 RK_PC7 1 &pcfg_pull_none>;
                        };
                };
 
                pwm0 {
                        pwm0_out: pwm0-out {
-                               rockchip,pins = <RK_GPIO3 27 RK_FUNC_1 &pcfg_pull_none>;
+                               rockchip,pins = <3 RK_PD3 1 &pcfg_pull_none>;
                        };
                };
 
                pwm1 {
                        pwm1_out: pwm1-out {
-                               rockchip,pins = <RK_GPIO3 28 RK_FUNC_1 &pcfg_pull_none>;
+                               rockchip,pins = <3 RK_PD4 1 &pcfg_pull_none>;
                        };
                };
 
                pwm2 {
                        pwm2_out: pwm2-out {
-                               rockchip,pins = <RK_GPIO3 29 RK_FUNC_1 &pcfg_pull_none>;
+                               rockchip,pins = <3 RK_PD5 1 &pcfg_pull_none>;
                        };
                };
 
                pwm3 {
                        pwm3_out: pwm3-out {
-                               rockchip,pins = <RK_GPIO3 30 RK_FUNC_1 &pcfg_pull_none>;
+                               rockchip,pins = <3 RK_PD6 1 &pcfg_pull_none>;
                        };
                };
 
                spi0 {
                        spi0_clk: spi0-clk {
-                               rockchip,pins = <RK_GPIO1 6 RK_FUNC_2 &pcfg_pull_up>;
+                               rockchip,pins = <1 RK_PA6 2 &pcfg_pull_up>;
                        };
                        spi0_cs0: spi0-cs0 {
-                               rockchip,pins = <RK_GPIO1 7 RK_FUNC_2 &pcfg_pull_up>;
+                               rockchip,pins = <1 RK_PA7 2 &pcfg_pull_up>;
                        };
                        spi0_tx: spi0-tx {
-                               rockchip,pins = <RK_GPIO1 5 RK_FUNC_2 &pcfg_pull_up>;
+                               rockchip,pins = <1 RK_PA5 2 &pcfg_pull_up>;
                        };
                        spi0_rx: spi0-rx {
-                               rockchip,pins = <RK_GPIO1 4 RK_FUNC_2 &pcfg_pull_up>;
+                               rockchip,pins = <1 RK_PA4 2 &pcfg_pull_up>;
                        };
                        spi0_cs1: spi0-cs1 {
-                               rockchip,pins = <RK_GPIO1 15 RK_FUNC_1 &pcfg_pull_up>;
+                               rockchip,pins = <1 RK_PB7 1 &pcfg_pull_up>;
                        };
                };
 
                spi1 {
                        spi1_clk: spi1-clk {
-                               rockchip,pins = <RK_GPIO0 30 RK_FUNC_1 &pcfg_pull_up>;
+                               rockchip,pins = <0 RK_PD6 1 &pcfg_pull_up>;
                        };
                        spi1_cs0: spi1-cs0 {
-                               rockchip,pins = <RK_GPIO0 31 RK_FUNC_1 &pcfg_pull_up>;
+                               rockchip,pins = <0 RK_PD7 1 &pcfg_pull_up>;
                        };
                        spi1_rx: spi1-rx {
-                               rockchip,pins = <RK_GPIO0 28 RK_FUNC_1 &pcfg_pull_up>;
+                               rockchip,pins = <0 RK_PD4 1 &pcfg_pull_up>;
                        };
                        spi1_tx: spi1-tx {
-                               rockchip,pins = <RK_GPIO0 29 RK_FUNC_1 &pcfg_pull_up>;
+                               rockchip,pins = <0 RK_PD5 1 &pcfg_pull_up>;
                        };
                        spi1_cs1: spi1-cs1 {
-                               rockchip,pins = <RK_GPIO1 14 RK_FUNC_2 &pcfg_pull_up>;
+                               rockchip,pins = <1 RK_PB6 2 &pcfg_pull_up>;
                        };
                };
 
                uart0 {
                        uart0_xfer: uart0-xfer {
-                               rockchip,pins = <RK_GPIO1 0 RK_FUNC_1 &pcfg_pull_up>,
-                                               <RK_GPIO1 1 RK_FUNC_1 &pcfg_pull_none>;
+                               rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up>,
+                                               <1 RK_PA1 1 &pcfg_pull_none>;
                        };
 
                        uart0_cts: uart0-cts {
-                               rockchip,pins = <RK_GPIO1 2 RK_FUNC_1 &pcfg_pull_none>;
+                               rockchip,pins = <1 RK_PA2 1 &pcfg_pull_none>;
                        };
 
                        uart0_rts: uart0-rts {
-                               rockchip,pins = <RK_GPIO1 3 RK_FUNC_1 &pcfg_pull_none>;
+                               rockchip,pins = <1 RK_PA3 1 &pcfg_pull_none>;
                        };
                };
 
                uart1 {
                        uart1_xfer: uart1-xfer {
-                               rockchip,pins = <RK_GPIO1 4 RK_FUNC_1 &pcfg_pull_up>,
-                                               <RK_GPIO1 5 RK_FUNC_1 &pcfg_pull_none>;
+                               rockchip,pins = <1 RK_PA4 1 &pcfg_pull_up>,
+                                               <1 RK_PA5 1 &pcfg_pull_none>;
                        };
 
                        uart1_cts: uart1-cts {
-                               rockchip,pins = <RK_GPIO1 6 RK_FUNC_1 &pcfg_pull_none>;
+                               rockchip,pins = <1 RK_PA6 1 &pcfg_pull_none>;
                        };
 
                        uart1_rts: uart1-rts {
-                               rockchip,pins = <RK_GPIO1 7 RK_FUNC_1 &pcfg_pull_none>;
+                               rockchip,pins = <1 RK_PA7 1 &pcfg_pull_none>;
                        };
                };
 
                uart2 {
                        uart2_xfer: uart2-xfer {
-                               rockchip,pins = <RK_GPIO1 8 RK_FUNC_1 &pcfg_pull_up>,
-                                               <RK_GPIO1 9 RK_FUNC_1 &pcfg_pull_none>;
+                               rockchip,pins = <1 RK_PB0 1 &pcfg_pull_up>,
+                                               <1 RK_PB1 1 &pcfg_pull_none>;
                        };
                        /* no rts / cts for uart2 */
                };
 
                uart3 {
                        uart3_xfer: uart3-xfer {
-                               rockchip,pins = <RK_GPIO1 10 RK_FUNC_1 &pcfg_pull_up>,
-                                               <RK_GPIO1 11 RK_FUNC_1 &pcfg_pull_none>;
+                               rockchip,pins = <1 RK_PB2 1 &pcfg_pull_up>,
+                                               <1 RK_PB3 1 &pcfg_pull_none>;
                        };
 
                        uart3_cts: uart3-cts {
-                               rockchip,pins = <RK_GPIO1 12 RK_FUNC_1 &pcfg_pull_none>;
+                               rockchip,pins = <1 RK_PB4 1 &pcfg_pull_none>;
                        };
 
                        uart3_rts: uart3-rts {
-                               rockchip,pins = <RK_GPIO1 13 RK_FUNC_1 &pcfg_pull_none>;
+                               rockchip,pins = <1 RK_PB5 1 &pcfg_pull_none>;
                        };
                };
 
                sd0 {
                        sd0_clk: sd0-clk {
-                               rockchip,pins = <RK_GPIO3 2 RK_FUNC_1 &pcfg_pull_none>;
+                               rockchip,pins = <3 RK_PA2 1 &pcfg_pull_none>;
                        };
 
                        sd0_cmd: sd0-cmd {
-                               rockchip,pins = <RK_GPIO3 3 RK_FUNC_1 &pcfg_pull_none>;
+                               rockchip,pins = <3 RK_PA3 1 &pcfg_pull_none>;
                        };
 
                        sd0_cd: sd0-cd {
-                               rockchip,pins = <RK_GPIO3 8 RK_FUNC_1 &pcfg_pull_none>;
+                               rockchip,pins = <3 RK_PB0 1 &pcfg_pull_none>;
                        };
 
                        sd0_wp: sd0-wp {
-                               rockchip,pins = <RK_GPIO3 9 RK_FUNC_1 &pcfg_pull_none>;
+                               rockchip,pins = <3 RK_PB1 1 &pcfg_pull_none>;
                        };
 
                        sd0_pwr: sd0-pwr {
-                               rockchip,pins = <RK_GPIO3 1 RK_FUNC_1 &pcfg_pull_none>;
+                               rockchip,pins = <3 RK_PA1 1 &pcfg_pull_none>;
                        };
 
                        sd0_bus1: sd0-bus-width1 {
-                               rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>;
+                               rockchip,pins = <3 RK_PA4 1 &pcfg_pull_none>;
                        };
 
                        sd0_bus4: sd0-bus-width4 {
-                               rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>,
-                                               <RK_GPIO3 5 RK_FUNC_1 &pcfg_pull_none>,
-                                               <RK_GPIO3 6 RK_FUNC_1 &pcfg_pull_none>,
-                                               <RK_GPIO3 7 RK_FUNC_1 &pcfg_pull_none>;
+                               rockchip,pins = <3 RK_PA4 1 &pcfg_pull_none>,
+                                               <3 RK_PA5 1 &pcfg_pull_none>,
+                                               <3 RK_PA6 1 &pcfg_pull_none>,
+                                               <3 RK_PA7 1 &pcfg_pull_none>;
                        };
                };
 
                sd1 {
                        sd1_clk: sd1-clk {
-                               rockchip,pins = <RK_GPIO3 21 RK_FUNC_1 &pcfg_pull_none>;
+                               rockchip,pins = <3 RK_PC5 1 &pcfg_pull_none>;
                        };
 
                        sd1_cmd: sd1-cmd {
-                               rockchip,pins = <RK_GPIO3 16 RK_FUNC_1 &pcfg_pull_none>;
+                               rockchip,pins = <3 RK_PC0 1 &pcfg_pull_none>;
                        };
 
                        sd1_cd: sd1-cd {
-                               rockchip,pins = <RK_GPIO3 22 RK_FUNC_1 &pcfg_pull_none>;
+                               rockchip,pins = <3 RK_PC6 1 &pcfg_pull_none>;
                        };
 
                        sd1_wp: sd1-wp {
-                               rockchip,pins = <RK_GPIO3 23 RK_FUNC_1 &pcfg_pull_none>;
+                               rockchip,pins = <3 RK_PC7 1 &pcfg_pull_none>;
                        };
 
                        sd1_bus1: sd1-bus-width1 {
-                               rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_none>;
+                               rockchip,pins = <3 RK_PC1 1 &pcfg_pull_none>;
                        };
 
                        sd1_bus4: sd1-bus-width4 {
-                               rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_none>,
-                                               <RK_GPIO3 18 RK_FUNC_1 &pcfg_pull_none>,
-                                               <RK_GPIO3 19 RK_FUNC_1 &pcfg_pull_none>,
-                                               <RK_GPIO3 20 RK_FUNC_1 &pcfg_pull_none>;
+                               rockchip,pins = <3 RK_PC1 1 &pcfg_pull_none>,
+                                               <3 RK_PC2 1 &pcfg_pull_none>,
+                                               <3 RK_PC3 1 &pcfg_pull_none>,
+                                               <3 RK_PC4 1 &pcfg_pull_none>;
                        };
                };
 
                i2s0 {
                        i2s0_bus: i2s0-bus {
-                               rockchip,pins = <RK_GPIO1 16 RK_FUNC_1 &pcfg_pull_none>,
-                                               <RK_GPIO1 17 RK_FUNC_1 &pcfg_pull_none>,
-                                               <RK_GPIO1 18 RK_FUNC_1 &pcfg_pull_none>,
-                                               <RK_GPIO1 19 RK_FUNC_1 &pcfg_pull_none>,
-                                               <RK_GPIO1 20 RK_FUNC_1 &pcfg_pull_none>,
-                                               <RK_GPIO1 21 RK_FUNC_1 &pcfg_pull_none>;
+                               rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none>,
+                                               <1 RK_PC1 1 &pcfg_pull_none>,
+                                               <1 RK_PC2 1 &pcfg_pull_none>,
+                                               <1 RK_PC3 1 &pcfg_pull_none>,
+                                               <1 RK_PC4 1 &pcfg_pull_none>,
+                                               <1 RK_PC5 1 &pcfg_pull_none>;
                        };
                };
 
                spdif {
                        spdif_tx: spdif-tx {
-                               rockchip,pins = <RK_GPIO1 14 RK_FUNC_1 &pcfg_pull_none>;
+                               rockchip,pins = <1 RK_PB6 1 &pcfg_pull_none>;
                        };
                };
        };

diff --git a/arch/arm/boot/dts/rk322x.dtsi b/arch/arm/boot/dts/rk322x.dtsi
index 29f1907..da102ff 100644 (file)
--- a/arch/arm/boot/dts/rk322x.dtsi
+++ b/arch/arm/boot/dts/rk322x.dtsi
@@ -865,228 +865,228 @@
 
                emmc {
                        emmc_clk: emmc-clk {
-                               rockchip,pins = <2 7 RK_FUNC_2 &pcfg_pull_none>;
+                               rockchip,pins = <2 RK_PA7 2 &pcfg_pull_none>;
                        };
 
                        emmc_cmd: emmc-cmd {
-                               rockchip,pins = <1 22 RK_FUNC_2 &pcfg_pull_none>;
+                               rockchip,pins = <1 RK_PC6 2 &pcfg_pull_none>;
                        };
 
                        emmc_bus8: emmc-bus8 {
-                               rockchip,pins = <1 24 RK_FUNC_2 &pcfg_pull_none>,
-                                               <1 25 RK_FUNC_2 &pcfg_pull_none>,
-                                               <1 26 RK_FUNC_2 &pcfg_pull_none>,
-                                               <1 27 RK_FUNC_2 &pcfg_pull_none>,
-                                               <1 28 RK_FUNC_2 &pcfg_pull_none>,
-                                               <1 29 RK_FUNC_2 &pcfg_pull_none>,
-                                               <1 30 RK_FUNC_2 &pcfg_pull_none>,
-                                               <1 31 RK_FUNC_2 &pcfg_pull_none>;
+                               rockchip,pins = <1 RK_PD0 2 &pcfg_pull_none>,
+                                               <1 RK_PD1 2 &pcfg_pull_none>,
+                                               <1 RK_PD2 2 &pcfg_pull_none>,
+                                               <1 RK_PD3 2 &pcfg_pull_none>,
+                                               <1 RK_PD4 2 &pcfg_pull_none>,
+                                               <1 RK_PD5 2 &pcfg_pull_none>,
+                                               <1 RK_PD6 2 &pcfg_pull_none>,
+                                               <1 RK_PD7 2 &pcfg_pull_none>;
                        };
                };
 
                gmac {
                        rgmii_pins: rgmii-pins {
-                               rockchip,pins = <2 14 RK_FUNC_1 &pcfg_pull_none>,
-                                               <2 12 RK_FUNC_1 &pcfg_pull_none>,
-                                               <2 25 RK_FUNC_1 &pcfg_pull_none>,
-                                               <2 19 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
-                                               <2 18 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
-                                               <2 22 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
-                                               <2 23 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
-                                               <2 9 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
-                                               <2 13 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
-                                               <2 17 RK_FUNC_1 &pcfg_pull_none>,
-                                               <2 16 RK_FUNC_1 &pcfg_pull_none>,
-                                               <2 21 RK_FUNC_2 &pcfg_pull_none>,
-                                               <2 20 RK_FUNC_2 &pcfg_pull_none>,
-                                               <2 11 RK_FUNC_1 &pcfg_pull_none>,
-                                               <2 8 RK_FUNC_1 &pcfg_pull_none>;
+                               rockchip,pins = <2 RK_PB6 1 &pcfg_pull_none>,
+                                               <2 RK_PB4 1 &pcfg_pull_none>,
+                                               <2 RK_PD1 1 &pcfg_pull_none>,
+                                               <2 RK_PC3 1 &pcfg_pull_none_drv_12ma>,
+                                               <2 RK_PC2 1 &pcfg_pull_none_drv_12ma>,
+                                               <2 RK_PC6 1 &pcfg_pull_none_drv_12ma>,
+                                               <2 RK_PC7 1 &pcfg_pull_none_drv_12ma>,
+                                               <2 RK_PB1 1 &pcfg_pull_none_drv_12ma>,
+                                               <2 RK_PB5 1 &pcfg_pull_none_drv_12ma>,
+                                               <2 RK_PC1 1 &pcfg_pull_none>,
+                                               <2 RK_PC0 1 &pcfg_pull_none>,
+                                               <2 RK_PC5 2 &pcfg_pull_none>,
+                                               <2 RK_PC4 2 &pcfg_pull_none>,
+                                               <2 RK_PB3 1 &pcfg_pull_none>,
+                                               <2 RK_PB0 1 &pcfg_pull_none>;
                        };
 
                        rmii_pins: rmii-pins {
-                               rockchip,pins = <2 14 RK_FUNC_1 &pcfg_pull_none>,
-                                               <2 12 RK_FUNC_1 &pcfg_pull_none>,
-                                               <2 25 RK_FUNC_1 &pcfg_pull_none>,
-                                               <2 19 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
-                                               <2 18 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
-                                               <2 13 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
-                                               <2 17 RK_FUNC_1 &pcfg_pull_none>,
-                                               <2 16 RK_FUNC_1 &pcfg_pull_none>,
-                                               <2 8 RK_FUNC_1 &pcfg_pull_none>,
-                                               <2 15 RK_FUNC_1 &pcfg_pull_none>;
+                               rockchip,pins = <2 RK_PB6 1 &pcfg_pull_none>,
+                                               <2 RK_PB4 1 &pcfg_pull_none>,
+                                               <2 RK_PD1 1 &pcfg_pull_none>,
+                                               <2 RK_PC3 1 &pcfg_pull_none_drv_12ma>,
+                                               <2 RK_PC2 1 &pcfg_pull_none_drv_12ma>,
+                                               <2 RK_PB5 1 &pcfg_pull_none_drv_12ma>,
+                                               <2 RK_PC1 1 &pcfg_pull_none>,
+                                               <2 RK_PC0 1 &pcfg_pull_none>,
+                                               <2 RK_PB0 1 &pcfg_pull_none>,
+                                               <2 RK_PB7 1 &pcfg_pull_none>;
                        };
 
                        phy_pins: phy-pins {
-                               rockchip,pins = <2 14 RK_FUNC_2 &pcfg_pull_none>,
-                                               <2 8 RK_FUNC_2 &pcfg_pull_none>;
+                               rockchip,pins = <2 RK_PB6 2 &pcfg_pull_none>,
+                                               <2 RK_PB0 2 &pcfg_pull_none>;
                        };
                };
 
                i2c0 {
                        i2c0_xfer: i2c0-xfer {
-                               rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>,
-                                               <0 1 RK_FUNC_1 &pcfg_pull_none>;
+                               rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>,
+                                               <0 RK_PA1 1 &pcfg_pull_none>;
                        };
                };
 
                i2c1 {
                        i2c1_xfer: i2c1-xfer {
-                               rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_none>,
-                                               <0 3 RK_FUNC_1 &pcfg_pull_none>;
+                               rockchip,pins = <0 RK_PA2 1 &pcfg_pull_none>,
+                                               <0 RK_PA3 1 &pcfg_pull_none>;
                        };
                };
 
                i2c2 {
                        i2c2_xfer: i2c2-xfer {
-                               rockchip,pins = <2 20 RK_FUNC_1 &pcfg_pull_none>,
-                                               <2 21 RK_FUNC_1 &pcfg_pull_none>;
+                               rockchip,pins = <2 RK_PC4 1 &pcfg_pull_none>,
+                                               <2 RK_PC5 1 &pcfg_pull_none>;
                        };
                };
 
                i2c3 {
                        i2c3_xfer: i2c3-xfer {
-                               rockchip,pins = <0 6 RK_FUNC_1 &pcfg_pull_none>,
-                                               <0 7 RK_FUNC_1 &pcfg_pull_none>;
+                               rockchip,pins = <0 RK_PA6 1 &pcfg_pull_none>,
+                                               <0 RK_PA7 1 &pcfg_pull_none>;
                        };
                };
 
                spi-0 {
                        spi0_clk: spi0-clk {
-                               rockchip,pins = <0 9 RK_FUNC_2 &pcfg_pull_up>;
+                               rockchip,pins = <0 RK_PB1 2 &pcfg_pull_up>;
                        };
                        spi0_cs0: spi0-cs0 {
-                               rockchip,pins = <0 14 RK_FUNC_2 &pcfg_pull_up>;
+                               rockchip,pins = <0 RK_PB6 2 &pcfg_pull_up>;
                        };
                        spi0_tx: spi0-tx {
-                               rockchip,pins = <0 11 RK_FUNC_2 &pcfg_pull_up>;
+                               rockchip,pins = <0 RK_PB3 2 &pcfg_pull_up>;
                        };
                        spi0_rx: spi0-rx {
-                               rockchip,pins = <0 13 RK_FUNC_2 &pcfg_pull_up>;
+                               rockchip,pins = <0 RK_PB5 2 &pcfg_pull_up>;
                        };
                        spi0_cs1: spi0-cs1 {
-                               rockchip,pins = <1 12 RK_FUNC_1 &pcfg_pull_up>;
+                               rockchip,pins = <1 RK_PB4 1 &pcfg_pull_up>;
                        };
                };
 
                spi-1 {
                        spi1_clk: spi1-clk {
-                               rockchip,pins = <0 23 RK_FUNC_2 &pcfg_pull_up>;
+                               rockchip,pins = <0 RK_PC7 2 &pcfg_pull_up>;
                        };
                        spi1_cs0: spi1-cs0 {
-                               rockchip,pins = <2 2 RK_FUNC_2 &pcfg_pull_up>;
+                               rockchip,pins = <2 RK_PA2 2 &pcfg_pull_up>;
                        };
                        spi1_rx: spi1-rx {
-                               rockchip,pins = <2 0 RK_FUNC_2 &pcfg_pull_up>;
+                               rockchip,pins = <2 RK_PA0 2 &pcfg_pull_up>;
                        };
                        spi1_tx: spi1-tx {
-                               rockchip,pins = <2 1 RK_FUNC_2 &pcfg_pull_up>;
+                               rockchip,pins = <2 RK_PA1 2 &pcfg_pull_up>;
                        };
                        spi1_cs1: spi1-cs1 {
-                               rockchip,pins = <2 3 RK_FUNC_2 &pcfg_pull_up>;
+                               rockchip,pins = <2 RK_PA3 2 &pcfg_pull_up>;
                        };
                };
 
                i2s1 {
                        i2s1_bus: i2s1-bus {
-                               rockchip,pins = <0 8 RK_FUNC_1 &pcfg_pull_none>,
-                                               <0 9 RK_FUNC_1 &pcfg_pull_none>,
-                                               <0 11 RK_FUNC_1 &pcfg_pull_none>,
-                                               <0 12 RK_FUNC_1 &pcfg_pull_none>,
-                                               <0 13 RK_FUNC_1 &pcfg_pull_none>,
-                                               <0 14 RK_FUNC_1 &pcfg_pull_none>,
-                                               <1 2 RK_FUNC_2 &pcfg_pull_none>,
-                                               <1 4 RK_FUNC_2 &pcfg_pull_none>,
-                                               <1 5 RK_FUNC_2 &pcfg_pull_none>;
+                               rockchip,pins = <0 RK_PB0 1 &pcfg_pull_none>,
+                                               <0 RK_PB1 1 &pcfg_pull_none>,
+                                               <0 RK_PB3 1 &pcfg_pull_none>,
+                                               <0 RK_PB4 1 &pcfg_pull_none>,
+                                               <0 RK_PB5 1 &pcfg_pull_none>,
+                                               <0 RK_PB6 1 &pcfg_pull_none>,
+                                               <1 RK_PA2 2 &pcfg_pull_none>,
+                                               <1 RK_PA4 2 &pcfg_pull_none>,
+                                               <1 RK_PA5 2 &pcfg_pull_none>;
                        };
                };
 
                pwm0 {
                        pwm0_pin: pwm0-pin {
-                               rockchip,pins = <3 21 RK_FUNC_1 &pcfg_pull_none>;
+                               rockchip,pins = <3 RK_PC5 1 &pcfg_pull_none>;
                        };
                };
 
                pwm1 {
                        pwm1_pin: pwm1-pin {
-                               rockchip,pins = <0 30 RK_FUNC_2 &pcfg_pull_none>;
+                               rockchip,pins = <0 RK_PD6 2 &pcfg_pull_none>;
                        };
                };
 
                pwm2 {
                        pwm2_pin: pwm2-pin {
-                               rockchip,pins = <1 12 RK_FUNC_2 &pcfg_pull_none>;
+                               rockchip,pins = <1 RK_PB4 2 &pcfg_pull_none>;
                        };
                };
 
                pwm3 {
                        pwm3_pin: pwm3-pin {
-                               rockchip,pins = <1 11 RK_FUNC_2 &pcfg_pull_none>;
+                               rockchip,pins = <1 RK_PB3 2 &pcfg_pull_none>;
                        };
                };
 
                spdif {
                        spdif_tx: spdif-tx {
-                               rockchip,pins = <3 31 RK_FUNC_2 &pcfg_pull_none>;
+                               rockchip,pins = <3 RK_PD7 2 &pcfg_pull_none>;
                        };
                };
 
                tsadc {
                        otp_gpio: otp-gpio {
-                               rockchip,pins = <0 24 RK_FUNC_GPIO &pcfg_pull_none>;
+                               rockchip,pins = <0 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
                        };
 
                        otp_out: otp-out {
-                               rockchip,pins = <0 24 RK_FUNC_2 &pcfg_pull_none>;
+                               rockchip,pins = <0 RK_PD0 2 &pcfg_pull_none>;
                        };
                };
 
                uart0 {
                        uart0_xfer: uart0-xfer {
-                               rockchip,pins = <2 26 RK_FUNC_1 &pcfg_pull_none>,
-                                               <2 27 RK_FUNC_1 &pcfg_pull_none>;
+                               rockchip,pins = <2 RK_PD2 1 &pcfg_pull_none>,
+                                               <2 RK_PD3 1 &pcfg_pull_none>;
                        };
 
                        uart0_cts: uart0-cts {
-                               rockchip,pins = <2 29 RK_FUNC_1 &pcfg_pull_none>;
+                               rockchip,pins = <2 RK_PD5 1 &pcfg_pull_none>;
                        };
 
                        uart0_rts: uart0-rts {
-                               rockchip,pins = <0 17 RK_FUNC_1 &pcfg_pull_none>;
+                               rockchip,pins = <0 RK_PC1 1 &pcfg_pull_none>;
                        };
                };
 
                uart1 {
                        uart1_xfer: uart1-xfer {
-                               rockchip,pins = <1 9 RK_FUNC_1 &pcfg_pull_none>,
-                                               <1 10 RK_FUNC_1 &pcfg_pull_none>;
+                               rockchip,pins = <1 RK_PB1 1 &pcfg_pull_none>,
+                                               <1 RK_PB2 1 &pcfg_pull_none>;
                        };
 
                        uart1_cts: uart1-cts {
-                               rockchip,pins = <1 8 RK_FUNC_1 &pcfg_pull_none>;
+                               rockchip,pins = <1 RK_PB0 1 &pcfg_pull_none>;
                        };
 
                        uart1_rts: uart1-rts {
-                               rockchip,pins = <1 11 RK_FUNC_1 &pcfg_pull_none>;
+                               rockchip,pins = <1 RK_PB3 1 &pcfg_pull_none>;
                        };
                };
 
                uart2 {
                        uart2_xfer: uart2-xfer {
-                               rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>,
-                                               <1 19 RK_FUNC_2 &pcfg_pull_none>;
+                               rockchip,pins = <1 RK_PC2 2 &pcfg_pull_up>,
+                                               <1 RK_PC3 2 &pcfg_pull_none>;
                        };
 
                        uart21_xfer: uart21-xfer {
-                               rockchip,pins = <1 10 RK_FUNC_2 &pcfg_pull_up>,
-                                               <1 9 RK_FUNC_2 &pcfg_pull_none>;
+                               rockchip,pins = <1 RK_PB2 2 &pcfg_pull_up>,
+                                               <1 RK_PB1 2 &pcfg_pull_none>;
                        };
 
                        uart2_cts: uart2-cts {
-                               rockchip,pins = <0 25 RK_FUNC_1 &pcfg_pull_none>;
+                               rockchip,pins = <0 RK_PD1 1 &pcfg_pull_none>;
                        };
 
                        uart2_rts: uart2-rts {
-                               rockchip,pins = <0 24 RK_FUNC_1 &pcfg_pull_none>;
+                               rockchip,pins = <0 RK_PD0 1 &pcfg_pull_none>;
                        };
                };
        };

diff --git a/arch/arm/boot/dts/rk3288-evb-act8846.dts b/arch/arm/boot/dts/rk3288-evb-act8846.dts
index 6592c80..8008076 100644 (file)
--- a/arch/arm/boot/dts/rk3288-evb-act8846.dts
+++ b/arch/arm/boot/dts/rk3288-evb-act8846.dts
@@ -175,13 +175,13 @@
 &pinctrl {
        lcd {
                lcd_en: lcd-en  {
-                       rockchip,pins = <7 3 RK_FUNC_GPIO &pcfg_pull_none>;
+                       rockchip,pins = <7 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
                };
        };
 
        wifi {
                wifi_pwr: wifi-pwr {
-                       rockchip,pins = <7 9 RK_FUNC_GPIO &pcfg_pull_none>;
+                       rockchip,pins = <7 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
                };
        };
 };

diff --git a/arch/arm/boot/dts/rk3288-evb.dtsi b/arch/arm/boot/dts/rk3288-evb.dtsi
index 97e4d55..8204407 100644 (file)
--- a/arch/arm/boot/dts/rk3288-evb.dtsi
+++ b/arch/arm/boot/dts/rk3288-evb.dtsi
@@ -314,25 +314,25 @@
 
        backlight {
                bl_en: bl-en {
-                       rockchip,pins = <7 2 RK_FUNC_GPIO &pcfg_pull_none>;
+                       rockchip,pins = <7 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
                };
        };
 
        buttons {
                pwrbtn: pwrbtn {
-                       rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_up>;
+                       rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;
                };
        };
 
        lcd {
                lcd_cs: lcd-cs {
-                       rockchip,pins = <7 4 RK_FUNC_GPIO &pcfg_pull_none>;
+                       rockchip,pins = <7 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
                };
        };
 
        pmic {
                pmic_int: pmic-int {
-                       rockchip,pins = <RK_GPIO0 4 RK_FUNC_GPIO &pcfg_pull_up>;
+                       rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>;
                };
        };
 
@@ -342,34 +342,34 @@
                 * high-speed mode on EVB board so bump up to 8ma.
                 */
                sdmmc_bus4: sdmmc-bus4 {
-                       rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up_drv_8ma>,
-                                       <6 17 RK_FUNC_1 &pcfg_pull_up_drv_8ma>,
-                                       <6 18 RK_FUNC_1 &pcfg_pull_up_drv_8ma>,
-                                       <6 19 RK_FUNC_1 &pcfg_pull_up_drv_8ma>;
+                       rockchip,pins = <6 RK_PC0 1 &pcfg_pull_up_drv_8ma>,
+                                       <6 RK_PC1 1 &pcfg_pull_up_drv_8ma>,
+                                       <6 RK_PC2 1 &pcfg_pull_up_drv_8ma>,
+                                       <6 RK_PC3 1 &pcfg_pull_up_drv_8ma>;
                };
 
                sdmmc_clk: sdmmc-clk {
-                       rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none_drv_8ma>;
+                       rockchip,pins = <6 RK_PC4 1 &pcfg_pull_none_drv_8ma>;
                };
 
                sdmmc_cmd: sdmmc-cmd {
-                       rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up_drv_8ma>;
+                       rockchip,pins = <6 RK_PC5 1 &pcfg_pull_up_drv_8ma>;
                };
 
                sdmmc_pwr: sdmmc-pwr {
-                       rockchip,pins = <7 11 RK_FUNC_GPIO &pcfg_pull_none>;
+                       rockchip,pins = <7 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
                };
        };
 
        usb {
                host_vbus_drv: host-vbus-drv {
-                       rockchip,pins = <0 14 RK_FUNC_GPIO &pcfg_pull_none>;
+                       rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
                };
        };
 
        eth_phy {
                eth_phy_pwr: eth-phy-pwr {
-                       rockchip,pins = <0 6 RK_FUNC_GPIO &pcfg_pull_none>;
+                       rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
                };
        };
 };

diff --git a/arch/arm/boot/dts/rk3288-fennec.dts b/arch/arm/boot/dts/rk3288-fennec.dts
index 29af26e..4847cf9 100644 (file)
--- a/arch/arm/boot/dts/rk3288-fennec.dts
+++ b/arch/arm/boot/dts/rk3288-fennec.dts
@@ -278,27 +278,27 @@
 
        gmac {
                phy_int: phy-int {
-                       rockchip,pins = <0 9 RK_FUNC_GPIO &pcfg_pull_up>;
+                       rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>;
                };
 
                phy_pmeb: phy-pmeb {
-                       rockchip,pins = <0 8 RK_FUNC_GPIO &pcfg_pull_up>;
+                       rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>;
                };
 
                phy_rst: phy-rst {
-                       rockchip,pins = <4 8 RK_FUNC_GPIO &pcfg_output_high>;
+                       rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_output_high>;
                };
        };
 
        pmic {
                pmic_int: pmic-int {
-                       rockchip,pins = <RK_GPIO0 4 RK_FUNC_GPIO &pcfg_pull_up>;
+                       rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>;
                };
        };
 
        usbphy {
                host_drv: host-drv {
-                       rockchip,pins = <0 14 RK_FUNC_GPIO &pcfg_pull_none>;
+                       rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
                };
        };
 };

diff --git a/arch/arm/boot/dts/rk3288-firefly-beta.dts b/arch/arm/boot/dts/rk3288-firefly-beta.dts
index 0f3c29d..135e883 100644 (file)
--- a/arch/arm/boot/dts/rk3288-firefly-beta.dts
+++ b/arch/arm/boot/dts/rk3288-firefly-beta.dts
@@ -18,13 +18,13 @@
 &pinctrl {
        act8846 {
                pmic_vsel: pmic-vsel {
-                       rockchip,pins = <7 1 RK_FUNC_GPIO &pcfg_output_low>;
+                       rockchip,pins = <7 RK_PA1 RK_FUNC_GPIO &pcfg_output_low>;
                };
        };
 
        ir {
                ir_int: ir-int {
-                       rockchip,pins = <7 5 RK_FUNC_GPIO &pcfg_pull_up>;
+                       rockchip,pins = <7 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;
                };
        };
 };

diff --git a/arch/arm/boot/dts/rk3288-firefly-reload-core.dtsi b/arch/arm/boot/dts/rk3288-firefly-reload-core.dtsi
index f57f286..61435d8 100644 (file)
--- a/arch/arm/boot/dts/rk3288-firefly-reload-core.dtsi
+++ b/arch/arm/boot/dts/rk3288-firefly-reload-core.dtsi
@@ -224,25 +224,25 @@
 
        act8846 {
                pwr_hold: pwr-hold {
-                       rockchip,pins = <0 1 RK_FUNC_GPIO &pcfg_output_high>;
+                       rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_output_high>;
                };
 
                pmic_vsel: pmic-vsel {
-                       rockchip,pins = <7 14 RK_FUNC_GPIO &pcfg_output_low>;
+                       rockchip,pins = <7 RK_PB6 RK_FUNC_GPIO &pcfg_output_low>;
                };
        };
 
        gmac {
                phy_int: phy-int {
-                       rockchip,pins = <0 9 RK_FUNC_GPIO &pcfg_pull_up>;
+                       rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>;
                };
 
                phy_pmeb: phy-pmeb {
-                       rockchip,pins = <0 8 RK_FUNC_GPIO &pcfg_pull_up>;
+                       rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>;
                };
 
                phy_rst: phy-rst {
-                       rockchip,pins = <4 8 RK_FUNC_GPIO &pcfg_output_high>;
+                       rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_output_high>;
                };
        };
 };

diff --git a/arch/arm/boot/dts/rk3288-firefly-reload.dts b/arch/arm/boot/dts/rk3288-firefly-reload.dts
index 3a646c5..1574383 100644 (file)
--- a/arch/arm/boot/dts/rk3288-firefly-reload.dts
+++ b/arch/arm/boot/dts/rk3288-firefly-reload.dts
@@ -306,39 +306,39 @@
 &pinctrl {
        ir {
                ir_int: ir-int {
-                       rockchip,pins = <7 0 RK_FUNC_GPIO &pcfg_pull_up>;
+                       rockchip,pins = <7 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>;
                };
        };
 
        dvp {
                dvp_pwr: dvp-pwr {
-                       rockchip,pins = <0 11 RK_FUNC_GPIO &pcfg_pull_none>;
+                       rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
                };
 
                cif_pwr: cif-pwr {
-                       rockchip,pins = <7 12 RK_FUNC_GPIO &pcfg_pull_none>;
+                       rockchip,pins = <7 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>;
                };
        };
 
        hym8563 {
                rtc_int: rtc-int {
-                       rockchip,pins = <7 4 RK_FUNC_GPIO &pcfg_pull_up>;
+                       rockchip,pins = <7 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>;
                };
        };
 
        keys {
                pwr_key: pwr-key {
-                       rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_up>;
+                       rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;
                };
        };
 
        leds {
                power_led: power-led {
-                       rockchip,pins = <8 2 RK_FUNC_GPIO &pcfg_pull_none>;
+                       rockchip,pins = <8 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
                };
 
                work_led: work-led {
-                       rockchip,pins = <8 1 RK_FUNC_GPIO &pcfg_pull_none>;
+                       rockchip,pins = <8 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>;
                };
        };
 
@@ -348,44 +348,44 @@
                 * high-speed mode on firefly board so bump up to 12ma.
                 */
                sdmmc_bus4: sdmmc-bus4 {
-                       rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up_drv_12ma>,
-                                       <6 17 RK_FUNC_1 &pcfg_pull_up_drv_12ma>,
-                                       <6 18 RK_FUNC_1 &pcfg_pull_up_drv_12ma>,
-                                       <6 19 RK_FUNC_1 &pcfg_pull_up_drv_12ma>;
+                       rockchip,pins = <6 RK_PC0 1 &pcfg_pull_up_drv_12ma>,
+                                       <6 RK_PC1 1 &pcfg_pull_up_drv_12ma>,
+                                       <6 RK_PC2 1 &pcfg_pull_up_drv_12ma>,
+                                       <6 RK_PC3 1 &pcfg_pull_up_drv_12ma>;
                };
 
                sdmmc_clk: sdmmc-clk {
-                       rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none_12ma>;
+                       rockchip,pins = <6 RK_PC4 1 &pcfg_pull_none_12ma>;
                };
 
                sdmmc_cmd: sdmmc-cmd {
-                       rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up_drv_12ma>;
+                       rockchip,pins = <6 RK_PC5 1 &pcfg_pull_up_drv_12ma>;
                };
 
                sdmmc_pwr: sdmmc-pwr {
-                       rockchip,pins = <7 11 RK_FUNC_GPIO &pcfg_pull_none>;
+                       rockchip,pins = <7 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
                };
        };
 
        sdio {
                wifi_enable: wifi-enable {
-                       rockchip,pins = <4 28 RK_FUNC_GPIO &pcfg_pull_none>;
+                       rockchip,pins = <4 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
                };
        };
 
        usb_host {
                host_vbus_drv: host-vbus-drv {
-                       rockchip,pins = <0 14 RK_FUNC_GPIO &pcfg_pull_none>;
+                       rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
                };
 
                usbhub_rst: usbhub-rst {
-                       rockchip,pins = <8 3 RK_FUNC_GPIO &pcfg_output_high>;
+                       rockchip,pins = <8 RK_PA3 RK_FUNC_GPIO &pcfg_output_high>;
                };
        };
 
        usb_otg {
                otg_vbus_drv: otg-vbus-drv {
-                       rockchip,pins = <0 12 RK_FUNC_GPIO &pcfg_pull_none>;
+                       rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>;
                };
        };
 };

diff --git a/arch/arm/boot/dts/rk3288-firefly.dts b/arch/arm/boot/dts/rk3288-firefly.dts
index 556ab42..313459d 100644 (file)
--- a/arch/arm/boot/dts/rk3288-firefly.dts
+++ b/arch/arm/boot/dts/rk3288-firefly.dts
@@ -18,13 +18,13 @@
 &pinctrl {
        act8846 {
                pmic_vsel: pmic-vsel {
-                       rockchip,pins = <7 14 RK_FUNC_GPIO &pcfg_output_low>;
+                       rockchip,pins = <7 RK_PB6 RK_FUNC_GPIO &pcfg_output_low>;
                };
        };
 
        ir {
                ir_int: ir-int {
-                       rockchip,pins = <7 0 RK_FUNC_GPIO &pcfg_pull_up>;
+                       rockchip,pins = <7 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>;
                };
        };
 };

diff --git a/arch/arm/boot/dts/rk3288-firefly.dtsi b/arch/arm/boot/dts/rk3288-firefly.dtsi
index a6ff7ea..5e0a190 100644 (file)
--- a/arch/arm/boot/dts/rk3288-firefly.dtsi
+++ b/arch/arm/boot/dts/rk3288-firefly.dtsi
@@ -392,49 +392,49 @@
 
        act8846 {
                pwr_hold: pwr-hold {
-                       rockchip,pins = <0 1 RK_FUNC_GPIO &pcfg_output_high>;
+                       rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_output_high>;
                };
        };
 
        dvp {
                dvp_pwr: dvp-pwr {
-                       rockchip,pins = <0 11 RK_FUNC_GPIO &pcfg_pull_none>;
+                       rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
                };
        };
 
        gmac {
                phy_int: phy-int {
-                       rockchip,pins = <0 9 RK_FUNC_GPIO &pcfg_pull_up>;
+                       rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>;
                };
 
                phy_pmeb: phy-pmeb {
-                       rockchip,pins = <0 8 RK_FUNC_GPIO &pcfg_pull_up>;
+                       rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>;
                };
 
                phy_rst: phy-rst {
-                       rockchip,pins = <4 8 RK_FUNC_GPIO &pcfg_output_high>;
+                       rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_output_high>;
                };
        };
 
        hym8563 {
                rtc_int: rtc-int {
-                       rockchip,pins = <7 4 RK_FUNC_GPIO &pcfg_pull_up>;
+                       rockchip,pins = <7 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>;
                };
        };
 
        keys {
                pwr_key: pwr-key {
-                       rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_up>;
+                       rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;
                };
        };
 
        leds {
                power_led: power-led {
-                       rockchip,pins = <8 2 RK_FUNC_GPIO &pcfg_pull_none>;
+                       rockchip,pins = <8 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
                };
 
                work_led: work-led {
-                       rockchip,pins = <8 1 RK_FUNC_GPIO &pcfg_pull_none>;
+                       rockchip,pins = <8 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>;
                };
        };
 
@@ -444,38 +444,38 @@
                 * high-speed mode on firefly board so bump up to 12ma.
                 */
                sdmmc_bus4: sdmmc-bus4 {
-                       rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up_drv_12ma>,
-                                       <6 17 RK_FUNC_1 &pcfg_pull_up_drv_12ma>,
-                                       <6 18 RK_FUNC_1 &pcfg_pull_up_drv_12ma>,
-                                       <6 19 RK_FUNC_1 &pcfg_pull_up_drv_12ma>;
+                       rockchip,pins = <6 RK_PC0 1 &pcfg_pull_up_drv_12ma>,
+                                       <6 RK_PC1 1 &pcfg_pull_up_drv_12ma>,
+                                       <6 RK_PC2 1 &pcfg_pull_up_drv_12ma>,
+                                       <6 RK_PC3 1 &pcfg_pull_up_drv_12ma>;
                };
 
                sdmmc_clk: sdmmc-clk {
-                       rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none_12ma>;
+                       rockchip,pins = <6 RK_PC4 1 &pcfg_pull_none_12ma>;
                };
 
                sdmmc_cmd: sdmmc-cmd {
-                       rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up_drv_12ma>;
+                       rockchip,pins = <6 RK_PC5 1 &pcfg_pull_up_drv_12ma>;
                };
 
                sdmmc_pwr: sdmmc-pwr {
-                       rockchip,pins = <7 11 RK_FUNC_GPIO &pcfg_pull_none>;
+                       rockchip,pins = <7 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
                };
        };
 
        usb_host {
                host_vbus_drv: host-vbus-drv {
-                       rockchip,pins = <0 14 RK_FUNC_GPIO &pcfg_pull_none>;
+                       rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
                };
 
                usbhub_rst: usbhub-rst {
-                       rockchip,pins = <8 3 RK_FUNC_GPIO &pcfg_output_high>;
+                       rockchip,pins = <8 RK_PA3 RK_FUNC_GPIO &pcfg_output_high>;
                };
        };
 
        usb_otg {
                otg_vbus_drv: otg-vbus-drv {
-                       rockchip,pins = <0 12 RK_FUNC_GPIO &pcfg_pull_none>;
+                       rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>;
                };
        };
 };

diff --git a/arch/arm/boot/dts/rk3288-miqi.dts b/arch/arm/boot/dts/rk3288-miqi.dts
index fb7365b..c41d012 100644 (file)
--- a/arch/arm/boot/dts/rk3288-miqi.dts
+++ b/arch/arm/boot/dts/rk3288-miqi.dts
@@ -296,29 +296,29 @@
 
        act8846 {
                pmic_int: pmic-int {
-                       rockchip,pins = <0 4 RK_FUNC_GPIO &pcfg_pull_up>;
+                       rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>;
                };
 
                pmic_sleep: pmic-sleep {
-                       rockchip,pins = <0 0 RK_FUNC_GPIO &pcfg_output_low>;
+                       rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_output_low>;
                };
 
                pmic_vsel: pmic-vsel {
-                       rockchip,pins = <7 1 RK_FUNC_GPIO &pcfg_output_low>;
+                       rockchip,pins = <7 RK_PA1 RK_FUNC_GPIO &pcfg_output_low>;
                };
        };
 
        gmac {
                phy_int: phy-int {
-                       rockchip,pins = <0 9 RK_FUNC_GPIO &pcfg_pull_up>;
+                       rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>;
                };
 
                phy_pmeb: phy-pmeb {
-                       rockchip,pins = <0 8 RK_FUNC_GPIO &pcfg_pull_up>;
+                       rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>;
                };
 
                phy_rst: phy-rst {
-                       rockchip,pins = <4 8 RK_FUNC_GPIO &pcfg_output_high>;
+                       rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_output_high>;
                };
        };
 
@@ -328,28 +328,28 @@
                 * high-speed mode on firefly board so bump up to 12ma.
                 */
                sdmmc_bus4: sdmmc-bus4 {
-                       rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up_drv_12ma>,
-                                       <6 17 RK_FUNC_1 &pcfg_pull_up_drv_12ma>,
-                                       <6 18 RK_FUNC_1 &pcfg_pull_up_drv_12ma>,
-                                       <6 19 RK_FUNC_1 &pcfg_pull_up_drv_12ma>;
+                       rockchip,pins = <6 RK_PC0 1 &pcfg_pull_up_drv_12ma>,
+                                       <6 RK_PC1 1 &pcfg_pull_up_drv_12ma>,
+                                       <6 RK_PC2 1 &pcfg_pull_up_drv_12ma>,
+                                       <6 RK_PC3 1 &pcfg_pull_up_drv_12ma>;
                };
 
                sdmmc_clk: sdmmc-clk {
-                       rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none_12ma>;
+                       rockchip,pins = <6 RK_PC4 1 &pcfg_pull_none_12ma>;
                };
 
                sdmmc_cmd: sdmmc-cmd {
-                       rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up_drv_12ma>;
+                       rockchip,pins = <6 RK_PC5 1 &pcfg_pull_up_drv_12ma>;
                };
 
                sdmmc_pwr: sdmmc-pwr {
-                       rockchip,pins = <7 11 RK_FUNC_GPIO &pcfg_pull_none>;
+                       rockchip,pins = <7 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
                };
        };
 
        usb_host {
                host_vbus_drv: host-vbus-drv {
-                       rockchip,pins = <0 14 RK_FUNC_GPIO &pcfg_pull_none>;
+                       rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
                };
        };
 };

diff --git a/arch/arm/boot/dts/rk3288-phycore-rdk.dts b/arch/arm/boot/dts/rk3288-phycore-rdk.dts
index 7077c34..1e33859 100644 (file)
--- a/arch/arm/boot/dts/rk3288-phycore-rdk.dts
+++ b/arch/arm/boot/dts/rk3288-phycore-rdk.dts
@@ -160,15 +160,15 @@
        buttons {
                user_button_pins: user-button-pins {
                        /* button 1 */
-                       rockchip,pins = <8 3 RK_FUNC_GPIO &pcfg_pull_up>,
+                       rockchip,pins = <8 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>,
                        /* button 2 */
-                                       <8 0 RK_FUNC_GPIO &pcfg_pull_up>;
+                                       <8 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>;
                };
        };
 
        rv4162 {
                i2c_rtc_int: i2c-rtc-int {
-                       rockchip,pins = <5 10 RK_FUNC_GPIO &pcfg_pull_up>;
+                       rockchip,pins = <5 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>;
                };
        };
 
@@ -178,44 +178,44 @@
                 * high-speed mode on pcm-947 board so bump up to 12 mA.
                 */
                sdmmc_bus4: sdmmc-bus4 {
-                       rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up_drv_12ma>,
-                                       <6 17 RK_FUNC_1 &pcfg_pull_up_drv_12ma>,
-                                       <6 18 RK_FUNC_1 &pcfg_pull_up_drv_12ma>,
-                                       <6 19 RK_FUNC_1 &pcfg_pull_up_drv_12ma>;
+                       rockchip,pins = <6 RK_PC0 1 &pcfg_pull_up_drv_12ma>,
+                                       <6 RK_PC1 1 &pcfg_pull_up_drv_12ma>,
+                                       <6 RK_PC2 1 &pcfg_pull_up_drv_12ma>,
+                                       <6 RK_PC3 1 &pcfg_pull_up_drv_12ma>;
                };
 
                sdmmc_clk: sdmmc-clk {
-                       rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none_12ma>;
+                       rockchip,pins = <6 RK_PC4 1 &pcfg_pull_none_12ma>;
                };
 
                sdmmc_cmd: sdmmc-cmd {
-                       rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up_drv_12ma>;
+                       rockchip,pins = <6 RK_PC5 1 &pcfg_pull_up_drv_12ma>;
                };
 
                sdmmc_pwr: sdmmc-pwr {
-                       rockchip,pins = <7 11 RK_FUNC_GPIO &pcfg_pull_none>;
+                       rockchip,pins = <7 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
                };
        };
 
        touchscreen {
                ts_irq_pin: ts-irq-pin {
-                       rockchip,pins = <5 15 RK_FUNC_GPIO &pcfg_pull_none>;
+                       rockchip,pins = <5 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
                };
        };
 
        usb_host {
                host0_vbus_drv: host0-vbus-drv {
-                       rockchip,pins = <2 13 RK_FUNC_GPIO &pcfg_pull_none>;
+                       rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
                };
 
                host1_vbus_drv: host1-vbus-drv {
-                       rockchip,pins = <2 0 RK_FUNC_GPIO &pcfg_pull_none>;
+                       rockchip,pins = <2 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
                };
        };
 
        usb_otg {
                otg_vbus_drv: otg-vbus-drv {
-                       rockchip,pins = <2 12 RK_FUNC_GPIO &pcfg_pull_none>;
+                       rockchip,pins = <2 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>;
                };
        };
 };

diff --git a/arch/arm/boot/dts/rk3288-phycore-som.dtsi b/arch/arm/boot/dts/rk3288-phycore-som.dtsi
index c218dd5..77a47b9 100644 (file)
--- a/arch/arm/boot/dts/rk3288-phycore-som.dtsi
+++ b/arch/arm/boot/dts/rk3288-phycore-som.dtsi
@@ -342,49 +342,49 @@
                 * We also have external pulls, so disable the internal ones.
                 */
                emmc_clk: emmc-clk {
-                       rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none_12ma>;
+                       rockchip,pins = <3 RK_PC2 2 &pcfg_pull_none_12ma>;
                };
 
                emmc_cmd: emmc-cmd {
-                       rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_none_12ma>;
+                       rockchip,pins = <3 RK_PC0 2 &pcfg_pull_none_12ma>;
                };
 
                emmc_bus8: emmc-bus8 {
-                       rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_none_12ma>,
-                                       <3 1 RK_FUNC_2 &pcfg_pull_none_12ma>,
-                                       <3 2 RK_FUNC_2 &pcfg_pull_none_12ma>,
-                                       <3 3 RK_FUNC_2 &pcfg_pull_none_12ma>,
-                                       <3 4 RK_FUNC_2 &pcfg_pull_none_12ma>,
-                                       <3 5 RK_FUNC_2 &pcfg_pull_none_12ma>,
-                                       <3 6 RK_FUNC_2 &pcfg_pull_none_12ma>,
-                                       <3 7 RK_FUNC_2 &pcfg_pull_none_12ma>;
+                       rockchip,pins = <3 RK_PA0 2 &pcfg_pull_none_12ma>,
+                                       <3 RK_PA1 2 &pcfg_pull_none_12ma>,
+                                       <3 RK_PA2 2 &pcfg_pull_none_12ma>,
+                                       <3 RK_PA3 2 &pcfg_pull_none_12ma>,
+                                       <3 RK_PA4 2 &pcfg_pull_none_12ma>,
+                                       <3 RK_PA5 2 &pcfg_pull_none_12ma>,
+                                       <3 RK_PA6 2 &pcfg_pull_none_12ma>,
+                                       <3 RK_PA7 2 &pcfg_pull_none_12ma>;
                };
        };
 
        gmac {
                phy_int: phy-int {
-                       rockchip,pins = <4 2 RK_FUNC_GPIO &pcfg_pull_up>;
+                       rockchip,pins = <4 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>;
                };
 
                phy_rst: phy-rst {
-                       rockchip,pins = <4 8 RK_FUNC_GPIO &pcfg_output_high>;
+                       rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_output_high>;
                };
        };
 
        leds {
                user_led: user-led {
-                       rockchip,pins = <7 2 RK_FUNC_GPIO &pcfg_output_high>;
+                       rockchip,pins = <7 RK_PA2 RK_FUNC_GPIO &pcfg_output_high>;
                };
        };
 
        pmic {
                pmic_int: pmic-int {
-                       rockchip,pins = <RK_GPIO0 4 RK_FUNC_GPIO &pcfg_pull_up>;
+                       rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>;
                };
 
                /* Pin for switching state between sleep and non-sleep state */
                pmic_sleep: pmic-sleep {
-                       rockchip,pins = <RK_GPIO0 0 RK_FUNC_GPIO &pcfg_pull_up>;
+                       rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>;
                };
        };
 };

diff --git a/arch/arm/boot/dts/rk3288-r89.dts b/arch/arm/boot/dts/rk3288-r89.dts
index 28972fb..a6ffc38 100644 (file)
--- a/arch/arm/boot/dts/rk3288-r89.dts
+++ b/arch/arm/boot/dts/rk3288-r89.dts
@@ -265,39 +265,39 @@
 
        act8846 {
                pmic_vsel: pmic-vsel {
-                       rockchip,pins = <7 1 RK_FUNC_GPIO &pcfg_output_low>;
+                       rockchip,pins = <7 RK_PA1 RK_FUNC_GPIO &pcfg_output_low>;
                };
 
                pwr_hold: pwr-hold {
-                       rockchip,pins = <0 6 RK_FUNC_GPIO &pcfg_output_high>;
+                       rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_output_high>;
                };
        };
 
        buttons {
                pwrbtn: pwrbtn {
-                       rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_up>;
+                       rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;
                };
        };
 
        ir {
                ir_int: ir-int {
-                       rockchip,pins = <7 0 RK_FUNC_GPIO &pcfg_pull_up>;
+                       rockchip,pins = <7 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>;
                };
        };
 
        pmic {
                pmic_int: pmic-int {
-                       rockchip,pins = <RK_GPIO0 4 RK_FUNC_GPIO &pcfg_pull_up>;
+                       rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>;
                };
        };
 
        usb {
                host_vbus_drv: host-vbus-drv {
-                       rockchip,pins = <0 14 RK_FUNC_GPIO &pcfg_pull_none>;
+                       rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
                };
 
                otg_vbus_drv: otg-vbus-drv {
-                       rockchip,pins = <0 12 RK_FUNC_GPIO &pcfg_pull_none>;
+                       rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>;
                };
        };
 };

diff --git a/arch/arm/boot/dts/rk3288-rock2-som.dtsi b/arch/arm/boot/dts/rk3288-rock2-som.dtsi
index 32e1ab3..9f9e2bf 100644 (file)
--- a/arch/arm/boot/dts/rk3288-rock2-som.dtsi
+++ b/arch/arm/boot/dts/rk3288-rock2-som.dtsi
@@ -231,13 +231,13 @@
 
        emmc {
                        emmc_reset: emmc-reset {
-                               rockchip,pins = <3 9 RK_FUNC_GPIO &pcfg_pull_none>;
+                               rockchip,pins = <3 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
                        };
        };
 
        gmac {
                phy_rst: phy-rst {
-                       rockchip,pins = <4 8 RK_FUNC_GPIO  &pcfg_output_high>;
+                       rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO  &pcfg_output_high>;
                };
        };
 };

diff --git a/arch/arm/boot/dts/rk3288-rock2-square.dts b/arch/arm/boot/dts/rk3288-rock2-square.dts
index 5b7e1c9..cdcdc92 100644 (file)
--- a/arch/arm/boot/dts/rk3288-rock2-square.dts
+++ b/arch/arm/boot/dts/rk3288-rock2-square.dts
@@ -204,53 +204,53 @@
 &pinctrl {
        ir {
                ir_int: ir-int {
-                       rockchip,pins = <8 1 RK_FUNC_GPIO &pcfg_pull_up>;
+                       rockchip,pins = <8 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>;
                };
        };
 
        keys {
                pwr_key: pwr-key {
-                       rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_up>;
+                       rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;
                };
        };
 
        pmic {
                pmic_int: pmic-int {
-                       rockchip,pins = <0 4 RK_FUNC_GPIO &pcfg_pull_up>;
+                       rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>;
                };
        };
 
        headphone {
                hp_det: hp-det {
-                       rockchip,pins = <7 7 RK_FUNC_GPIO &pcfg_pull_none>;
+                       rockchip,pins = <7 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>;
                };
 
                phone_ctl: phone-ctl {
-                       rockchip,pins = <8 0 RK_FUNC_GPIO &pcfg_pull_up>;
+                       rockchip,pins = <8 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>;
                };
        };
 
        usb {
                host_vbus_drv: host-vbus-drv {
-                       rockchip,pins = <0 14 RK_FUNC_GPIO &pcfg_pull_none>;
+                       rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
                };
        };
 
        sata {
                sata_pwr_en: sata-pwr-en {
-                       rockchip,pins = <0 13 RK_FUNC_GPIO &pcfg_pull_none>;
+                       rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
                };
        };
 
        sdmmc {
                sdmmc_pwr: sdmmc-pwr {
-                       rockchip,pins = <7 11 RK_FUNC_GPIO &pcfg_pull_none>;
+                       rockchip,pins = <7 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
                };
        };
 
        sdio {
                wifi_enable: wifi-enable {
-                       rockchip,pins = <4 28 RK_FUNC_GPIO &pcfg_pull_none>;
+                       rockchip,pins = <4 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
                };
        };
 };

diff --git a/arch/arm/boot/dts/rk3288-tinker-s.dts b/arch/arm/boot/dts/rk3288-tinker-s.dts
index d97da89..970e138 100644 (file)
--- a/arch/arm/boot/dts/rk3288-tinker-s.dts
+++ b/arch/arm/boot/dts/rk3288-tinker-s.dts
@@ -23,3 +23,8 @@
        mmc-ddr-1_8v;
        status = "okay";
 };
+
+&hdmi {
+       pinctrl-names = "default";
+       pinctrl-0 = <&hdmi_cec_c0>;
+};

diff --git a/arch/arm/boot/dts/rk3288-tinker.dtsi b/arch/arm/boot/dts/rk3288-tinker.dtsi
index ef653c3..2935768 100644 (file)
--- a/arch/arm/boot/dts/rk3288-tinker.dtsi
+++ b/arch/arm/boot/dts/rk3288-tinker.dtsi
@@ -5,6 +5,7 @@
 
 #include "rk3288.dtsi"
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/clock/rockchip,rk808.h>
 
 / {
        chosen {
@@ -61,6 +62,16 @@
                };
        };
 
+       sdio_pwrseq: sdio-pwrseq {
+               compatible = "mmc-pwrseq-simple";
+               clocks = <&rk808 RK808_CLKOUT1>;
+               clock-names = "ext_clock";
+               pinctrl-names = "default";
+               pinctrl-0 = <&wifi_enable>;
+               reset-gpios = <&gpio4 RK_PD3 GPIO_ACTIVE_LOW>,
+                       <&gpio4 RK_PD4 GPIO_ACTIVE_LOW>;
+       };
+
        sound {
                compatible = "simple-audio-card";
                simple-audio-card,format = "i2s";
@@ -338,6 +349,7 @@
        status = "okay";
 
        sdcard-supply = <&vccio_sd>;
+       wifi-supply = <&vcc_18>;
 };
 
 &pinctrl {
@@ -352,68 +364,75 @@
 
        backlight {
                bl_en: bl-en {
-                       rockchip,pins = <7 2 RK_FUNC_GPIO &pcfg_pull_none>;
+                       rockchip,pins = <7 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
                };
        };
 
        buttons {
                pwrbtn: pwrbtn {
-                       rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_up>;
+                       rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;
                };
        };
 
        eth_phy {
                eth_phy_pwr: eth-phy-pwr {
-                       rockchip,pins = <0 6 RK_FUNC_GPIO &pcfg_pull_none>;
+                       rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
                };
        };
 
        pmic {
                pmic_int: pmic-int {
-                       rockchip,pins = <RK_GPIO0 4 RK_FUNC_GPIO \
+                       rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO \
                                        &pcfg_pull_up>;
                };
 
                dvs_1: dvs-1 {
-                       rockchip,pins = <RK_GPIO0 11 RK_FUNC_GPIO \
+                       rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO \
                                        &pcfg_pull_down>;
                };
 
                dvs_2: dvs-2 {
-                       rockchip,pins = <RK_GPIO0 12 RK_FUNC_GPIO \
+                       rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO \
                                        &pcfg_pull_down>;
                };
        };
 
        sdmmc {
                sdmmc_bus4: sdmmc-bus4 {
-                       rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up_drv_8ma>,
-                                       <6 17 RK_FUNC_1 &pcfg_pull_up_drv_8ma>,
-                                       <6 18 RK_FUNC_1 &pcfg_pull_up_drv_8ma>,
-                                       <6 19 RK_FUNC_1 &pcfg_pull_up_drv_8ma>;
+                       rockchip,pins = <6 RK_PC0 1 &pcfg_pull_up_drv_8ma>,
+                                       <6 RK_PC1 1 &pcfg_pull_up_drv_8ma>,
+                                       <6 RK_PC2 1 &pcfg_pull_up_drv_8ma>,
+                                       <6 RK_PC3 1 &pcfg_pull_up_drv_8ma>;
                };
 
                sdmmc_clk: sdmmc-clk {
-                       rockchip,pins = <6 20 RK_FUNC_1 \
+                       rockchip,pins = <6 RK_PC4 1 \
                                        &pcfg_pull_none_drv_8ma>;
                };
 
                sdmmc_cmd: sdmmc-cmd {
-                       rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up_drv_8ma>;
+                       rockchip,pins = <6 RK_PC5 1 &pcfg_pull_up_drv_8ma>;
                };
 
                sdmmc_pwr: sdmmc-pwr {
-                       rockchip,pins = <7 11 RK_FUNC_GPIO &pcfg_pull_none>;
+                       rockchip,pins = <7 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
                };
        };
 
        usb {
                host_vbus_drv: host-vbus-drv {
-                       rockchip,pins = <0 14 RK_FUNC_GPIO &pcfg_pull_none>;
+                       rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
                };
 
                pwr_3g: pwr-3g {
-                       rockchip,pins = <7 8 RK_FUNC_GPIO &pcfg_pull_none>;
+                       rockchip,pins = <7 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
+               };
+       };
+
+       sdio {
+               wifi_enable: wifi-enable {
+                       rockchip,pins = <4 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>,
+                               <4 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
                };
        };
 };
@@ -440,6 +459,24 @@
        vqmmc-supply = <&vccio_sd>;
 };
 
+&sdio0 {
+       bus-width = <4>;
+       cap-sd-highspeed;
+       cap-sdio-irq;
+       keep-power-in-suspend;
+       max-frequency = <50000000>;
+       mmc-pwrseq = <&sdio_pwrseq>;
+       non-removable;
+       pinctrl-names = "default";
+       pinctrl-0 = <&sdio0_bus4>, <&sdio0_cmd>, <&sdio0_clk>, <&sdio0_int>;
+       sd-uhs-sdr12;
+       sd-uhs-sdr25;
+       sd-uhs-sdr50;
+       vmmc-supply = <&vcc_io>;
+       vqmmc-supply = <&vcc_18>;
+       status = "okay";
+};
+
 &tsadc {
        rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */
        rockchip,hw-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */

diff --git a/arch/arm/boot/dts/rk3288-veyron-analog-audio.dtsi b/arch/arm/boot/dts/rk3288-veyron-analog-audio.dtsi
index eaf9216..445270a 100644 (file)
--- a/arch/arm/boot/dts/rk3288-veyron-analog-audio.dtsi
+++ b/arch/arm/boot/dts/rk3288-veyron-analog-audio.dtsi
@@ -73,7 +73,7 @@
 &pinctrl {
        codec {
                hp_det: hp-det {
-                       rockchip,pins = <6 5 RK_FUNC_GPIO &pcfg_pull_up>;
+                       rockchip,pins = <6 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;
                };
 
                /*
@@ -82,17 +82,17 @@
                 * we've got a ts3a227e chip but the driver requires it.
                 */
                int_codec: int-codec {
-                       rockchip,pins = <6 7 RK_FUNC_GPIO &pcfg_pull_down>;
+                       rockchip,pins = <6 RK_PA7 RK_FUNC_GPIO &pcfg_pull_down>;
                };
 
                mic_det: mic-det {
-                       rockchip,pins = <6 11 RK_FUNC_GPIO &pcfg_pull_up>;
+                       rockchip,pins = <6 RK_PB3 RK_FUNC_GPIO &pcfg_pull_up>;
                };
        };
 
        headset {
                ts3a227e_int_l: ts3a227e-int-l {
-                       rockchip,pins = <0 3 RK_FUNC_GPIO &pcfg_pull_up>;
+                       rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
                };
        };
 };

diff --git a/arch/arm/boot/dts/rk3288-veyron-brain.dts b/arch/arm/boot/dts/rk3288-veyron-brain.dts
index 5c94a33..406146c 100644 (file)
--- a/arch/arm/boot/dts/rk3288-veyron-brain.dts
+++ b/arch/arm/boot/dts/rk3288-veyron-brain.dts
@@ -42,23 +42,23 @@
 &pinctrl {
        hdmi {
                vcc50_hdmi_en: vcc50-hdmi-en {
-                       rockchip,pins = <7 2 RK_FUNC_GPIO &pcfg_pull_none>;
+                       rockchip,pins = <7 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
                };
        };
 
        pmic {
                dvs_1: dvs-1 {
-                       rockchip,pins = <7 11 RK_FUNC_GPIO &pcfg_pull_down>;
+                       rockchip,pins = <7 RK_PB3 RK_FUNC_GPIO &pcfg_pull_down>;
                };
 
                dvs_2: dvs-2 {
-                       rockchip,pins = <7 15 RK_FUNC_GPIO &pcfg_pull_down>;
+                       rockchip,pins = <7 RK_PB7 RK_FUNC_GPIO &pcfg_pull_down>;
                };
        };
 
        usb-host {
                usb2_pwr_en: usb2-pwr-en {
-                       rockchip,pins = <0 12 RK_FUNC_GPIO &pcfg_pull_none>;
+                       rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>;
                };
        };
 };

diff --git a/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi b/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi
index b54746d..fbef345 100644 (file)
--- a/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi
+++ b/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi
@@ -176,8 +176,7 @@
                        regulator-min-microvolt = <3300000>;
                        regulator-max-microvolt = <3300000>;
                        regulator-state-mem {
-                               regulator-on-in-suspend;
-                               regulator-suspend-microvolt = <3300000>;
+                               regulator-off-in-suspend;
                        };
                };
        };
@@ -229,6 +228,8 @@
 &pinctrl {
        pinctrl-0 = <
                /* Common for sleep and wake, but no owners */
+               &ddr0_retention
+               &ddrio_pwroff
                &global_pwroff
 
                /* Wake only */
@@ -236,6 +237,8 @@
        >;
        pinctrl-1 = <
                /* Common for sleep and wake, but no owners */
+               &ddr0_retention
+               &ddrio_pwroff
                &global_pwroff
 
                /* Sleep only */
@@ -244,51 +247,51 @@
 
        backlight {
                bl_en: bl-en {
-                       rockchip,pins = <7 2 RK_FUNC_GPIO &pcfg_pull_none>;
+                       rockchip,pins = <7 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
                };
        };
 
        buttons {
                ap_lid_int_l: ap-lid-int-l {
-                       rockchip,pins = <0 6 RK_FUNC_GPIO &pcfg_pull_up>;
+                       rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>;
                };
        };
 
        charger {
                ac_present_ap: ac-present-ap {
-                       rockchip,pins = <0 8 RK_FUNC_GPIO &pcfg_pull_up>;
+                       rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>;
                };
        };
 
        cros-ec {
                ec_int: ec-int {
-                       rockchip,pins = <7 7 RK_FUNC_GPIO &pcfg_pull_none>;
+                       rockchip,pins = <7 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>;
                };
        };
 
        suspend {
                suspend_l_wake: suspend-l-wake {
-                       rockchip,pins = <0 17 RK_FUNC_GPIO &pcfg_output_low>;
+                       rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_output_low>;
                };
 
                suspend_l_sleep: suspend-l-sleep {
-                       rockchip,pins = <0 17 RK_FUNC_GPIO &pcfg_output_high>;
+                       rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_output_high>;
                };
        };
 
        trackpad {
                trackpad_int: trackpad-int {
-                       rockchip,pins = <7 3 RK_FUNC_GPIO &pcfg_pull_up>;
+                       rockchip,pins = <7 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
                };
        };
 
        usb-host {
                host1_pwr_en: host1-pwr-en {
-                       rockchip,pins = <0 11 RK_FUNC_GPIO &pcfg_pull_none>;
+                       rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
                };
 
                usbotg_pwren_h: usbotg-pwren-h {
-                       rockchip,pins = <0 12 RK_FUNC_GPIO &pcfg_pull_none>;
+                       rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>;
                };
        };
 };

diff --git a/arch/arm/boot/dts/rk3288-veyron-jaq.dts b/arch/arm/boot/dts/rk3288-veyron-jaq.dts
index 9d6814c..e248f55 100644 (file)
--- a/arch/arm/boot/dts/rk3288-veyron-jaq.dts
+++ b/arch/arm/boot/dts/rk3288-veyron-jaq.dts
@@ -138,39 +138,39 @@
 &pinctrl {
        backlight {
                bl_pwr_en: bl_pwr_en {
-                       rockchip,pins = <2 12 RK_FUNC_GPIO &pcfg_pull_none>;
+                       rockchip,pins = <2 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>;
                };
        };
 
        buck-5v {
                drv_5v: drv-5v {
-                       rockchip,pins = <7 21 RK_FUNC_GPIO &pcfg_pull_none>;
+                       rockchip,pins = <7 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
                };
        };
 
        hdmi {
                vcc50_hdmi_en: vcc50-hdmi-en {
-                       rockchip,pins = <5 19 RK_FUNC_GPIO &pcfg_pull_none>;
+                       rockchip,pins = <5 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
                };
        };
 
        lcd {
                lcd_enable_h: lcd-en {
-                       rockchip,pins = <7 14 RK_FUNC_GPIO &pcfg_pull_none>;
+                       rockchip,pins = <7 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
                };
 
                avdd_1v8_disp_en: avdd-1v8-disp-en {
-                       rockchip,pins = <2 13 RK_FUNC_GPIO &pcfg_pull_none>;
+                       rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
                };
        };
 
        pmic {
                dvs_1: dvs-1 {
-                       rockchip,pins = <7 12 RK_FUNC_GPIO &pcfg_pull_down>;
+                       rockchip,pins = <7 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>;
                };
 
                dvs_2: dvs-2 {
-                       rockchip,pins = <7 15 RK_FUNC_GPIO &pcfg_pull_down>;
+                       rockchip,pins = <7 RK_PB7 RK_FUNC_GPIO &pcfg_pull_down>;
                };
        };
 };

diff --git a/arch/arm/boot/dts/rk3288-veyron-jerry.dts b/arch/arm/boot/dts/rk3288-veyron-jerry.dts
index 2ba8989..b1613af 100644 (file)
--- a/arch/arm/boot/dts/rk3288-veyron-jerry.dts
+++ b/arch/arm/boot/dts/rk3288-veyron-jerry.dts
@@ -11,7 +11,10 @@
 
 / {
        model = "Google Jerry";
-       compatible = "google,veyron-jerry-rev7", "google,veyron-jerry-rev6",
+       compatible = "google,veyron-jerry-rev15", "google,veyron-jerry-rev14",
+                    "google,veyron-jerry-rev13", "google,veyron-jerry-rev12",
+                    "google,veyron-jerry-rev11", "google,veyron-jerry-rev10",
+                    "google,veyron-jerry-rev7", "google,veyron-jerry-rev6",
                     "google,veyron-jerry-rev5", "google,veyron-jerry-rev4",
                     "google,veyron-jerry-rev3", "google,veyron-jerry",
                     "google,veyron", "rockchip,rk3288";
@@ -61,7 +64,9 @@
 
 &rk808 {
        pinctrl-names = "default";
-       pinctrl-0 = <&pmic_int_l>;
+       pinctrl-0 = <&pmic_int_l &dvs_1 &dvs_2>;
+       dvs-gpios = <&gpio7 RK_PB4 GPIO_ACTIVE_HIGH>,
+                   <&gpio7 RK_PB7 GPIO_ACTIVE_HIGH>;
 
        regulators {
                mic_vcc: LDO_REG2 {
@@ -101,39 +106,39 @@
 &pinctrl {
        backlight {
                bl_pwr_en: bl_pwr_en {
-                       rockchip,pins = <2 12 RK_FUNC_GPIO &pcfg_pull_none>;
+                       rockchip,pins = <2 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>;
                };
        };
 
        buck-5v {
                drv_5v: drv-5v {
-                       rockchip,pins = <7 21 RK_FUNC_GPIO &pcfg_pull_none>;
+                       rockchip,pins = <7 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
                };
        };
 
        hdmi {
                vcc50_hdmi_en: vcc50-hdmi-en {
-                       rockchip,pins = <5 19 RK_FUNC_GPIO &pcfg_pull_none>;
+                       rockchip,pins = <5 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
                };
        };
 
        lcd {
                lcd_enable_h: lcd-en {
-                       rockchip,pins = <7 14 RK_FUNC_GPIO &pcfg_pull_none>;
+                       rockchip,pins = <7 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
                };
 
                avdd_1v8_disp_en: avdd-1v8-disp-en {
-                       rockchip,pins = <2 13 RK_FUNC_GPIO &pcfg_pull_none>;
+                       rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
                };
        };
 
        pmic {
                dvs_1: dvs-1 {
-                       rockchip,pins = <7 12 RK_FUNC_GPIO &pcfg_pull_down>;
+                       rockchip,pins = <7 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>;
                };
 
                dvs_2: dvs-2 {
-                       rockchip,pins = <7 15 RK_FUNC_GPIO &pcfg_pull_down>;
+                       rockchip,pins = <7 RK_PB7 RK_FUNC_GPIO &pcfg_pull_down>;
                };
        };
 };

diff --git a/arch/arm/boot/dts/rk3288-veyron-mickey.dts b/arch/arm/boot/dts/rk3288-veyron-mickey.dts
index d889ab3..e852594 100644 (file)
--- a/arch/arm/boot/dts/rk3288-veyron-mickey.dts
+++ b/arch/arm/boot/dts/rk3288-veyron-mickey.dts
@@ -186,17 +186,17 @@
 &pinctrl {
        hdmi {
                power_hdmi_on: power-hdmi-on {
-                       rockchip,pins = <7 11 RK_FUNC_GPIO &pcfg_pull_none>;
+                       rockchip,pins = <7 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
                };
        };
 
        pmic {
                dvs_1: dvs-1 {
-                       rockchip,pins = <7 12 RK_FUNC_GPIO &pcfg_pull_down>;
+                       rockchip,pins = <7 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>;
                };
 
                dvs_2: dvs-2 {
-                       rockchip,pins = <7 15 RK_FUNC_GPIO &pcfg_pull_down>;
+                       rockchip,pins = <7 RK_PB7 RK_FUNC_GPIO &pcfg_pull_down>;
                };
        };
 };

diff --git a/arch/arm/boot/dts/rk3288-veyron-mighty.dts b/arch/arm/boot/dts/rk3288-veyron-mighty.dts
new file mode 100644 (file)
index 0000000..27fbc07
--- /dev/null
+++ b/arch/arm/boot/dts/rk3288-veyron-mighty.dts
@@ -0,0 +1,34 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Google Veyron Mighty Rev 1+ board device tree source
+ *
+ * Copyright 2015 Google, Inc
+ */
+
+/dts-v1/;
+
+#include "rk3288-veyron-jaq.dts"
+
+/ {
+       model = "Google Mighty";
+       compatible = "google,veyron-mighty-rev5", "google,veyron-mighty-rev4",
+                    "google,veyron-mighty-rev3", "google,veyron-mighty-rev2",
+                    "google,veyron-mighty-rev1", "google,veyron-mighty",
+                    "google,veyron", "rockchip,rk3288";
+};
+
+&sdmmc {
+       pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_gpio
+                       &sdmmc_wp_gpio &sdmmc_bus4>;
+       wp-gpios = <&gpio7 10 GPIO_ACTIVE_HIGH>;
+
+       /delete-property/ disable-wp;
+};
+
+&pinctrl {
+       sdmmc {
+               sdmmc_wp_gpio: sdmmc-wp-gpio {
+                       rockchip,pins = <7 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>;
+               };
+       };
+};

diff --git a/arch/arm/boot/dts/rk3288-veyron-minnie.dts b/arch/arm/boot/dts/rk3288-veyron-minnie.dts
index f95d0c5..468a181 100644 (file)
--- a/arch/arm/boot/dts/rk3288-veyron-minnie.dts
+++ b/arch/arm/boot/dts/rk3288-veyron-minnie.dts
@@ -191,65 +191,65 @@
 &pinctrl {
        backlight {
                bl_pwr_en: bl_pwr_en {
-                       rockchip,pins = <2 12 RK_FUNC_GPIO &pcfg_pull_none>;
+                       rockchip,pins = <2 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>;
                };
        };
 
        buck-5v {
                drv_5v: drv-5v {
-                       rockchip,pins = <7 21 RK_FUNC_GPIO &pcfg_pull_none>;
+                       rockchip,pins = <7 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
                };
        };
 
        buttons {
                volum_down_l: volum-down-l {
-                       rockchip,pins = <5 11 RK_FUNC_GPIO &pcfg_pull_up>;
+                       rockchip,pins = <5 RK_PB3 RK_FUNC_GPIO &pcfg_pull_up>;
                };
 
                volum_up_l: volum-up-l {
-                       rockchip,pins = <5 10 RK_FUNC_GPIO &pcfg_pull_up>;
+                       rockchip,pins = <5 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>;
                };
        };
 
        hdmi {
                vcc50_hdmi_en: vcc50-hdmi-en {
-                       rockchip,pins = <5 19 RK_FUNC_GPIO &pcfg_pull_none>;
+                       rockchip,pins = <5 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
                };
        };
 
        lcd {
                lcd_enable_h: lcd-en {
-                       rockchip,pins = <7 14 RK_FUNC_GPIO &pcfg_pull_none>;
+                       rockchip,pins = <7 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
                };
 
                avdd_1v8_disp_en: avdd-1v8-disp-en {
-                       rockchip,pins = <2 13 RK_FUNC_GPIO &pcfg_pull_none>;
+                       rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
                };
        };
 
        pmic {
                dvs_1: dvs-1 {
-                       rockchip,pins = <7 12 RK_FUNC_GPIO &pcfg_pull_down>;
+                       rockchip,pins = <7 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>;
                };
 
                dvs_2: dvs-2 {
-                       rockchip,pins = <7 15 RK_FUNC_GPIO &pcfg_pull_down>;
+                       rockchip,pins = <7 RK_PB7 RK_FUNC_GPIO &pcfg_pull_down>;
                };
        };
 
        prochot {
                gpio_prochot: gpio-prochot {
-                       rockchip,pins = <2 8 RK_FUNC_GPIO &pcfg_pull_none>;
+                       rockchip,pins = <2 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
                };
        };
 
        touchscreen {
                touch_int: touch-int {
-                       rockchip,pins = <2 14 RK_FUNC_GPIO &pcfg_pull_none>;
+                       rockchip,pins = <2 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
                };
 
                touch_rst: touch-rst {
-                       rockchip,pins = <2 15 RK_FUNC_GPIO &pcfg_pull_none>;
+                       rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
                };
        };
 };

diff --git a/arch/arm/boot/dts/rk3288-veyron-pinky.dts b/arch/arm/boot/dts/rk3288-veyron-pinky.dts
index 2950aad..9645be7 100644 (file)
--- a/arch/arm/boot/dts/rk3288-veyron-pinky.dts
+++ b/arch/arm/boot/dts/rk3288-veyron-pinky.dts
@@ -55,19 +55,19 @@
 &pinctrl {
        buttons {
                pwr_key_h: pwr-key-h {
-                       rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_none>;
+                       rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
                };
        };
 
        emmc {
                emmc_reset: emmc-reset {
-                       rockchip,pins = <7 12 RK_FUNC_GPIO &pcfg_pull_up>;
+                       rockchip,pins = <7 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>;
                };
        };
 
        sdmmc {
                sdmmc_wp_gpio: sdmmc-wp-gpio {
-                       rockchip,pins = <7 10 RK_FUNC_GPIO &pcfg_pull_up>;
+                       rockchip,pins = <7 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>;
                };
        };
 };

diff --git a/arch/arm/boot/dts/rk3288-veyron-sdmmc.dtsi b/arch/arm/boot/dts/rk3288-veyron-sdmmc.dtsi
index a457044..fe950f9 100644 (file)
--- a/arch/arm/boot/dts/rk3288-veyron-sdmmc.dtsi
+++ b/arch/arm/boot/dts/rk3288-veyron-sdmmc.dtsi
@@ -16,18 +16,18 @@
                 * We also have external pulls, so disable the internal ones.
                 */
                sdmmc_bus4: sdmmc-bus4 {
-                       rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_none_drv_8ma>,
-                                       <6 17 RK_FUNC_1 &pcfg_pull_none_drv_8ma>,
-                                       <6 18 RK_FUNC_1 &pcfg_pull_none_drv_8ma>,
-                                       <6 19 RK_FUNC_1 &pcfg_pull_none_drv_8ma>;
+                       rockchip,pins = <6 RK_PC0 1 &pcfg_pull_none_drv_8ma>,
+                                       <6 RK_PC1 1 &pcfg_pull_none_drv_8ma>,
+                                       <6 RK_PC2 1 &pcfg_pull_none_drv_8ma>,
+                                       <6 RK_PC3 1 &pcfg_pull_none_drv_8ma>;
                };
 
                sdmmc_clk: sdmmc-clk {
-                       rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none_drv_8ma>;
+                       rockchip,pins = <6 RK_PC4 1 &pcfg_pull_none_drv_8ma>;
                };
 
                sdmmc_cmd: sdmmc-cmd {
-                       rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_none_drv_8ma>;
+                       rockchip,pins = <6 RK_PC5 1 &pcfg_pull_none_drv_8ma>;
                };
 
                /*
@@ -37,12 +37,12 @@
                 * think there's a card inserted
                 */
                sdmmc_cd_disabled: sdmmc-cd-disabled {
-                       rockchip,pins = <6 22 RK_FUNC_GPIO &pcfg_pull_none>;
+                       rockchip,pins = <6 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
                };
 
                /* This is where we actually hook up CD */
                sdmmc_cd_gpio: sdmmc-cd-gpio {
-                       rockchip,pins = <7 5 RK_FUNC_GPIO &pcfg_pull_none>;
+                       rockchip,pins = <7 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
                };
        };
 };

diff --git a/arch/arm/boot/dts/rk3288-veyron-speedy.dts b/arch/arm/boot/dts/rk3288-veyron-speedy.dts
index e16421d..2ac8748 100644 (file)
--- a/arch/arm/boot/dts/rk3288-veyron-speedy.dts
+++ b/arch/arm/boot/dts/rk3288-veyron-speedy.dts
@@ -104,39 +104,39 @@
 &pinctrl {
        backlight {
                bl_pwr_en: bl_pwr_en {
-                       rockchip,pins = <2 12 RK_FUNC_GPIO &pcfg_pull_none>;
+                       rockchip,pins = <2 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>;
                };
        };
 
        buck-5v {
                drv_5v: drv-5v {
-                       rockchip,pins = <7 21 RK_FUNC_GPIO &pcfg_pull_none>;
+                       rockchip,pins = <7 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
                };
        };
 
        hdmi {
                vcc50_hdmi_en: vcc50-hdmi-en {
-                       rockchip,pins = <5 19 RK_FUNC_GPIO &pcfg_pull_none>;
+                       rockchip,pins = <5 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
                };
        };
 
        lcd {
                lcd_enable_h: lcd-en {
-                       rockchip,pins = <7 14 RK_FUNC_GPIO &pcfg_pull_none>;
+                       rockchip,pins = <7 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
                };
 
                avdd_1v8_disp_en: avdd-1v8-disp-en {
-                       rockchip,pins = <2 13 RK_FUNC_GPIO &pcfg_pull_none>;
+                       rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
                };
        };
 
        pmic {
                dvs_1: dvs-1 {
-                       rockchip,pins = <7 12 RK_FUNC_GPIO &pcfg_pull_down>;
+                       rockchip,pins = <7 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>;
                };
 
                dvs_2: dvs-2 {
-                       rockchip,pins = <7 15 RK_FUNC_GPIO &pcfg_pull_down>;
+                       rockchip,pins = <7 RK_PB7 RK_FUNC_GPIO &pcfg_pull_down>;
                };
        };
 };

diff --git a/arch/arm/boot/dts/rk3288-veyron.dtsi b/arch/arm/boot/dts/rk3288-veyron.dtsi
index 192dbc0..1252522 100644 (file)
--- a/arch/arm/boot/dts/rk3288-veyron.dtsi
+++ b/arch/arm/boot/dts/rk3288-veyron.dtsi
@@ -60,12 +60,19 @@
                pinctrl-0 = <&bt_enable_l>, <&wifi_enable_h>;
 
                /*
-                * On the module itself this is one of these (depending
-                * on the actual card populated):
+                * Depending on the actual card populated GPIO4 D4 and D5
+                * correspond to one of these signals on the module:
+                *
+                * D4:
                 * - SDIO_RESET_L_WL_REG_ON
                 * - PDN (power down when low)
+                *
+                * D5:
+                * - BT_I2S_WS_BT_RFDISABLE_L
+                * - No connect
                 */
-               reset-gpios = <&gpio4 RK_PD4 GPIO_ACTIVE_LOW>;
+               reset-gpios = <&gpio4 RK_PD4 GPIO_ACTIVE_LOW>,
+                             <&gpio4 RK_PD5 GPIO_ACTIVE_LOW>;
        };
 
        vcc_5v: vcc-5v {
@@ -93,6 +100,23 @@
                regulator-boot-on;
                vin-supply = <&vcc_5v>;
        };
+
+       vdd_logic: vdd-logic {
+               compatible = "pwm-regulator";
+               regulator-name = "vdd_logic";
+
+               pwms = <&pwm1 0 1994 0>;
+               pwm-supply = <&vcc33_sys>;
+
+               pwm-dutycycle-range = <0x7b 0>;
+               pwm-dutycycle-unit = <0x94>;
+
+               regulator-always-on;
+               regulator-boot-on;
+               regulator-min-microvolt = <950000>;
+               regulator-max-microvolt = <1350000>;
+               regulator-ramp-delay = <4000>;
+       };
 };
 
 &cpu0 {
@@ -193,8 +217,7 @@
                                regulator-max-microvolt = <1250000>;
                                regulator-ramp-delay = <6001>;
                                regulator-state-mem {
-                                       regulator-on-in-suspend;
-                                       regulator-suspend-microvolt = <1000000>;
+                                       regulator-off-in-suspend;
                                };
                        };
 
@@ -376,10 +399,6 @@
 &uart0 {
        status = "okay";
 
-       /* We need to go faster than 24MHz, so adjust clock parents / rates */
-       assigned-clocks = <&cru SCLK_UART0>;
-       assigned-clock-rates = <48000000>;
-
        /* Pins don't include flow control by default; add that in */
        pinctrl-names = "default";
        pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
@@ -431,10 +450,14 @@
        pinctrl-names = "default", "sleep";
        pinctrl-0 = <
                /* Common for sleep and wake, but no owners */
+               &ddr0_retention
+               &ddrio_pwroff
                &global_pwroff
        >;
        pinctrl-1 = <
                /* Common for sleep and wake, but no owners */
+               &ddr0_retention
+               &ddrio_pwroff
                &global_pwroff
        >;
 
@@ -458,13 +481,13 @@
 
        buttons {
                pwr_key_l: pwr-key-l {
-                       rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_up>;
+                       rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;
                };
        };
 
        emmc {
                emmc_reset: emmc-reset {
-                       rockchip,pins = <2 9 RK_FUNC_GPIO &pcfg_pull_none>;
+                       rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
                };
 
                /*
@@ -472,51 +495,51 @@
                 * We also have external pulls, so disable the internal ones.
                 */
                emmc_clk: emmc-clk {
-                       rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none_drv_8ma>;
+                       rockchip,pins = <3 RK_PC2 2 &pcfg_pull_none_drv_8ma>;
                };
 
                emmc_cmd: emmc-cmd {
-                       rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_none_drv_8ma>;
+                       rockchip,pins = <3 RK_PC0 2 &pcfg_pull_none_drv_8ma>;
                };
 
                emmc_bus8: emmc-bus8 {
-                       rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_none_drv_8ma>,
-                                       <3 1 RK_FUNC_2 &pcfg_pull_none_drv_8ma>,
-                                       <3 2 RK_FUNC_2 &pcfg_pull_none_drv_8ma>,
-                                       <3 3 RK_FUNC_2 &pcfg_pull_none_drv_8ma>,
-                                       <3 4 RK_FUNC_2 &pcfg_pull_none_drv_8ma>,
-                                       <3 5 RK_FUNC_2 &pcfg_pull_none_drv_8ma>,
-                                       <3 6 RK_FUNC_2 &pcfg_pull_none_drv_8ma>,
-                                       <3 7 RK_FUNC_2 &pcfg_pull_none_drv_8ma>;
+                       rockchip,pins = <3 RK_PA0 2 &pcfg_pull_none_drv_8ma>,
+                                       <3 RK_PA1 2 &pcfg_pull_none_drv_8ma>,
+                                       <3 RK_PA2 2 &pcfg_pull_none_drv_8ma>,
+                                       <3 RK_PA3 2 &pcfg_pull_none_drv_8ma>,
+                                       <3 RK_PA4 2 &pcfg_pull_none_drv_8ma>,
+                                       <3 RK_PA5 2 &pcfg_pull_none_drv_8ma>,
+                                       <3 RK_PA6 2 &pcfg_pull_none_drv_8ma>,
+                                       <3 RK_PA7 2 &pcfg_pull_none_drv_8ma>;
                };
        };
 
        pmic {
                pmic_int_l: pmic-int-l {
-                       rockchip,pins = <RK_GPIO0 4 RK_FUNC_GPIO &pcfg_pull_up>;
+                       rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>;
                };
        };
 
        reboot {
                ap_warm_reset_h: ap-warm-reset-h {
-                       rockchip,pins = <RK_GPIO0 13 RK_FUNC_GPIO &pcfg_pull_none>;
+                       rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
                };
        };
 
        recovery-switch {
                rec_mode_l: rec-mode-l {
-                       rockchip,pins = <0 9 RK_FUNC_GPIO &pcfg_pull_up>;
+                       rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>;
                };
        };
 
        sdio0 {
                wifi_enable_h: wifienable-h {
-                       rockchip,pins = <4 28 RK_FUNC_GPIO &pcfg_pull_none>;
+                       rockchip,pins = <4 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
                };
 
                /* NOTE: mislabelled on schematic; should be bt_enable_h */
                bt_enable_l: bt-enable-l {
-                       rockchip,pins = <4 29 RK_FUNC_GPIO &pcfg_pull_none>;
+                       rockchip,pins = <4 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
                };
 
                /*
@@ -524,30 +547,30 @@
                 * We also have external pulls, so disable the internal ones.
                 */
                sdio0_bus4: sdio0-bus4 {
-                       rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_none_drv_8ma>,
-                                       <4 21 RK_FUNC_1 &pcfg_pull_none_drv_8ma>,
-                                       <4 22 RK_FUNC_1 &pcfg_pull_none_drv_8ma>,
-                                       <4 23 RK_FUNC_1 &pcfg_pull_none_drv_8ma>;
+                       rockchip,pins = <4 RK_PC4 1 &pcfg_pull_none_drv_8ma>,
+                                       <4 RK_PC5 1 &pcfg_pull_none_drv_8ma>,
+                                       <4 RK_PC6 1 &pcfg_pull_none_drv_8ma>,
+                                       <4 RK_PC7 1 &pcfg_pull_none_drv_8ma>;
                };
 
                sdio0_cmd: sdio0-cmd {
-                       rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_none_drv_8ma>;
+                       rockchip,pins = <4 RK_PD0 1 &pcfg_pull_none_drv_8ma>;
                };
 
                sdio0_clk: sdio0-clk {
-                       rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none_drv_8ma>;
+                       rockchip,pins = <4 RK_PD1 1 &pcfg_pull_none_drv_8ma>;
                };
        };
 
        tpm {
                tpm_int_h: tpm-int-h {
-                       rockchip,pins = <7 4 RK_FUNC_GPIO &pcfg_pull_none>;
+                       rockchip,pins = <7 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
                };
        };
 
        write-protect {
                fw_wp_ap: fw-wp-ap {
-                       rockchip,pins = <7 6 RK_FUNC_GPIO &pcfg_pull_none>;
+                       rockchip,pins = <7 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
                };
        };
 };

diff --git a/arch/arm/boot/dts/rk3288-vyasa.dts b/arch/arm/boot/dts/rk3288-vyasa.dts
index 40b232e..ba06e9f 100644 (file)
--- a/arch/arm/boot/dts/rk3288-vyasa.dts
+++ b/arch/arm/boot/dts/rk3288-vyasa.dts
@@ -448,13 +448,13 @@
 
        pmic {
                pmic_int: pmic-int {
-                       rockchip,pins = <RK_GPIO0 4 RK_FUNC_GPIO &pcfg_pull_up>;
+                       rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>;
                };
        };
 
        usb_host {
                phy_pwr_en: phy-pwr-en {
-                       rockchip,pins = <RK_GPIO2 RK_PB1 RK_FUNC_GPIO &pcfg_output_high>;
+                       rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_output_high>;
                };
 
                usb2_pwr_en: usb2-pwr-en {
@@ -464,7 +464,7 @@
 
        usb_otg {
                otg_vbus_drv: otg-vbus-drv {
-                       rockchip,pins = <RK_GPIO0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>;
+                       rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>;
 
                };
        };

diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 8ce3dd2..aa017ab 100644 (file)
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -64,6 +64,7 @@
                        #cooling-cells = <2>; /* min followed by max */
                        clock-latency = <40000>;
                        clocks = <&cru ARMCLK>;
+                       dynamic-power-coefficient = <370>;
                };
                cpu1: cpu@501 {
                        device_type = "cpu";
@@ -74,6 +75,7 @@
                        #cooling-cells = <2>; /* min followed by max */
                        clock-latency = <40000>;
                        clocks = <&cru ARMCLK>;
+                       dynamic-power-coefficient = <370>;
                };
                cpu2: cpu@502 {
                        device_type = "cpu";
@@ -84,6 +86,7 @@
                        #cooling-cells = <2>; /* min followed by max */
                        clock-latency = <40000>;
                        clocks = <&cru ARMCLK>;
+                       dynamic-power-coefficient = <370>;
                };
                cpu3: cpu@503 {
                        device_type = "cpu";
@@ -94,6 +97,7 @@
                        #cooling-cells = <2>; /* min followed by max */
                        clock-latency = <40000>;
                        clocks = <&cru ARMCLK>;
+                       dynamic-power-coefficient = <370>;
                };
        };
 
@@ -569,6 +573,7 @@
                pinctrl-1 = <&otp_out>;
                pinctrl-2 = <&otp_gpio>;
                #thermal-sensor-cells = <1>;
+               rockchip,grf = <&grf>;
                rockchip,hw-tshut-temp = <95000>;
                status = "disabled";
        };
@@ -1383,19 +1388,6 @@
                reg = <0x0 0xffaf0080 0x0 0x20>;
        };
 
-       gic: interrupt-controller@ffc01000 {
-               compatible = "arm,gic-400";
-               interrupt-controller;
-               #interrupt-cells = <3>;
-               #address-cells = <0>;
-
-               reg = <0x0 0xffc01000 0x0 0x1000>,
-                     <0x0 0xffc02000 0x0 0x2000>,
-                     <0x0 0xffc04000 0x0 0x2000>,
-                     <0x0 0xffc06000 0x0 0x2000>;
-               interrupts = <GIC_PPI 9 0xf04>;
-       };
-
        efuse: efuse@ffb40000 {
                compatible = "rockchip,rk3288-efuse";
                reg = <0x0 0xffb40000 0x0 0x20>;
@@ -1409,6 +1401,19 @@
                };
        };
 
+       gic: interrupt-controller@ffc01000 {
+               compatible = "arm,gic-400";
+               interrupt-controller;
+               #interrupt-cells = <3>;
+               #address-cells = <0>;
+
+               reg = <0x0 0xffc01000 0x0 0x1000>,
+                     <0x0 0xffc02000 0x0 0x2000>,
+                     <0x0 0xffc04000 0x0 0x2000>,
+                     <0x0 0xffc06000 0x0 0x2000>;
+               interrupts = <GIC_PPI 9 0xf04>;
+       };
+
        pinctrl: pinctrl {
                compatible = "rockchip,rk3288-pinctrl";
                rockchip,grf = <&grf>;
@@ -1536,16 +1541,16 @@
 
                hdmi {
                        hdmi_cec_c0: hdmi-cec-c0 {
-                               rockchip,pins = <7 RK_PC0 RK_FUNC_2 &pcfg_pull_none>;
+                               rockchip,pins = <7 RK_PC0 2 &pcfg_pull_none>;
                        };
 
                        hdmi_cec_c7: hdmi-cec-c7 {
-                               rockchip,pins = <7 RK_PC7 RK_FUNC_4 &pcfg_pull_none>;
+                               rockchip,pins = <7 RK_PC7 4 &pcfg_pull_none>;
                        };
 
                        hdmi_ddc: hdmi-ddc {
-                               rockchip,pins = <7 19 RK_FUNC_2 &pcfg_pull_none>,
-                                               <7 20 RK_FUNC_2 &pcfg_pull_none>;
+                               rockchip,pins = <7 RK_PC3 2 &pcfg_pull_none>,
+                                               <7 RK_PC4 2 &pcfg_pull_none>;
                        };
                };
 
@@ -1568,421 +1573,421 @@
 
                sleep {
                        global_pwroff: global-pwroff {
-                               rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>;
+                               rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>;
                        };
 
                        ddrio_pwroff: ddrio-pwroff {
-                               rockchip,pins = <0 1 RK_FUNC_1 &pcfg_pull_none>;
+                               rockchip,pins = <0 RK_PA1 1 &pcfg_pull_none>;
                        };
 
                        ddr0_retention: ddr0-retention {
-                               rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_up>;
+                               rockchip,pins = <0 RK_PA2 1 &pcfg_pull_up>;
                        };
 
                        ddr1_retention: ddr1-retention {
-                               rockchip,pins = <0 3 RK_FUNC_1 &pcfg_pull_up>;
+                               rockchip,pins = <0 RK_PA3 1 &pcfg_pull_up>;
                        };
                };
 
                edp {
                        edp_hpd: edp-hpd {
-                               rockchip,pins = <7 11 RK_FUNC_2 &pcfg_pull_down>;
+                               rockchip,pins = <7 RK_PB3 2 &pcfg_pull_down>;
                        };
                };
 
                i2c0 {
                        i2c0_xfer: i2c0-xfer {
-                               rockchip,pins = <0 15 RK_FUNC_1 &pcfg_pull_none>,
-                                               <0 16 RK_FUNC_1 &pcfg_pull_none>;
+                               rockchip,pins = <0 RK_PB7 1 &pcfg_pull_none>,
+                                               <0 RK_PC0 1 &pcfg_pull_none>;
                        };
                };
 
                i2c1 {
                        i2c1_xfer: i2c1-xfer {
-                               rockchip,pins = <8 4 RK_FUNC_1 &pcfg_pull_none>,
-                                               <8 5 RK_FUNC_1 &pcfg_pull_none>;
+                               rockchip,pins = <8 RK_PA4 1 &pcfg_pull_none>,
+                                               <8 RK_PA5 1 &pcfg_pull_none>;
                        };
                };
 
                i2c2 {
                        i2c2_xfer: i2c2-xfer {
-                               rockchip,pins = <6 9 RK_FUNC_1 &pcfg_pull_none>,
-                                               <6 10 RK_FUNC_1 &pcfg_pull_none>;
+                               rockchip,pins = <6 RK_PB1 1 &pcfg_pull_none>,
+                                               <6 RK_PB2 1 &pcfg_pull_none>;
                        };
                };
 
                i2c3 {
                        i2c3_xfer: i2c3-xfer {
-                               rockchip,pins = <2 16 RK_FUNC_1 &pcfg_pull_none>,
-                                               <2 17 RK_FUNC_1 &pcfg_pull_none>;
+                               rockchip,pins = <2 RK_PC0 1 &pcfg_pull_none>,
+                                               <2 RK_PC1 1 &pcfg_pull_none>;
                        };
                };
 
                i2c4 {
                        i2c4_xfer: i2c4-xfer {
-                               rockchip,pins = <7 17 RK_FUNC_1 &pcfg_pull_none>,
-                                               <7 18 RK_FUNC_1 &pcfg_pull_none>;
+                               rockchip,pins = <7 RK_PC1 1 &pcfg_pull_none>,
+                                               <7 RK_PC2 1 &pcfg_pull_none>;
                        };
                };
 
                i2c5 {
                        i2c5_xfer: i2c5-xfer {
-                               rockchip,pins = <7 19 RK_FUNC_1 &pcfg_pull_none>,
-                                               <7 20 RK_FUNC_1 &pcfg_pull_none>;
+                               rockchip,pins = <7 RK_PC3 1 &pcfg_pull_none>,
+                                               <7 RK_PC4 1 &pcfg_pull_none>;
                        };
                };
 
                i2s0 {
                        i2s0_bus: i2s0-bus {
-                               rockchip,pins = <6 0 RK_FUNC_1 &pcfg_pull_none>,
-                                               <6 1 RK_FUNC_1 &pcfg_pull_none>,
-                                               <6 2 RK_FUNC_1 &pcfg_pull_none>,
-                                               <6 3 RK_FUNC_1 &pcfg_pull_none>,
-                                               <6 4 RK_FUNC_1 &pcfg_pull_none>,
-                                               <6 8 RK_FUNC_1 &pcfg_pull_none>;
+                               rockchip,pins = <6 RK_PA0 1 &pcfg_pull_none>,
+                                               <6 RK_PA1 1 &pcfg_pull_none>,
+                                               <6 RK_PA2 1 &pcfg_pull_none>,
+                                               <6 RK_PA3 1 &pcfg_pull_none>,
+                                               <6 RK_PA4 1 &pcfg_pull_none>,
+                                               <6 RK_PB0 1 &pcfg_pull_none>;
                        };
                };
 
                lcdc {
                        lcdc_ctl: lcdc-ctl {
-                               rockchip,pins = <1 24 RK_FUNC_1 &pcfg_pull_none>,
-                                               <1 25 RK_FUNC_1 &pcfg_pull_none>,
-                                               <1 26 RK_FUNC_1 &pcfg_pull_none>,
-                                               <1 27 RK_FUNC_1 &pcfg_pull_none>;
+                               rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>,
+                                               <1 RK_PD1 1 &pcfg_pull_none>,
+                                               <1 RK_PD2 1 &pcfg_pull_none>,
+                                               <1 RK_PD3 1 &pcfg_pull_none>;
                        };
                };
 
                sdmmc {
                        sdmmc_clk: sdmmc-clk {
-                               rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none>;
+                               rockchip,pins = <6 RK_PC4 1 &pcfg_pull_none>;
                        };
 
                        sdmmc_cmd: sdmmc-cmd {
-                               rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up>;
+                               rockchip,pins = <6 RK_PC5 1 &pcfg_pull_up>;
                        };
 
                        sdmmc_cd: sdmmc-cd {
-                               rockchip,pins = <6 22 RK_FUNC_1 &pcfg_pull_up>;
+                               rockchip,pins = <6 RK_PC6 1 &pcfg_pull_up>;
                        };
 
                        sdmmc_bus1: sdmmc-bus1 {
-                               rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>;
+                               rockchip,pins = <6 RK_PC0 1 &pcfg_pull_up>;
                        };
 
                        sdmmc_bus4: sdmmc-bus4 {
-                               rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>,
-                                               <6 17 RK_FUNC_1 &pcfg_pull_up>,
-                                               <6 18 RK_FUNC_1 &pcfg_pull_up>,
-                                               <6 19 RK_FUNC_1 &pcfg_pull_up>;
+                               rockchip,pins = <6 RK_PC0 1 &pcfg_pull_up>,
+                                               <6 RK_PC1 1 &pcfg_pull_up>,
+                                               <6 RK_PC2 1 &pcfg_pull_up>,
+                                               <6 RK_PC3 1 &pcfg_pull_up>;
                        };
                };
 
                sdio0 {
                        sdio0_bus1: sdio0-bus1 {
-                               rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>;
+                               rockchip,pins = <4 RK_PC4 1 &pcfg_pull_up>;
                        };
 
                        sdio0_bus4: sdio0-bus4 {
-                               rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>,
-                                               <4 21 RK_FUNC_1 &pcfg_pull_up>,
-                                               <4 22 RK_FUNC_1 &pcfg_pull_up>,
-                                               <4 23 RK_FUNC_1 &pcfg_pull_up>;
+                               rockchip,pins = <4 RK_PC4 1 &pcfg_pull_up>,
+                                               <4 RK_PC5 1 &pcfg_pull_up>,
+                                               <4 RK_PC6 1 &pcfg_pull_up>,
+                                               <4 RK_PC7 1 &pcfg_pull_up>;
                        };
 
                        sdio0_cmd: sdio0-cmd {
-                               rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_up>;
+                               rockchip,pins = <4 RK_PD0 1 &pcfg_pull_up>;
                        };
 
                        sdio0_clk: sdio0-clk {
-                               rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none>;
+                               rockchip,pins = <4 RK_PD1 1 &pcfg_pull_none>;
                        };
 
                        sdio0_cd: sdio0-cd {
-                               rockchip,pins = <4 26 RK_FUNC_1 &pcfg_pull_up>;
+                               rockchip,pins = <4 RK_PD2 1 &pcfg_pull_up>;
                        };
 
                        sdio0_wp: sdio0-wp {
-                               rockchip,pins = <4 27 RK_FUNC_1 &pcfg_pull_up>;
+                               rockchip,pins = <4 RK_PD3 1 &pcfg_pull_up>;
                        };
 
                        sdio0_pwr: sdio0-pwr {
-                               rockchip,pins = <4 28 RK_FUNC_1 &pcfg_pull_up>;
+                               rockchip,pins = <4 RK_PD4 1 &pcfg_pull_up>;
                        };
 
                        sdio0_bkpwr: sdio0-bkpwr {
-                               rockchip,pins = <4 29 RK_FUNC_1 &pcfg_pull_up>;
+                               rockchip,pins = <4 RK_PD5 1 &pcfg_pull_up>;
                        };
 
                        sdio0_int: sdio0-int {
-                               rockchip,pins = <4 30 RK_FUNC_1 &pcfg_pull_up>;
+                               rockchip,pins = <4 RK_PD6 1 &pcfg_pull_up>;
                        };
                };
 
                sdio1 {
                        sdio1_bus1: sdio1-bus1 {
-                               rockchip,pins = <3 24 4 &pcfg_pull_up>;
+                               rockchip,pins = <3 RK_PD0 4 &pcfg_pull_up>;
                        };
 
                        sdio1_bus4: sdio1-bus4 {
-                               rockchip,pins = <3 24 4 &pcfg_pull_up>,
-                                               <3 25 4 &pcfg_pull_up>,
-                                               <3 26 4 &pcfg_pull_up>,
-                                               <3 27 4 &pcfg_pull_up>;
+                               rockchip,pins = <3 RK_PD0 4 &pcfg_pull_up>,
+                                               <3 RK_PD1 4 &pcfg_pull_up>,
+                                               <3 RK_PD2 4 &pcfg_pull_up>,
+                                               <3 RK_PD3 4 &pcfg_pull_up>;
                        };
 
                        sdio1_cd: sdio1-cd {
-                               rockchip,pins = <3 28 4 &pcfg_pull_up>;
+                               rockchip,pins = <3 RK_PD4 4 &pcfg_pull_up>;
                        };
 
                        sdio1_wp: sdio1-wp {
-                               rockchip,pins = <3 29 4 &pcfg_pull_up>;
+                               rockchip,pins = <3 RK_PD5 4 &pcfg_pull_up>;
                        };
 
                        sdio1_bkpwr: sdio1-bkpwr {
-                               rockchip,pins = <3 30 4 &pcfg_pull_up>;
+                               rockchip,pins = <3 RK_PD6 4 &pcfg_pull_up>;
                        };
 
                        sdio1_int: sdio1-int {
-                               rockchip,pins = <3 31 4 &pcfg_pull_up>;
+                               rockchip,pins = <3 RK_PD7 4 &pcfg_pull_up>;
                        };
 
                        sdio1_cmd: sdio1-cmd {
-                               rockchip,pins = <4 6 4 &pcfg_pull_up>;
+                               rockchip,pins = <4 RK_PA6 4 &pcfg_pull_up>;
                        };
 
                        sdio1_clk: sdio1-clk {
-                               rockchip,pins = <4 7 4 &pcfg_pull_none>;
+                               rockchip,pins = <4 RK_PA7 4 &pcfg_pull_none>;
                        };
 
                        sdio1_pwr: sdio1-pwr {
-                               rockchip,pins = <4 9 4 &pcfg_pull_up>;
+                               rockchip,pins = <4 RK_PB1 4 &pcfg_pull_up>;
                        };
                };
 
                emmc {
                        emmc_clk: emmc-clk {
-                               rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none>;
+                               rockchip,pins = <3 RK_PC2 2 &pcfg_pull_none>;
                        };
 
                        emmc_cmd: emmc-cmd {
-                               rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_up>;
+                               rockchip,pins = <3 RK_PC0 2 &pcfg_pull_up>;
                        };
 
                        emmc_pwr: emmc-pwr {
-                               rockchip,pins = <3 9 RK_FUNC_2 &pcfg_pull_up>;
+                               rockchip,pins = <3 RK_PB1 2 &pcfg_pull_up>;
                        };
 
                        emmc_bus1: emmc-bus1 {
-                               rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>;
+                               rockchip,pins = <3 RK_PA0 2 &pcfg_pull_up>;
                        };
 
                        emmc_bus4: emmc-bus4 {
-                               rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
-                                               <3 1 RK_FUNC_2 &pcfg_pull_up>,
-                                               <3 2 RK_FUNC_2 &pcfg_pull_up>,
-                                               <3 3 RK_FUNC_2 &pcfg_pull_up>;
+                               rockchip,pins = <3 RK_PA0 2 &pcfg_pull_up>,
+                                               <3 RK_PA1 2 &pcfg_pull_up>,
+                                               <3 RK_PA2 2 &pcfg_pull_up>,
+                                               <3 RK_PA3 2 &pcfg_pull_up>;
                        };
 
                        emmc_bus8: emmc-bus8 {
-                               rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
-                                               <3 1 RK_FUNC_2 &pcfg_pull_up>,
-                                               <3 2 RK_FUNC_2 &pcfg_pull_up>,
-                                               <3 3 RK_FUNC_2 &pcfg_pull_up>,
-                                               <3 4 RK_FUNC_2 &pcfg_pull_up>,
-                                               <3 5 RK_FUNC_2 &pcfg_pull_up>,
-                                               <3 6 RK_FUNC_2 &pcfg_pull_up>,
-                                               <3 7 RK_FUNC_2 &pcfg_pull_up>;
+                               rockchip,pins = <3 RK_PA0 2 &pcfg_pull_up>,
+                                               <3 RK_PA1 2 &pcfg_pull_up>,
+                                               <3 RK_PA2 2 &pcfg_pull_up>,
+                                               <3 RK_PA3 2 &pcfg_pull_up>,
+                                               <3 RK_PA4 2 &pcfg_pull_up>,
+                                               <3 RK_PA5 2 &pcfg_pull_up>,
+                                               <3 RK_PA6 2 &pcfg_pull_up>,
+                                               <3 RK_PA7 2 &pcfg_pull_up>;
                        };
                };
 
                spi0 {
                        spi0_clk: spi0-clk {
-                               rockchip,pins = <5 12 RK_FUNC_1 &pcfg_pull_up>;
+                               rockchip,pins = <5 RK_PB4 1 &pcfg_pull_up>;
                        };
                        spi0_cs0: spi0-cs0 {
-                               rockchip,pins = <5 13 RK_FUNC_1 &pcfg_pull_up>;
+                               rockchip,pins = <5 RK_PB5 1 &pcfg_pull_up>;
                        };
                        spi0_tx: spi0-tx {
-                               rockchip,pins = <5 14 RK_FUNC_1 &pcfg_pull_up>;
+                               rockchip,pins = <5 RK_PB6 1 &pcfg_pull_up>;
                        };
                        spi0_rx: spi0-rx {
-                               rockchip,pins = <5 15 RK_FUNC_1 &pcfg_pull_up>;
+                               rockchip,pins = <5 RK_PB7 1 &pcfg_pull_up>;
                        };
                        spi0_cs1: spi0-cs1 {
-                               rockchip,pins = <5 16 RK_FUNC_1 &pcfg_pull_up>;
+                               rockchip,pins = <5 RK_PC0 1 &pcfg_pull_up>;
                        };
                };
                spi1 {
                        spi1_clk: spi1-clk {
-                               rockchip,pins = <7 12 RK_FUNC_2 &pcfg_pull_up>;
+                               rockchip,pins = <7 RK_PB4 2 &pcfg_pull_up>;
                        };
                        spi1_cs0: spi1-cs0 {
-                               rockchip,pins = <7 13 RK_FUNC_2 &pcfg_pull_up>;
+                               rockchip,pins = <7 RK_PB5 2 &pcfg_pull_up>;
                        };
                        spi1_rx: spi1-rx {
-                               rockchip,pins = <7 14 RK_FUNC_2 &pcfg_pull_up>;
+                               rockchip,pins = <7 RK_PB6 2 &pcfg_pull_up>;
                        };
                        spi1_tx: spi1-tx {
-                               rockchip,pins = <7 15 RK_FUNC_2 &pcfg_pull_up>;
+                               rockchip,pins = <7 RK_PB7 2 &pcfg_pull_up>;
                        };
                };
 
                spi2 {
                        spi2_cs1: spi2-cs1 {
-                               rockchip,pins = <8 3 RK_FUNC_1 &pcfg_pull_up>;
+                               rockchip,pins = <8 RK_PA3 1 &pcfg_pull_up>;
                        };
                        spi2_clk: spi2-clk {
-                               rockchip,pins = <8 6 RK_FUNC_1 &pcfg_pull_up>;
+                               rockchip,pins = <8 RK_PA6 1 &pcfg_pull_up>;
                        };
                        spi2_cs0: spi2-cs0 {
-                               rockchip,pins = <8 7 RK_FUNC_1 &pcfg_pull_up>;
+                               rockchip,pins = <8 RK_PA7 1 &pcfg_pull_up>;
                        };
                        spi2_rx: spi2-rx {
-                               rockchip,pins = <8 8 RK_FUNC_1 &pcfg_pull_up>;
+                               rockchip,pins = <8 RK_PB0 1 &pcfg_pull_up>;
                        };
                        spi2_tx: spi2-tx {
-                               rockchip,pins = <8 9 RK_FUNC_1 &pcfg_pull_up>;
+                               rockchip,pins = <8 RK_PB1 1 &pcfg_pull_up>;
                        };
                };
 
                uart0 {
                        uart0_xfer: uart0-xfer {
-                               rockchip,pins = <4 16 RK_FUNC_1 &pcfg_pull_up>,
-                                               <4 17 RK_FUNC_1 &pcfg_pull_none>;
+                               rockchip,pins = <4 RK_PC0 1 &pcfg_pull_up>,
+                                               <4 RK_PC1 1 &pcfg_pull_none>;
                        };
 
                        uart0_cts: uart0-cts {
-                               rockchip,pins = <4 18 RK_FUNC_1 &pcfg_pull_up>;
+                               rockchip,pins = <4 RK_PC2 1 &pcfg_pull_up>;
                        };
 
                        uart0_rts: uart0-rts {
-                               rockchip,pins = <4 19 RK_FUNC_1 &pcfg_pull_none>;
+                               rockchip,pins = <4 RK_PC3 1 &pcfg_pull_none>;
                        };
                };
 
                uart1 {
                        uart1_xfer: uart1-xfer {
-                               rockchip,pins = <5 8 RK_FUNC_1 &pcfg_pull_up>,
-                                               <5 9 RK_FUNC_1 &pcfg_pull_none>;
+                               rockchip,pins = <5 RK_PB0 1 &pcfg_pull_up>,
+                                               <5 RK_PB1 1 &pcfg_pull_none>;
                        };
 
                        uart1_cts: uart1-cts {
-                               rockchip,pins = <5 10 RK_FUNC_1 &pcfg_pull_up>;
+                               rockchip,pins = <5 RK_PB2 1 &pcfg_pull_up>;
                        };
 
                        uart1_rts: uart1-rts {
-                               rockchip,pins = <5 11 RK_FUNC_1 &pcfg_pull_none>;
+                               rockchip,pins = <5 RK_PB3 1 &pcfg_pull_none>;
                        };
                };
 
                uart2 {
                        uart2_xfer: uart2-xfer {
-                               rockchip,pins = <7 22 RK_FUNC_1 &pcfg_pull_up>,
-                                               <7 23 RK_FUNC_1 &pcfg_pull_none>;
+                               rockchip,pins = <7 RK_PC6 1 &pcfg_pull_up>,
+                                               <7 RK_PC7 1 &pcfg_pull_none>;
                        };
                        /* no rts / cts for uart2 */
                };
 
                uart3 {
                        uart3_xfer: uart3-xfer {
-                               rockchip,pins = <7 7 RK_FUNC_1 &pcfg_pull_up>,
-                                               <7 8 RK_FUNC_1 &pcfg_pull_none>;
+                               rockchip,pins = <7 RK_PA7 1 &pcfg_pull_up>,
+                                               <7 RK_PB0 1 &pcfg_pull_none>;
                        };
 
                        uart3_cts: uart3-cts {
-                               rockchip,pins = <7 9 RK_FUNC_1 &pcfg_pull_up>;
+                               rockchip,pins = <7 RK_PB1 1 &pcfg_pull_up>;
                        };
 
                        uart3_rts: uart3-rts {
-                               rockchip,pins = <7 10 RK_FUNC_1 &pcfg_pull_none>;
+                               rockchip,pins = <7 RK_PB2 1 &pcfg_pull_none>;
                        };
                };
 
                uart4 {
                        uart4_xfer: uart4-xfer {
-                               rockchip,pins = <5 15 3 &pcfg_pull_up>,
-                                               <5 14 3 &pcfg_pull_none>;
+                               rockchip,pins = <5 RK_PB7 3 &pcfg_pull_up>,
+                                               <5 RK_PB6 3 &pcfg_pull_none>;
                        };
 
                        uart4_cts: uart4-cts {
-                               rockchip,pins = <5 12 3 &pcfg_pull_up>;
+                               rockchip,pins = <5 RK_PB4 3 &pcfg_pull_up>;
                        };
 
                        uart4_rts: uart4-rts {
-                               rockchip,pins = <5 13 3 &pcfg_pull_none>;
+                               rockchip,pins = <5 RK_PB5 3 &pcfg_pull_none>;
                        };
                };
 
                tsadc {
                        otp_gpio: otp-gpio {
-                               rockchip,pins = <0 10 RK_FUNC_GPIO &pcfg_pull_none>;
+                               rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
                        };
 
                        otp_out: otp-out {
-                               rockchip,pins = <0 10 RK_FUNC_1 &pcfg_pull_none>;
+                               rockchip,pins = <0 RK_PB2 1 &pcfg_pull_none>;
                        };
                };
 
                pwm0 {
                        pwm0_pin: pwm0-pin {
-                               rockchip,pins = <7 0 RK_FUNC_1 &pcfg_pull_none>;
+                               rockchip,pins = <7 RK_PA0 1 &pcfg_pull_none>;
                        };
                };
 
                pwm1 {
                        pwm1_pin: pwm1-pin {
-                               rockchip,pins = <7 1 RK_FUNC_1 &pcfg_pull_none>;
+                               rockchip,pins = <7 RK_PA1 1 &pcfg_pull_none>;
                        };
                };
 
                pwm2 {
                        pwm2_pin: pwm2-pin {
-                               rockchip,pins = <7 22 3 &pcfg_pull_none>;
+                               rockchip,pins = <7 RK_PC6 3 &pcfg_pull_none>;
                        };
                };
 
                pwm3 {
                        pwm3_pin: pwm3-pin {
-                               rockchip,pins = <7 23 3 &pcfg_pull_none>;
+                               rockchip,pins = <7 RK_PC7 3 &pcfg_pull_none>;
                        };
                };
 
                gmac {
                        rgmii_pins: rgmii-pins {
-                               rockchip,pins = <3 30 3 &pcfg_pull_none>,
-                                               <3 31 3 &pcfg_pull_none>,
-                                               <3 26 3 &pcfg_pull_none>,
-                                               <3 27 3 &pcfg_pull_none>,
-                                               <3 28 3 &pcfg_pull_none_12ma>,
-                                               <3 29 3 &pcfg_pull_none_12ma>,
-                                               <3 24 3 &pcfg_pull_none_12ma>,
-                                               <3 25 3 &pcfg_pull_none_12ma>,
-                                               <4 0 3 &pcfg_pull_none>,
-                                               <4 5 3 &pcfg_pull_none>,
-                                               <4 6 3 &pcfg_pull_none>,
-                                               <4 9 3 &pcfg_pull_none_12ma>,
-                                               <4 4 3 &pcfg_pull_none_12ma>,
-                                               <4 1 3 &pcfg_pull_none>,
-                                               <4 3 3 &pcfg_pull_none>;
+                               rockchip,pins = <3 RK_PD6 3 &pcfg_pull_none>,
+                                               <3 RK_PD7 3 &pcfg_pull_none>,
+                                               <3 RK_PD2 3 &pcfg_pull_none>,
+                                               <3 RK_PD3 3 &pcfg_pull_none>,
+                                               <3 RK_PD4 3 &pcfg_pull_none_12ma>,
+                                               <3 RK_PD5 3 &pcfg_pull_none_12ma>,
+                                               <3 RK_PD0 3 &pcfg_pull_none_12ma>,
+                                               <3 RK_PD1 3 &pcfg_pull_none_12ma>,
+                                               <4 RK_PA0 3 &pcfg_pull_none>,
+                                               <4 RK_PA5 3 &pcfg_pull_none>,
+                                               <4 RK_PA6 3 &pcfg_pull_none>,
+                                               <4 RK_PB1 3 &pcfg_pull_none_12ma>,
+                                               <4 RK_PA4 3 &pcfg_pull_none_12ma>,
+                                               <4 RK_PA1 3 &pcfg_pull_none>,
+                                               <4 RK_PA3 3 &pcfg_pull_none>;
                        };
 
                        rmii_pins: rmii-pins {
-                               rockchip,pins = <3 30 3 &pcfg_pull_none>,
-                                               <3 31 3 &pcfg_pull_none>,
-                                               <3 28 3 &pcfg_pull_none>,
-                                               <3 29 3 &pcfg_pull_none>,
-                                               <4 0 3 &pcfg_pull_none>,
-                                               <4 5 3 &pcfg_pull_none>,
-                                               <4 4 3 &pcfg_pull_none>,
-                                               <4 1 3 &pcfg_pull_none>,
-                                               <4 2 3 &pcfg_pull_none>,
-                                               <4 3 3 &pcfg_pull_none>;
+                               rockchip,pins = <3 RK_PD6 3 &pcfg_pull_none>,
+                                               <3 RK_PD7 3 &pcfg_pull_none>,
+                                               <3 RK_PD4 3 &pcfg_pull_none>,
+                                               <3 RK_PD5 3 &pcfg_pull_none>,
+                                               <4 RK_PA0 3 &pcfg_pull_none>,
+                                               <4 RK_PA5 3 &pcfg_pull_none>,
+                                               <4 RK_PA4 3 &pcfg_pull_none>,
+                                               <4 RK_PA1 3 &pcfg_pull_none>,
+                                               <4 RK_PA2 3 &pcfg_pull_none>,
+                                               <4 RK_PA3 3 &pcfg_pull_none>;
                        };
                };
 
                spdif {
                        spdif_tx: spdif-tx {
-                               rockchip,pins = <RK_GPIO6 11 RK_FUNC_1 &pcfg_pull_none>;
+                               rockchip,pins = <6 RK_PB3 1 &pcfg_pull_none>;
                        };
                };
        };

diff --git a/arch/arm/boot/dts/rv1108-elgin-r1.dts b/arch/arm/boot/dts/rv1108-elgin-r1.dts
index 1c4507b..b1db924 100644 (file)
--- a/arch/arm/boot/dts/rv1108-elgin-r1.dts
+++ b/arch/arm/boot/dts/rv1108-elgin-r1.dts
@@ -37,7 +37,6 @@
 &emmc {
        bus-width = <8>;
        cap-mmc-highspeed;
-       disable-wp;
        no-sd;
        no-sdio;
        non-removable;

diff --git a/arch/arm/boot/dts/rv1108.dtsi b/arch/arm/boot/dts/rv1108.dtsi
index f47ac86..5876690 100644 (file)
--- a/arch/arm/boot/dts/rv1108.dtsi
+++ b/arch/arm/boot/dts/rv1108.dtsi
@@ -682,58 +682,58 @@
 
                emmc {
                        emmc_bus8: emmc-bus8 {
-                               rockchip,pins = <2 RK_PA0 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,
-                                               <2 RK_PA1 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,
-                                               <2 RK_PA2 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,
-                                               <2 RK_PA3 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,
-                                               <2 RK_PA4 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,
-                                               <2 RK_PA5 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,
-                                               <2 RK_PA6 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,
-                                               <2 RK_PA7 RK_FUNC_2 &pcfg_pull_up_drv_8ma>;
+                               rockchip,pins = <2 RK_PA0 2 &pcfg_pull_up_drv_8ma>,
+                                               <2 RK_PA1 2 &pcfg_pull_up_drv_8ma>,
+                                               <2 RK_PA2 2 &pcfg_pull_up_drv_8ma>,
+                                               <2 RK_PA3 2 &pcfg_pull_up_drv_8ma>,
+                                               <2 RK_PA4 2 &pcfg_pull_up_drv_8ma>,
+                                               <2 RK_PA5 2 &pcfg_pull_up_drv_8ma>,
+                                               <2 RK_PA6 2 &pcfg_pull_up_drv_8ma>,
+                                               <2 RK_PA7 2 &pcfg_pull_up_drv_8ma>;
                        };
 
                        emmc_clk: emmc-clk {
-                               rockchip,pins = <2 RK_PB6 RK_FUNC_1 &pcfg_pull_none_drv_8ma>;
+                               rockchip,pins = <2 RK_PB6 1 &pcfg_pull_none_drv_8ma>;
                        };
 
                        emmc_cmd: emmc-cmd {
-                               rockchip,pins = <2 RK_PB4 RK_FUNC_2 &pcfg_pull_up_drv_8ma>;
+                               rockchip,pins = <2 RK_PB4 2 &pcfg_pull_up_drv_8ma>;
                        };
                };
 
                gmac {
                        rmii_pins: rmii-pins {
-                               rockchip,pins = <1 RK_PC5 RK_FUNC_2 &pcfg_pull_none>,
-                                               <1 RK_PC3 RK_FUNC_2 &pcfg_pull_none>,
-                                               <1 RK_PC4 RK_FUNC_2 &pcfg_pull_none>,
-                                               <1 RK_PB2 RK_FUNC_3 &pcfg_pull_none_drv_12ma>,
-                                               <1 RK_PB3 RK_FUNC_3 &pcfg_pull_none_drv_12ma>,
-                                               <1 RK_PB4 RK_FUNC_3 &pcfg_pull_none_drv_12ma>,
-                                               <1 RK_PB5 RK_FUNC_3 &pcfg_pull_none>,
-                                               <1 RK_PB6 RK_FUNC_3 &pcfg_pull_none>,
-                                               <1 RK_PB7 RK_FUNC_3 &pcfg_pull_none>,
-                                               <1 RK_PC2 RK_FUNC_3 &pcfg_pull_none>;
+                               rockchip,pins = <1 RK_PC5 2 &pcfg_pull_none>,
+                                               <1 RK_PC3 2 &pcfg_pull_none>,
+                                               <1 RK_PC4 2 &pcfg_pull_none>,
+                                               <1 RK_PB2 3 &pcfg_pull_none_drv_12ma>,
+                                               <1 RK_PB3 3 &pcfg_pull_none_drv_12ma>,
+                                               <1 RK_PB4 3 &pcfg_pull_none_drv_12ma>,
+                                               <1 RK_PB5 3 &pcfg_pull_none>,
+                                               <1 RK_PB6 3 &pcfg_pull_none>,
+                                               <1 RK_PB7 3 &pcfg_pull_none>,
+                                               <1 RK_PC2 3 &pcfg_pull_none>;
                        };
                };
 
                i2c0 {
                        i2c0_xfer: i2c0-xfer {
-                               rockchip,pins = <0 RK_PB1 RK_FUNC_1 &pcfg_pull_none_smt>,
-                                               <0 RK_PB2 RK_FUNC_1 &pcfg_pull_none_smt>;
+                               rockchip,pins = <0 RK_PB1 1 &pcfg_pull_none_smt>,
+                                               <0 RK_PB2 1 &pcfg_pull_none_smt>;
                        };
                };
 
                i2c1 {
                        i2c1_xfer: i2c1-xfer {
-                               rockchip,pins = <2 RK_PD3 RK_FUNC_1 &pcfg_pull_up>,
-                                               <2 RK_PD4 RK_FUNC_1 &pcfg_pull_up>;
+                               rockchip,pins = <2 RK_PD3 1 &pcfg_pull_up>,
+                                               <2 RK_PD4 1 &pcfg_pull_up>;
                        };
                };
 
                i2c2m1 {
                        i2c2m1_xfer: i2c2m1-xfer {
-                               rockchip,pins = <0 RK_PC2 RK_FUNC_2 &pcfg_pull_none>,
-                                               <0 RK_PC6 RK_FUNC_3 &pcfg_pull_none>;
+                               rockchip,pins = <0 RK_PC2 2 &pcfg_pull_none>,
+                                               <0 RK_PC6 3 &pcfg_pull_none>;
                        };
 
                        i2c2m1_gpio: i2c2m1-gpio {
@@ -744,8 +744,8 @@
 
                i2c2m05v {
                        i2c2m05v_xfer: i2c2m05v-xfer {
-                               rockchip,pins = <1 RK_PD5 RK_FUNC_2 &pcfg_pull_none>,
-                                               <1 RK_PD4 RK_FUNC_2 &pcfg_pull_none>;
+                               rockchip,pins = <1 RK_PD5 2 &pcfg_pull_none>,
+                                               <1 RK_PD4 2 &pcfg_pull_none>;
                        };
 
                        i2c2m05v_gpio: i2c2m05v-gpio {
@@ -756,123 +756,123 @@
 
                i2c3 {
                        i2c3_xfer: i2c3-xfer {
-                               rockchip,pins = <0 RK_PB6 RK_FUNC_1 &pcfg_pull_none>,
-                                               <0 RK_PC4 RK_FUNC_2 &pcfg_pull_none>;
+                               rockchip,pins = <0 RK_PB6 1 &pcfg_pull_none>,
+                                               <0 RK_PC4 2 &pcfg_pull_none>;
                        };
                };
 
                pwm0 {
                        pwm0_pin: pwm0-pin {
-                               rockchip,pins = <0 RK_PC5 RK_FUNC_1 &pcfg_pull_none>;
+                               rockchip,pins = <0 RK_PC5 1 &pcfg_pull_none>;
                        };
                };
 
                pwm1 {
                        pwm1_pin: pwm1-pin {
-                               rockchip,pins = <0 RK_PC4 RK_FUNC_1 &pcfg_pull_none>;
+                               rockchip,pins = <0 RK_PC4 1 &pcfg_pull_none>;
                        };
                };
 
                pwm2 {
                        pwm2_pin: pwm2-pin {
-                               rockchip,pins = <0 RK_PC6 RK_FUNC_1 &pcfg_pull_none>;
+                               rockchip,pins = <0 RK_PC6 1 &pcfg_pull_none>;
                        };
                };
 
                pwm3 {
                        pwm3_pin: pwm3-pin {
-                               rockchip,pins = <0 RK_PC0 RK_FUNC_1 &pcfg_pull_none>;
+                               rockchip,pins = <0 RK_PC0 1 &pcfg_pull_none>;
                        };
                };
 
                pwm4 {
                        pwm4_pin: pwm4-pin {
-                               rockchip,pins = <1 RK_PC1 RK_FUNC_3 &pcfg_pull_none>;
+                               rockchip,pins = <1 RK_PC1 3 &pcfg_pull_none>;
                        };
                };
 
                pwm5 {
                        pwm5_pin: pwm5-pin {
-                               rockchip,pins = <1 RK_PA7 RK_FUNC_2 &pcfg_pull_none>;
+                               rockchip,pins = <1 RK_PA7 2 &pcfg_pull_none>;
                        };
                };
 
                pwm6 {
                        pwm6_pin: pwm6-pin {
-                               rockchip,pins = <1 RK_PB0 RK_FUNC_2 &pcfg_pull_none>;
+                               rockchip,pins = <1 RK_PB0 2 &pcfg_pull_none>;
                        };
                };
 
                pwm7 {
                        pwm7_pin: pwm7-pin {
-                               rockchip,pins = <1 RK_PB1 RK_FUNC_2 &pcfg_pull_none>;
+                               rockchip,pins = <1 RK_PB1 2 &pcfg_pull_none>;
                        };
                };
 
                sdmmc {
                        sdmmc_clk: sdmmc-clk {
-                               rockchip,pins = <3 RK_PC4 RK_FUNC_1 &pcfg_pull_none_drv_4ma>;
+                               rockchip,pins = <3 RK_PC4 1 &pcfg_pull_none_drv_4ma>;
                        };
 
                        sdmmc_cmd: sdmmc-cmd {
-                               rockchip,pins = <3 RK_PC5 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
+                               rockchip,pins = <3 RK_PC5 1 &pcfg_pull_up_drv_4ma>;
                        };
 
                        sdmmc_cd: sdmmc-cd {
-                               rockchip,pins = <0 RK_PA1 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
+                               rockchip,pins = <0 RK_PA1 1 &pcfg_pull_up_drv_4ma>;
                        };
 
                        sdmmc_bus1: sdmmc-bus1 {
-                               rockchip,pins = <3 RK_PC3 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
+                               rockchip,pins = <3 RK_PC3 1 &pcfg_pull_up_drv_4ma>;
                        };
 
                        sdmmc_bus4: sdmmc-bus4 {
-                               rockchip,pins = <3 RK_PC3 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
-                                               <3 RK_PC2 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
-                                               <3 RK_PC1 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
-                                               <3 RK_PC0 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
+                               rockchip,pins = <3 RK_PC3 1 &pcfg_pull_up_drv_4ma>,
+                                               <3 RK_PC2 1 &pcfg_pull_up_drv_4ma>,
+                                               <3 RK_PC1 1 &pcfg_pull_up_drv_4ma>,
+                                               <3 RK_PC0 1 &pcfg_pull_up_drv_4ma>;
                        };
                };
 
                spim0 {
                        spim0_clk: spim0-clk {
-                               rockchip,pins = <1 RK_PD0 RK_FUNC_2 &pcfg_pull_up>;
+                               rockchip,pins = <1 RK_PD0 2 &pcfg_pull_up>;
                        };
 
                        spim0_cs0: spim0-cs0 {
-                               rockchip,pins = <1 RK_PD1 RK_FUNC_2 &pcfg_pull_up>;
+                               rockchip,pins = <1 RK_PD1 2 &pcfg_pull_up>;
                        };
 
                        spim0_tx: spim0-tx {
-                               rockchip,pins = <1 RK_PD3 RK_FUNC_2 &pcfg_pull_up>;
+                               rockchip,pins = <1 RK_PD3 2 &pcfg_pull_up>;
                        };
 
                        spim0_rx: spim0-rx {
-                               rockchip,pins = <1 RK_PD2 RK_FUNC_2 &pcfg_pull_up>;
+                               rockchip,pins = <1 RK_PD2 2 &pcfg_pull_up>;
                        };
                };
 
                spim1 {
                        spim1_clk: spim1-clk {
-                               rockchip,pins = <0 RK_PA3 RK_FUNC_1 &pcfg_pull_up>;
+                               rockchip,pins = <0 RK_PA3 1 &pcfg_pull_up>;
                        };
 
                        spim1_cs0: spim1-cs0 {
-                               rockchip,pins = <0 RK_PA4 RK_FUNC_1 &pcfg_pull_up>;
+                               rockchip,pins = <0 RK_PA4 1 &pcfg_pull_up>;
                        };
 
                        spim1_rx: spim1-rx {
-                               rockchip,pins = <0 RK_PB0 RK_FUNC_1 &pcfg_pull_up>;
+                               rockchip,pins = <0 RK_PB0 1 &pcfg_pull_up>;
                        };
 
                        spim1_tx: spim1-tx {
-                               rockchip,pins = <0 RK_PA7 RK_FUNC_1 &pcfg_pull_up>;
+                               rockchip,pins = <0 RK_PA7 1 &pcfg_pull_up>;
                        };
                };
 
                tsadc {
                        otp_out: otp-out {
-                               rockchip,pins = <0 RK_PB7 RK_FUNC_1 &pcfg_pull_none>;
+                               rockchip,pins = <0 RK_PB7 1 &pcfg_pull_none>;
                        };
 
                        otp_gpio: otp-gpio {
@@ -882,16 +882,16 @@
 
                uart0 {
                        uart0_xfer: uart0-xfer {
-                               rockchip,pins = <3 RK_PA6 RK_FUNC_1 &pcfg_pull_up>,
-                                               <3 RK_PA5 RK_FUNC_1 &pcfg_pull_none>;
+                               rockchip,pins = <3 RK_PA6 1 &pcfg_pull_up>,
+                                               <3 RK_PA5 1 &pcfg_pull_none>;
                        };
 
                        uart0_cts: uart0-cts {
-                               rockchip,pins = <3 RK_PA4 RK_FUNC_1 &pcfg_pull_none>;
+                               rockchip,pins = <3 RK_PA4 1 &pcfg_pull_none>;
                        };
 
                        uart0_rts: uart0-rts {
-                               rockchip,pins = <3 RK_PA3 RK_FUNC_1 &pcfg_pull_none>;
+                               rockchip,pins = <3 RK_PA3 1 &pcfg_pull_none>;
                        };
 
                        uart0_rts_gpio: uart0-rts-gpio {
@@ -901,40 +901,40 @@
 
                uart1 {
                        uart1_xfer: uart1-xfer {
-                               rockchip,pins = <1 RK_PD3 RK_FUNC_1 &pcfg_pull_up>,
-                                               <1 RK_PD2 RK_FUNC_1 &pcfg_pull_none>;
+                               rockchip,pins = <1 RK_PD3 1 &pcfg_pull_up>,
+                                               <1 RK_PD2 1 &pcfg_pull_none>;
                        };
 
                        uart1_cts: uart1-cts {
-                               rockchip,pins = <1 RK_PD0 RK_FUNC_1 &pcfg_pull_none>;
+                               rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>;
                        };
 
                        uart1_rts: uart1-rts {
-                               rockchip,pins = <1 RK_PD1 RK_FUNC_1 &pcfg_pull_none>;
+                               rockchip,pins = <1 RK_PD1 1 &pcfg_pull_none>;
                        };
                };
 
                uart2m0 {
                        uart2m0_xfer: uart2m0-xfer {
-                               rockchip,pins = <2 RK_PD2 RK_FUNC_1 &pcfg_pull_up>,
-                                               <2 RK_PD1 RK_FUNC_1 &pcfg_pull_none>;
+                               rockchip,pins = <2 RK_PD2 1 &pcfg_pull_up>,
+                                               <2 RK_PD1 1 &pcfg_pull_none>;
                        };
                };
 
                uart2m1 {
                        uart2m1_xfer: uart2m1-xfer {
-                               rockchip,pins = <3 RK_PC3 RK_FUNC_2 &pcfg_pull_up>,
-                                               <3 RK_PC2 RK_FUNC_2 &pcfg_pull_none>;
+                               rockchip,pins = <3 RK_PC3 2 &pcfg_pull_up>,
+                                               <3 RK_PC2 2 &pcfg_pull_none>;
                        };
                };
 
                uart2_5v {
                        uart2_5v_cts: uart2_5v-cts {
-                               rockchip,pins = <1 RK_PD4 RK_FUNC_1 &pcfg_pull_none>;
+                               rockchip,pins = <1 RK_PD4 1 &pcfg_pull_none>;
                        };
 
                        uart2_5v_rts: uart2_5v-rts {
-                               rockchip,pins = <1 RK_PD5 RK_FUNC_1 &pcfg_pull_none>;
+                               rockchip,pins = <1 RK_PD5 1 &pcfg_pull_none>;
                        };
                };
        };

diff --git a/arch/arm/boot/dts/s5pv210-goni.dts b/arch/arm/boot/dts/s5pv210-goni.dts
index eb6d192..fbbd937 100644 (file)
--- a/arch/arm/boot/dts/s5pv210-goni.dts
+++ b/arch/arm/boot/dts/s5pv210-goni.dts
@@ -376,7 +376,7 @@
                vdd_core-supply = <&ldo14_reg>;
 
                clock-frequency = <16000000>;
-               clocks = <&clock_cam 0>;
+               clocks = <&camera 0>;
                clock-names = "mclk";
                nreset-gpios = <&gpb 2 0>;
                nstby-gpios = <&gpb 0 0>;

diff --git a/arch/arm/boot/dts/s5pv210.dtsi b/arch/arm/boot/dts/s5pv210.dtsi
index a44d5eb..2ad642f 100644 (file)
--- a/arch/arm/boot/dts/s5pv210.dtsi
+++ b/arch/arm/boot/dts/s5pv210.dtsi
@@ -585,12 +585,10 @@
                        clock-names = "sclk_cam0", "sclk_cam1";
                        #address-cells = <1>;
                        #size-cells = <1>;
+                       #clock-cells = <1>;
+                       clock-output-names = "cam_a_clkout", "cam_b_clkout";
                        ranges;
 
-                       clock_cam: clock-controller {
-                               #clock-cells = <1>;
-                       };
-
                        csis0: csis@fa600000 {
                                compatible = "samsung,s5pv210-csis";
                                reg = <0xfa600000 0x4000>;

diff --git a/arch/arm/boot/dts/sama5d2.dtsi b/arch/arm/boot/dts/sama5d2.dtsi
index d159ee4..2e2c1a7 100644 (file)
--- a/arch/arm/boot/dts/sama5d2.dtsi
+++ b/arch/arm/boot/dts/sama5d2.dtsi
@@ -1,46 +1,9 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
 /*
  * sama5d2.dtsi - Device Tree Include file for SAMA5D2 family SoC
  *
  *  Copyright (C) 2015 Atmel,
  *                2015 Ludovic Desroches <ludovic.desroches@atmel.com>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- *  a) This file is free software; you can redistribute it and/or
- *     modify it under the terms of the GNU General Public License as
- *     published by the Free Software Foundation; either version 2 of the
- *     License, or (at your option) any later version.
- *
- *     This file is distributed in the hope that it will be useful,
- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *     GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- *  b) Permission is hereby granted, free of charge, to any person
- *     obtaining a copy of this software and associated documentation
- *     files (the "Software"), to deal in the Software without
- *     restriction, including without limitation the rights to use,
- *     copy, modify, merge, publish, distribute, sublicense, and/or
- *     sell copies of the Software, and to permit persons to whom the
- *     Software is furnished to do so, subject to the following
- *     conditions:
- *
- *     The above copyright notice and this permission notice shall be
- *     included in all copies or substantial portions of the Software.
- *
- *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- *     OTHER DEALINGS IN THE SOFTWARE.
  */
 
 #include <dt-bindings/dma/at91.h>
@@ -688,13 +651,13 @@
                                ranges = <0 0xf8044000 0x1420>;
                        };
 
-                       rstc@f8048000 {
+                       reset_controller: rstc@f8048000 {
                                compatible = "atmel,sama5d3-rstc";
                                reg = <0xf8048000 0x10>;
                                clocks = <&clk32k>;
                        };
 
-                       shdwc@f8048010 {
+                       shutdown_controller: shdwc@f8048010 {
                                compatible = "atmel,sama5d2-shdwc";
                                reg = <0xf8048010 0x10>;
                                clocks = <&clk32k>;
@@ -710,7 +673,7 @@
                                clocks = <&pmc PMC_TYPE_CORE PMC_MCK2>;
                        };
 
-                       watchdog@f8048040 {
+                       watchdog: watchdog@f8048040 {
                                compatible = "atmel,sama5d4-wdt";
                                reg = <0xf8048040 0x10>;
                                interrupts = <4 IRQ_TYPE_LEVEL_HIGH 7>;

diff --git a/arch/arm/boot/dts/sama5d36ek_cmp.dts b/arch/arm/boot/dts/sama5d36ek_cmp.dts
index b632143..66695b9 100644 (file)
--- a/arch/arm/boot/dts/sama5d36ek_cmp.dts
+++ b/arch/arm/boot/dts/sama5d36ek_cmp.dts
@@ -1,45 +1,8 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
 /*
  * sama5d36ek_cmp.dts - Device Tree file for SAMA5D36-EK CMP board
  *
  *  Copyright (C) 2016 Atmel,
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- *  a) This file is free software; you can redistribute it and/or
- *     modify it under the terms of the GNU General Public License as
- *     published by the Free Software Foundation; either version 2 of the
- *     License, or (at your option) any later version.
- *
- *     This file is distributed in the hope that it will be useful,
- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *     GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- *  b) Permission is hereby granted, free of charge, to any person
- *     obtaining a copy of this software and associated documentation
- *     files (the "Software"), to deal in the Software without
- *     restriction, including without limitation the rights to use,
- *     copy, modify, merge, publish, distribute, sublicense, and/or
- *     sell copies of the Software, and to permit persons to whom the
- *     Software is furnished to do so, subject to the following
- *     conditions:
- *
- *     The above copyright notice and this permission notice shall be
- *     included in all copies or substantial portions of the Software.
- *
- *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- *     OTHER DEALINGS IN THE SOFTWARE.
  */
 /dts-v1/;
 #include "sama5d36.dtsi"

diff --git a/arch/arm/boot/dts/sama5d3xcm_cmp.dtsi b/arch/arm/boot/dts/sama5d3xcm_cmp.dtsi
index a02f590..9d25636 100644 (file)
--- a/arch/arm/boot/dts/sama5d3xcm_cmp.dtsi
+++ b/arch/arm/boot/dts/sama5d3xcm_cmp.dtsi
@@ -1,45 +1,8 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
 /*
  * sama5d3xcm_cmp.dtsi - Device Tree Include file for SAMA5D36 CMP CPU Module
  *
  *  Copyright (C) 2016 Atmel,
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- *  a) This file is free software; you can redistribute it and/or
- *     modify it under the terms of the GNU General Public License as
- *     published by the Free Software Foundation; either version 2 of the
- *     License, or (at your option) any later version.
- *
- *     This file is distributed in the hope that it will be useful,
- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *     GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- *  b) Permission is hereby granted, free of charge, to any person
- *     obtaining a copy of this software and associated documentation
- *     files (the "Software"), to deal in the Software without
- *     restriction, including without limitation the rights to use,
- *     copy, modify, merge, publish, distribute, sublicense, and/or
- *     sell copies of the Software, and to permit persons to whom the
- *     Software is furnished to do so, subject to the following
- *     conditions:
- *
- *     The above copyright notice and this permission notice shall be
- *     included in all copies or substantial portions of the Software.
- *
- *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- *     OTHER DEALINGS IN THE SOFTWARE.
  */
 
 / {

diff --git a/arch/arm/boot/dts/sama5d3xmb_cmp.dtsi b/arch/arm/boot/dts/sama5d3xmb_cmp.dtsi
index 97e171d..8a6916a 100644 (file)
--- a/arch/arm/boot/dts/sama5d3xmb_cmp.dtsi
+++ b/arch/arm/boot/dts/sama5d3xmb_cmp.dtsi
@@ -1,45 +1,8 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
 /*
  * sama5d3xmb_cmp.dts - Device Tree file for SAMA5D3x CMP mother board
  *
  *  Copyright (C) 2016 Atmel,
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- *  a) This file is free software; you can redistribute it and/or
- *     modify it under the terms of the GNU General Public License as
- *     published by the Free Software Foundation; either version 2 of the
- *     License, or (at your option) any later version.
- *
- *     This file is distributed in the hope that it will be useful,
- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *     GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- *  b) Permission is hereby granted, free of charge, to any person
- *     obtaining a copy of this software and associated documentation
- *     files (the "Software"), to deal in the Software without
- *     restriction, including without limitation the rights to use,
- *     copy, modify, merge, publish, distribute, sublicense, and/or
- *     sell copies of the Software, and to permit persons to whom the
- *     Software is furnished to do so, subject to the following
- *     conditions:
- *
- *     The above copyright notice and this permission notice shall be
- *     included in all copies or substantial portions of the Software.
- *
- *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- *     OTHER DEALINGS IN THE SOFTWARE.
  */
 #include "sama5d3xcm_cmp.dtsi"
 

diff --git a/arch/arm/boot/dts/sama5d4.dtsi b/arch/arm/boot/dts/sama5d4.dtsi
index 6c1e41f..6ab27a7 100644 (file)
--- a/arch/arm/boot/dts/sama5d4.dtsi
+++ b/arch/arm/boot/dts/sama5d4.dtsi
@@ -1,46 +1,9 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
 /*
  * sama5d4.dtsi - Device Tree Include file for SAMA5D4 family SoC
  *
  *  Copyright (C) 2014 Atmel,
  *                2014 Nicolas Ferre <nicolas.ferre@atmel.com>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- *  a) This file is free software; you can redistribute it and/or
- *     modify it under the terms of the GNU General Public License as
- *     published by the Free Software Foundation; either version 2 of the
- *     License, or (at your option) any later version.
- *
- *     This file is distributed in the hope that it will be useful,
- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *     GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- *  b) Permission is hereby granted, free of charge, to any person
- *     obtaining a copy of this software and associated documentation
- *     files (the "Software"), to deal in the Software without
- *     restriction, including without limitation the rights to use,
- *     copy, modify, merge, publish, distribute, sublicense, and/or
- *     sell copies of the Software, and to permit persons to whom the
- *     Software is furnished to do so, subject to the following
- *     conditions:
- *
- *     The above copyright notice and this permission notice shall be
- *     included in all copies or substantial portions of the Software.
- *
- *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- *     OTHER DEALINGS IN THE SOFTWARE.
  */
 
 #include <dt-bindings/clock/at91.h>

diff --git a/arch/arm/boot/dts/socfpga_arria10_socdk_sdmmc.dts b/arch/arm/boot/dts/socfpga_arria10_socdk_sdmmc.dts
index df2bab1..64dc079 100644 (file)
--- a/arch/arm/boot/dts/socfpga_arria10_socdk_sdmmc.dts
+++ b/arch/arm/boot/dts/socfpga_arria10_socdk_sdmmc.dts
@@ -9,6 +9,7 @@
 &mmc {
        status = "okay";
        cap-sd-highspeed;
+       cap-mmc-highspeed;
        broken-cd;
        bus-width = <4>;
 };

diff --git a/arch/arm/boot/dts/ste-dbx5x0.dtsi b/arch/arm/boot/dts/ste-dbx5x0.dtsi
index e6ed7c0..81fabf0 100644 (file)
--- a/arch/arm/boot/dts/ste-dbx5x0.dtsi
+++ b/arch/arm/boot/dts/ste-dbx5x0.dtsi
@@ -1196,21 +1196,73 @@
                        status = "disabled";
                };
 
+               gpu@a0300000 {
+                       /*
+                        * This block is referred to as "Smart Graphics Adapter SGA500"
+                        * in documentation but is in practice a pretty straight-forward
+                        * MALI-400 GPU block.
+                        */
+                       compatible = "stericsson,db8500-mali", "arm,mali-400";
+                       reg = <0xa0300000 0x10000>;
+                       interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-names = "gp",
+                                         "gpmmu",
+                                         "pp0",
+                                         "ppmmu0",
+                                         "combined";
+                       clocks = <&prcmu_clk PRCMU_ACLK>, <&prcmu_clk PRCMU_SGACLK>;
+                       clock-names = "bus", "core";
+                       mali-supply = <&db8500_sga_reg>;
+                       power-domains = <&pm_domains DOMAIN_VAPE>;
+               };
+
                mcde@a0350000 {
-                       compatible = "stericsson,mcde";
-                       reg = <0xa0350000 0x1000>, /* MCDE */
-                             <0xa0351000 0x1000>, /* DSI link 1 */
-                             <0xa0352000 0x1000>, /* DSI link 2 */
-                             <0xa0353000 0x1000>; /* DSI link 3 */
+                       compatible = "ste,mcde";
+                       reg = <0xa0350000 0x1000>;
                        interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
+                       epod-supply = <&db8500_b2r2_mcde_reg>;
+                       vana-supply = <&ab8500_ldo_ana_reg>;
                        clocks = <&prcmu_clk PRCMU_MCDECLK>, /* Main MCDE clock */
                                 <&prcmu_clk PRCMU_LCDCLK>, /* LCD clock */
-                                <&prcmu_clk PRCMU_PLLDSI>, /* HDMI clock */
-                                <&prcmu_clk PRCMU_DSI0CLK>, /* DSI 0 */
-                                <&prcmu_clk PRCMU_DSI1CLK>, /* DSI 1 */
-                                <&prcmu_clk PRCMU_DSI0ESCCLK>, /* TVout clock 0 */
-                                <&prcmu_clk PRCMU_DSI1ESCCLK>, /* TVout clock 1 */
-                                <&prcmu_clk PRCMU_DSI2ESCCLK>; /* TVout clock 2 */
+                                <&prcmu_clk PRCMU_PLLDSI>; /* HDMI clock */
+                       clock-names = "mcde", "lcd", "hdmi";
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       ranges;
+                       status = "disabled";
+
+                       dsi0: dsi@a0351000 {
+                               compatible = "ste,mcde-dsi";
+                               reg = <0xa0351000 0x1000>;
+                               vana-supply = <&ab8500_ldo_ana_reg>;
+                               clocks = <&prcmu_clk PRCMU_DSI0CLK>, <&prcmu_clk PRCMU_DSI0ESCCLK>;
+                               clock-names = "hs", "lp";
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                       };
+                       dsi1: dsi@a0352000 {
+                               compatible = "ste,mcde-dsi";
+                               reg = <0xa0352000 0x1000>;
+                               vana-supply = <&ab8500_ldo_ana_reg>;
+                               clocks = <&prcmu_clk PRCMU_DSI1CLK>, <&prcmu_clk PRCMU_DSI1ESCCLK>;
+                               clock-names = "hs", "lp";
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                       };
+                       dsi2: dsi@a0353000 {
+                               compatible = "ste,mcde-dsi";
+                               reg = <0xa0353000 0x1000>;
+                               vana-supply = <&ab8500_ldo_ana_reg>;
+                               /* This DSI port only has the Low Power / Energy Save clock */
+                               clocks = <&prcmu_clk PRCMU_DSI2ESCCLK>;
+                               clock-names = "lp";
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                       };
                };
 
                cryp@a03cb000 {

diff --git a/arch/arm/boot/dts/ste-href-stuib.dtsi b/arch/arm/boot/dts/ste-href-stuib.dtsi
index 35e944d..eeaea21 100644 (file)
--- a/arch/arm/boot/dts/ste-href-stuib.dtsi
+++ b/arch/arm/boot/dts/ste-href-stuib.dtsi
@@ -190,5 +190,18 @@
                                };
                        };
                };
+
+               mcde@a0350000 {
+                       status = "okay";
+
+                       dsi@a0351000 {
+                               panel {
+                                       compatible = "samsung,s6d16d0";
+                                       reg = <0>;
+                                       vdd1-supply = <&ab8500_ldo_aux1_reg>;
+                                       reset-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
+                               };
+                       };
+               };
        };
 };

diff --git a/arch/arm/boot/dts/ste-href-tvk1281618.dtsi b/arch/arm/boot/dts/ste-href-tvk1281618.dtsi
index 0e7d77d..7686844 100644 (file)
--- a/arch/arm/boot/dts/ste-href-tvk1281618.dtsi
+++ b/arch/arm/boot/dts/ste-href-tvk1281618.dtsi
@@ -274,5 +274,18 @@
                                };
                        };
                };
+
+               mcde@a0350000 {
+                       status = "okay";
+
+                       dsi@a0351000 {
+                               panel {
+                                       compatible = "samsung,s6d16d0";
+                                       reg = <0>;
+                                       vdd1-supply = <&ab8500_ldo_aux1_reg>;
+                                       reset-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
+                               };
+                       };
+               };
        };
 };

diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi
index 588b6ef..4a49544 100644 (file)
--- a/arch/arm/boot/dts/stm32f429.dtsi
+++ b/arch/arm/boot/dts/stm32f429.dtsi
@@ -80,6 +80,19 @@
        };
 
        soc {
+               romem: nvmem@1fff7800 {
+                       compatible = "st,stm32f4-otp";
+                       reg = <0x1fff7800 0x400>;
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       ts_cal1: calib@22c {
+                               reg = <0x22c 0x2>;
+                       };
+                       ts_cal2: calib@22e {
+                               reg = <0x22e 0x2>;
+                       };
+               };
+
                timer2: timer@40000000 {
                        compatible = "st,stm32-timer";
                        reg = <0x40000000 0x400>;

diff --git a/arch/arm/boot/dts/stm32f769-disco.dts b/arch/arm/boot/dts/stm32f769-disco.dts
index 3c72168..6f1d0ac 100644 (file)
--- a/arch/arm/boot/dts/stm32f769-disco.dts
+++ b/arch/arm/boot/dts/stm32f769-disco.dts
@@ -102,6 +102,10 @@
        };
 };
 
+&rcc {
+       compatible = "st,stm32f769-rcc", "st,stm32f746-rcc", "st,stm32-rcc";
+};
+
 &cec {
        pinctrl-0 = <&cec_pins_a>;
        pinctrl-names = "default";

diff --git a/arch/arm/boot/dts/stm32h743-pinctrl.dtsi b/arch/arm/boot/dts/stm32h743-pinctrl.dtsi
index 980b276..e44e7ba 100644 (file)
--- a/arch/arm/boot/dts/stm32h743-pinctrl.dtsi
+++ b/arch/arm/boot/dts/stm32h743-pinctrl.dtsi
@@ -188,6 +188,74 @@
                                };
                        };
 
+                       sdmmc1_b4_pins_a: sdmmc1-b4-0 {
+                               pins {
+                                       pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
+                                                <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
+                                                <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
+                                                <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */
+                                                <STM32_PINMUX('C', 12, AF12)>, /* SDMMC1_CK */
+                                                <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
+                                       slew-rate = <3>;
+                                       drive-push-pull;
+                                       bias-disable;
+                               };
+                       };
+
+                       sdmmc1_b4_od_pins_a: sdmmc1-b4-od-0 {
+                               pins1 {
+                                       pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
+                                                <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
+                                                <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
+                                                <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */
+                                                <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */
+                                       slew-rate = <3>;
+                                       drive-push-pull;
+                                       bias-disable;
+                               };
+                               pins2{
+                                       pinmux = <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
+                                       slew-rate = <3>;
+                                       drive-open-drain;
+                                       bias-disable;
+                               };
+                       };
+
+                       sdmmc1_b4_sleep_pins_a: sdmmc1-b4-sleep-0 {
+                               pins {
+                                       pinmux = <STM32_PINMUX('C', 8, ANALOG)>, /* SDMMC1_D0 */
+                                                <STM32_PINMUX('C', 9, ANALOG)>, /* SDMMC1_D1 */
+                                                <STM32_PINMUX('C', 10, ANALOG)>, /* SDMMC1_D2 */
+                                                <STM32_PINMUX('C', 11, ANALOG)>, /* SDMMC1_D3 */
+                                                <STM32_PINMUX('C', 12, ANALOG)>, /* SDMMC1_CK */
+                                                <STM32_PINMUX('D', 2, ANALOG)>; /* SDMMC1_CMD */
+                               };
+                       };
+
+                       sdmmc1_dir_pins_a: sdmmc1-dir-0 {
+                               pins1 {
+                                       pinmux = <STM32_PINMUX('C', 6, AF8)>, /* SDMMC1_D0DIR */
+                                                <STM32_PINMUX('C', 7, AF8)>, /* SDMMC1_D123DIR */
+                                                <STM32_PINMUX('B', 9, AF7)>; /* SDMMC1_CDIR */
+                                       slew-rate = <3>;
+                                       drive-push-pull;
+                                       bias-pull-up;
+                               };
+                               pins2{
+                                       pinmux = <STM32_PINMUX('B', 8, AF7)>; /* SDMMC1_CKIN */
+                                       bias-pull-up;
+                               };
+                       };
+
+                       sdmmc1_dir_sleep_pins_a: sdmmc1-dir-sleep-0 {
+                               pins {
+                                       pinmux = <STM32_PINMUX('C', 6, ANALOG)>, /* SDMMC1_D0DIR */
+                                                <STM32_PINMUX('C', 7, ANALOG)>, /* SDMMC1_D123DIR */
+                                                <STM32_PINMUX('B', 9, ANALOG)>, /* SDMMC1_CDIR */
+                                                <STM32_PINMUX('B', 8, ANALOG)>; /* SDMMC1_CKIN */
+                               };
+                       };
+
                        usart1_pins: usart1@0 {
                                pins1 {
                                        pinmux = <STM32_PINMUX('B', 14, AF4)>; /* USART1_TX */

diff --git a/arch/arm/boot/dts/stm32h743.dtsi b/arch/arm/boot/dts/stm32h743.dtsi
index 5cac79e..c065266 100644 (file)
--- a/arch/arm/boot/dts/stm32h743.dtsi
+++ b/arch/arm/boot/dts/stm32h743.dtsi
@@ -339,6 +339,20 @@
                        dma-requests = <32>;
                };
 
+               sdmmc1: sdmmc@52007000 {
+                       compatible = "arm,pl18x", "arm,primecell";
+                       arm,primecell-periphid = <0x10153180>;
+                       reg = <0x52007000 0x1000>;
+                       interrupts = <49>;
+                       interrupt-names = "cmd_irq";
+                       clocks = <&rcc SDMMC1_CK>;
+                       clock-names = "apb_pclk";
+                       resets = <&rcc STM32H7_AHB3_RESET(SDMMC1)>;
+                       cap-sd-highspeed;
+                       cap-mmc-highspeed;
+                       max-frequency = <120000000>;
+               };
+
                exti: interrupt-controller@58000000 {
                        compatible = "st,stm32h7-exti";
                        interrupt-controller;

diff --git a/arch/arm/boot/dts/stm32h743i-disco.dts b/arch/arm/boot/dts/stm32h743i-disco.dts
index dd06c8f..3acd2e9 100644 (file)
--- a/arch/arm/boot/dts/stm32h743i-disco.dts
+++ b/arch/arm/boot/dts/stm32h743i-disco.dts
@@ -61,6 +61,14 @@
        aliases {
                serial0 = &usart2;
        };
+
+       v3v3: regulator-v3v3 {
+               compatible = "regulator-fixed";
+               regulator-name = "v3v3";
+               regulator-min-microvolt = <3300000>;
+               regulator-max-microvolt = <3300000>;
+               regulator-always-on;
+       };
 };
 
 &clk_hse {
@@ -84,6 +92,18 @@
        };
 };
 
+&sdmmc1 {
+       pinctrl-names = "default", "opendrain", "sleep";
+       pinctrl-0 = <&sdmmc1_b4_pins_a>;
+       pinctrl-1 = <&sdmmc1_b4_od_pins_a>;
+       pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>;
+       broken-cd;
+       st,neg-edge;
+       bus-width = <4>;
+       vmmc-supply = <&v3v3>;
+       status = "okay";
+};
+
 &usart2 {
        pinctrl-0 = <&usart2_pins>;
        pinctrl-names = "default";

diff --git a/arch/arm/boot/dts/stm32h743i-eval.dts b/arch/arm/boot/dts/stm32h743i-eval.dts
index ebc3f09..ab78ad5 100644 (file)
--- a/arch/arm/boot/dts/stm32h743i-eval.dts
+++ b/arch/arm/boot/dts/stm32h743i-eval.dts
@@ -70,13 +70,20 @@
                regulator-always-on;
        };
 
+       v2v9_sd: regulator-v2v9_sd {
+               compatible = "regulator-fixed";
+               regulator-name = "v2v9_sd";
+               regulator-min-microvolt = <2900000>;
+               regulator-max-microvolt = <2900000>;
+               regulator-always-on;
+       };
+
        usbotg_hs_phy: usb-phy {
                #phy-cells = <0>;
                compatible = "usb-nop-xceiv";
                clocks = <&rcc USB1ULPI_CK>;
                clock-names = "main_clk";
        };
-
 };
 
 &adc_12 {
@@ -122,6 +129,20 @@
        };
 };
 
+&sdmmc1 {
+       pinctrl-names = "default", "opendrain", "sleep";
+       pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_a>;
+       pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_dir_pins_a>;
+       pinctrl-2 = <&sdmmc1_b4_sleep_pins_a &sdmmc1_dir_sleep_pins_a>;
+       broken-cd;
+       st,sig-dir;
+       st,neg-edge;
+       st,use-ckin;
+       bus-width = <4>;
+       vmmc-supply = <&v2v9_sd>;
+       status = "okay";
+};
+
 &usart1 {
        pinctrl-0 = <&usart1_pins>;
        pinctrl-names = "default";

diff --git a/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi
index 9ec4694..85c417d 100644 (file)
--- a/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi
+++ b/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi
@@ -157,6 +157,27 @@
                                };
                        };
 
+                       cec_pins_sleep_a: cec-sleep-0 {
+                               pins {
+                                       pinmux = <STM32_PINMUX('A', 15, ANALOG)>; /* HDMI_CEC */
+                               };
+                       };
+
+                       cec_pins_b: cec-1 {
+                               pins {
+                                       pinmux = <STM32_PINMUX('B', 6, AF5)>;
+                                       bias-disable;
+                                       drive-open-drain;
+                                       slew-rate = <0>;
+                               };
+                       };
+
+                       cec_pins_sleep_b: cec-sleep-1 {
+                               pins {
+                                       pinmux = <STM32_PINMUX('B', 6, ANALOG)>; /* HDMI_CEC */
+                               };
+                       };
+
                        ethernet0_rgmii_pins_a: rgmii-0 {
                                pins1 {
                                        pinmux = <STM32_PINMUX('G', 5, AF11)>, /* ETH_RGMII_CLK125 */
@@ -213,6 +234,13 @@
                                };
                        };
 
+                       i2c1_pins_sleep_a: i2c1-1 {
+                               pins {
+                                       pinmux = <STM32_PINMUX('D', 12, ANALOG)>, /* I2C1_SCL */
+                                                <STM32_PINMUX('F', 15, ANALOG)>; /* I2C1_SDA */
+                               };
+                       };
+
                        i2c2_pins_a: i2c2-0 {
                                pins {
                                        pinmux = <STM32_PINMUX('H', 4, AF4)>, /* I2C2_SCL */
@@ -223,6 +251,13 @@
                                };
                        };
 
+                       i2c2_pins_sleep_a: i2c2-1 {
+                               pins {
+                                       pinmux = <STM32_PINMUX('H', 4, ANALOG)>, /* I2C2_SCL */
+                                                <STM32_PINMUX('H', 5, ANALOG)>; /* I2C2_SDA */
+                               };
+                       };
+
                        i2c5_pins_a: i2c5-0 {
                                pins {
                                        pinmux = <STM32_PINMUX('A', 11, AF4)>, /* I2C5_SCL */
@@ -233,6 +268,152 @@
                                };
                        };
 
+                       i2c5_pins_sleep_a: i2c5-1 {
+                               pins {
+                                       pinmux = <STM32_PINMUX('A', 11, ANALOG)>, /* I2C5_SCL */
+                                                <STM32_PINMUX('A', 12, ANALOG)>; /* I2C5_SDA */
+
+                               };
+                       };
+
+                       ltdc_pins_a: ltdc-a-0 {
+                               pins {
+                                       pinmux = <STM32_PINMUX('G',  7, AF14)>, /* LCD_CLK */
+                                                <STM32_PINMUX('I', 10, AF14)>, /* LCD_HSYNC */
+                                                <STM32_PINMUX('I',  9, AF14)>, /* LCD_VSYNC */
+                                                <STM32_PINMUX('F', 10, AF14)>, /* LCD_DE */
+                                                <STM32_PINMUX('H',  2, AF14)>, /* LCD_R0 */
+                                                <STM32_PINMUX('H',  3, AF14)>, /* LCD_R1 */
+                                                <STM32_PINMUX('H',  8, AF14)>, /* LCD_R2 */
+                                                <STM32_PINMUX('H',  9, AF14)>, /* LCD_R3 */
+                                                <STM32_PINMUX('H', 10, AF14)>, /* LCD_R4 */
+                                                <STM32_PINMUX('C',  0, AF14)>, /* LCD_R5 */
+                                                <STM32_PINMUX('H', 12, AF14)>, /* LCD_R6 */
+                                                <STM32_PINMUX('E', 15, AF14)>, /* LCD_R7 */
+                                                <STM32_PINMUX('E',  5, AF14)>, /* LCD_G0 */
+                                                <STM32_PINMUX('E',  6, AF14)>, /* LCD_G1 */
+                                                <STM32_PINMUX('H', 13, AF14)>, /* LCD_G2 */
+                                                <STM32_PINMUX('H', 14, AF14)>, /* LCD_G3 */
+                                                <STM32_PINMUX('H', 15, AF14)>, /* LCD_G4 */
+                                                <STM32_PINMUX('I',  0, AF14)>, /* LCD_G5 */
+                                                <STM32_PINMUX('I',  1, AF14)>, /* LCD_G6 */
+                                                <STM32_PINMUX('I',  2, AF14)>, /* LCD_G7 */
+                                                <STM32_PINMUX('D',  9, AF14)>, /* LCD_B0 */
+                                                <STM32_PINMUX('G', 12, AF14)>, /* LCD_B1 */
+                                                <STM32_PINMUX('G', 10, AF14)>, /* LCD_B2 */
+                                                <STM32_PINMUX('D', 10, AF14)>, /* LCD_B3 */
+                                                <STM32_PINMUX('I',  4, AF14)>, /* LCD_B4 */
+                                                <STM32_PINMUX('A',  3, AF14)>, /* LCD_B5 */
+                                                <STM32_PINMUX('B',  8, AF14)>, /* LCD_B6 */
+                                                <STM32_PINMUX('D',  8, AF14)>; /* LCD_B7 */
+                                       bias-disable;
+                                       drive-push-pull;
+                                       slew-rate = <1>;
+                               };
+                       };
+
+                       ltdc_pins_sleep_a: ltdc-a-1 {
+                               pins {
+                                       pinmux = <STM32_PINMUX('G',  7, ANALOG)>, /* LCD_CLK */
+                                                <STM32_PINMUX('I', 10, ANALOG)>, /* LCD_HSYNC */
+                                                <STM32_PINMUX('I',  9, ANALOG)>, /* LCD_VSYNC */
+                                                <STM32_PINMUX('F', 10, ANALOG)>, /* LCD_DE */
+                                                <STM32_PINMUX('H',  2, ANALOG)>, /* LCD_R0 */
+                                                <STM32_PINMUX('H',  3, ANALOG)>, /* LCD_R1 */
+                                                <STM32_PINMUX('H',  8, ANALOG)>, /* LCD_R2 */
+                                                <STM32_PINMUX('H',  9, ANALOG)>, /* LCD_R3 */
+                                                <STM32_PINMUX('H', 10, ANALOG)>, /* LCD_R4 */
+                                                <STM32_PINMUX('C',  0, ANALOG)>, /* LCD_R5 */
+                                                <STM32_PINMUX('H', 12, ANALOG)>, /* LCD_R6 */
+                                                <STM32_PINMUX('E', 15, ANALOG)>, /* LCD_R7 */
+                                                <STM32_PINMUX('E',  5, ANALOG)>, /* LCD_G0 */
+                                                <STM32_PINMUX('E',  6, ANALOG)>, /* LCD_G1 */
+                                                <STM32_PINMUX('H', 13, ANALOG)>, /* LCD_G2 */
+                                                <STM32_PINMUX('H', 14, ANALOG)>, /* LCD_G3 */
+                                                <STM32_PINMUX('H', 15, ANALOG)>, /* LCD_G4 */
+                                                <STM32_PINMUX('I',  0, ANALOG)>, /* LCD_G5 */
+                                                <STM32_PINMUX('I',  1, ANALOG)>, /* LCD_G6 */
+                                                <STM32_PINMUX('I',  2, ANALOG)>, /* LCD_G7 */
+                                                <STM32_PINMUX('D',  9, ANALOG)>, /* LCD_B0 */
+                                                <STM32_PINMUX('G', 12, ANALOG)>, /* LCD_B1 */
+                                                <STM32_PINMUX('G', 10, ANALOG)>, /* LCD_B2 */
+                                                <STM32_PINMUX('D', 10, ANALOG)>, /* LCD_B3 */
+                                                <STM32_PINMUX('I',  4, ANALOG)>, /* LCD_B4 */
+                                                <STM32_PINMUX('A',  3, ANALOG)>, /* LCD_B5 */
+                                                <STM32_PINMUX('B',  8, ANALOG)>, /* LCD_B6 */
+                                                <STM32_PINMUX('D',  8, ANALOG)>; /* LCD_B7 */
+                               };
+                       };
+
+                       ltdc_pins_b: ltdc-b-0 {
+                               pins {
+                                       pinmux = <STM32_PINMUX('I', 14, AF14)>, /* LCD_CLK */
+                                                <STM32_PINMUX('I', 12, AF14)>, /* LCD_HSYNC */
+                                                <STM32_PINMUX('I', 13, AF14)>, /* LCD_VSYNC */
+                                                <STM32_PINMUX('K',  7, AF14)>, /* LCD_DE */
+                                                <STM32_PINMUX('I', 15, AF14)>, /* LCD_R0 */
+                                                <STM32_PINMUX('J',  0, AF14)>, /* LCD_R1 */
+                                                <STM32_PINMUX('J',  1, AF14)>, /* LCD_R2 */
+                                                <STM32_PINMUX('J',  2, AF14)>, /* LCD_R3 */
+                                                <STM32_PINMUX('J',  3, AF14)>, /* LCD_R4 */
+                                                <STM32_PINMUX('J',  4, AF14)>, /* LCD_R5 */
+                                                <STM32_PINMUX('J',  5, AF14)>, /* LCD_R6 */
+                                                <STM32_PINMUX('J',  6, AF14)>, /* LCD_R7 */
+                                                <STM32_PINMUX('J',  7, AF14)>, /* LCD_G0 */
+                                                <STM32_PINMUX('J',  8, AF14)>, /* LCD_G1 */
+                                                <STM32_PINMUX('J',  9, AF14)>, /* LCD_G2 */
+                                                <STM32_PINMUX('J', 10, AF14)>, /* LCD_G3 */
+                                                <STM32_PINMUX('J', 11, AF14)>, /* LCD_G4 */
+                                                <STM32_PINMUX('K',  0, AF14)>, /* LCD_G5 */
+                                                <STM32_PINMUX('K',  1, AF14)>, /* LCD_G6 */
+                                                <STM32_PINMUX('K',  2, AF14)>, /* LCD_G7 */
+                                                <STM32_PINMUX('J', 12, AF14)>, /* LCD_B0 */
+                                                <STM32_PINMUX('J', 13, AF14)>, /* LCD_B1 */
+                                                <STM32_PINMUX('J', 14, AF14)>, /* LCD_B2 */
+                                                <STM32_PINMUX('J', 15, AF14)>, /* LCD_B3 */
+                                                <STM32_PINMUX('K',  3, AF14)>, /* LCD_B4 */
+                                                <STM32_PINMUX('K',  4, AF14)>, /* LCD_B5 */
+                                                <STM32_PINMUX('K',  5, AF14)>, /* LCD_B6 */
+                                                <STM32_PINMUX('K',  6, AF14)>; /* LCD_B7 */
+                                       bias-disable;
+                                       drive-push-pull;
+                                       slew-rate = <1>;
+                               };
+                       };
+
+                       ltdc_pins_sleep_b: ltdc-b-1 {
+                               pins {
+                                       pinmux = <STM32_PINMUX('I', 14, ANALOG)>, /* LCD_CLK */
+                                                <STM32_PINMUX('I', 12, ANALOG)>, /* LCD_HSYNC */
+                                                <STM32_PINMUX('I', 13, ANALOG)>, /* LCD_VSYNC */
+                                                <STM32_PINMUX('K',  7, ANALOG)>, /* LCD_DE */
+                                                <STM32_PINMUX('I', 15, ANALOG)>, /* LCD_R0 */
+                                                <STM32_PINMUX('J',  0, ANALOG)>, /* LCD_R1 */
+                                                <STM32_PINMUX('J',  1, ANALOG)>, /* LCD_R2 */
+                                                <STM32_PINMUX('J',  2, ANALOG)>, /* LCD_R3 */
+                                                <STM32_PINMUX('J',  3, ANALOG)>, /* LCD_R4 */
+                                                <STM32_PINMUX('J',  4, ANALOG)>, /* LCD_R5 */
+                                                <STM32_PINMUX('J',  5, ANALOG)>, /* LCD_R6 */
+                                                <STM32_PINMUX('J',  6, ANALOG)>, /* LCD_R7 */
+                                                <STM32_PINMUX('J',  7, ANALOG)>, /* LCD_G0 */
+                                                <STM32_PINMUX('J',  8, ANALOG)>, /* LCD_G1 */
+                                                <STM32_PINMUX('J',  9, ANALOG)>, /* LCD_G2 */
+                                                <STM32_PINMUX('J', 10, ANALOG)>, /* LCD_G3 */
+                                                <STM32_PINMUX('J', 11, ANALOG)>, /* LCD_G4 */
+                                                <STM32_PINMUX('K',  0, ANALOG)>, /* LCD_G5 */
+                                                <STM32_PINMUX('K',  1, ANALOG)>, /* LCD_G6 */
+                                                <STM32_PINMUX('K',  2, ANALOG)>, /* LCD_G7 */
+                                                <STM32_PINMUX('J', 12, ANALOG)>, /* LCD_B0 */
+                                                <STM32_PINMUX('J', 13, ANALOG)>, /* LCD_B1 */
+                                                <STM32_PINMUX('J', 14, ANALOG)>, /* LCD_B2 */
+                                                <STM32_PINMUX('J', 15, ANALOG)>, /* LCD_B3 */
+                                                <STM32_PINMUX('K',  3, ANALOG)>, /* LCD_B4 */
+                                                <STM32_PINMUX('K',  4, ANALOG)>, /* LCD_B5 */
+                                                <STM32_PINMUX('K',  5, ANALOG)>, /* LCD_B6 */
+                                                <STM32_PINMUX('K',  6, ANALOG)>; /* LCD_B7 */
+                               };
+                       };
+
                        m_can1_pins_a: m-can1-0 {
                                pins1 {
                                        pinmux = <STM32_PINMUX('H', 13, AF9)>; /* CAN1_TX */
@@ -325,6 +506,87 @@
                                };
                        };
 
+                       sdmmc1_b4_pins_a: sdmmc1-b4-0 {
+                               pins {
+                                       pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
+                                                <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
+                                                <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
+                                                <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */
+                                                <STM32_PINMUX('C', 12, AF12)>, /* SDMMC1_CK */
+                                                <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
+                                       slew-rate = <3>;
+                                       drive-push-pull;
+                                       bias-disable;
+                               };
+                       };
+
+                       sdmmc1_b4_od_pins_a: sdmmc1-b4-od-0 {
+                               pins1 {
+                                       pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
+                                                <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
+                                                <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
+                                                <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */
+                                                <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */
+                                       slew-rate = <3>;
+                                       drive-push-pull;
+                                       bias-disable;
+                               };
+                               pins2{
+                                       pinmux = <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
+                                       slew-rate = <3>;
+                                       drive-open-drain;
+                                       bias-disable;
+                               };
+                       };
+
+                       sdmmc1_b4_sleep_pins_a: sdmmc1-b4-sleep-0 {
+                               pins {
+                                       pinmux = <STM32_PINMUX('C', 8, ANALOG)>, /* SDMMC1_D0 */
+                                                <STM32_PINMUX('C', 9, ANALOG)>, /* SDMMC1_D1 */
+                                                <STM32_PINMUX('C', 10, ANALOG)>, /* SDMMC1_D2 */
+                                                <STM32_PINMUX('C', 11, ANALOG)>, /* SDMMC1_D3 */
+                                                <STM32_PINMUX('C', 12, ANALOG)>, /* SDMMC1_CK */
+                                                <STM32_PINMUX('D', 2, ANALOG)>; /* SDMMC1_CMD */
+                               };
+                       };
+
+                       sdmmc1_dir_pins_a: sdmmc1-dir-0 {
+                               pins1 {
+                                       pinmux = <STM32_PINMUX('F', 2, AF11)>, /* SDMMC1_D0DIR */
+                                                <STM32_PINMUX('C', 7, AF8)>, /* SDMMC1_D123DIR */
+                                                <STM32_PINMUX('B', 9, AF11)>; /* SDMMC1_CDIR */
+                                       slew-rate = <3>;
+                                       drive-push-pull;
+                                       bias-pull-up;
+                               };
+                               pins2{
+                                       pinmux = <STM32_PINMUX('E', 4, AF8)>; /* SDMMC1_CKIN */
+                                       bias-pull-up;
+                               };
+                       };
+
+                       sdmmc1_dir_sleep_pins_a: sdmmc1-dir-sleep-0 {
+                               pins {
+                                       pinmux = <STM32_PINMUX('F', 2, ANALOG)>, /* SDMMC1_D0DIR */
+                                                <STM32_PINMUX('C', 7, ANALOG)>, /* SDMMC1_D123DIR */
+                                                <STM32_PINMUX('B', 9, ANALOG)>, /* SDMMC1_CDIR */
+                                                <STM32_PINMUX('E', 4, ANALOG)>; /* SDMMC1_CKIN */
+                               };
+                       };
+
+                       spdifrx_pins_a: spdifrx-0 {
+                               pins {
+                                       pinmux = <STM32_PINMUX('G', 12, AF8)>; /* SPDIF_IN1 */
+                                       bias-disable;
+                               };
+                       };
+
+                       spdifrx_sleep_pins_a: spdifrx-1 {
+                               pins {
+                                       pinmux = <STM32_PINMUX('G', 12, ANALOG)>; /* SPDIF_IN1 */
+                               };
+                       };
+
                        uart4_pins_a: uart4-0 {
                                pins1 {
                                        pinmux = <STM32_PINMUX('G', 11, AF6)>; /* UART4_TX */
@@ -371,6 +633,13 @@
                                };
                        };
 
+                       i2c4_pins_sleep_a: i2c4-1 {
+                               pins {
+                                       pinmux = <STM32_PINMUX('Z', 4, ANALOG)>, /* I2C4_SCL */
+                                                <STM32_PINMUX('Z', 5, ANALOG)>; /* I2C4_SDA */
+                               };
+                       };
+
                        spi1_pins_a: spi1-0 {
                                pins1 {
                                        pinmux = <STM32_PINMUX('Z', 0, AF5)>, /* SPI1_SCK */

diff --git a/arch/arm/boot/dts/stm32mp157a-dk1.dts b/arch/arm/boot/dts/stm32mp157a-dk1.dts
new file mode 100644 (file)
index 0000000..098dbfb
--- /dev/null
+++ b/arch/arm/boot/dts/stm32mp157a-dk1.dts
@@ -0,0 +1,250 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
+ * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
+ */
+
+/dts-v1/;
+
+#include "stm32mp157c.dtsi"
+#include "stm32mp157-pinctrl.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/mfd/st,stpmic1.h>
+
+/ {
+       model = "STMicroelectronics STM32MP157A-DK1 Discovery Board";
+       compatible = "st,stm32mp157a-dk1", "st,stm32mp157";
+
+       aliases {
+               ethernet0 = &ethernet0;
+               serial0 = &uart4;
+       };
+
+       chosen {
+               stdout-path = "serial0:115200n8";
+       };
+
+       memory@c0000000 {
+               reg = <0xc0000000 0x20000000>;
+       };
+
+       led {
+               compatible = "gpio-leds";
+               blue {
+                       label = "heartbeat";
+                       gpios = <&gpiod 11 GPIO_ACTIVE_HIGH>;
+                       linux,default-trigger = "heartbeat";
+                       default-state = "off";
+               };
+       };
+};
+
+&cec {
+       pinctrl-names = "default", "sleep";
+       pinctrl-0 = <&cec_pins_b>;
+       pinctrl-1 = <&cec_pins_sleep_b>;
+       status = "okay";
+};
+
+&ethernet0 {
+       status = "okay";
+       pinctrl-0 = <&ethernet0_rgmii_pins_a>;
+       pinctrl-1 = <&ethernet0_rgmii_pins_sleep_a>;
+       pinctrl-names = "default", "sleep";
+       phy-mode = "rgmii";
+       max-speed = <1000>;
+       phy-handle = <&phy0>;
+
+       mdio0 {
+               #address-cells = <1>;
+               #size-cells = <0>;
+               compatible = "snps,dwmac-mdio";
+               phy0: ethernet-phy@0 {
+                       reg = <0>;
+               };
+       };
+};
+
+
+&i2c4 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&i2c4_pins_a>;
+       i2c-scl-rising-time-ns = <185>;
+       i2c-scl-falling-time-ns = <20>;
+       status = "okay";
+       /* spare dmas for other usage */
+       /delete-property/dmas;
+       /delete-property/dma-names;
+
+       pmic: stpmic@33 {
+               compatible = "st,stpmic1";
+               reg = <0x33>;
+               interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>;
+               interrupt-controller;
+               #interrupt-cells = <2>;
+               status = "okay";
+
+               regulators {
+                       compatible = "st,stpmic1-regulators";
+                       ldo1-supply = <&v3v3>;
+                       ldo3-supply = <&vdd_ddr>;
+                       ldo6-supply = <&v3v3>;
+                       pwr_sw1-supply = <&bst_out>;
+                       pwr_sw2-supply = <&bst_out>;
+
+                       vddcore: buck1 {
+                               regulator-name = "vddcore";
+                               regulator-min-microvolt = <800000>;
+                               regulator-max-microvolt = <1350000>;
+                               regulator-always-on;
+                               regulator-initial-mode = <0>;
+                               regulator-over-current-protection;
+                       };
+
+                       vdd_ddr: buck2 {
+                               regulator-name = "vdd_ddr";
+                               regulator-min-microvolt = <1350000>;
+                               regulator-max-microvolt = <1350000>;
+                               regulator-always-on;
+                               regulator-initial-mode = <0>;
+                               regulator-over-current-protection;
+                       };
+
+                       vdd: buck3 {
+                               regulator-name = "vdd";
+                               regulator-min-microvolt = <3300000>;
+                               regulator-max-microvolt = <3300000>;
+                               regulator-always-on;
+                               st,mask-reset;
+                               regulator-initial-mode = <0>;
+                               regulator-over-current-protection;
+                       };
+
+                       v3v3: buck4 {
+                               regulator-name = "v3v3";
+                               regulator-min-microvolt = <3300000>;
+                               regulator-max-microvolt = <3300000>;
+                               regulator-always-on;
+                               regulator-over-current-protection;
+                               regulator-initial-mode = <0>;
+                       };
+
+                       v1v8_audio: ldo1 {
+                               regulator-name = "v1v8_audio";
+                               regulator-min-microvolt = <1800000>;
+                               regulator-max-microvolt = <1800000>;
+                               regulator-always-on;
+                               interrupts = <IT_CURLIM_LDO1 0>;
+                       };
+
+                       v3v3_hdmi: ldo2 {
+                               regulator-name = "v3v3_hdmi";
+                               regulator-min-microvolt = <3300000>;
+                               regulator-max-microvolt = <3300000>;
+                               regulator-always-on;
+                               interrupts = <IT_CURLIM_LDO2 0>;
+                       };
+
+                       vtt_ddr: ldo3 {
+                               regulator-name = "vtt_ddr";
+                               regulator-min-microvolt = <500000>;
+                               regulator-max-microvolt = <750000>;
+                               regulator-always-on;
+                               regulator-over-current-protection;
+                       };
+
+                       vdd_usb: ldo4 {
+                               regulator-name = "vdd_usb";
+                               regulator-min-microvolt = <3300000>;
+                               regulator-max-microvolt = <3300000>;
+                               interrupts = <IT_CURLIM_LDO4 0>;
+                       };
+
+                       vdda: ldo5 {
+                               regulator-name = "vdda";
+                               regulator-min-microvolt = <2900000>;
+                               regulator-max-microvolt = <2900000>;
+                               interrupts = <IT_CURLIM_LDO5 0>;
+                               regulator-boot-on;
+                       };
+
+                       v1v2_hdmi: ldo6 {
+                               regulator-name = "v1v2_hdmi";
+                               regulator-min-microvolt = <1200000>;
+                               regulator-max-microvolt = <1200000>;
+                               regulator-always-on;
+                               interrupts = <IT_CURLIM_LDO6 0>;
+                       };
+
+                       vref_ddr: vref_ddr {
+                               regulator-name = "vref_ddr";
+                               regulator-always-on;
+                               regulator-over-current-protection;
+                       };
+
+                        bst_out: boost {
+                               regulator-name = "bst_out";
+                               interrupts = <IT_OCP_BOOST 0>;
+                        };
+
+                       vbus_otg: pwr_sw1 {
+                               regulator-name = "vbus_otg";
+                               interrupts = <IT_OCP_OTG 0>;
+                        };
+
+                        vbus_sw: pwr_sw2 {
+                               regulator-name = "vbus_sw";
+                               interrupts = <IT_OCP_SWOUT 0>;
+                               regulator-active-discharge;
+                        };
+               };
+
+               onkey {
+                       compatible = "st,stpmic1-onkey";
+                       interrupts = <IT_PONKEY_F 0>, <IT_PONKEY_R 0>;
+                       interrupt-names = "onkey-falling", "onkey-rising";
+                       power-off-time-sec = <10>;
+                       status = "okay";
+               };
+
+               watchdog {
+                       compatible = "st,stpmic1-wdt";
+                       status = "disabled";
+               };
+       };
+};
+
+&ipcc {
+       status = "okay";
+};
+
+&iwdg2 {
+       timeout-sec = <32>;
+       status = "okay";
+};
+
+&rng1 {
+       status = "okay";
+};
+
+&rtc {
+       status = "okay";
+};
+
+&sdmmc1 {
+       pinctrl-names = "default", "opendrain", "sleep";
+       pinctrl-0 = <&sdmmc1_b4_pins_a>;
+       pinctrl-1 = <&sdmmc1_b4_od_pins_a>;
+       pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>;
+       broken-cd;
+       st,neg-edge;
+       bus-width = <4>;
+       vmmc-supply = <&v3v3>;
+       status = "okay";
+};
+
+&uart4 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&uart4_pins_a>;
+       status = "okay";
+};

diff --git a/arch/arm/boot/dts/stm32mp157c-dk2.dts b/arch/arm/boot/dts/stm32mp157c-dk2.dts
new file mode 100644 (file)
index 0000000..20ea601
--- /dev/null
+++ b/arch/arm/boot/dts/stm32mp157c-dk2.dts
@@ -0,0 +1,76 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
+ * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
+ */
+
+/dts-v1/;
+
+#include "stm32mp157a-dk1.dts"
+
+/ {
+       model = "STMicroelectronics STM32MP157C-DK2 Discovery Board";
+       compatible = "st,stm32mp157c-dk2", "st,stm32mp157";
+
+       reg18: reg18 {
+               compatible = "regulator-fixed";
+               regulator-name = "reg18";
+               regulator-min-microvolt = <1800000>;
+               regulator-max-microvolt = <1800000>;
+               regulator-always-on;
+       };
+};
+
+&dsi {
+       #address-cells = <1>;
+       #size-cells = <0>;
+       status = "okay";
+       phy-dsi-supply = <&reg18>;
+
+       ports {
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               port@0 {
+                       reg = <0>;
+                       dsi_in: endpoint {
+                               remote-endpoint = <&ltdc_ep1_out>;
+                       };
+               };
+
+               port@1 {
+                       reg = <1>;
+                       dsi_out: endpoint {
+                               remote-endpoint = <&panel_in>;
+                       };
+               };
+       };
+
+       panel@0 {
+               compatible = "orisetech,otm8009a";
+               reg = <0>;
+               reset-gpios = <&gpioe 4 GPIO_ACTIVE_LOW>;
+               power-supply = <&v3v3>;
+               status = "okay";
+
+               port {
+                       panel_in: endpoint {
+                               remote-endpoint = <&dsi_out>;
+                       };
+               };
+       };
+};
+
+&ltdc {
+       status = "okay";
+
+       port {
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               ltdc_ep1_out: endpoint@1 {
+                       reg = <1>;
+                       remote-endpoint = <&dsi_in>;
+               };
+       };
+};

diff --git a/arch/arm/boot/dts/stm32mp157c-ed1.dts b/arch/arm/boot/dts/stm32mp157c-ed1.dts
index d66edb0..62a8c78 100644 (file)
--- a/arch/arm/boot/dts/stm32mp157c-ed1.dts
+++ b/arch/arm/boot/dts/stm32mp157c-ed1.dts
@@ -7,6 +7,8 @@
 
 #include "stm32mp157c.dtsi"
 #include "stm32mp157-pinctrl.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/mfd/st,stpmic1.h>
 
 / {
        model = "STMicroelectronics STM32MP157C eval daughter";
@@ -41,12 +43,17 @@
                regulator-always-on;
        };
 
-       vdd_usb: vdd-usb {
-               compatible = "regulator-fixed";
-               regulator-name = "vdd_usb";
-               regulator-min-microvolt = <3300000>;
-               regulator-max-microvolt = <3300000>;
+       sd_switch: regulator-sd_switch {
+               compatible = "regulator-gpio";
+               regulator-name = "sd_switch";
+               regulator-min-microvolt = <1800000>;
+               regulator-max-microvolt = <2900000>;
+               regulator-type = "voltage";
                regulator-always-on;
+
+               gpios = <&gpiof 14 GPIO_ACTIVE_HIGH>;
+               gpios-states = <0>;
+               states = <1800000 0x1 2900000 0x0>;
        };
 };
 
@@ -60,6 +67,149 @@
        i2c-scl-rising-time-ns = <185>;
        i2c-scl-falling-time-ns = <20>;
        status = "okay";
+       /* spare dmas for other usage */
+       /delete-property/dmas;
+       /delete-property/dma-names;
+
+       pmic: stpmic@33 {
+               compatible = "st,stpmic1";
+               reg = <0x33>;
+               interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>;
+               interrupt-controller;
+               #interrupt-cells = <2>;
+               status = "okay";
+
+               regulators {
+                       compatible = "st,stpmic1-regulators";
+                       ldo1-supply = <&v3v3>;
+                       ldo2-supply = <&v3v3>;
+                       ldo3-supply = <&vdd_ddr>;
+                       ldo5-supply = <&v3v3>;
+                       ldo6-supply = <&v3v3>;
+                       pwr_sw1-supply = <&bst_out>;
+                       pwr_sw2-supply = <&bst_out>;
+
+                       vddcore: buck1 {
+                               regulator-name = "vddcore";
+                               regulator-min-microvolt = <800000>;
+                               regulator-max-microvolt = <1350000>;
+                               regulator-always-on;
+                               regulator-initial-mode = <0>;
+                               regulator-over-current-protection;
+                       };
+
+                       vdd_ddr: buck2 {
+                               regulator-name = "vdd_ddr";
+                               regulator-min-microvolt = <1350000>;
+                               regulator-max-microvolt = <1350000>;
+                               regulator-always-on;
+                               regulator-initial-mode = <0>;
+                               regulator-over-current-protection;
+                       };
+
+                       vdd: buck3 {
+                               regulator-name = "vdd";
+                               regulator-min-microvolt = <3300000>;
+                               regulator-max-microvolt = <3300000>;
+                               regulator-always-on;
+                               st,mask-reset;
+                               regulator-initial-mode = <0>;
+                               regulator-over-current-protection;
+                       };
+
+                       v3v3: buck4 {
+                               regulator-name = "v3v3";
+                               regulator-min-microvolt = <3300000>;
+                               regulator-max-microvolt = <3300000>;
+                               regulator-always-on;
+                               regulator-over-current-protection;
+                               regulator-initial-mode = <0>;
+                       };
+
+                       vdda: ldo1 {
+                               regulator-name = "vdda";
+                               regulator-min-microvolt = <2900000>;
+                               regulator-max-microvolt = <2900000>;
+                               interrupts = <IT_CURLIM_LDO1 0>;
+                       };
+
+                       v2v8: ldo2 {
+                               regulator-name = "v2v8";
+                               regulator-min-microvolt = <2800000>;
+                               regulator-max-microvolt = <2800000>;
+                               interrupts = <IT_CURLIM_LDO2 0>;
+                       };
+
+                       vtt_ddr: ldo3 {
+                               regulator-name = "vtt_ddr";
+                               regulator-min-microvolt = <500000>;
+                               regulator-max-microvolt = <750000>;
+                               regulator-always-on;
+                               regulator-over-current-protection;
+                       };
+
+                       vdd_usb: ldo4 {
+                               regulator-name = "vdd_usb";
+                               regulator-min-microvolt = <3300000>;
+                               regulator-max-microvolt = <3300000>;
+                               interrupts = <IT_CURLIM_LDO4 0>;
+                       };
+
+                       vdd_sd: ldo5 {
+                               regulator-name = "vdd_sd";
+                               regulator-min-microvolt = <2900000>;
+                               regulator-max-microvolt = <2900000>;
+                               interrupts = <IT_CURLIM_LDO5 0>;
+                               regulator-boot-on;
+                       };
+
+                       v1v8: ldo6 {
+                               regulator-name = "v1v8";
+                               regulator-min-microvolt = <1800000>;
+                               regulator-max-microvolt = <1800000>;
+                               interrupts = <IT_CURLIM_LDO6 0>;
+                       };
+
+                       vref_ddr: vref_ddr {
+                               regulator-name = "vref_ddr";
+                               regulator-always-on;
+                               regulator-over-current-protection;
+                       };
+
+                       bst_out: boost {
+                               regulator-name = "bst_out";
+                               interrupts = <IT_OCP_BOOST 0>;
+                       };
+
+                       vbus_otg: pwr_sw1 {
+                               regulator-name = "vbus_otg";
+                               interrupts = <IT_OCP_OTG 0>;
+                        };
+
+                        vbus_sw: pwr_sw2 {
+                               regulator-name = "vbus_sw";
+                               interrupts = <IT_OCP_SWOUT 0>;
+                               regulator-active-discharge;
+                        };
+               };
+
+               onkey {
+                       compatible = "st,stpmic1-onkey";
+                       interrupts = <IT_PONKEY_F 0>, <IT_PONKEY_R 0>;
+                       interrupt-names = "onkey-falling", "onkey-rising";
+                       power-off-time-sec = <10>;
+                       status = "okay";
+               };
+
+               watchdog {
+                       compatible = "st,stpmic1-wdt";
+                       status = "disabled";
+               };
+       };
+};
+
+&ipcc {
+       status = "okay";
 };
 
 &iwdg2 {
@@ -75,6 +225,21 @@
        status = "okay";
 };
 
+&sdmmc1 {
+       pinctrl-names = "default", "opendrain", "sleep";
+       pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_a>;
+       pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_dir_pins_a>;
+       pinctrl-2 = <&sdmmc1_b4_sleep_pins_a &sdmmc1_dir_sleep_pins_a>;
+       broken-cd;
+       st,sig-dir;
+       st,neg-edge;
+       st,use-ckin;
+       bus-width = <4>;
+       vmmc-supply = <&vdd_sd>;
+       vqmmc-supply = <&sd_switch>;
+       status = "okay";
+};
+
 &timers6 {
        status = "okay";
        /* spare dmas for other usage */

diff --git a/arch/arm/boot/dts/stm32mp157c.dtsi b/arch/arm/boot/dts/stm32mp157c.dtsi
index f8bbfff..2afeee6 100644 (file)
--- a/arch/arm/boot/dts/stm32mp157c.dtsi
+++ b/arch/arm/boot/dts/stm32mp157c.dtsi
@@ -379,6 +379,19 @@
                        status = "disabled";
                };
 
+               spdifrx: audio-controller@4000d000 {
+                       compatible = "st,stm32h7-spdifrx";
+                       #sound-dai-cells = <0>;
+                       reg = <0x4000d000 0x400>;
+                       clocks = <&rcc SPDIF_K>;
+                       clock-names = "kclk";
+                       interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
+                       dmas = <&dmamux1 93 0x400 0x01>,
+                              <&dmamux1 94 0x400 0x01>;
+                       dma-names = "rx", "rx-ctrl";
+                       status = "disabled";
+               };
+
                usart2: serial@4000e000 {
                        compatible = "st,stm32h7-uart";
                        reg = <0x4000e000 0x400>;
@@ -886,6 +899,21 @@
                        status = "disabled";
                };
 
+               ipcc: mailbox@4c001000 {
+                       compatible = "st,stm32mp1-ipcc";
+                       #mbox-cells = <1>;
+                       reg = <0x4c001000 0x400>;
+                       st,proc-id = <0>;
+                       interrupts-extended =
+                               <&intc GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
+                               <&intc GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
+                               <&exti 61 1>;
+                       interrupt-names = "rx", "tx", "wakeup";
+                       clocks = <&rcc IPCC>;
+                       wakeup-source;
+                       status = "disabled";
+               };
+
                rcc: rcc@50000000 {
                        compatible = "st,stm32mp1-rcc", "syscon";
                        reg = <0x50000000 0x1000>;
@@ -903,6 +931,7 @@
                syscfg: syscon@50020000 {
                        compatible = "st,stm32mp157-syscfg", "syscon";
                        reg = <0x50020000 0x400>;
+                       clocks = <&rcc SYSCFG>;
                };
 
                lptimer2: timer@50021000 {
@@ -1050,6 +1079,20 @@
                        status = "disabled";
                };
 
+               sdmmc1: sdmmc@58005000 {
+                       compatible = "arm,pl18x", "arm,primecell";
+                       arm,primecell-periphid = <0x10153180>;
+                       reg = <0x58005000 0x1000>;
+                       interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-names = "cmd_irq";
+                       clocks = <&rcc SDMMC1_K>;
+                       clock-names = "apb_pclk";
+                       resets = <&rcc SDMMC1_R>;
+                       cap-sd-highspeed;
+                       cap-mmc-highspeed;
+                       max-frequency = <120000000>;
+               };
+
                crc1: crc@58009000 {
                        compatible = "st,stm32f7-crc";
                        reg = <0x58009000 0x400>;
@@ -1199,6 +1242,19 @@
                        status = "disabled";
                };
 
+               bsec: nvmem@5c005000 {
+                       compatible = "st,stm32mp15-bsec";
+                       reg = <0x5c005000 0x400>;
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       ts_cal1: calib@5c {
+                               reg = <0x5c 0x2>;
+                       };
+                       ts_cal2: calib@5e {
+                               reg = <0x5e 0x2>;
+                       };
+               };
+
                i2c6: i2c@5c009000 {
                        compatible = "st,stm32f7-i2c";
                        reg = <0x5c009000 0x400>;

diff --git a/arch/arm/boot/dts/sun4i-a10-chuwi-v7-cw0825.dts b/arch/arm/boot/dts/sun4i-a10-chuwi-v7-cw0825.dts
index cf7b392..7426298 100644 (file)
--- a/arch/arm/boot/dts/sun4i-a10-chuwi-v7-cw0825.dts
+++ b/arch/arm/boot/dts/sun4i-a10-chuwi-v7-cw0825.dts
@@ -131,20 +131,6 @@
        status = "okay";
 };
 
-&pio {
-       usb0_id_detect_pin: usb0-id-detect-pin {
-               pins = "PH4";
-               function = "gpio_in";
-               bias-pull-up;
-       };
-
-       usb0_vbus_detect_pin: usb0-vbus-detect-pin {
-               pins = "PH5";
-               function = "gpio_in";
-               bias-pull-down;
-       };
-};
-
 &reg_usb0_vbus {
        status = "okay";
 };
@@ -165,10 +151,8 @@
 };
 
 &usbphy {
-       pinctrl-names = "default";
-       pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>;
-       usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
-       usb0_vbus_det-gpio = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */
+       usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */
+       usb0_vbus_det-gpios = <&pio 7 5 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* PH5 */
        usb0_vbus-supply = <&reg_usb0_vbus>;
        usb2_vbus-supply = <&reg_usb2_vbus>;
        status = "okay";

diff --git a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
index 197a1f2..7306c65 100644 (file)
--- a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
+++ b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
@@ -184,12 +184,6 @@
                function = "gpio_out";
                drive-strength = <20>;
        };
-
-       usb0_id_detect_pin: usb0-id-detect-pin {
-               pins = "PH4";
-               function = "gpio_in";
-               bias-pull-up;
-       };
 };
 
 &reg_ahci_5v {
@@ -254,9 +248,7 @@
 };
 
 &usbphy {
-       pinctrl-names = "default";
-       pinctrl-0 = <&usb0_id_detect_pin>;
-       usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
+       usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */
        usb1_vbus-supply = <&reg_usb1_vbus>;
        usb2_vbus-supply = <&reg_usb2_vbus>;
        status = "okay";

diff --git a/arch/arm/boot/dts/sun4i-a10-dserve-dsrv9703c.dts b/arch/arm/boot/dts/sun4i-a10-dserve-dsrv9703c.dts
index 896e27a..8ee3ff4 100644 (file)
--- a/arch/arm/boot/dts/sun4i-a10-dserve-dsrv9703c.dts
+++ b/arch/arm/boot/dts/sun4i-a10-dserve-dsrv9703c.dts
@@ -158,20 +158,6 @@
        status = "okay";
 };
 
-&pio {
-       usb0_id_detect_pin: usb0-id-detect-pin {
-               pins = "PH4";
-               function = "gpio_in";
-               bias-pull-up;
-       };
-
-       usb0_vbus_detect_pin: usb0-vbus-detect-pin {
-               pins = "PH5";
-               function = "gpio_in";
-               bias-pull-down;
-       };
-};
-
 &pwm {
        pinctrl-names = "default";
        pinctrl-0 = <&pwm0_pin>;
@@ -223,10 +209,8 @@
 };
 
 &usbphy {
-       pinctrl-names = "default";
-       pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>;
-       usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
-       usb0_vbus_det-gpio = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */
+       usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */
+       usb0_vbus_det-gpios = <&pio 7 5 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* PH5 */
        usb0_vbus-supply = <&reg_usb0_vbus>;
        usb2_vbus-supply = <&reg_usb2_vbus>;
        status = "okay";

diff --git a/arch/arm/boot/dts/sun4i-a10-hyundai-a7hd.dts b/arch/arm/boot/dts/sun4i-a10-hyundai-a7hd.dts
index f63767c..bf2044b 100644 (file)
--- a/arch/arm/boot/dts/sun4i-a10-hyundai-a7hd.dts
+++ b/arch/arm/boot/dts/sun4i-a10-hyundai-a7hd.dts
@@ -86,20 +86,6 @@
        status = "okay";
 };
 
-&pio {
-       usb0_id_detect_pin: usb0-id-detect-pin {
-               pins = "PH4";
-               function = "gpio_in";
-               bias-pull-up;
-       };
-
-       usb0_vbus_detect_pin: usb0-vbus-detect-pin {
-               pins = "PH5";
-               function = "gpio_in";
-               bias-pull-down;
-       };
-};
-
 &reg_usb0_vbus {
        status = "okay";
 };
@@ -121,10 +107,8 @@
 };
 
 &usbphy {
-       pinctrl-names = "default";
-       pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>;
-       usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
-       usb0_vbus_det-gpio = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */
+       usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */
+       usb0_vbus_det-gpios = <&pio 7 5 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* PH5 */
        usb0_vbus-supply = <&reg_usb0_vbus>;
        usb2_vbus-supply = <&reg_usb2_vbus>;
        status = "okay";

diff --git a/arch/arm/boot/dts/sun4i-a10-inet1.dts b/arch/arm/boot/dts/sun4i-a10-inet1.dts
index 26d0c1d..ca87838 100644 (file)
--- a/arch/arm/boot/dts/sun4i-a10-inet1.dts
+++ b/arch/arm/boot/dts/sun4i-a10-inet1.dts
@@ -164,20 +164,6 @@
        status = "okay";
 };
 
-&pio {
-       usb0_id_detect_pin: usb0-id-detect-pin {
-               pins = "PH4";
-               function = "gpio_in";
-               bias-pull-up;
-       };
-
-       usb0_vbus_detect_pin: usb0-vbus-detect-pin {
-               pins = "PH5";
-               function = "gpio_in";
-               bias-pull-down;
-       };
-};
-
 &pwm {
        pinctrl-names = "default";
        pinctrl-0 = <&pwm0_pin>;
@@ -233,10 +219,8 @@
 };
 
 &usbphy {
-       pinctrl-names = "default";
-       pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>;
-       usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
-       usb0_vbus_det-gpio = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */
+       usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */
+       usb0_vbus_det-gpios = <&pio 7 5 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* PH5 */
        usb0_vbus-supply = <&reg_usb0_vbus>;
        usb1_vbus-supply = <&reg_usb1_vbus>;
        usb2_vbus-supply = <&reg_usb2_vbus>;

diff --git a/arch/arm/boot/dts/sun4i-a10-inet97fv2.dts b/arch/arm/boot/dts/sun4i-a10-inet97fv2.dts
index 71c27ea..76016f2 100644 (file)
--- a/arch/arm/boot/dts/sun4i-a10-inet97fv2.dts
+++ b/arch/arm/boot/dts/sun4i-a10-inet97fv2.dts
@@ -150,20 +150,6 @@
        status = "okay";
 };
 
-&pio {
-       usb0_id_detect_pin: usb0-id-detect-pin {
-               pins = "PH4";
-               function = "gpio_in";
-               bias-pull-up;
-       };
-
-       usb0_vbus_detect_pin: usb0-vbus-detect-pin {
-               pins = "PH5";
-               function = "gpio_in";
-               bias-pull-down;
-       };
-};
-
 &reg_dcdc2 {
        regulator-always-on;
        regulator-min-microvolt = <1000000>;
@@ -209,10 +195,8 @@
 };
 
 &usbphy {
-       pinctrl-names = "default";
-       pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>;
-       usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
-       usb0_vbus_det-gpio = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */
+       usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */
+       usb0_vbus_det-gpios = <&pio 7 5 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* PH5 */
        usb0_vbus-supply = <&reg_usb0_vbus>;
        usb2_vbus-supply = <&reg_usb2_vbus>;
        status = "okay";

diff --git a/arch/arm/boot/dts/sun4i-a10-inet9f-rev03.dts b/arch/arm/boot/dts/sun4i-a10-inet9f-rev03.dts
index 2f0d966..0a562b2 100644 (file)
--- a/arch/arm/boot/dts/sun4i-a10-inet9f-rev03.dts
+++ b/arch/arm/boot/dts/sun4i-a10-inet9f-rev03.dts
@@ -61,8 +61,6 @@
 
        gpio-keys {
                compatible = "gpio-keys-polled";
-               pinctrl-names = "default";
-               pinctrl-0 = <&key_pins_inet9f>;
                poll-interval = <20>;
 
                left-joystick-left {
@@ -70,7 +68,7 @@
                        linux,code = <ABS_X>;
                        linux,input-type = <EV_ABS>;
                        linux,input-value = <0xffffffff>; /* -1 */
-                       gpios = <&pio 0 6 GPIO_ACTIVE_LOW>; /* PA6 */
+                       gpios = <&pio 0 6 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA6 */
                };
 
                left-joystick-right {
@@ -78,7 +76,7 @@
                        linux,code = <ABS_X>;
                        linux,input-type = <EV_ABS>;
                        linux,input-value = <1>;
-                       gpios = <&pio 0 5 GPIO_ACTIVE_LOW>; /* PA5 */
+                       gpios = <&pio 0 5 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA5 */
                };
 
                left-joystick-up {
@@ -86,7 +84,7 @@
                        linux,code = <ABS_Y>;
                        linux,input-type = <EV_ABS>;
                        linux,input-value = <0xffffffff>; /* -1 */
-                       gpios = <&pio 0 8 GPIO_ACTIVE_LOW>; /* PA8 */
+                       gpios = <&pio 0 8 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA8 */
                };
 
                left-joystick-down {
@@ -94,7 +92,7 @@
                        linux,code = <ABS_Y>;
                        linux,input-type = <EV_ABS>;
                        linux,input-value = <1>;
-                       gpios = <&pio 0 9 GPIO_ACTIVE_LOW>; /* PA9 */
+                       gpios = <&pio 0 9 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA9 */
                };
 
                right-joystick-left {
@@ -102,7 +100,7 @@
                        linux,code = <ABS_Z>;
                        linux,input-type = <EV_ABS>;
                        linux,input-value = <0xffffffff>; /* -1 */
-                       gpios = <&pio 0 1 GPIO_ACTIVE_LOW>; /* PA1 */
+                       gpios = <&pio 0 1 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA1 */
                };
 
                right-joystick-right {
@@ -110,7 +108,7 @@
                        linux,code = <ABS_Z>;
                        linux,input-type = <EV_ABS>;
                        linux,input-value = <1>;
-                       gpios = <&pio 0 0 GPIO_ACTIVE_LOW>; /* PA0 */
+                       gpios = <&pio 0 0 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA0 */
                };
 
                right-joystick-up {
@@ -118,7 +116,7 @@
                        linux,code = <ABS_RZ>;
                        linux,input-type = <EV_ABS>;
                        linux,input-value = <0xffffffff>; /* -1 */
-                       gpios = <&pio 0 3 GPIO_ACTIVE_LOW>; /* PA3 */
+                       gpios = <&pio 0 3 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA3 */
                };
 
                right-joystick-down {
@@ -126,7 +124,7 @@
                        linux,code = <ABS_RZ>;
                        linux,input-type = <EV_ABS>;
                        linux,input-value = <1>;
-                       gpios = <&pio 0 4 GPIO_ACTIVE_LOW>; /* PA4 */
+                       gpios = <&pio 0 4 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA4 */
                };
 
                dpad-left {
@@ -134,7 +132,7 @@
                        linux,code = <ABS_HAT0X>;
                        linux,input-type = <EV_ABS>;
                        linux,input-value = <0xffffffff>; /* -1 */
-                       gpios = <&pio 7 23 GPIO_ACTIVE_LOW>; /* PH23 */
+                       gpios = <&pio 7 23 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PH23 */
                };
 
                dpad-right {
@@ -142,7 +140,7 @@
                        linux,code = <ABS_HAT0X>;
                        linux,input-type = <EV_ABS>;
                        linux,input-value = <1>;
-                       gpios = <&pio 7 24 GPIO_ACTIVE_LOW>; /* PH24 */
+                       gpios = <&pio 7 24 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PH24 */
                };
 
                dpad-up {
@@ -150,7 +148,7 @@
                        linux,code = <ABS_HAT0Y>;
                        linux,input-type = <EV_ABS>;
                        linux,input-value = <0xffffffff>; /* -1 */
-                       gpios = <&pio 7 25 GPIO_ACTIVE_LOW>; /* PH25 */
+                       gpios = <&pio 7 25 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PH25 */
                };
 
                dpad-down {
@@ -158,55 +156,55 @@
                        linux,code = <ABS_HAT0Y>;
                        linux,input-type = <EV_ABS>;
                        linux,input-value = <1>;
-                       gpios = <&pio 7 26 GPIO_ACTIVE_LOW>; /* PH26 */
+                       gpios = <&pio 7 26 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PH26 */
                };
 
                x {
                        label = "Button X";
                        linux,code = <BTN_X>;
-                       gpios = <&pio 0 16 GPIO_ACTIVE_LOW>; /* PA16 */
+                       gpios = <&pio 0 16 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA16 */
                };
 
                y {
                        label = "Button Y";
                        linux,code = <BTN_Y>;
-                       gpios = <&pio 0 14 GPIO_ACTIVE_LOW>; /* PA14 */
+                       gpios = <&pio 0 14 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA14 */
                };
 
                a {
                        label = "Button A";
                        linux,code = <BTN_A>;
-                       gpios = <&pio 0 17 GPIO_ACTIVE_LOW>; /* PA17 */
+                       gpios = <&pio 0 17 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA17 */
                };
 
                b {
                        label = "Button B";
                        linux,code = <BTN_B>;
-                       gpios = <&pio 0 15 GPIO_ACTIVE_LOW>; /* PA15 */
+                       gpios = <&pio 0 15 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA15 */
                };
 
                select {
                        label = "Select Button";
                        linux,code = <BTN_SELECT>;
-                       gpios = <&pio 0 11 GPIO_ACTIVE_LOW>; /* PA11 */
+                       gpios = <&pio 0 11 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA11 */
                };
 
                start {
                        label = "Start Button";
                        linux,code = <BTN_START>;
-                       gpios = <&pio 0 12 GPIO_ACTIVE_LOW>; /* PA12 */
+                       gpios = <&pio 0 12 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA12 */
                };
 
                top-left {
                        label = "Top Left Button";
                        linux,code = <BTN_TL>;
-                       gpios = <&pio 7 22 GPIO_ACTIVE_LOW>; /* PH22 */
+                       gpios = <&pio 7 22 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PH22 */
                };
 
                top-right {
                        label = "Top Right Button";
                        linux,code = <BTN_TR>;
-                       gpios = <&pio 0 13 GPIO_ACTIVE_LOW>; /* PA13 */
+                       gpios = <&pio 0 13 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA13 */
                };
        };
 };
@@ -306,30 +304,6 @@
        status = "okay";
 };
 
-&pio {
-       key_pins_inet9f: key-pins {
-               pins = "PA0", "PA1", "PA3", "PA4",
-                      "PA5", "PA6", "PA8", "PA9",
-                      "PA11", "PA12", "PA13",
-                      "PA14", "PA15", "PA16", "PA17",
-                      "PH22", "PH23", "PH24", "PH25", "PH26";
-               function = "gpio_in";
-               bias-pull-up;
-       };
-
-       usb0_id_detect_pin: usb0-id-detect-pin {
-               pins = "PH4";
-               function = "gpio_in";
-               bias-pull-up;
-       };
-
-       usb0_vbus_detect_pin: usb0-vbus-detect-pin {
-               pins = "PH5";
-               function = "gpio_in";
-               bias-pull-down;
-       };
-};
-
 &reg_dcdc2 {
        regulator-always-on;
        regulator-min-microvolt = <1000000>;
@@ -375,10 +349,8 @@
 };
 
 &usbphy {
-       pinctrl-names = "default";
-       pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>;
-       usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
-       usb0_vbus_det-gpio = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */
+       usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */
+       usb0_vbus_det-gpios = <&pio 7 5 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* PH5 */
        usb0_vbus-supply = <&reg_usb0_vbus>;
        usb2_vbus-supply = <&reg_usb2_vbus>;
        status = "okay";

diff --git a/arch/arm/boot/dts/sun4i-a10-marsboard.dts b/arch/arm/boot/dts/sun4i-a10-marsboard.dts
index 0dbf695..58ad2ad 100644 (file)
--- a/arch/arm/boot/dts/sun4i-a10-marsboard.dts
+++ b/arch/arm/boot/dts/sun4i-a10-marsboard.dts
@@ -148,14 +148,6 @@
        status = "okay";
 };
 
-&pio {
-       usb0_id_detect_pin: usb0-id-detect-pin {
-               pins = "PH4";
-               function = "gpio_in";
-               bias-pull-up;
-       };
-};
-
 &reg_usb1_vbus {
        status = "okay";
 };
@@ -183,9 +175,7 @@
 };
 
 &usbphy {
-       pinctrl-names = "default";
-       pinctrl-0 = <&usb0_id_detect_pin>;
-       usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
+       usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */
        usb1_vbus-supply = <&reg_usb1_vbus>;
        usb2_vbus-supply = <&reg_usb2_vbus>;
        status = "okay";

diff --git a/arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts b/arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts
index b74a614..a8e537f 100644 (file)
--- a/arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts
+++ b/arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts
@@ -186,18 +186,6 @@
                function = "gpio_out";
                drive-strength = <20>;
        };
-
-       usb0_id_detect_pin: usb0-id-detect-pin {
-               pins = "PH4";
-               function = "gpio_in";
-               bias-pull-up;
-       };
-
-       usb0_vbus_detect_pin: usb0-vbus-detect-pin {
-               pins = "PH5";
-               function = "gpio_in";
-               bias-pull-down;
-       };
 };
 
 &reg_ahci_5v {
@@ -229,10 +217,8 @@
 };
 
 &usbphy {
-       pinctrl-names = "default";
-       pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>;
-       usb0_id_det-gpio   = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
-       usb0_vbus_det-gpio = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */
+       usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */
+       usb0_vbus_det-gpios = <&pio 7 5 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH5 */
        usb0_vbus-supply   = <&reg_usb0_vbus>;
        usb1_vbus-supply = <&reg_usb1_vbus>;
        usb2_vbus-supply = <&reg_usb2_vbus>;

diff --git a/arch/arm/boot/dts/sun4i-a10-pcduino.dts b/arch/arm/boot/dts/sun4i-a10-pcduino.dts
index d82a604..0f1e781 100644 (file)
--- a/arch/arm/boot/dts/sun4i-a10-pcduino.dts
+++ b/arch/arm/boot/dts/sun4i-a10-pcduino.dts
@@ -154,14 +154,6 @@
        status = "okay";
 };
 
-&pio {
-       usb0_id_detect_pin: usb0-id-detect-pin {
-               pins = "PH4";
-               function = "gpio_in";
-               bias-pull-up;
-       };
-};
-
 #include "axp209.dtsi"
 
 &reg_dcdc2 {
@@ -201,9 +193,7 @@
 };
 
 &usbphy {
-       pinctrl-names = "default";
-       pinctrl-0 = <&usb0_id_detect_pin>;
-       usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
+       usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */
        usb1_vbus-supply = <&reg_vcc5v0>; /* USB1 VBUS is always on */
        usb2_vbus-supply = <&reg_vcc5v0>; /* USB2 VBUS is always on */
        status = "okay";

diff --git a/arch/arm/boot/dts/sun4i-a10-pov-protab2-ips9.dts b/arch/arm/boot/dts/sun4i-a10-pov-protab2-ips9.dts
index 84b25be..24a3d23 100644 (file)
--- a/arch/arm/boot/dts/sun4i-a10-pov-protab2-ips9.dts
+++ b/arch/arm/boot/dts/sun4i-a10-pov-protab2-ips9.dts
@@ -146,20 +146,6 @@
        status = "okay";
 };
 
-&pio {
-       usb0_id_detect_pin: usb0-id-detect-pin {
-               pins = "PH4";
-               function = "gpio_in";
-               bias-pull-up;
-       };
-
-       usb0_vbus_detect_pin: usb0-vbus-detect-pin {
-               pins = "PH5";
-               function = "gpio_in";
-               bias-pull-down;
-       };
-};
-
 &pwm {
        pinctrl-names = "default";
        pinctrl-0 = <&pwm0_pin>;
@@ -211,10 +197,8 @@
 };
 
 &usbphy {
-       pinctrl-names = "default";
-       pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>;
-       usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
-       usb0_vbus_det-gpio = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */
+       usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */
+       usb0_vbus_det-gpios = <&pio 7 5 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* PH5 */
        usb0_vbus-supply = <&reg_usb0_vbus>;
        usb1_vbus-supply = <&reg_usb1_vbus>;
        status = "okay";

diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
index 73c3ac4..e88daa4 100644 (file)
--- a/arch/arm/boot/dts/sun4i-a10.dtsi
+++ b/arch/arm/boot/dts/sun4i-a10.dtsi
@@ -267,7 +267,7 @@
                        #dma-cells = <2>;
                };
 
-               nfc: nand@1c03000 {
+               nfc: nand-controller@1c03000 {
                        compatible = "allwinner,sun4i-a10-nand";
                        reg = <0x01c03000 0x1000>;
                        interrupts = <37>;
@@ -342,6 +342,7 @@
                                      "tcon-ch0",
                                      "tcon-ch1";
                        clock-output-names = "tcon0-pixel-clock";
+                       #clock-cells = <0>;
                        dmas = <&dma SUN4I_DMA_DEDICATED 14>;
 
                        ports {
@@ -391,6 +392,7 @@
                                      "tcon-ch0",
                                      "tcon-ch1";
                        clock-output-names = "tcon1-pixel-clock";
+                       #clock-cells = <0>;
                        dmas = <&dma SUN4I_DMA_DEDICATED 15>;
 
                        ports {
@@ -494,13 +496,14 @@
                        phy-names = "usb";
                        extcon = <&usbphy 0>;
                        allwinner,sram = <&otg_sram 1>;
+                       dr_mode = "otg";
                        status = "disabled";
                };
 
                usbphy: phy@1c13400 {
                        #phy-cells = <1>;
                        compatible = "allwinner,sun4i-a10-usb-phy";
-                       reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>;
+                       reg = <0x01c13400 0x10>, <0x01c14800 0x4>, <0x01c1c800 0x4>;
                        reg-names = "phy_ctrl", "pmu1", "pmu2";
                        clocks = <&ccu CLK_USB_PHY>;
                        clock-names = "usb_phy";
@@ -517,7 +520,6 @@
                        interrupts = <39>;
                        clocks = <&ccu CLK_AHB_EHCI0>;
                        phys = <&usbphy 1>;
-                       phy-names = "usb";
                        status = "disabled";
                };
 
@@ -527,7 +529,6 @@
                        interrupts = <64>;
                        clocks = <&ccu CLK_USB_OHCI0>, <&ccu CLK_AHB_OHCI0>;
                        phys = <&usbphy 1>;
-                       phy-names = "usb";
                        status = "disabled";
                };
 
@@ -607,7 +608,6 @@
                        interrupts = <40>;
                        clocks = <&ccu CLK_AHB_EHCI1>;
                        phys = <&usbphy 2>;
-                       phy-names = "usb";
                        status = "disabled";
                };
 
@@ -617,7 +617,6 @@
                        interrupts = <65>;
                        clocks = <&ccu CLK_USB_OHCI1>, <&ccu CLK_AHB_OHCI1>;
                        phys = <&usbphy 2>;
-                       phy-names = "usb";
                        status = "disabled";
                };
 

diff --git a/arch/arm/boot/dts/sun5i-a10s-auxtek-t004.dts b/arch/arm/boot/dts/sun5i-a10s-auxtek-t004.dts
index c88f089..8af0eae 100644 (file)
--- a/arch/arm/boot/dts/sun5i-a10s-auxtek-t004.dts
+++ b/arch/arm/boot/dts/sun5i-a10s-auxtek-t004.dts
@@ -119,12 +119,6 @@
 };
 
 &pio {
-       usb0_id_detect_pin: usb0-id-detect-pin {
-               pins = "PG12";
-               function = "gpio_in";
-               bias-pull-up;
-       };
-
        led_pins_t004: led-pin {
                pins = "PB2";
                function = "gpio_out";
@@ -149,9 +143,7 @@
 };
 
 &usbphy {
-       pinctrl-names = "default";
-       pinctrl-0 = <&usb0_id_detect_pin>;
-       usb0_id_det-gpio = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */
+       usb0_id_det-gpios = <&pio 6 12 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PG12 */
        usb1_vbus-supply = <&reg_usb1_vbus>;
        status = "okay";
 };

diff --git a/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts b/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts
index 262c2ff..5340b41 100644 (file)
--- a/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts
+++ b/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts
@@ -218,12 +218,6 @@
                function = "gpio_out";
                drive-strength = <20>;
        };
-
-       usb0_id_detect_pin: usb0-id-detect-pin {
-               pins = "PG12";
-               function = "gpio_in";
-               bias-pull-up;
-       };
 };
 
 &reg_usb0_vbus {
@@ -271,9 +265,7 @@
 };
 
 &usbphy {
-       pinctrl-names = "default";
-       pinctrl-0 = <&usb0_id_detect_pin>;
-       usb0_id_det-gpio = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */
+       usb0_id_det-gpios = <&pio 6 12 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PG12 */
        usb0_vbus-supply = <&reg_usb0_vbus>;
        usb1_vbus-supply = <&reg_usb1_vbus>;
        status = "okay";

diff --git a/arch/arm/boot/dts/sun5i-a13-empire-electronix-d709.dts b/arch/arm/boot/dts/sun5i-a13-empire-electronix-d709.dts
index f3cede9..a23bf24 100644 (file)
--- a/arch/arm/boot/dts/sun5i-a13-empire-electronix-d709.dts
+++ b/arch/arm/boot/dts/sun5i-a13-empire-electronix-d709.dts
@@ -127,20 +127,6 @@
        status = "okay";
 };
 
-&pio {
-       usb0_vbus_detect_pin: usb0-vbus-detect-pin {
-               pins = "PG1";
-               function = "gpio_in";
-               bias-pull-down;
-       };
-
-       usb0_id_detect_pin: usb0-id-detect-pin {
-               pins = "PG2";
-               function = "gpio_in";
-               bias-pull-up;
-       };
-};
-
 &pwm {
        pinctrl-names = "default";
        pinctrl-0 = <&pwm0_pin>;
@@ -195,10 +181,8 @@
 };
 
 &usbphy {
-       pinctrl-names = "default";
-       pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>;
-       usb0_id_det-gpio = <&pio 6 2 GPIO_ACTIVE_HIGH>; /* PG2 */
-       usb0_vbus_det-gpio = <&pio 6 1 GPIO_ACTIVE_HIGH>; /* PG1 */
+       usb0_id_det-gpios = <&pio 6 2 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PG2 */
+       usb0_vbus_det-gpios = <&pio 6 1 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* PG1 */
        usb0_vbus-supply = <&reg_usb0_vbus>;
        usb1_vbus-supply = <&reg_ldo3>;
        status = "okay";

diff --git a/arch/arm/boot/dts/sun5i-a13-hsg-h702.dts b/arch/arm/boot/dts/sun5i-a13-hsg-h702.dts
index 9369f74..9b9f2a5 100644 (file)
--- a/arch/arm/boot/dts/sun5i-a13-hsg-h702.dts
+++ b/arch/arm/boot/dts/sun5i-a13-hsg-h702.dts
@@ -124,14 +124,6 @@
        status = "okay";
 };
 
-&pio {
-       usb0_id_detect_pin: usb0-id-detect-pin {
-               pins = "PG2";
-               function = "gpio_in";
-               bias-pull-up;
-       };
-};
-
 #include "axp209.dtsi"
 
 &reg_dcdc2 {
@@ -182,9 +174,7 @@
 };
 
 &usbphy {
-       pinctrl-names = "default";
-       pinctrl-0 = <&usb0_id_detect_pin>;
-       usb0_id_det-gpios = <&pio 6 2 GPIO_ACTIVE_HIGH>; /* PG2 */
+       usb0_id_det-gpios = <&pio 6 2 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PG2 */
        usb0_vbus_det-gpios = <&pio 6 1 GPIO_ACTIVE_HIGH>; /* PG1 */
        usb0_vbus-supply = <&reg_usb0_vbus>;
        usb1_vbus-supply = <&reg_ldo3>;

diff --git a/arch/arm/boot/dts/sun5i-a13-licheepi-one.dts b/arch/arm/boot/dts/sun5i-a13-licheepi-one.dts
index ca8f3fd..ba8d75b 100644 (file)
--- a/arch/arm/boot/dts/sun5i-a13-licheepi-one.dts
+++ b/arch/arm/boot/dts/sun5i-a13-licheepi-one.dts
@@ -206,9 +206,8 @@
 };
 
 &usbphy {
-       pinctrl-names = "default";
-       usb0_id_det-gpio = <&pio 6 2 GPIO_ACTIVE_HIGH>; /* PG2 */
-       usb0_vbus_det-gpio = <&pio 6 1 GPIO_ACTIVE_HIGH>; /* PG1 */
+       usb0_id_det-gpios = <&pio 6 2 GPIO_ACTIVE_HIGH>; /* PG2 */
+       usb0_vbus_det-gpios = <&pio 6 1 GPIO_ACTIVE_HIGH>; /* PG1 */
        usb0_vbus-supply = <&reg_usb0_vbus>;
        usb1_vbus-supply = <&reg_vcc5v0>;
        status = "okay";

diff --git a/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts b/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts
index 943868e..5df398d 100644 (file)
--- a/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts
+++ b/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts
@@ -109,18 +109,6 @@
                function = "gpio_out";
                drive-strength = <20>;
        };
-
-       usb0_id_detect_pin: usb0-id-detect-pin {
-               pins = "PG2";
-               function = "gpio_in";
-               bias-pull-up;
-       };
-
-       usb0_vbus_detect_pin: usb0-vbus-detect-pin {
-               pins = "PG1";
-               function = "gpio_in";
-               bias-pull-down;
-       };
 };
 
 &reg_usb0_vbus {
@@ -145,10 +133,8 @@
 };
 
 &usbphy {
-       pinctrl-names = "default";
-       pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>;
-       usb0_id_det-gpio = <&pio 6 2 GPIO_ACTIVE_HIGH>; /* PG2 */
-       usb0_vbus_det-gpio = <&pio 6 1 GPIO_ACTIVE_HIGH>; /* PG1 */
+       usb0_id_det-gpios = <&pio 6 2 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PG2 */
+       usb0_vbus_det-gpios = <&pio 6 1 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* PG1 */
        usb0_vbus-supply = <&reg_usb0_vbus>;
        usb1_vbus-supply = <&reg_usb1_vbus>;
        status = "okay";

diff --git a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts
index 9409c23..3910122 100644 (file)
--- a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts
+++ b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts
@@ -74,8 +74,6 @@
 
        bridge {
                compatible = "dumb-vga-dac";
-               #address-cells = <1>;
-               #size-cells = <0>;
 
                ports {
                        #address-cells = <1>;
@@ -204,18 +202,6 @@
                function = "gpio_out";
                drive-strength = <20>;
        };
-
-       usb0_id_detect_pin: usb0-id-detect-pin {
-               pins = "PG2";
-               function = "gpio_in";
-               bias-pull-up;
-       };
-
-       usb0_vbus_detect_pin: usb0-vbus-detect-pin {
-               pins = "PG1";
-               function = "gpio_in";
-               bias-pull-down;
-       };
 };
 
 &reg_usb0_vbus {
@@ -253,10 +239,8 @@
 };
 
 &usbphy {
-       pinctrl-names = "default";
-       pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>;
-       usb0_id_det-gpio = <&pio 6 2 GPIO_ACTIVE_HIGH>; /* PG2 */
-       usb0_vbus_det-gpio = <&pio 6 1 GPIO_ACTIVE_HIGH>; /* PG1 */
+       usb0_id_det-gpios = <&pio 6 2 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PG2 */
+       usb0_vbus_det-gpios = <&pio 6 1 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* PG1 */
        usb0_vbus-supply = <&reg_usb0_vbus>;
        usb1_vbus-supply = <&reg_usb1_vbus>;
        status = "okay";

diff --git a/arch/arm/boot/dts/sun5i-a13-q8-tablet.dts b/arch/arm/boot/dts/sun5i-a13-q8-tablet.dts
index 7257f39..fde559a 100644 (file)
--- a/arch/arm/boot/dts/sun5i-a13-q8-tablet.dts
+++ b/arch/arm/boot/dts/sun5i-a13-q8-tablet.dts
@@ -53,16 +53,9 @@
                power-supply = <&reg_vcc3v3>;
                enable-gpios = <&axp_gpio 0 GPIO_ACTIVE_HIGH>; /* AXP GPIO0 */
                backlight = <&backlight>;
-               #address-cells = <1>;
-               #size-cells = <0>;
 
-               port@0 {
-                       reg = <0>;
-                       #address-cells = <1>;
-                       #size-cells = <0>;
-
-                       panel_input: endpoint@0 {
-                               reg = <0>;
+               port {
+                       panel_input: endpoint {
                                remote-endpoint = <&tcon0_out_lcd>;
                        };
                };

diff --git a/arch/arm/boot/dts/sun5i-a13-utoo-p66.dts b/arch/arm/boot/dts/sun5i-a13-utoo-p66.dts
index 732873c..be486d2 100644 (file)
--- a/arch/arm/boot/dts/sun5i-a13-utoo-p66.dts
+++ b/arch/arm/boot/dts/sun5i-a13-utoo-p66.dts
@@ -58,13 +58,11 @@
                /delete-property/stdout-path;
        };
 
-       i2c_lcd: i2c-gpio {
+       i2c_lcd: i2c {
                /* The lcd panel i2c interface is hooked up via gpios */
                compatible = "i2c-gpio";
-               pinctrl-names = "default";
-               pinctrl-0 = <&i2c_lcd_pins>;
-               gpios = <&pio 6 12 GPIO_ACTIVE_HIGH>, /* PG12, sda */
-                       <&pio 6 10 GPIO_ACTIVE_HIGH>; /* PG10, scl */
+               sda-gpios = <&pio 6 12 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PG12 */
+               scl-gpios = <&pio 6 10 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PG10 */
                i2c-gpio,delay-us = <5>;
        };
 };
@@ -94,14 +92,6 @@
        };
 };
 
-&pio {
-       i2c_lcd_pins: i2c-lcd-pin {
-               pins = "PG10", "PG12";
-               function = "gpio_out";
-               bias-pull-up;
-       };
-};
-
 &reg_usb0_vbus {
        gpio = <&pio 1 4 GPIO_ACTIVE_HIGH>; /* PB4 */
 };

diff --git a/arch/arm/boot/dts/sun5i-gr8-chip-pro.dts b/arch/arm/boot/dts/sun5i-gr8-chip-pro.dts
index 3f70b8c..a32cde3 100644 (file)
--- a/arch/arm/boot/dts/sun5i-gr8-chip-pro.dts
+++ b/arch/arm/boot/dts/sun5i-gr8-chip-pro.dts
@@ -133,8 +133,6 @@
        status = "okay";
 
        nand@0 {
-               #address-cells = <2>;
-               #size-cells = <2>;
                reg = <0>;
                allwinner,rb = <0>;
                nand-ecc-mode = "hw";
@@ -233,7 +231,7 @@
 };
 
 &usbphy {
-       usb0_id_det-gpio = <&pio 6 2 GPIO_ACTIVE_HIGH>; /* PG2 */
+       usb0_id_det-gpios = <&pio 6 2 GPIO_ACTIVE_HIGH>; /* PG2 */
        usb0_vbus_power-supply = <&usb_power_supply>;
        usb1_vbus-supply = <&reg_vcc5v0>;
        status = "okay";

diff --git a/arch/arm/boot/dts/sun5i-gr8-evb.dts b/arch/arm/boot/dts/sun5i-gr8-evb.dts
index 86e46aa..d003b89 100644 (file)
--- a/arch/arm/boot/dts/sun5i-gr8-evb.dts
+++ b/arch/arm/boot/dts/sun5i-gr8-evb.dts
@@ -325,8 +325,8 @@
 };
 
 &usbphy {
-       usb0_id_det-gpio = <&pio 6 2 GPIO_ACTIVE_HIGH>; /* PG2 */
-       usb0_vbus_det-gpio = <&pio 6 1 GPIO_ACTIVE_HIGH>; /* PG1 */
+       usb0_id_det-gpios = <&pio 6 2 GPIO_ACTIVE_HIGH>; /* PG2 */
+       usb0_vbus_det-gpios = <&pio 6 1 GPIO_ACTIVE_HIGH>; /* PG1 */
        usb0_vbus_power-supply = <&usb_power_supply>;
        usb1_vbus-supply = <&reg_usb1_vbus>;
        status = "okay";

diff --git a/arch/arm/boot/dts/sun5i-r8-chip.dts b/arch/arm/boot/dts/sun5i-r8-chip.dts
index f4298fa..4bf4943 100644 (file)
--- a/arch/arm/boot/dts/sun5i-r8-chip.dts
+++ b/arch/arm/boot/dts/sun5i-r8-chip.dts
@@ -84,9 +84,7 @@
 
        onewire {
                compatible = "w1-gpio";
-               gpios = <&pio 3 2 GPIO_ACTIVE_HIGH>; /* PD2 */
-               pinctrl-names = "default";
-               pinctrl-0 = <&chip_w1_pin>;
+               gpios = <&pio 3 2 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PD2 */
        };
 };
 
@@ -173,14 +171,6 @@
        status = "okay";
 };
 
-&pio {
-       chip_w1_pin: chip-w1-pin {
-               pins = "PD2";
-               function = "gpio_in";
-               bias-pull-up;
-       };
-};
-
 &reg_dcdc2 {
        regulator-min-microvolt = <1000000>;
        regulator-max-microvolt = <1400000>;
@@ -279,7 +269,7 @@
 &usbphy {
        status = "okay";
 
-       usb0_id_det-gpio = <&pio 6 2 GPIO_ACTIVE_HIGH>; /* PG2 */
+       usb0_id_det-gpios = <&pio 6 2 GPIO_ACTIVE_HIGH>; /* PG2 */
        usb0_vbus_power-supply = <&usb_power_supply>;
        usb0_vbus-supply = <&reg_usb0_vbus>;
        usb1_vbus-supply = <&reg_vcc5v0>;

diff --git a/arch/arm/boot/dts/sun5i-reference-design-tablet.dtsi b/arch/arm/boot/dts/sun5i-reference-design-tablet.dtsi
index 5b1f0e1..1a9926d 100644 (file)
--- a/arch/arm/boot/dts/sun5i-reference-design-tablet.dtsi
+++ b/arch/arm/boot/dts/sun5i-reference-design-tablet.dtsi
@@ -132,20 +132,6 @@
        status = "okay";
 };
 
-&pio {
-       usb0_vbus_detect_pin: usb0-vbus-detect-pin {
-               pins = "PG1";
-               function = "gpio_in";
-               bias-pull-down;
-       };
-
-       usb0_id_detect_pin: usb0-id-detect-pin {
-               pins = "PG2";
-               function = "gpio_in";
-               bias-pull-up;
-       };
-};
-
 &reg_dcdc2 {
        regulator-always-on;
        regulator-min-microvolt = <1000000>;
@@ -198,10 +184,8 @@
 };
 
 &usbphy {
-       pinctrl-names = "default";
-       pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>;
-       usb0_id_det-gpio = <&pio 6 2 GPIO_ACTIVE_HIGH>; /* PG2 */
-       usb0_vbus_det-gpio = <&pio 6 1 GPIO_ACTIVE_HIGH>; /* PG1 */
+       usb0_id_det-gpios = <&pio 6 2 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PG2 */
+       usb0_vbus_det-gpios = <&pio 6 1 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* PG1 */
        usb0_vbus_power-supply = <&usb_power_supply>;
        usb0_vbus-supply = <&reg_usb0_vbus>;
        usb1_vbus-supply = <&reg_ldo3>;

diff --git a/arch/arm/boot/dts/sun5i.dtsi b/arch/arm/boot/dts/sun5i.dtsi
index 5497d98..2fb438c 100644 (file)
--- a/arch/arm/boot/dts/sun5i.dtsi
+++ b/arch/arm/boot/dts/sun5i.dtsi
@@ -127,6 +127,7 @@
                compatible = "simple-bus";
                #address-cells = <1>;
                #size-cells = <1>;
+               dma-ranges;
                ranges;
 
                system-control@1c00000 {
@@ -181,6 +182,14 @@
                        };
                };
 
+               mbus: dram-controller@1c01000 {
+                       compatible = "allwinner,sun5i-a13-mbus";
+                       reg = <0x01c01000 0x1000>;
+                       clocks = <&ccu 99>;
+                       dma-ranges = <0x00000000 0x40000000 0x20000000>;
+                       #interconnect-cells = <1>;
+               };
+
                dma: dma-controller@1c02000 {
                        compatible = "allwinner,sun4i-a10-dma";
                        reg = <0x01c02000 0x1000>;
@@ -189,7 +198,7 @@
                        #dma-cells = <2>;
                };
 
-               nfc: nand@1c03000 {
+               nfc: nand-controller@1c03000 {
                        compatible = "allwinner,sun4i-a10-nand";
                        reg = <0x01c03000 0x1000>;
                        interrupts = <37>;
@@ -238,11 +247,8 @@
                        status = "disabled";
 
                        port {
-                               #address-cells = <1>;
-                               #size-cells = <0>;
 
-                               tve0_in_tcon0: endpoint@0 {
-                                       reg = <0>;
+                               tve0_in_tcon0: endpoint {
                                        remote-endpoint = <&tcon0_out_tve0>;
                                };
                        };
@@ -278,6 +284,7 @@
                                      "tcon-ch0",
                                      "tcon-ch1";
                        clock-output-names = "tcon-pixel-clock";
+                       #clock-cells = <0>;
                        status = "disabled";
 
                        ports {
@@ -285,12 +292,9 @@
                                #size-cells = <0>;
 
                                tcon0_in: port@0 {
-                                       #address-cells = <1>;
-                                       #size-cells = <0>;
                                        reg = <0>;
 
-                                       tcon0_in_be0: endpoint@0 {
-                                               reg = <0>;
+                                       tcon0_in_be0: endpoint {
                                                remote-endpoint = <&be0_out_tcon0>;
                                        };
                                };
@@ -365,13 +369,14 @@
                        phy-names = "usb";
                        extcon = <&usbphy 0>;
                        allwinner,sram = <&otg_sram 1>;
+                       dr_mode = "otg";
                        status = "disabled";
                };
 
                usbphy: phy@1c13400 {
                        #phy-cells = <1>;
                        compatible = "allwinner,sun5i-a13-usb-phy";
-                       reg = <0x01c13400 0x10 0x01c14800 0x4>;
+                       reg = <0x01c13400 0x10>, <0x01c14800 0x4>;
                        reg-names = "phy_ctrl", "pmu1";
                        clocks = <&ccu CLK_USB_PHY0>;
                        clock-names = "usb_phy";
@@ -386,7 +391,6 @@
                        interrupts = <39>;
                        clocks = <&ccu CLK_AHB_EHCI>;
                        phys = <&usbphy 1>;
-                       phy-names = "usb";
                        status = "disabled";
                };
 
@@ -396,7 +400,6 @@
                        interrupts = <40>;
                        clocks = <&ccu CLK_USB_OHCI>, <&ccu CLK_AHB_OHCI>;
                        phys = <&usbphy 1>;
-                       phy-names = "usb";
                        status = "disabled";
                };
 
@@ -501,18 +504,18 @@
                                bias-pull-up;
                        };
 
-                       mmc2_8bit_pins: mmc2-8bit-pins {
+                       mmc2_4bit_pc_pins: mmc2-4bit-pc-pins {
                                pins = "PC6", "PC7", "PC8", "PC9",
-                                      "PC10", "PC11", "PC12", "PC13",
-                                      "PC14", "PC15";
+                                      "PC10", "PC11";
                                function = "mmc2";
                                drive-strength = <30>;
                                bias-pull-up;
                        };
 
-                       mmc2_4bit_pc_pins: mmc2-4bit-pc-pins {
+                       mmc2_8bit_pins: mmc2-8bit-pins {
                                pins = "PC6", "PC7", "PC8", "PC9",
-                                      "PC10", "PC11";
+                                      "PC10", "PC11", "PC12", "PC13",
+                                      "PC14", "PC15";
                                function = "mmc2";
                                drive-strength = <30>;
                                bias-pull-up;
@@ -536,6 +539,11 @@
                                function = "nand0";
                        };
 
+                       pwm0_pin: pwm0-pin {
+                               pins = "PB2";
+                               function = "pwm";
+                       };
+
                        spi2_pe_pins: spi2-pe-pins {
                                pins = "PE1", "PE2", "PE3";
                                function = "spi2";
@@ -575,11 +583,6 @@
                                pins = "PG11", "PG12";
                                function = "uart3";
                        };
-
-                       pwm0_pin: pwm0-pin {
-                               pins = "PB2";
-                               function = "pwm";
-                       };
                };
 
                timer@1c20c00 {
@@ -727,6 +730,8 @@
                        clock-names = "ahb", "mod",
                                      "ram";
                        resets = <&ccu RST_DE_FE>;
+                       interconnects = <&mbus 19>;
+                       interconnect-names = "dma-mem";
                        status = "disabled";
 
                        ports {
@@ -734,12 +739,9 @@
                                #size-cells = <0>;
 
                                fe0_out: port@1 {
-                                       #address-cells = <1>;
-                                       #size-cells = <0>;
                                        reg = <1>;
 
-                                       fe0_out_be0: endpoint@0 {
-                                               reg = <0>;
+                                       fe0_out_be0: endpoint {
                                                remote-endpoint = <&be0_in_fe0>;
                                        };
                                };
@@ -755,6 +757,8 @@
                        clock-names = "ahb", "mod",
                                      "ram";
                        resets = <&ccu RST_DE_BE>;
+                       interconnects = <&mbus 18>;
+                       interconnect-names = "dma-mem";
                        status = "disabled";
 
                        assigned-clocks = <&ccu CLK_DE_BE>;
@@ -765,23 +769,17 @@
                                #size-cells = <0>;
 
                                be0_in: port@0 {
-                                       #address-cells = <1>;
-                                       #size-cells = <0>;
                                        reg = <0>;
 
-                                       be0_in_fe0: endpoint@0 {
-                                               reg = <0>;
+                                       be0_in_fe0: endpoint {
                                                remote-endpoint = <&fe0_out_be0>;
                                        };
                                };
 
                                be0_out: port@1 {
-                                       #address-cells = <1>;
-                                       #size-cells = <0>;
                                        reg = <1>;
 
-                                       be0_out_tcon0: endpoint@0 {
-                                               reg = <0>;
+                                       be0_out_tcon0: endpoint {
                                                remote-endpoint = <&tcon0_in_be0>;
                                        };
                                };

diff --git a/arch/arm/boot/dts/sun6i-a31-colombus.dts b/arch/arm/boot/dts/sun6i-a31-colombus.dts
index 0b7bedf..c3d56dc 100644 (file)
--- a/arch/arm/boot/dts/sun6i-a31-colombus.dts
+++ b/arch/arm/boot/dts/sun6i-a31-colombus.dts
@@ -63,10 +63,8 @@
        i2c_lcd: i2c {
                /* The lcd panel i2c interface is hooked up via gpios */
                compatible = "i2c-gpio";
-               pinctrl-names = "default";
-               pinctrl-0 = <&i2c_lcd_pins>;
-               gpios = <&pio 0 23 GPIO_ACTIVE_HIGH>, /* PA23, sda */
-                       <&pio 0 24 GPIO_ACTIVE_HIGH>; /* PA24, scl */
+               sda-gpios = <&pio 0 23 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PA23 */
+               scl-gpios = <&pio 0 24 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PA24 */
                i2c-gpio,delay-us = <5>;
        };
 };
@@ -113,14 +111,6 @@
        status = "okay";
 };
 
-&pio {
-       i2c_lcd_pins: i2c-lcd-pins {
-               pins = "PA23", "PA24";
-               function = "gpio_out";
-               bias-pull-up;
-       };
-};
-
 &reg_usb2_vbus {
        gpio = <&pio 7 24 GPIO_ACTIVE_HIGH>;
        status = "okay";

diff --git a/arch/arm/boot/dts/sun6i-a31-hummingbird.dts b/arch/arm/boot/dts/sun6i-a31-hummingbird.dts
index e17a65b..09832b4 100644 (file)
--- a/arch/arm/boot/dts/sun6i-a31-hummingbird.dts
+++ b/arch/arm/boot/dts/sun6i-a31-hummingbird.dts
@@ -86,31 +86,23 @@
        vga-dac {
                compatible = "dumb-vga-dac";
                vdd-supply = <&reg_vga_3v3>;
-               #address-cells = <1>;
-               #size-cells = <0>;
 
                ports {
                        #address-cells = <1>;
                        #size-cells = <0>;
 
                        port@0 {
-                               #address-cells = <1>;
-                               #size-cells = <0>;
                                reg = <0>;
 
-                               vga_dac_in: endpoint@0 {
-                                       reg = <0>;
+                               vga_dac_in: endpoint {
                                        remote-endpoint = <&tcon0_out_vga>;
                                };
                        };
 
                        port@1 {
-                               #address-cells = <1>;
-                               #size-cells = <0>;
                                reg = <1>;
 
-                               vga_dac_out: endpoint@0 {
-                                       reg = <0>;
+                               vga_dac_out: endpoint {
                                        remote-endpoint = <&vga_con_in>;
                                };
                        };
@@ -335,8 +327,8 @@
 };
 
 &usbphy {
-       usb0_id_det-gpio = <&pio 0 15 GPIO_ACTIVE_HIGH>; /* PA15 */
-       usb0_vbus_det-gpio = <&pio 0 16 GPIO_ACTIVE_HIGH>; /* PA16 */
+       usb0_id_det-gpios = <&pio 0 15 GPIO_ACTIVE_HIGH>; /* PA15 */
+       usb0_vbus_det-gpios = <&pio 0 16 GPIO_ACTIVE_HIGH>; /* PA16 */
        usb0_vbus_power-supply = <&usb_power_supply>;
        usb0_vbus-supply = <&reg_drivevbus>;
        usb1_vbus-supply = <&reg_usb1_vbus>;

diff --git a/arch/arm/boot/dts/sun6i-a31-i7.dts b/arch/arm/boot/dts/sun6i-a31-i7.dts
index 0832ac5..091eb2a 100644 (file)
--- a/arch/arm/boot/dts/sun6i-a31-i7.dts
+++ b/arch/arm/boot/dts/sun6i-a31-i7.dts
@@ -157,7 +157,6 @@
 &spdif {
        pinctrl-names = "default";
        pinctrl-0 = <&spdif_tx_pin>;
-       spdif-out = "okay";
        status = "okay";
 };
 

diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
index 13304b8..c04efad 100644 (file)
--- a/arch/arm/boot/dts/sun6i-a31.dtsi
+++ b/arch/arm/boot/dts/sun6i-a31.dtsi
@@ -292,6 +292,7 @@
                                      "tcon-ch0",
                                      "tcon-ch1";
                        clock-output-names = "tcon0-pixel-clock";
+                       #clock-cells = <0>;
 
                        ports {
                                #address-cells = <1>;
@@ -340,6 +341,7 @@
                                      "tcon-ch0",
                                      "tcon-ch1";
                        clock-output-names = "tcon1-pixel-clock";
+                       #clock-cells = <0>;
 
                        ports {
                                #address-cells = <1>;
@@ -491,8 +493,6 @@
                                };
 
                                hdmi_out: port@1 {
-                                       #address-cells = <1>;
-                                       #size-cells = <0>;
                                        reg = <1>;
                                };
                        };
@@ -508,6 +508,7 @@
                        phys = <&usbphy 0>;
                        phy-names = "usb";
                        extcon = <&usbphy 0>;
+                       dr_mode = "otg";
                        status = "disabled";
                };
 
@@ -542,7 +543,6 @@
                        clocks = <&ccu CLK_AHB1_EHCI0>;
                        resets = <&ccu RST_AHB1_EHCI0>;
                        phys = <&usbphy 1>;
-                       phy-names = "usb";
                        status = "disabled";
                };
 
@@ -553,7 +553,6 @@
                        clocks = <&ccu CLK_AHB1_OHCI0>, <&ccu CLK_USB_OHCI0>;
                        resets = <&ccu RST_AHB1_OHCI0>;
                        phys = <&usbphy 1>;
-                       phy-names = "usb";
                        status = "disabled";
                };
 
@@ -564,7 +563,6 @@
                        clocks = <&ccu CLK_AHB1_EHCI1>;
                        resets = <&ccu RST_AHB1_EHCI1>;
                        phys = <&usbphy 2>;
-                       phy-names = "usb";
                        status = "disabled";
                };
 
@@ -575,7 +573,6 @@
                        clocks = <&ccu CLK_AHB1_OHCI1>, <&ccu CLK_USB_OHCI1>;
                        resets = <&ccu RST_AHB1_OHCI1>;
                        phys = <&usbphy 2>;
-                       phy-names = "usb";
                        status = "disabled";
                };
 
@@ -1029,7 +1026,7 @@
                };
 
                gic: interrupt-controller@1c81000 {
-                       compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
+                       compatible = "arm,gic-400";
                        reg = <0x01c81000 0x1000>,
                              <0x01c82000 0x2000>,
                              <0x01c84000 0x2000>,
@@ -1229,12 +1226,9 @@
                                };
 
                                be0_out: port@1 {
-                                       #address-cells = <1>;
-                                       #size-cells = <0>;
                                        reg = <1>;
 
-                                       be0_out_drc0: endpoint@0 {
-                                               reg = <0>;
+                                       be0_out_drc0: endpoint {
                                                remote-endpoint = <&drc0_in_be0>;
                                        };
                                };
@@ -1259,12 +1253,9 @@
                                #size-cells = <0>;
 
                                drc0_in: port@0 {
-                                       #address-cells = <1>;
-                                       #size-cells = <0>;
                                        reg = <0>;
 
-                                       drc0_in_be0: endpoint@0 {
-                                               reg = <0>;
+                                       drc0_in_be0: endpoint {
                                                remote-endpoint = <&be0_out_drc0>;
                                        };
                                };
@@ -1380,7 +1371,6 @@
                        gpio-controller;
                        interrupt-controller;
                        #interrupt-cells = <3>;
-                       #size-cells = <0>;
                        #gpio-cells = <3>;
 
                        s_ir_rx_pin: s-ir-rx-pin {

diff --git a/arch/arm/boot/dts/sun6i-a31s-primo81.dts b/arch/arm/boot/dts/sun6i-a31s-primo81.dts
index 60b355f..bc3170a 100644 (file)
--- a/arch/arm/boot/dts/sun6i-a31s-primo81.dts
+++ b/arch/arm/boot/dts/sun6i-a31s-primo81.dts
@@ -260,7 +260,7 @@
 };
 
 &usbphy {
-       usb0_id_det-gpio = <&pio 0 15 GPIO_ACTIVE_HIGH>; /* PA15 */
+       usb0_id_det-gpios = <&pio 0 15 GPIO_ACTIVE_HIGH>; /* PA15 */
        usb0_vbus_power-supply = <&usb_power_supply>;
        usb0_vbus-supply = <&reg_drivevbus>;
        usb1_vbus-supply = <&reg_dldo1>;

diff --git a/arch/arm/boot/dts/sun6i-reference-design-tablet.dtsi b/arch/arm/boot/dts/sun6i-reference-design-tablet.dtsi
index 86143de..7de2abd 100644 (file)
--- a/arch/arm/boot/dts/sun6i-reference-design-tablet.dtsi
+++ b/arch/arm/boot/dts/sun6i-reference-design-tablet.dtsi
@@ -73,14 +73,6 @@
        status = "okay";
 };
 
-&pio {
-       usb0_id_detect_pin: usb0-id-detect-pin {
-               pins = "PA15";
-               function = "gpio_in";
-               bias-pull-up;
-       };
-};
-
 &p2wi {
        status = "okay";
 
@@ -173,9 +165,7 @@
 };
 
 &usbphy {
-       pinctrl-names = "default";
-       pinctrl-0 = <&usb0_id_detect_pin>;
-       usb0_id_det-gpio = <&pio 0 15 GPIO_ACTIVE_HIGH>; /* PA15 */
+       usb0_id_det-gpios = <&pio 0 15 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PA15 */
        usb0_vbus_power-supply = <&usb_power_supply>;
        usb0_vbus-supply = <&reg_drivevbus>;
        usb1_vbus-supply = <&reg_dldo1>;

diff --git a/arch/arm/boot/dts/sun7i-a20-bananapi.dts b/arch/arm/boot/dts/sun7i-a20-bananapi.dts
index 81bc85d..4df9216 100644 (file)
--- a/arch/arm/boot/dts/sun7i-a20-bananapi.dts
+++ b/arch/arm/boot/dts/sun7i-a20-bananapi.dts
@@ -246,12 +246,6 @@
                        "SPI-MISO", "SPI-CE1", "",
                "IO-6", "IO-3", "IO-2", "IO-0", "", "", "", "",
                "", "", "", "", "", "", "", "";
-
-       usb0_id_detect_pin: usb0-id-detect-pin {
-               pins = "PH4";
-               function = "gpio_in";
-               bias-pull-up;
-       };
 };
 
 #include "axp209.dtsi"
@@ -329,9 +323,7 @@
 };
 
 &usbphy {
-       pinctrl-names = "default";
-       pinctrl-0 = <&usb0_id_detect_pin>;
-       usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
+       usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */
        usb0_vbus_power-supply = <&usb_power_supply>;
        usb0_vbus-supply = <&reg_usb0_vbus>;
        usb1_vbus-supply = <&reg_usb1_vbus>;

diff --git a/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts b/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts
index 200685b..08e5a5a 100644 (file)
--- a/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts
+++ b/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts
@@ -173,14 +173,6 @@
        status = "okay";
 };
 
-&pio {
-       usb0_id_detect_pin: usb0-id-detect-pin {
-               pins = "PH4";
-               function = "gpio_in";
-               bias-pull-up;
-       };
-};
-
 &reg_ahci_5v {
        status = "okay";
 };
@@ -236,9 +228,7 @@
 };
 
 &usbphy {
-       pinctrl-names = "default";
-       pinctrl-0 = <&usb0_id_detect_pin>;
-       usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
+       usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */
        usb1_vbus-supply = <&reg_usb1_vbus>;
        usb2_vbus-supply = <&reg_usb2_vbus>;
        status = "okay";

diff --git a/arch/arm/boot/dts/sun7i-a20-lamobo-r1.dts b/arch/arm/boot/dts/sun7i-a20-lamobo-r1.dts
index f91e1be..3e170cf 100644 (file)
--- a/arch/arm/boot/dts/sun7i-a20-lamobo-r1.dts
+++ b/arch/arm/boot/dts/sun7i-a20-lamobo-r1.dts
@@ -229,14 +229,6 @@
        status = "okay";
 };
 
-&pio {
-       usb0_id_detect_pin: usb0-id-detect-pin {
-               pins = "PH4";
-               function = "gpio_in";
-               bias-pull-up;
-       };
-};
-
 #include "axp209.dtsi"
 
 &ac_power_supply {
@@ -322,9 +314,7 @@
 };
 
 &usbphy {
-       pinctrl-names = "default";
-       pinctrl-0 = <&usb0_id_detect_pin>;
-       usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
+       usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */
        usb0_vbus_power-supply = <&usb_power_supply>;
        usb0_vbus-supply = <&reg_usb0_vbus>;
        usb2_vbus-supply = <&reg_usb2_vbus>;

diff --git a/arch/arm/boot/dts/sun7i-a20-olimex-som204-evb.dts b/arch/arm/boot/dts/sun7i-a20-olimex-som204-evb.dts
index 823aabc..c34a83f 100644 (file)
--- a/arch/arm/boot/dts/sun7i-a20-olimex-som204-evb.dts
+++ b/arch/arm/boot/dts/sun7i-a20-olimex-som204-evb.dts
@@ -314,8 +314,8 @@
 };
 
 &usbphy {
-       usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
-       usb0_vbus_det-gpio = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */
+       usb0_id_det-gpios = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
+       usb0_vbus_det-gpios = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */
        usb0_vbus_power-supply = <&usb_power_supply>;
        usb0_vbus-supply = <&reg_usb0_vbus>;
        usb1_vbus-supply = <&reg_usb1_vbus>;

diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-lime.dts b/arch/arm/boot/dts/sun7i-a20-olinuxino-lime.dts
index 5e41119..e40dd47 100644 (file)
--- a/arch/arm/boot/dts/sun7i-a20-olinuxino-lime.dts
+++ b/arch/arm/boot/dts/sun7i-a20-olinuxino-lime.dts
@@ -174,18 +174,6 @@
                function = "gpio_out";
                drive-strength = <20>;
        };
-
-       usb0_id_detect_pin: usb0-id-detect-pin {
-               pins = "PH4";
-               function = "gpio_in";
-               bias-pull-up;
-       };
-
-       usb0_vbus_detect_pin: usb0-vbus-detect-pin {
-               pins = "PH5";
-               function = "gpio_in";
-               bias-pull-down;
-       };
 };
 
 &reg_ahci_5v {
@@ -217,10 +205,8 @@
 };
 
 &usbphy {
-       pinctrl-names = "default";
-       pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>;
-       usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
-       usb0_vbus_det-gpio = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */
+       usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */
+       usb0_vbus_det-gpios = <&pio 7 5 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* PH5 */
        usb0_vbus-supply = <&reg_usb0_vbus>;
        usb1_vbus-supply = <&reg_usb1_vbus>;
        usb2_vbus-supply = <&reg_usb2_vbus>;

diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-lime2.dts b/arch/arm/boot/dts/sun7i-a20-olinuxino-lime2.dts
index 4e1c590..95c6f89 100644 (file)
--- a/arch/arm/boot/dts/sun7i-a20-olinuxino-lime2.dts
+++ b/arch/arm/boot/dts/sun7i-a20-olinuxino-lime2.dts
@@ -174,23 +174,17 @@
 };
 
 &pio {
+       vcc-pa-supply = <&reg_vcc3v3>;
+       vcc-pc-supply = <&reg_vcc3v3>;
+       vcc-pe-supply = <&reg_ldo3>;
+       vcc-pf-supply = <&reg_vcc3v3>;
+       vcc-pg-supply = <&reg_ldo4>;
+
        led_pins_olinuxinolime: led-pins {
                pins = "PH2";
                function = "gpio_out";
                drive-strength = <20>;
        };
-
-       usb0_id_detect_pin: usb0-id-detect-pin {
-               pins = "PH4";
-               function = "gpio_in";
-               bias-pull-up;
-       };
-
-       usb0_vbus_detect_pin: usb0-vbus-detect-pin {
-               pins = "PH5";
-               function = "gpio_in";
-               bias-pull-down;
-       };
 };
 
 &reg_ahci_5v {
@@ -267,10 +261,8 @@
 };
 
 &usbphy {
-       pinctrl-names = "default";
-       pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>;
-       usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
-       usb0_vbus_det-gpio = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */
+       usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */
+       usb0_vbus_det-gpios = <&pio 7 5 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* PH5 */
        usb0_vbus-supply = <&reg_usb0_vbus>;
        usb1_vbus-supply = <&reg_usb1_vbus>;
        usb2_vbus-supply = <&reg_usb2_vbus>;

diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts
index 840ae11..0dcba07 100644 (file)
--- a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts
+++ b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts
@@ -252,18 +252,6 @@
                function = "gpio_out";
                drive-strength = <20>;
        };
-
-       usb0_id_detect_pin: usb0-id-detect-pin {
-               pins = "PH4";
-               function = "gpio_in";
-               bias-pull-up;
-       };
-
-       usb0_vbus_detect_pin: usb0-vbus-detect-pin {
-               pins = "PH5";
-               function = "gpio_in";
-               bias-pull-down;
-       };
 };
 
 #include "axp209.dtsi"
@@ -355,10 +343,8 @@
 };
 
 &usbphy {
-       pinctrl-names = "default";
-       pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>;
-       usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
-       usb0_vbus_det-gpio = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */
+       usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */
+       usb0_vbus_det-gpios = <&pio 7 5 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* PH5 */
        usb0_vbus-supply = <&reg_usb0_vbus>;
        usb1_vbus-supply = <&reg_usb1_vbus>;
        usb2_vbus-supply = <&reg_usb2_vbus>;

diff --git a/arch/arm/boot/dts/sun7i-a20-orangepi-mini.dts b/arch/arm/boot/dts/sun7i-a20-orangepi-mini.dts
index 1588108..9628041 100644 (file)
--- a/arch/arm/boot/dts/sun7i-a20-orangepi-mini.dts
+++ b/arch/arm/boot/dts/sun7i-a20-orangepi-mini.dts
@@ -176,14 +176,6 @@
        status = "okay";
 };
 
-&pio {
-       usb0_id_detect_pin: usb0-id-detect-pin {
-               pins = "PH4";
-               function = "gpio_in";
-               bias-pull-up;
-       };
-};
-
 &reg_dcdc2 {
        regulator-always-on;
        regulator-min-microvolt = <1000000>;
@@ -239,9 +231,7 @@
 };
 
 &usbphy {
-       pinctrl-names = "default";
-       pinctrl-0 = <&usb0_id_detect_pin>;
-       usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
+       usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */
        usb0_vbus_power-supply = <&usb_power_supply>;
        usb0_vbus-supply = <&reg_usb0_vbus>;
        usb1_vbus-supply = <&reg_usb1_vbus>;

diff --git a/arch/arm/boot/dts/sun7i-a20-orangepi.dts b/arch/arm/boot/dts/sun7i-a20-orangepi.dts
index d64de2e..7b35326 100644 (file)
--- a/arch/arm/boot/dts/sun7i-a20-orangepi.dts
+++ b/arch/arm/boot/dts/sun7i-a20-orangepi.dts
@@ -135,14 +135,6 @@
        status = "okay";
 };
 
-&pio {
-       usb0_id_detect_pin: usb0-id-detect-pin {
-               pins = "PH4";
-               function = "gpio_in";
-               bias-pull-up;
-       };
-};
-
 &reg_dcdc2 {
        regulator-always-on;
        regulator-min-microvolt = <1000000>;
@@ -198,9 +190,7 @@
 };
 
 &usbphy {
-       pinctrl-names = "default";
-       pinctrl-0 = <&usb0_id_detect_pin>;
-       usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
+       usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */
        usb0_vbus_power-supply = <&usb_power_supply>;
        usb0_vbus-supply = <&reg_usb0_vbus>;
        usb1_vbus-supply = <&reg_usb1_vbus>;

diff --git a/arch/arm/boot/dts/sun7i-a20-pcduino3-nano.dts b/arch/arm/boot/dts/sun7i-a20-pcduino3-nano.dts
index 538ea15..173b676 100644 (file)
--- a/arch/arm/boot/dts/sun7i-a20-pcduino3-nano.dts
+++ b/arch/arm/boot/dts/sun7i-a20-pcduino3-nano.dts
@@ -168,14 +168,6 @@
        status = "okay";
 };
 
-&pio {
-       usb0_id_detect_pin: usb0-id-detect-pin {
-               pins = "PH4";
-               function = "gpio_in";
-               bias-pull-up;
-       };
-};
-
 &reg_ahci_5v {
        gpio = <&pio 7 2 GPIO_ACTIVE_HIGH>; /* PH2 */
        status = "okay";
@@ -226,9 +218,7 @@
 };
 
 &usbphy {
-       pinctrl-names = "default";
-       pinctrl-0 = <&usb0_id_detect_pin>;
-       usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
+       usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */
        usb1_vbus-supply = <&reg_usb1_vbus>;
        usb2_vbus-supply = <&reg_usb1_vbus>;
        status = "okay";

diff --git a/arch/arm/boot/dts/sun7i-a20-pcduino3.dts b/arch/arm/boot/dts/sun7i-a20-pcduino3.dts
index a72ed43..14a88aa 100644 (file)
--- a/arch/arm/boot/dts/sun7i-a20-pcduino3.dts
+++ b/arch/arm/boot/dts/sun7i-a20-pcduino3.dts
@@ -168,14 +168,6 @@
        status = "okay";
 };
 
-&pio {
-       usb0_id_detect_pin: usb0-id-detect-pin {
-               pins = "PH4";
-               function = "gpio_in";
-               bias-pull-up;
-       };
-};
-
 &reg_ahci_5v {
        gpio = <&pio 7 2 GPIO_ACTIVE_HIGH>;
        status = "okay";
@@ -226,9 +218,7 @@
 };
 
 &usbphy {
-       pinctrl-names = "default";
-       pinctrl-0 = <&usb0_id_detect_pin>;
-       usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
+       usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */
        usb1_vbus-supply = <&reg_usb1_vbus>;
        usb2_vbus-supply = <&reg_usb2_vbus>;
        status = "okay";

diff --git a/arch/arm/boot/dts/sun7i-a20-wexler-tab7200.dts b/arch/arm/boot/dts/sun7i-a20-wexler-tab7200.dts
index ffade25..6a66b04 100644 (file)
--- a/arch/arm/boot/dts/sun7i-a20-wexler-tab7200.dts
+++ b/arch/arm/boot/dts/sun7i-a20-wexler-tab7200.dts
@@ -156,14 +156,6 @@
        status = "okay";
 };
 
-&pio {
-       usb0_id_detect_pin: usb0-id-detect-pin {
-               pins = "PH4";
-               function = "gpio_in";
-               bias-pull-up;
-       };
-};
-
 &pwm {
        pinctrl-names = "default";
        pinctrl-0 = <&pwm0_pin>;
@@ -223,9 +215,7 @@
 };
 
 &usbphy {
-       pinctrl-names = "default";
-       pinctrl-0 = <&usb0_id_detect_pin>;
-       usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
+       usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */
        usb0_vbus_power-supply = <&usb_power_supply>;
        usb0_vbus-supply = <&reg_usb0_vbus>;
        usb1_vbus-supply = <&reg_usb1_vbus>;

diff --git a/arch/arm/boot/dts/sun7i-a20-wits-pro-a20-dkt.dts b/arch/arm/boot/dts/sun7i-a20-wits-pro-a20-dkt.dts
index c27e560..f8475a3 100644 (file)
--- a/arch/arm/boot/dts/sun7i-a20-wits-pro-a20-dkt.dts
+++ b/arch/arm/boot/dts/sun7i-a20-wits-pro-a20-dkt.dts
@@ -145,14 +145,6 @@
        status = "okay";
 };
 
-&pio {
-       usb0_id_detect_pin: usb0-id-detect-pin {
-               pins = "PH4";
-               function = "gpio_in";
-               bias-pull-up;
-       };
-};
-
 &reg_dcdc2 {
        regulator-always-on;
        regulator-min-microvolt = <1000000>;
@@ -206,9 +198,7 @@
 };
 
 &usbphy {
-       pinctrl-names = "default";
-       pinctrl-0 = <&usb0_id_detect_pin>;
-       usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
+       usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */
        usb0_vbus_power-supply = <&usb_power_supply>;
        usb0_vbus-supply = <&reg_usb0_vbus>;
        usb1_vbus-supply = <&reg_usb1_vbus>;

diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
index 641a8fa..9ad8e44 100644 (file)
--- a/arch/arm/boot/dts/sun7i-a20.dtsi
+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
@@ -333,7 +333,7 @@
                        #dma-cells = <2>;
                };
 
-               nfc: nand@1c03000 {
+               nfc: nand-controller@1c03000 {
                        compatible = "allwinner,sun4i-a10-nand";
                        reg = <0x01c03000 0x1000>;
                        interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
@@ -406,6 +406,7 @@
                                      "tcon-ch0",
                                      "tcon-ch1";
                        clock-output-names = "tcon0-pixel-clock";
+                       #clock-cells = <0>;
                        dmas = <&dma SUN4I_DMA_DEDICATED 14>;
 
                        ports {
@@ -455,6 +456,7 @@
                                      "tcon-ch0",
                                      "tcon-ch1";
                        clock-output-names = "tcon1-pixel-clock";
+                       #clock-cells = <0>;
                        dmas = <&dma SUN4I_DMA_DEDICATED 15>;
 
                        ports {
@@ -586,13 +588,14 @@
                        phy-names = "usb";
                        extcon = <&usbphy 0>;
                        allwinner,sram = <&otg_sram 1>;
+                       dr_mode = "otg";
                        status = "disabled";
                };
 
                usbphy: phy@1c13400 {
                        #phy-cells = <1>;
                        compatible = "allwinner,sun7i-a20-usb-phy";
-                       reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>;
+                       reg = <0x01c13400 0x10>, <0x01c14800 0x4>, <0x01c1c800 0x4>;
                        reg-names = "phy_ctrl", "pmu1", "pmu2";
                        clocks = <&ccu CLK_USB_PHY>;
                        clock-names = "usb_phy";
@@ -609,7 +612,6 @@
                        interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
                        clocks = <&ccu CLK_AHB_EHCI0>;
                        phys = <&usbphy 1>;
-                       phy-names = "usb";
                        status = "disabled";
                };
 
@@ -619,7 +621,6 @@
                        interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
                        clocks = <&ccu CLK_USB_OHCI0>, <&ccu CLK_AHB_OHCI0>;
                        phys = <&usbphy 1>;
-                       phy-names = "usb";
                        status = "disabled";
                };
 
@@ -702,7 +703,6 @@
                        interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
                        clocks = <&ccu CLK_AHB_EHCI1>;
                        phys = <&usbphy 2>;
-                       phy-names = "usb";
                        status = "disabled";
                };
 
@@ -712,7 +712,6 @@
                        interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
                        clocks = <&ccu CLK_USB_OHCI1>, <&ccu CLK_AHB_OHCI1>;
                        phys = <&usbphy 2>;
-                       phy-names = "usb";
                        status = "disabled";
                };
 
@@ -751,21 +750,31 @@
                        #interrupt-cells = <3>;
                        #gpio-cells = <3>;
 
+                       /omit-if-no-ref/
+                       can_pa_pins: can-pa-pins {
+                               pins = "PA16", "PA17";
+                               function = "can";
+                       };
+
+                       /omit-if-no-ref/
                        can_ph_pins: can-ph-pins {
                                pins = "PH20", "PH21";
                                function = "can";
                        };
 
+                       /omit-if-no-ref/
                        clk_out_a_pin: clk-out-a-pin {
                                pins = "PI12";
                                function = "clk_out_a";
                        };
 
+                       /omit-if-no-ref/
                        clk_out_b_pin: clk-out-b-pin {
                                pins = "PI13";
                                function = "clk_out_b";
                        };
 
+                       /omit-if-no-ref/
                        emac_pa_pins: emac-pa-pins {
                                pins = "PA0", "PA1", "PA2",
                                       "PA3", "PA4", "PA5", "PA6",
@@ -775,6 +784,17 @@
                                function = "emac";
                        };
 
+                       /omit-if-no-ref/
+                       emac_ph_pins: emac-ph-pins {
+                               pins = "PH8", "PH9", "PH10", "PH11",
+                                      "PH14", "PH15", "PH16", "PH17",
+                                      "PH18", "PH19", "PH20", "PH21",
+                                      "PH22", "PH23", "PH24", "PH25",
+                                      "PH26";
+                               function = "emac";
+                       };
+
+                       /omit-if-no-ref/
                        gmac_mii_pins: gmac-mii-pins {
                                pins = "PA0", "PA1", "PA2",
                                       "PA3", "PA4", "PA5", "PA6",
@@ -784,6 +804,7 @@
                                function = "gmac";
                        };
 
+                       /omit-if-no-ref/
                        gmac_rgmii_pins: gmac-rgmii-pins {
                                pins = "PA0", "PA1", "PA2",
                                       "PA3", "PA4", "PA5", "PA6",
@@ -798,46 +819,55 @@
                                drive-strength = <40>;
                        };
 
+                       /omit-if-no-ref/
                        i2c0_pins: i2c0-pins {
                                pins = "PB0", "PB1";
                                function = "i2c0";
                        };
 
+                       /omit-if-no-ref/
                        i2c1_pins: i2c1-pins {
                                pins = "PB18", "PB19";
                                function = "i2c1";
                        };
 
+                       /omit-if-no-ref/
                        i2c2_pins: i2c2-pins {
                                pins = "PB20", "PB21";
                                function = "i2c2";
                        };
 
+                       /omit-if-no-ref/
                        i2c3_pins: i2c3-pins {
                                pins = "PI0", "PI1";
                                function = "i2c3";
                        };
 
+                       /omit-if-no-ref/
                        ir0_rx_pin: ir0-rx-pin {
                                pins = "PB4";
                                function = "ir0";
                        };
 
+                       /omit-if-no-ref/
                        ir0_tx_pin: ir0-tx-pin {
                                pins = "PB3";
                                function = "ir0";
                        };
 
+                       /omit-if-no-ref/
                        ir1_rx_pin: ir1-rx-pin {
                                pins = "PB23";
                                function = "ir1";
                        };
 
+                       /omit-if-no-ref/
                        ir1_tx_pin: ir1-tx-pin {
                                pins = "PB22";
                                function = "ir1";
                        };
 
+                       /omit-if-no-ref/
                        mmc0_pins: mmc0-pins {
                                pins = "PF0", "PF1", "PF2",
                                       "PF3", "PF4", "PF5";
@@ -846,6 +876,7 @@
                                bias-pull-up;
                        };
 
+                       /omit-if-no-ref/
                        mmc2_pins: mmc2-pins {
                                pins = "PC6", "PC7", "PC8",
                                       "PC9", "PC10", "PC11";
@@ -854,6 +885,7 @@
                                bias-pull-up;
                        };
 
+                       /omit-if-no-ref/
                        mmc3_pins: mmc3-pins {
                                pins = "PI4", "PI5", "PI6",
                                       "PI7", "PI8", "PI9";
@@ -862,127 +894,206 @@
                                bias-pull-up;
                        };
 
+                       /omit-if-no-ref/
                        ps2_0_pins: ps2-0-pins {
                                pins = "PI20", "PI21";
                                function = "ps2";
                        };
 
+                       /omit-if-no-ref/
                        ps2_1_ph_pins: ps2-1-ph-pins {
                                pins = "PH12", "PH13";
                                function = "ps2";
                        };
 
+                       /omit-if-no-ref/
                        pwm0_pin: pwm0-pin {
                                pins = "PB2";
                                function = "pwm";
                        };
 
+                       /omit-if-no-ref/
                        pwm1_pin: pwm1-pin {
                                pins = "PI3";
                                function = "pwm";
                        };
 
+                       /omit-if-no-ref/
                        spdif_tx_pin: spdif-tx-pin {
                                pins = "PB13";
                                function = "spdif";
                                bias-pull-up;
                        };
 
+                       /omit-if-no-ref/
                        spi0_pi_pins: spi0-pi-pins {
                                pins = "PI11", "PI12", "PI13";
                                function = "spi0";
                        };
 
+                       /omit-if-no-ref/
                        spi0_cs0_pi_pin: spi0-cs0-pi-pin {
                                pins = "PI10";
                                function = "spi0";
                        };
 
+                       /omit-if-no-ref/
                        spi0_cs1_pi_pin: spi0-cs1-pi-pin {
                                pins = "PI14";
                                function = "spi0";
                        };
 
+                       /omit-if-no-ref/
                        spi1_pi_pins: spi1-pi-pins {
                                pins = "PI17", "PI18", "PI19";
                                function = "spi1";
                        };
 
+                       /omit-if-no-ref/
                        spi1_cs0_pi_pin: spi1-cs0-pi-pin {
                                pins = "PI16";
                                function = "spi1";
                        };
 
+                       /omit-if-no-ref/
                        spi2_pb_pins: spi2-pb-pins {
                                pins = "PB15", "PB16", "PB17";
                                function = "spi2";
                        };
 
+                       /omit-if-no-ref/
                        spi2_cs0_pb_pin: spi2-cs0-pb-pin {
                                pins = "PB14";
                                function = "spi2";
                        };
 
+                       /omit-if-no-ref/
                        spi2_pc_pins: spi2-pc-pins {
                                pins = "PC20", "PC21", "PC22";
                                function = "spi2";
                        };
 
+                       /omit-if-no-ref/
                        spi2_cs0_pc_pin: spi2-cs0-pc-pin {
                                pins = "PC19";
                                function = "spi2";
                        };
 
+                       /omit-if-no-ref/
                        uart0_pb_pins: uart0-pb-pins {
                                pins = "PB22", "PB23";
                                function = "uart0";
                        };
 
+                       /omit-if-no-ref/
+                       uart0_pf_pins: uart0-pf-pins {
+                               pins = "PF2", "PF4";
+                               function = "uart0";
+                       };
+
+                       /omit-if-no-ref/
+                       uart1_pa_pins: uart1-pa-pins {
+                               pins = "PA10", "PA11";
+                               function = "uart1";
+                       };
+
+                       /omit-if-no-ref/
+                       uart1_cts_rts_pa_pins: uart1-cts-rts-pa-pins {
+                               pins = "PA12", "PA13";
+                               function = "uart1";
+                       };
+
+                       /omit-if-no-ref/
+                       uart2_pa_pins: uart2-pa-pins {
+                               pins = "PA2", "PA3";
+                               function = "uart2";
+                       };
+
+                       /omit-if-no-ref/
+                       uart2_cts_rts_pa_pins: uart2-cts-rts-pa-pins {
+                               pins = "PA0", "PA1";
+                               function = "uart2";
+                       };
+
+                       /omit-if-no-ref/
                        uart2_pi_pins: uart2-pi-pins {
                                pins = "PI18", "PI19";
                                function = "uart2";
                        };
 
+                       /omit-if-no-ref/
                        uart2_cts_rts_pi_pins: uart2-cts-rts-pi-pins {
                                pins = "PI16", "PI17";
                                function = "uart2";
                        };
 
+                       /omit-if-no-ref/
                        uart3_pg_pins: uart3-pg-pins {
                                pins = "PG6", "PG7";
                                function = "uart3";
                        };
 
+                       /omit-if-no-ref/
                        uart3_cts_rts_pg_pins: uart3-cts-rts-pg-pins {
                                pins = "PG8", "PG9";
                                function = "uart3";
                        };
 
+                       /omit-if-no-ref/
                        uart3_ph_pins: uart3-ph-pins {
                                pins = "PH0", "PH1";
                                function = "uart3";
                        };
 
+                       /omit-if-no-ref/
+                       uart3_cts_rts_ph_pins: uart3-cts-rts-ph-pins {
+                               pins = "PH2", "PH3";
+                               function = "uart3";
+                       };
+
+                       /omit-if-no-ref/
                        uart4_pg_pins: uart4-pg-pins {
                                pins = "PG10", "PG11";
                                function = "uart4";
                        };
 
+                       /omit-if-no-ref/
                        uart4_ph_pins: uart4-ph-pins {
                                pins = "PH4", "PH5";
                                function = "uart4";
                        };
 
+                       /omit-if-no-ref/
+                       uart5_ph_pins: uart5-ph-pins {
+                               pins = "PH6", "PH7";
+                               function = "uart5";
+                       };
+
+                       /omit-if-no-ref/
                        uart5_pi_pins: uart5-pi-pins {
                                pins = "PI10", "PI11";
                                function = "uart5";
                        };
 
+                       /omit-if-no-ref/
+                       uart6_pa_pins: uart6-pa-pins {
+                               pins = "PA12", "PA13";
+                               function = "uart6";
+                       };
+
+                       /omit-if-no-ref/
                        uart6_pi_pins: uart6-pi-pins {
                                pins = "PI12", "PI13";
                                function = "uart6";
                        };
 
+                       /omit-if-no-ref/
+                       uart7_pa_pins: uart7-pa-pins {
+                               pins = "PA14", "PA15";
+                               function = "uart7";
+                       };
+
+                       /omit-if-no-ref/
                        uart7_pi_pins: uart7-pi-pins {
                                pins = "PI20", "PI21";
                                function = "uart7";
@@ -1341,7 +1452,7 @@
                };
 
                gic: interrupt-controller@1c81000 {
-                       compatible = "arm,gic-400", "arm,cortex-a7-gic", "arm,cortex-a15-gic";
+                       compatible = "arm,gic-400";
                        reg = <0x01c81000 0x1000>,
                              <0x01c82000 0x2000>,
                              <0x01c84000 0x2000>,

diff --git a/arch/arm/boot/dts/sun8i-a23-a33.dtsi b/arch/arm/boot/dts/sun8i-a23-a33.dtsi
index 14a7d02..af2fa69 100644 (file)
--- a/arch/arm/boot/dts/sun8i-a23-a33.dtsi
+++ b/arch/arm/boot/dts/sun8i-a23-a33.dtsi
@@ -161,16 +161,18 @@
                        #dma-cells = <1>;
                };
 
-               nfc: nand@1c03000 {
-                       compatible = "allwinner,sun4i-a10-nand";
+               nfc: nand-controller@1c03000 {
+                       compatible = "allwinner,sun8i-a23-nand-controller";
                        reg = <0x01c03000 0x1000>;
                        interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
                        clocks = <&ccu CLK_BUS_NAND>, <&ccu CLK_NAND>;
                        clock-names = "ahb", "mod";
                        resets = <&ccu RST_BUS_NAND>;
                        reset-names = "ahb";
+                       dmas = <&dma 5>;
+                       dma-names = "rxtx";
                        pinctrl-names = "default";
-                       pinctrl-0 = <&nand_pins &nand_pins_cs0 &nand_pins_rb0>;
+                       pinctrl-0 = <&nand_pins &nand_cs0_pin &nand_rb0_pin>;
                        status = "disabled";
                        #address-cells = <1>;
                        #size-cells = <0>;
@@ -185,6 +187,7 @@
                        clock-names = "ahb",
                                      "tcon-ch0";
                        clock-output-names = "tcon-pixel-clock";
+                       #clock-cells = <0>;
                        resets = <&ccu RST_BUS_LCD>;
                        reset-names = "lcd";
                        status = "disabled";
@@ -194,19 +197,14 @@
                                #size-cells = <0>;
 
                                tcon0_in: port@0 {
-                                       #address-cells = <1>;
-                                       #size-cells = <0>;
                                        reg = <0>;
 
-                                       tcon0_in_drc0: endpoint@0 {
-                                               reg = <0>;
+                                       tcon0_in_drc0: endpoint {
                                                remote-endpoint = <&drc0_out_tcon0>;
                                        };
                                };
 
                                tcon0_out: port@1 {
-                                       #address-cells = <1>;
-                                       #size-cells = <0>;
                                        reg = <1>;
                                };
                        };
@@ -281,6 +279,7 @@
                        phys = <&usbphy 0>;
                        phy-names = "usb";
                        extcon = <&usbphy 0>;
+                       dr_mode = "otg";
                        status = "disabled";
                };
 
@@ -308,7 +307,6 @@
                        clocks = <&ccu CLK_BUS_EHCI>;
                        resets = <&ccu RST_BUS_EHCI>;
                        phys = <&usbphy 1>;
-                       phy-names = "usb";
                        status = "disabled";
                };
 
@@ -319,7 +317,6 @@
                        clocks = <&ccu CLK_BUS_OHCI>, <&ccu CLK_USB_OHCI>;
                        resets = <&ccu RST_BUS_OHCI>;
                        phys = <&usbphy 1>;
-                       phy-names = "usb";
                        status = "disabled";
                };
 
@@ -398,25 +395,25 @@
                                function = "nand0";
                        };
 
-                       nand_pins_cs0: nand-pins-cs0 {
+                       nand_cs0_pin: nand-cs0-pin {
                                pins = "PC4";
                                function = "nand0";
                                bias-pull-up;
                        };
 
-                       nand_pins_cs1: nand-pins-cs1 {
+                       nand_cs1_pin: nand-cs1-pin {
                                pins = "PC3";
                                function = "nand0";
                                bias-pull-up;
                        };
 
-                       nand_pins_rb0: nand-pins-rb0 {
+                       nand_rb0_pin: nand-rb0-pin {
                                pins = "PC6";
                                function = "nand0";
                                bias-pull-up;
                        };
 
-                       nand_pins_rb1: nand-pins-rb1 {
+                       nand_rb1_pin: nand-rb1-pin {
                                pins = "PC7";
                                function = "nand0";
                                bias-pull-up;
@@ -604,7 +601,7 @@
                };
 
                gic: interrupt-controller@1c81000 {
-                       compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
+                       compatible = "arm,gic-400";
                        reg = <0x01c81000 0x1000>,
                              <0x01c82000 0x2000>,
                              <0x01c84000 0x2000>,
@@ -629,12 +626,9 @@
                                #size-cells = <0>;
 
                                fe0_out: port@1 {
-                                       #address-cells = <1>;
-                                       #size-cells = <0>;
                                        reg = <1>;
 
-                                       fe0_out_be0: endpoint@0 {
-                                               reg = <0>;
+                                       fe0_out_be0: endpoint {
                                                remote-endpoint = <&be0_in_fe0>;
                                        };
                                };
@@ -656,23 +650,17 @@
                                #size-cells = <0>;
 
                                be0_in: port@0 {
-                                       #address-cells = <1>;
-                                       #size-cells = <0>;
                                        reg = <0>;
 
-                                       be0_in_fe0: endpoint@0 {
-                                               reg = <0>;
+                                       be0_in_fe0: endpoint {
                                                remote-endpoint = <&fe0_out_be0>;
                                        };
                                };
 
                                be0_out: port@1 {
-                                       #address-cells = <1>;
-                                       #size-cells = <0>;
                                        reg = <1>;
 
-                                       be0_out_drc0: endpoint@0 {
-                                               reg = <0>;
+                                       be0_out_drc0: endpoint {
                                                remote-endpoint = <&drc0_in_be0>;
                                        };
                                };
@@ -696,23 +684,17 @@
                                #size-cells = <0>;
 
                                drc0_in: port@0 {
-                                       #address-cells = <1>;
-                                       #size-cells = <0>;
                                        reg = <0>;
 
-                                       drc0_in_be0: endpoint@0 {
-                                               reg = <0>;
+                                       drc0_in_be0: endpoint {
                                                remote-endpoint = <&be0_out_drc0>;
                                        };
                                };
 
                                drc0_out: port@1 {
-                                       #address-cells = <1>;
-                                       #size-cells = <0>;
                                        reg = <1>;
 
-                                       drc0_out_tcon0: endpoint@0 {
-                                               reg = <0>;
+                                       drc0_out_tcon0: endpoint {
                                                remote-endpoint = <&tcon0_in_drc0>;
                                        };
                                };
@@ -801,6 +783,20 @@
                        status = "disabled";
                };
 
+               r_i2c: i2c@1f02400 {
+                       compatible = "allwinner,sun8i-a23-i2c",
+                                    "allwinner,sun6i-a31-i2c";
+                       reg = <0x01f02400 0x400>;
+                       interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
+                       pinctrl-names = "default";
+                       pinctrl-0 = <&r_i2c_pins>;
+                       clocks = <&apb0_gates 6>;
+                       resets = <&apb0_rst 6>;
+                       status = "disabled";
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+               };
+
                r_pio: pinctrl@1f02c00 {
                        compatible = "allwinner,sun8i-a23-r-pinctrl";
                        reg = <0x01f02c00 0x400>;
@@ -813,6 +809,12 @@
                        #interrupt-cells = <3>;
                        #gpio-cells = <3>;
 
+                       r_i2c_pins: r-i2c-pins {
+                               pins = "PL0", "PL1";
+                               function = "s_i2c";
+                               bias-pull-up;
+                       };
+
                        r_rsb_pins: r-rsb-pins {
                                pins = "PL0", "PL1";
                                function = "s_rsb";

diff --git a/arch/arm/boot/dts/sun8i-a23-q8-tablet.dts b/arch/arm/boot/dts/sun8i-a23-q8-tablet.dts
index d4dab7c..5659c63 100644 (file)
--- a/arch/arm/boot/dts/sun8i-a23-q8-tablet.dts
+++ b/arch/arm/boot/dts/sun8i-a23-q8-tablet.dts
@@ -65,3 +65,9 @@
 &panel {
        compatible = "bananapi,s070wv20-ct16", "simple-panel";
 };
+
+&tcon0_out {
+       tcon0_out_lcd: endpoint {
+               remote-endpoint = <&panel_input>;
+       };
+};

diff --git a/arch/arm/boot/dts/sun8i-a33-q8-tablet.dts b/arch/arm/boot/dts/sun8i-a33-q8-tablet.dts
index b0bc236..9c5750c 100644 (file)
--- a/arch/arm/boot/dts/sun8i-a33-q8-tablet.dts
+++ b/arch/arm/boot/dts/sun8i-a33-q8-tablet.dts
@@ -48,3 +48,10 @@
        model = "Q8 A33 Tablet";
        compatible = "allwinner,q8-a33", "allwinner,sun8i-a33";
 };
+
+&tcon0_out {
+       tcon0_out_lcd: endpoint@0 {
+               reg = <0>;
+               remote-endpoint = <&panel_input>;
+       };
+};

diff --git a/arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts b/arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts
index f366726..785798e 100644 (file)
--- a/arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts
+++ b/arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts
@@ -63,16 +63,9 @@
 
        panel {
                compatible = "netron-dy,e231732";
-               #address-cells = <1>;
-               #size-cells = <0>;
 
-               port@0 {
-                       reg = <0>;
-                       #address-cells = <1>;
-                       #size-cells = <0>;
-
-                       panel_input: endpoint@0 {
-                               reg = <0>;
+               port {
+                       panel_input: endpoint {
                                remote-endpoint = <&tcon0_out_panel>;
                        };
                };

diff --git a/arch/arm/boot/dts/sun8i-a33.dtsi b/arch/arm/boot/dts/sun8i-a33.dtsi
index 1111a64..1532a0e 100644 (file)
--- a/arch/arm/boot/dts/sun8i-a33.dtsi
+++ b/arch/arm/boot/dts/sun8i-a33.dtsi
@@ -265,19 +265,12 @@
                        phys = <&dphy>;
                        phy-names = "dphy";
                        status = "disabled";
+                       #address-cells = <1>;
+                       #size-cells = <0>;
 
-                       ports {
-                               #address-cells = <1>;
-                               #size-cells = <0>;
-
-                               port@0 {
-                                       #address-cells = <1>;
-                                       #size-cells = <0>;
-                                       reg = <0>;
-
-                                       dsi_in_tcon0: endpoint {
-                                               remote-endpoint = <&tcon0_out_dsi>;
-                                       };
+                       port {
+                               dsi_in_tcon0: endpoint {
+                                       remote-endpoint = <&tcon0_out_dsi>;
                                };
                        };
                };
@@ -420,6 +413,9 @@
 };
 
 &tcon0_out {
+       #address-cells = <1>;
+       #size-cells = <0>;
+
        tcon0_out_dsi: endpoint@1 {
                reg = <1>;
                remote-endpoint = <&dsi_in_tcon0>;

diff --git a/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts b/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts
index 838be7b..9d34eab 100644 (file)
--- a/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts
+++ b/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts
@@ -389,7 +389,19 @@
        };
 };
 
+&usb_otg {
+       dr_mode = "otg";
+       status = "okay";
+};
+
+&usb_power_supply {
+       status = "okay";
+};
+
 &usbphy {
+       usb0_id_det-gpios = <&pio 7 11 GPIO_ACTIVE_HIGH>; /* PH11 */
+       usb0_vbus_power-supply = <&usb_power_supply>;
+       usb0_vbus-supply = <&reg_drivevbus>;
        usb1_vbus-supply = <&reg_usb1_vbus>;
        status = "okay";
 };

diff --git a/arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts b/arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts
index fcbec3d..ea299d3 100644 (file)
--- a/arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts
+++ b/arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts
@@ -420,7 +420,19 @@
        };
 };
 
+&usb_otg {
+       dr_mode = "otg";
+       status = "okay";
+};
+
+&usb_power_supply {
+       status = "okay";
+};
+
 &usbphy {
+       usb0_id_det-gpios = <&pio 7 11 GPIO_ACTIVE_HIGH>; /* PH11 */
+       usb0_vbus_power-supply = <&usb_power_supply>;
+       usb0_vbus-supply = <&reg_drivevbus>;
        usb1_vbus-supply = <&reg_usb1_vbus>;
        usb2_vbus-supply = <&reg_usb2_vbus>;
        status = "okay";

diff --git a/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts b/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts
index 98e8cea..66d0780 100644 (file)
--- a/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts
+++ b/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts
@@ -46,6 +46,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/pwm/pwm.h>
+#include <dt-bindings/input/input.h>
 
 / {
        model = "TBS A711 Tablet";
@@ -98,6 +99,13 @@
                };
        };
 
+       reg_gps: reg-gps {
+               compatible = "regulator-fixed";
+               regulator-name = "gps";
+               regulator-min-microvolt = <3000000>;
+               regulator-max-microvolt = <3000000>;
+       };
+
        reg_vbat: reg-vbat {
                compatible = "regulator-fixed";
                regulator-name = "vbat";
@@ -156,6 +164,18 @@
        status = "okay";
 };
 
+&i2c1 {
+       clock-frequency = <400000>;
+       status = "okay";
+
+       accelerometer@18 {
+               compatible = "bosch,bma250";
+               reg = <0x18>;
+               interrupt-parent = <&pio>;
+               interrupts = <7 10 IRQ_TYPE_EDGE_RISING>; /* PH10 / EINT10 */
+       };
+};
+
 &mmc0 {
        vmmc-supply = <&reg_dcdc1>;
        pinctrl-names = "default";
@@ -200,6 +220,25 @@
        status = "okay";
 };
 
+&r_lradc {
+       vref-supply = <&reg_aldo2>;
+       status = "okay";
+
+       button@210 {
+               label = "Volume Up";
+               linux,code = <KEY_VOLUMEUP>;
+               channel = <0>;
+               voltage = <210000>;
+       };
+
+       button@410 {
+               label = "Volume Down";
+               linux,code = <KEY_VOLUMEDOWN>;
+               channel = <0>;
+               voltage = <410000>;
+       };
+};
+
 &r_rsb {
        status = "okay";
 
@@ -391,8 +430,7 @@
 };
 
 &tcon0_out {
-       tcon0_out_lcd: endpoint@0 {
-               reg = <0>;
+       tcon0_out_lcd: endpoint {
                remote-endpoint = <&panel_input>;
        };
 };
@@ -407,7 +445,34 @@
 &uart1 {
        pinctrl-names = "default";
        pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>;
+       uart-has-rtscts;
+       status = "okay";
+
+       bluetooth {
+               compatible = "brcm,bcm20702a1";
+               clocks = <&ac100_rtc 1>;
+               clock-names = "lpo";
+               vbat-supply = <&reg_vbat>;
+               vddio-supply = <&reg_dldo1>;
+               device-wakeup-gpios = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */
+               host-wakeup-gpios = <&r_pio 0 5 GPIO_ACTIVE_HIGH>; /* PL5 */
+               shutdown-gpios = <&r_pio 0 4 GPIO_ACTIVE_HIGH>; /* PL4 */
+               max-speed = <1500000>;
+       };
+};
+
+&uart2 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&uart2_pb_pins>;
        status = "okay";
+
+       gnss {
+               compatible = "u-blox,neo-6m";
+
+               v-bckp-supply = <&reg_rtc_ldo>;
+               vcc-supply = <&reg_gps>;
+               current-speed = <9600>;
+       };
 };
 
 &usb_otg {
@@ -418,7 +483,7 @@
 &usbphy {
        usb0_id_det-gpios = <&pio 7 11 GPIO_ACTIVE_HIGH>; /* PH11 */
        usb0_vbus-supply = <&reg_drivevbus>;
-       usb1_vbus_supply = <&reg_vmain>;
-       usb2_vbus_supply = <&reg_vmain>;
+       usb1_vbus-supply = <&reg_vmain>;
+       usb2_vbus-supply = <&reg_vmain>;
        status = "okay";
 };

diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi
index b099d2f..392b0ca 100644 (file)
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -61,79 +61,91 @@
                #size-cells = <0>;
 
                cpu0: cpu@0 {
-                       clocks = <&ccu CLK_C0CPUX>;
-                       clock-names = "cpu";
                        compatible = "arm,cortex-a7";
                        device_type = "cpu";
+                       clocks = <&ccu CLK_C0CPUX>;
                        operating-points-v2 = <&cpu0_opp_table>;
                        cci-control-port = <&cci_control0>;
                        enable-method = "allwinner,sun8i-a83t-smp";
                        reg = <0>;
+                       #cooling-cells = <2>;
                };
 
                cpu@1 {
                        compatible = "arm,cortex-a7";
                        device_type = "cpu";
+                       clocks = <&ccu CLK_C0CPUX>;
                        operating-points-v2 = <&cpu0_opp_table>;
                        cci-control-port = <&cci_control0>;
                        enable-method = "allwinner,sun8i-a83t-smp";
                        reg = <1>;
+                       #cooling-cells = <2>;
                };
 
                cpu@2 {
                        compatible = "arm,cortex-a7";
                        device_type = "cpu";
+                       clocks = <&ccu CLK_C0CPUX>;
                        operating-points-v2 = <&cpu0_opp_table>;
                        cci-control-port = <&cci_control0>;
                        enable-method = "allwinner,sun8i-a83t-smp";
                        reg = <2>;
+                       #cooling-cells = <2>;
                };
 
                cpu@3 {
                        compatible = "arm,cortex-a7";
                        device_type = "cpu";
+                       clocks = <&ccu CLK_C0CPUX>;
                        operating-points-v2 = <&cpu0_opp_table>;
                        cci-control-port = <&cci_control0>;
                        enable-method = "allwinner,sun8i-a83t-smp";
                        reg = <3>;
+                       #cooling-cells = <2>;
                };
 
                cpu100: cpu@100 {
-                       clocks = <&ccu CLK_C1CPUX>;
-                       clock-names = "cpu";
                        compatible = "arm,cortex-a7";
                        device_type = "cpu";
+                       clocks = <&ccu CLK_C1CPUX>;
                        operating-points-v2 = <&cpu1_opp_table>;
                        cci-control-port = <&cci_control1>;
                        enable-method = "allwinner,sun8i-a83t-smp";
                        reg = <0x100>;
+                       #cooling-cells = <2>;
                };
 
                cpu@101 {
                        compatible = "arm,cortex-a7";
                        device_type = "cpu";
+                       clocks = <&ccu CLK_C1CPUX>;
                        operating-points-v2 = <&cpu1_opp_table>;
                        cci-control-port = <&cci_control1>;
                        enable-method = "allwinner,sun8i-a83t-smp";
                        reg = <0x101>;
+                       #cooling-cells = <2>;
                };
 
                cpu@102 {
                        compatible = "arm,cortex-a7";
                        device_type = "cpu";
+                       clocks = <&ccu CLK_C1CPUX>;
                        operating-points-v2 = <&cpu1_opp_table>;
                        cci-control-port = <&cci_control1>;
                        enable-method = "allwinner,sun8i-a83t-smp";
                        reg = <0x102>;
+                       #cooling-cells = <2>;
                };
 
                cpu@103 {
                        compatible = "arm,cortex-a7";
                        device_type = "cpu";
+                       clocks = <&ccu CLK_C1CPUX>;
                        operating-points-v2 = <&cpu1_opp_table>;
                        cci-control-port = <&cci_control1>;
                        enable-method = "allwinner,sun8i-a83t-smp";
                        reg = <0x103>;
+                       #cooling-cells = <2>;
                };
        };
 
@@ -333,6 +345,11 @@
                                                reg = <0>;
                                                remote-endpoint = <&tcon0_in_mixer0>;
                                        };
+
+                                       mixer0_out_tcon1: endpoint@1 {
+                                               reg = <1>;
+                                               remote-endpoint = <&tcon1_in_mixer0>;
+                                       };
                                };
                        };
                };
@@ -351,9 +368,17 @@
                                #size-cells = <0>;
 
                                mixer1_out: port@1 {
+                                       #address-cells = <1>;
+                                       #size-cells = <0>;
                                        reg = <1>;
 
-                                       mixer1_out_tcon1: endpoint {
+                                       mixer1_out_tcon0: endpoint@0 {
+                                               reg = <0>;
+                                               remote-endpoint = <&tcon0_in_mixer1>;
+                                       };
+
+                                       mixer1_out_tcon1: endpoint@1 {
+                                               reg = <1>;
                                                remote-endpoint = <&tcon1_in_mixer1>;
                                        };
                                };
@@ -420,6 +445,7 @@
                        clocks = <&ccu CLK_BUS_TCON0>, <&ccu CLK_TCON0>;
                        clock-names = "ahb", "tcon-ch0";
                        clock-output-names = "tcon-pixel-clock";
+                       #clock-cells = <0>;
                        resets = <&ccu RST_BUS_TCON0>, <&ccu RST_BUS_LVDS>;
                        reset-names = "lcd", "lvds";
 
@@ -436,11 +462,14 @@
                                                reg = <0>;
                                                remote-endpoint = <&mixer0_out_tcon0>;
                                        };
+
+                                       tcon0_in_mixer1: endpoint@1 {
+                                               reg = <1>;
+                                               remote-endpoint = <&mixer1_out_tcon0>;
+                                       };
                                };
 
                                tcon0_out: port@1 {
-                                       #address-cells = <1>;
-                                       #size-cells = <0>;
                                        reg = <1>;
                                };
                        };
@@ -460,9 +489,17 @@
                                #size-cells = <0>;
 
                                tcon1_in: port@0 {
+                                       #address-cells = <1>;
+                                       #size-cells = <0>;
                                        reg = <0>;
 
-                                       tcon1_in_mixer1: endpoint {
+                                       tcon1_in_mixer0: endpoint@0 {
+                                               reg = <0>;
+                                               remote-endpoint = <&mixer0_out_tcon1>;
+                                       };
+
+                                       tcon1_in_mixer1: endpoint@1 {
+                                               reg = <1>;
                                                remote-endpoint = <&mixer1_out_tcon1>;
                                        };
                                };
@@ -557,6 +594,7 @@
                        phys = <&usbphy 0>;
                        phy-names = "usb";
                        extcon = <&usbphy 0>;
+                       dr_mode = "otg";
                        status = "disabled";
                };
 
@@ -594,7 +632,6 @@
                        clocks = <&ccu CLK_BUS_EHCI0>;
                        resets = <&ccu RST_BUS_EHCI0>;
                        phys = <&usbphy 1>;
-                       phy-names = "usb";
                        status = "disabled";
                };
 
@@ -606,7 +643,6 @@
                        clocks = <&ccu CLK_BUS_OHCI0>, <&ccu CLK_USB_OHCI0>;
                        resets = <&ccu RST_BUS_OHCI0>;
                        phys = <&usbphy 1>;
-                       phy-names = "usb";
                        status = "disabled";
                };
 
@@ -618,7 +654,6 @@
                        clocks = <&ccu CLK_BUS_EHCI1>;
                        resets = <&ccu RST_BUS_EHCI1>;
                        phys = <&usbphy 2>;
-                       phy-names = "usb";
                        status = "disabled";
                };
 
@@ -671,6 +706,12 @@
                                function = "i2c1";
                        };
 
+                       /omit-if-no-ref/
+                       i2c2_pe_pins: i2c2-pe-pins {
+                               pins = "PE14", "PE15";
+                               function = "i2c2";
+                       };
+
                        i2c2_ph_pins: i2c2-ph-pins {
                                pins = "PH4", "PH5";
                                function = "i2c2";
@@ -742,6 +783,12 @@
                                pins = "PG8", "PG9";
                                function = "uart1";
                        };
+
+                       /omit-if-no-ref/
+                       uart2_pb_pins: uart2-pb-pins {
+                               pins = "PB0", "PB1";
+                               function = "uart2";
+                       };
                };
 
                timer@1c20c00 {
@@ -847,6 +894,39 @@
                        status = "disabled";
                };
 
+               uart2: serial@1c28800 {
+                       compatible = "snps,dw-apb-uart";
+                       reg = <0x01c28800 0x400>;
+                       interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
+                       reg-shift = <2>;
+                       reg-io-width = <4>;
+                       clocks = <&ccu CLK_BUS_UART2>;
+                       resets = <&ccu RST_BUS_UART2>;
+                       status = "disabled";
+               };
+
+               uart3: serial@1c28c00 {
+                       compatible = "snps,dw-apb-uart";
+                       reg = <0x01c28c00 0x400>;
+                       interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
+                       reg-shift = <2>;
+                       reg-io-width = <4>;
+                       clocks = <&ccu CLK_BUS_UART3>;
+                       resets = <&ccu RST_BUS_UART3>;
+                       status = "disabled";
+               };
+
+               uart4: serial@1c29000 {
+                       compatible = "snps,dw-apb-uart";
+                       reg = <0x01c29000 0x400>;
+                       interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+                       reg-shift = <2>;
+                       reg-io-width = <4>;
+                       clocks = <&ccu CLK_BUS_UART4>;
+                       resets = <&ccu RST_BUS_UART4>;
+                       status = "disabled";
+               };
+
                i2c0: i2c@1c2ac00 {
                        compatible = "allwinner,sun8i-a83t-i2c",
                                     "allwinner,sun6i-a31-i2c";
@@ -907,7 +987,7 @@
                };
 
                gic: interrupt-controller@1c81000 {
-                       compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
+                       compatible = "arm,gic-400";
                        reg = <0x01c81000 0x1000>,
                              <0x01c82000 0x2000>,
                              <0x01c84000 0x2000>,
@@ -998,6 +1078,13 @@
                        status = "disabled";
                };
 
+               r_lradc: lradc@1f03c00 {
+                       compatible = "allwinner,sun8i-a83t-r-lradc";
+                       reg = <0x01f03c00 0x100>;
+                       interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
+                       status = "disabled";
+               };
+
                r_pio: pinctrl@1f02c00 {
                        compatible = "allwinner,sun8i-a83t-r-pinctrl";
                        reg = <0x01f02c00 0x400>;

diff --git a/arch/arm/boot/dts/sun8i-h2-plus-bananapi-m2-zero.dts b/arch/arm/boot/dts/sun8i-h2-plus-bananapi-m2-zero.dts
index 1db2541..78a37a4 100644 (file)
--- a/arch/arm/boot/dts/sun8i-h2-plus-bananapi-m2-zero.dts
+++ b/arch/arm/boot/dts/sun8i-h2-plus-bananapi-m2-zero.dts
@@ -28,7 +28,6 @@
 
        leds {
                compatible = "gpio-leds";
-               pinctrl-names = "default";
 
                pwr_led {
                        label = "bananapi-m2-zero:red:pwr";
@@ -39,7 +38,6 @@
 
        gpio_keys {
                compatible = "gpio-keys";
-               pinctrl-names = "default";
 
                sw4 {
                        label = "power";
@@ -67,8 +65,9 @@
 
        wifi_pwrseq: wifi_pwrseq {
                compatible = "mmc-pwrseq-simple";
-               pinctrl-names = "default";
                reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */
+               clocks = <&rtc 1>;
+               clock-names = "ext_clock";
        };
 };
 
@@ -115,14 +114,27 @@
 
 &uart0 {
        pinctrl-names = "default";
-       pinctrl-0 = <&uart0_pins_a>;
+       pinctrl-0 = <&uart0_pa_pins>;
        status = "okay";
 };
 
 &uart1 {
        pinctrl-names = "default";
        pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>;
+       uart-has-rtscts;
        status = "okay";
+
+       bluetooth {
+               compatible = "brcm,bcm43438-bt";
+               clocks = <&rtc 1>;
+               clock-names = "lpo";
+               vbat-supply = <&reg_vcc3v3>;
+               vddio-supply = <&reg_vcc3v3>;
+               device-wakeup-gpios = <&pio 6 13 GPIO_ACTIVE_HIGH>; /* PG13 */
+               host-wakeup-gpios = <&pio 6 11 GPIO_ACTIVE_HIGH>; /* PG11 */
+               shutdown-gpios = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */
+       };
+
 };
 
 &usb_otg {

diff --git a/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts b/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts
index 84cd9c0..4970eda 100644 (file)
--- a/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts
+++ b/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts
@@ -178,7 +178,7 @@
 
 &uart0 {
        pinctrl-names = "default";
-       pinctrl-0 = <&uart0_pins_a>;
+       pinctrl-0 = <&uart0_pa_pins>;
        status = "okay";
 };
 

diff --git a/arch/arm/boot/dts/sun8i-h3-beelink-x2.dts b/arch/arm/boot/dts/sun8i-h3-beelink-x2.dts
index 25540b7..6277f13 100644 (file)
--- a/arch/arm/boot/dts/sun8i-h3-beelink-x2.dts
+++ b/arch/arm/boot/dts/sun8i-h3-beelink-x2.dts
@@ -142,7 +142,7 @@
 
 &ir {
        pinctrl-names = "default";
-       pinctrl-0 = <&ir_pins_a>;
+       pinctrl-0 = <&r_ir_rx_pin>;
        status = "okay";
 };
 
@@ -193,13 +193,13 @@
 
 &spdif {
        pinctrl-names = "default";
-       pinctrl-0 = <&spdif_tx_pins_a>;
+       pinctrl-0 = <&spdif_tx_pin>;
        status = "okay";
 };
 
 &uart0 {
        pinctrl-names = "default";
-       pinctrl-0 = <&uart0_pins_a>;
+       pinctrl-0 = <&uart0_pa_pins>;
        status = "okay";
 };
 

diff --git a/arch/arm/boot/dts/sun8i-h3-mapleboard-mp130.dts b/arch/arm/boot/dts/sun8i-h3-mapleboard-mp130.dts
index 2c952ea..ff0a7a9 100644 (file)
--- a/arch/arm/boot/dts/sun8i-h3-mapleboard-mp130.dts
+++ b/arch/arm/boot/dts/sun8i-h3-mapleboard-mp130.dts
@@ -84,15 +84,14 @@
 
 &ir {
        pinctrl-names = "default";
-       pinctrl-0 = <&ir_pins_a>;
+       pinctrl-0 = <&r_ir_rx_pin>;
        status = "okay";
 };
 
 &mmc0 {
        vmmc-supply = <&reg_vcc3v3>;
        bus-width = <4>;
-       cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */
-       cd-inverted;
+       cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
        status = "okay";
 };
 
@@ -120,7 +119,7 @@
 
 &uart0 {
        pinctrl-names = "default";
-       pinctrl-0 = <&uart0_pins_a>;
+       pinctrl-0 = <&uart0_pa_pins>;
        status = "okay";
 };
 

diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts b/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts
index 4ec94d7..4ba533b 100644 (file)
--- a/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts
+++ b/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts
@@ -64,7 +64,6 @@
 
        wifi_pwrseq: wifi_pwrseq {
                compatible = "mmc-pwrseq-simple";
-               pinctrl-names = "default";
                reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */
        };
 
@@ -121,7 +120,7 @@
 
 &ir {
        pinctrl-names = "default";
-       pinctrl-0 = <&ir_pins_a>;
+       pinctrl-0 = <&r_ir_rx_pin>;
        status = "okay";
 };
 

diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi-m1.dts b/arch/arm/boot/dts/sun8i-h3-nanopi-m1.dts
index 9412668..69243dc 100644 (file)
--- a/arch/arm/boot/dts/sun8i-h3-nanopi-m1.dts
+++ b/arch/arm/boot/dts/sun8i-h3-nanopi-m1.dts
@@ -93,7 +93,7 @@
 
 &ir {
        pinctrl-names = "default";
-       pinctrl-0 = <&ir_pins_a>;
+       pinctrl-0 = <&r_ir_rx_pin>;
        status = "okay";
 };
 

diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi-neo-air.dts b/arch/arm/boot/dts/sun8i-h3-nanopi-neo-air.dts
index 6246d3e..07867a0 100644 (file)
--- a/arch/arm/boot/dts/sun8i-h3-nanopi-neo-air.dts
+++ b/arch/arm/boot/dts/sun8i-h3-nanopi-neo-air.dts
@@ -105,7 +105,7 @@
 
 &uart0 {
        pinctrl-names = "default";
-       pinctrl-0 = <&uart0_pins_a>;
+       pinctrl-0 = <&uart0_pa_pins>;
        status = "okay";
 };
 

diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi.dtsi b/arch/arm/boot/dts/sun8i-h3-nanopi.dtsi
index f110ee3..4df29a6 100644 (file)
--- a/arch/arm/boot/dts/sun8i-h3-nanopi.dtsi
+++ b/arch/arm/boot/dts/sun8i-h3-nanopi.dtsi
@@ -59,8 +59,6 @@
 
        leds {
                compatible = "gpio-leds";
-               pinctrl-names = "default";
-               pinctrl-0 = <&leds_npi>, <&leds_r_npi>;
 
                status {
                        label = "nanopi:blue:status";
@@ -78,8 +76,6 @@
        r_gpio_keys {
                compatible = "gpio-keys";
                input-name = "k1";
-               pinctrl-names = "default";
-               pinctrl-0 = <&sw_r_npi>;
 
                k1 {
                        label = "k1";
@@ -104,28 +100,9 @@
        status = "okay";
 };
 
-&pio {
-       leds_npi: led_pins {
-               pins = "PA10";
-               function = "gpio_out";
-       };
-};
-
-&r_pio {
-       leds_r_npi: led_pins {
-               pins = "PL10";
-               function = "gpio_out";
-       };
-
-       sw_r_npi: key_pins {
-               pins = "PL3";
-               function = "gpio_in";
-       };
-};
-
 &uart0 {
        pinctrl-names = "default";
-       pinctrl-0 = <&uart0_pins_a>;
+       pinctrl-0 = <&uart0_pa_pins>;
        status = "okay";
 };
 

diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts
index f1fc6bd..597c425 100644 (file)
--- a/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts
+++ b/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts
@@ -75,8 +75,6 @@
 
        leds {
                compatible = "gpio-leds";
-               pinctrl-names = "default";
-               pinctrl-0 = <&leds_opc>, <&leds_r_opc>;
 
                status_led {
                        label = "orangepi:red:status";
@@ -92,8 +90,6 @@
 
        r_gpio_keys {
                compatible = "gpio-keys";
-               pinctrl-names = "default";
-               pinctrl-0 = <&sw_r_opc>;
 
                sw2 {
                        label = "sw2";
@@ -110,8 +106,6 @@
 
        wifi_pwrseq: wifi_pwrseq {
                compatible = "mmc-pwrseq-simple";
-               pinctrl-names = "default";
-               pinctrl-0 = <&wifi_pwrseq_pin_orangepi>;
                reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 WIFI_EN */
        };
 };
@@ -152,7 +146,7 @@
 
 &ir {
        pinctrl-names = "default";
-       pinctrl-0 = <&ir_pins_a>;
+       pinctrl-0 = <&r_ir_rx_pin>;
        status = "okay";
 };
 
@@ -179,30 +173,6 @@
        };
 };
 
-&pio {
-       leds_opc: led_pins {
-               pins = "PA15";
-               function = "gpio_out";
-       };
-};
-
-&r_pio {
-       leds_r_opc: led_pins {
-               pins = "PL10";
-               function = "gpio_out";
-       };
-
-       sw_r_opc: key_pins {
-               pins = "PL3", "PL4";
-               function = "gpio_in";
-       };
-
-       wifi_pwrseq_pin_orangepi: wifi_pwrseq_pin {
-               pins = "PL7";
-               function = "gpio_out";
-       };
-};
-
 &reg_usb1_vbus {
        gpio = <&pio 6 13 GPIO_ACTIVE_HIGH>;
        status = "okay";
@@ -210,7 +180,7 @@
 
 &uart0 {
        pinctrl-names = "default";
-       pinctrl-0 = <&uart0_pins_a>;
+       pinctrl-0 = <&uart0_pa_pins>;
        status = "okay";
 };
 

diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-lite.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-lite.dts
index 476ae8e..6f9c97a 100644 (file)
--- a/arch/arm/boot/dts/sun8i-h3-orangepi-lite.dts
+++ b/arch/arm/boot/dts/sun8i-h3-orangepi-lite.dts
@@ -74,8 +74,6 @@
 
        leds {
                compatible = "gpio-leds";
-               pinctrl-names = "default";
-               pinctrl-0 = <&leds_opc>, <&leds_r_opc>;
 
                pwr_led {
                        label = "orangepi:green:pwr";
@@ -91,8 +89,6 @@
 
        r_gpio_keys {
                compatible = "gpio-keys";
-               pinctrl-names = "default";
-               pinctrl-0 = <&sw_r_opc>;
 
                sw4 {
                        label = "sw4";
@@ -126,7 +122,7 @@
 
 &ir {
        pinctrl-names = "default";
-       pinctrl-0 = <&ir_pins_a>;
+       pinctrl-0 = <&r_ir_rx_pin>;
        status = "okay";
 };
 
@@ -160,28 +156,9 @@
        status = "okay";
 };
 
-&pio {
-       leds_opc: led_pins {
-               pins = "PA15";
-               function = "gpio_out";
-       };
-};
-
-&r_pio {
-       leds_r_opc: led_pins {
-               pins = "PL10";
-               function = "gpio_out";
-       };
-
-       sw_r_opc: key_pins {
-               pins = "PL3";
-               function = "gpio_in";
-       };
-};
-
 &uart0 {
        pinctrl-names = "default";
-       pinctrl-0 = <&uart0_pins_a>;
+       pinctrl-0 = <&uart0_pa_pins>;
        status = "okay";
 };
 

diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts
index 245fd65..8408491 100644 (file)
--- a/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts
+++ b/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts
@@ -73,8 +73,6 @@
 
        leds {
                compatible = "gpio-leds";
-               pinctrl-names = "default";
-               pinctrl-0 = <&leds_opc>, <&leds_r_opc>;
 
                pwr_led {
                        label = "orangepi:green:pwr";
@@ -90,8 +88,6 @@
 
        r_gpio_keys {
                compatible = "gpio-keys";
-               pinctrl-names = "default";
-               pinctrl-0 = <&sw_r_opc>;
 
                sw4 {
                        label = "sw4";
@@ -166,25 +162,6 @@
        status = "okay";
 };
 
-&pio {
-       leds_opc: led_pins {
-               pins = "PA15";
-               function = "gpio_out";
-       };
-};
-
-&r_pio {
-       leds_r_opc: led_pins {
-               pins = "PL10";
-               function = "gpio_out";
-       };
-
-       sw_r_opc: key_pins {
-               pins = "PL3";
-               function = "gpio_in";
-       };
-};
-
 &reg_usb0_vbus {
        gpio = <&r_pio 0 2 GPIO_ACTIVE_HIGH>; /* PL2 */
        status = "okay";
@@ -192,7 +169,7 @@
 
 &uart0 {
        pinctrl-names = "default";
-       pinctrl-0 = <&uart0_pins_a>;
+       pinctrl-0 = <&uart0_pa_pins>;
        status = "okay";
 };
 

diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts
index 4624033..5aff8ec 100644 (file)
--- a/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts
+++ b/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts
@@ -73,8 +73,6 @@
 
        leds {
                compatible = "gpio-leds";
-               pinctrl-names = "default";
-               pinctrl-0 = <&leds_opc>, <&leds_r_opc>;
 
                pwr_led {
                        label = "orangepi:green:pwr";
@@ -90,8 +88,6 @@
 
        r_gpio_keys {
                compatible = "gpio-keys";
-               pinctrl-names = "default";
-               pinctrl-0 = <&sw_r_opc>;
 
                sw4 {
                        label = "sw4";
@@ -152,7 +148,7 @@
 
 &ir {
        pinctrl-names = "default";
-       pinctrl-0 = <&ir_pins_a>;
+       pinctrl-0 = <&r_ir_rx_pin>;
        status = "okay";
 };
 
@@ -179,13 +175,6 @@
        status = "okay";
 };
 
-&pio {
-       leds_opc: led_pins {
-               pins = "PA15";
-               function = "gpio_out";
-       };
-};
-
 &r_i2c {
        status = "okay";
 
@@ -210,18 +199,6 @@
        };
 };
 
-&r_pio {
-       leds_r_opc: led_pins {
-               pins = "PL10";
-               function = "gpio_out";
-       };
-
-       sw_r_opc: key_pins {
-               pins = "PL3";
-               function = "gpio_in";
-       };
-};
-
 &reg_usb0_vbus {
        gpio = <&r_pio 0 2 GPIO_ACTIVE_HIGH>; /* PL2 */
        status = "okay";
@@ -229,7 +206,7 @@
 
 &uart0 {
        pinctrl-names = "default";
-       pinctrl-0 = <&uart0_pins_a>;
+       pinctrl-0 = <&uart0_pa_pins>;
        status = "okay";
 };
 

diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts
index ac8438c..97f4978 100644 (file)
--- a/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts
+++ b/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts
@@ -63,8 +63,6 @@
 
        reg_usb3_vbus: usb3-vbus {
                compatible = "regulator-fixed";
-               pinctrl-names = "default";
-               pinctrl-0 = <&usb3_vbus_pin_a>;
                regulator-name = "usb3-vbus";
                regulator-min-microvolt = <5000000>;
                regulator-max-microvolt = <5000000>;
@@ -116,13 +114,6 @@
        bias-pull-up;
 };
 
-&pio {
-       usb3_vbus_pin_a: usb3_vbus_pin {
-               pins = "PG11";
-               function = "gpio_out";
-       };
-};
-
 &r_i2c {
        status = "okay";
 

diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-zero-plus2.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-zero-plus2.dts
index c834048..b8f46e2 100644 (file)
--- a/arch/arm/boot/dts/sun8i-h3-orangepi-zero-plus2.dts
+++ b/arch/arm/boot/dts/sun8i-h3-orangepi-zero-plus2.dts
@@ -79,7 +79,6 @@
 
        wifi_pwrseq: wifi_pwrseq {
                compatible = "mmc-pwrseq-simple";
-               pinctrl-names = "default";
                reset-gpios = <&pio 0 9 GPIO_ACTIVE_LOW>; /* PA9 */
                post-power-on-delay-ms = <200>;
        };
@@ -135,6 +134,6 @@
 
 &uart0 {
        pinctrl-names = "default";
-       pinctrl-0 = <&uart0_pins_a>;
+       pinctrl-0 = <&uart0_pa_pins>;
        status = "okay";
 };

diff --git a/arch/arm/boot/dts/sun8i-h3-rervision-dvk.dts b/arch/arm/boot/dts/sun8i-h3-rervision-dvk.dts
new file mode 100644 (file)
index 0000000..4738f3a
--- /dev/null
+++ b/arch/arm/boot/dts/sun8i-h3-rervision-dvk.dts
@@ -0,0 +1,114 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2019 Bootlin
+ * Author: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
+ */
+
+/dts-v1/;
+#include "sun8i-h3.dtsi"
+#include "sunxi-common-regulators.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+/ {
+       model = "RerVision H3-DVK";
+       compatible = "rervision,h3-dvk", "allwinner,sun8i-h3";
+
+       aliases {
+               ethernet0 = &emac;
+               serial0 = &uart0;
+       };
+
+       chosen {
+               stdout-path = "serial0:115200n8";
+       };
+
+       connector {
+               compatible = "hdmi-connector";
+               type = "a";
+
+               port {
+                       hdmi_con_in: endpoint {
+                               remote-endpoint = <&hdmi_out_con>;
+                       };
+               };
+       };
+};
+
+&de {
+       status = "okay";
+};
+
+&ehci1 {
+       status = "okay";
+};
+
+&ehci2 {
+       status = "okay";
+};
+
+&ehci3 {
+       status = "okay";
+};
+
+&emac {
+       phy-handle = <&int_mii_phy>;
+       phy-mode = "mii";
+       allwinner,leds-active-low;
+       status = "okay";
+};
+
+&hdmi {
+       status = "okay";
+};
+
+&hdmi_out {
+       hdmi_out_con: endpoint {
+               remote-endpoint = <&hdmi_con_in>;
+       };
+};
+
+&mmc0 {
+       bus-width = <4>;
+       cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
+       status = "okay";
+       vmmc-supply = <&reg_vcc3v3>;
+};
+
+&mmc2 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&mmc2_8bit_pins>;
+       vmmc-supply = <&reg_vcc3v3>;
+       bus-width = <8>;
+       non-removable;
+       cap-mmc-hw-reset;
+       status = "okay";
+};
+
+&ohci1 {
+       status = "okay";
+};
+
+&ohci2 {
+       status = "okay";
+};
+
+&ohci3 {
+       status = "okay";
+};
+
+&uart0 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&uart0_pa_pins>;
+       status = "okay";
+};
+
+&usb_otg {
+       status = "okay";
+       dr_mode = "peripheral";
+};
+
+&usbphy {
+       status = "okay";
+};

diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
index 959d265..e37c30e 100644 (file)
--- a/arch/arm/boot/dts/sun8i-h3.dtsi
+++ b/arch/arm/boot/dts/sun8i-h3.dtsi
@@ -231,3 +231,7 @@
 &rtc {
        compatible = "allwinner,sun8i-h3-rtc";
 };
+
+&sid {
+       compatible = "allwinner,sun8i-h3-sid";
+};

diff --git a/arch/arm/boot/dts/sun8i-q8-common.dtsi b/arch/arm/boot/dts/sun8i-q8-common.dtsi
index 53104f4..3d9a152 100644 (file)
--- a/arch/arm/boot/dts/sun8i-q8-common.dtsi
+++ b/arch/arm/boot/dts/sun8i-q8-common.dtsi
@@ -54,16 +54,9 @@
                backlight = <&backlight>;
                enable-gpios = <&pio 7 7 GPIO_ACTIVE_HIGH>; /* PH7 */
                power-supply = <&reg_dc1sw>;
-               #address-cells = <1>;
-               #size-cells = <0>;
 
-               port@0 {
-                       reg = <0>;
-                       #address-cells = <1>;
-                       #size-cells = <0>;
-
-                       panel_input: endpoint@0 {
-                               reg = <0>;
+               port {
+                       panel_input: endpoint {
                                remote-endpoint = <&tcon0_out_lcd>;
                        };
                };
@@ -120,13 +113,6 @@
        status = "okay";
 };
 
-&tcon0_out {
-       tcon0_out_lcd: endpoint@0 {
-               reg = <0>;
-               remote-endpoint = <&panel_input>;
-       };
-};
-
 &usbphy {
        usb1_vbus-supply = <&reg_dldo1>;
 };

diff --git a/arch/arm/boot/dts/sun8i-r16-nintendo-nes-classic.dts b/arch/arm/boot/dts/sun8i-r16-nintendo-nes-classic.dts
index 32cf1ab..246dec5 100644 (file)
--- a/arch/arm/boot/dts/sun8i-r16-nintendo-nes-classic.dts
+++ b/arch/arm/boot/dts/sun8i-r16-nintendo-nes-classic.dts
@@ -34,8 +34,6 @@
 
        /* 2Gb Macronix MX30LF2G18AC (3V) */
        nand@0 {
-               #address-cells = <1>;
-               #size-cells = <1>;
                reg = <0>;
                allwinner,rb = <0>;
                nand-ecc-mode = "hw";

diff --git a/arch/arm/boot/dts/sun8i-r16-parrot.dts b/arch/arm/boot/dts/sun8i-r16-parrot.dts
index 316998e..4f48eec 100644 (file)
--- a/arch/arm/boot/dts/sun8i-r16-parrot.dts
+++ b/arch/arm/boot/dts/sun8i-r16-parrot.dts
@@ -158,14 +158,6 @@
        status = "okay";
 };
 
-&pio {
-       usb0_id_det: usb0-id-detect-pin {
-               pins = "PD10";
-               function = "gpio_in";
-               bias-pull-up;
-       };
-};
-
 &r_rsb {
        status = "okay";
 
@@ -314,10 +306,8 @@
 
 &usbphy {
        status = "okay";
-       pinctrl-names = "default";
-       pinctrl-0 = <&usb0_id_det>;
        usb0_vbus-supply = <&reg_drivevbus>;
-       usb0_id_det-gpios = <&pio 3 10 GPIO_ACTIVE_HIGH>; /* PD10 */
+       usb0_id_det-gpios = <&pio 3 10 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PD10 */
        usb0_vbus_power-supply = <&usb_power_supply>;
        usb1_vbus-supply = <&reg_usb1_vbus>;
 };

diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/boot/dts/sun8i-r40.dtsi
index 06b6858..bb856e5 100644 (file)
--- a/arch/arm/boot/dts/sun8i-r40.dtsi
+++ b/arch/arm/boot/dts/sun8i-r40.dtsi
@@ -273,7 +273,6 @@
                        clocks = <&ccu CLK_BUS_EHCI1>;
                        resets = <&ccu RST_BUS_EHCI1>;
                        phys = <&usbphy 1>;
-                       phy-names = "usb";
                        status = "disabled";
                };
 
@@ -285,7 +284,6 @@
                                 <&ccu CLK_USB_OHCI1>;
                        resets = <&ccu RST_BUS_OHCI1>;
                        phys = <&usbphy 1>;
-                       phy-names = "usb";
                        status = "disabled";
                };
 
@@ -296,7 +294,6 @@
                        clocks = <&ccu CLK_BUS_EHCI2>;
                        resets = <&ccu RST_BUS_EHCI2>;
                        phys = <&usbphy 2>;
-                       phy-names = "usb";
                        status = "disabled";
                };
 
@@ -308,7 +305,6 @@
                                 <&ccu CLK_USB_OHCI2>;
                        resets = <&ccu RST_BUS_OHCI2>;
                        phys = <&usbphy 2>;
-                       phy-names = "usb";
                        status = "disabled";
                };
 
@@ -562,9 +558,7 @@
                        interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
                        clocks = <&ccu CLK_BUS_SATA>, <&ccu CLK_SATA>;
                        resets = <&ccu RST_BUS_SATA>;
-                       resets-name = "ahci";
-                       #address-cells = <1>;
-                       #size-cells = <0>;
+                       reset-names = "ahci";
                        status = "disabled";
 
                };
@@ -614,12 +608,9 @@
                                #size-cells = <0>;
 
                                tcon_top_mixer0_in: port@0 {
-                                       #address-cells = <1>;
-                                       #size-cells = <0>;
                                        reg = <0>;
 
-                                       tcon_top_mixer0_in_mixer0: endpoint@0 {
-                                               reg = <0>;
+                                       tcon_top_mixer0_in_mixer0: endpoint {
                                                remote-endpoint = <&mixer0_out_tcon_top>;
                                        };
                                };

diff --git a/arch/arm/boot/dts/sun8i-reference-design-tablet.dtsi b/arch/arm/boot/dts/sun8i-reference-design-tablet.dtsi
index 189e479..b3d8b8f 100644 (file)
--- a/arch/arm/boot/dts/sun8i-reference-design-tablet.dtsi
+++ b/arch/arm/boot/dts/sun8i-reference-design-tablet.dtsi
@@ -86,14 +86,6 @@
        status = "okay";
 };
 
-&pio {
-       usb0_id_detect_pin: usb0-id-detect-pin {
-               pins = "PH8";
-               function = "gpio_in";
-               bias-pull-up;
-       };
-};
-
 &r_rsb {
        status = "okay";
 
@@ -224,9 +216,7 @@
 };
 
 &usbphy {
-       pinctrl-names = "default";
-       pinctrl-0 = <&usb0_id_detect_pin>;
-       usb0_id_det-gpio = <&pio 7 8 GPIO_ACTIVE_HIGH>; /* PH8 */
+       usb0_id_det-gpios = <&pio 7 8 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH8 */
        usb0_vbus_power-supply = <&usb_power_supply>;
        usb0_vbus-supply = <&reg_drivevbus>;
        status = "okay";

diff --git a/arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts b/arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts
index 99c8cf7..2e4587d 100644 (file)
--- a/arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts
+++ b/arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts
@@ -96,6 +96,6 @@
 };
 
 &usbphy {
-       usb0_id_det-gpio = <&pio 5 6 GPIO_ACTIVE_HIGH>;
+       usb0_id_det-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>;
        status = "okay";
 };

diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi b/arch/arm/boot/dts/sun8i-v3s.dtsi
index 21e1806..df72b17 100644 (file)
--- a/arch/arm/boot/dts/sun8i-v3s.dtsi
+++ b/arch/arm/boot/dts/sun8i-v3s.dtsi
@@ -129,12 +129,9 @@
                                #size-cells = <0>;
 
                                mixer0_out: port@1 {
-                                       #address-cells = <1>;
-                                       #size-cells = <0>;
                                        reg = <1>;
 
-                                       mixer0_out_tcon0: endpoint@0 {
-                                               reg = <0>;
+                                       mixer0_out_tcon0: endpoint {
                                                remote-endpoint = <&tcon0_in_mixer0>;
                                        };
                                };
@@ -150,6 +147,7 @@
                        clock-names = "ahb",
                                      "tcon-ch0";
                        clock-output-names = "tcon-pixel-clock";
+                       #clock-cells = <0>;
                        resets = <&ccu RST_BUS_TCON0>;
                        reset-names = "lcd";
                        status = "disabled";
@@ -159,12 +157,9 @@
                                #size-cells = <0>;
 
                                tcon0_in: port@0 {
-                                       #address-cells = <1>;
-                                       #size-cells = <0>;
                                        reg = <0>;
 
-                                       tcon0_in_mixer0: endpoint@0 {
-                                               reg = <0>;
+                                       tcon0_in_mixer0: endpoint {
                                                remote-endpoint = <&mixer0_out_tcon0>;
                                        };
                                };
@@ -419,7 +414,7 @@
                };
 
                gic: interrupt-controller@1c81000 {
-                       compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
+                       compatible = "arm,gic-400";
                        reg = <0x01c81000 0x1000>,
                              <0x01c82000 0x1000>,
                              <0x01c84000 0x2000>,

diff --git a/arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts b/arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts
index bf97f62..f05cabd 100644 (file)
--- a/arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts
+++ b/arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts
@@ -105,6 +105,24 @@
 
 #include "axp22x.dtsi"
 
+&mmc0 {
+       vmmc-supply = <&reg_dcdc1>;
+       bus-width = <4>;
+       cd-gpios = <&pio 7 13 GPIO_ACTIVE_LOW>; /* PH13 */
+       status = "okay";
+};
+
+&mmc1 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&mmc1_pg_pins>;
+       vmmc-supply = <&reg_dldo2>;
+       vqmmc-supply = <&reg_dldo1>;
+       mmc-pwrseq = <&wifi_pwrseq>;
+       bus-width = <4>;
+       non-removable;
+       status = "okay";
+};
+
 &reg_aldo3 {
        regulator-always-on;
        regulator-min-microvolt = <2700000>;
@@ -152,24 +170,6 @@
        regulator-name = "vcc-wifi";
 };
 
-&mmc0 {
-       vmmc-supply = <&reg_dcdc1>;
-       bus-width = <4>;
-       cd-gpios = <&pio 7 13 GPIO_ACTIVE_LOW>; /* PH13 */
-       status = "okay";
-};
-
-&mmc1 {
-       pinctrl-names = "default";
-       pinctrl-0 = <&mmc1_pg_pins>;
-       vmmc-supply = <&reg_dldo2>;
-       vqmmc-supply = <&reg_dldo1>;
-       mmc-pwrseq = <&wifi_pwrseq>;
-       bus-width = <4>;
-       non-removable;
-       status = "okay";
-};
-
 &uart0 {
        pinctrl-names = "default";
        pinctrl-0 = <&uart0_pb_pins>;

diff --git a/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts b/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts
index 28c0349..18156ff 100644 (file)
--- a/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts
+++ b/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts
@@ -89,31 +89,23 @@
        vga-dac {
                compatible = "corpro,gm7123", "adi,adv7123", "dumb-vga-dac";
                vdd-supply = <&reg_dcdc1>;
-               #address-cells = <1>;
-               #size-cells = <0>;
 
                ports {
                        #address-cells = <1>;
                        #size-cells = <0>;
 
                        port@0 {
-                               #address-cells = <1>;
-                               #size-cells = <0>;
                                reg = <0>;
 
-                               vga_dac_in: endpoint@0 {
-                                       reg = <0>;
+                               vga_dac_in: endpoint {
                                        remote-endpoint = <&tcon0_out_vga>;
                                };
                        };
 
                        port@1 {
-                               #address-cells = <1>;
-                               #size-cells = <0>;
                                reg = <1>;
 
-                               vga_dac_out: endpoint@0 {
-                                       reg = <0>;
+                               vga_dac_out: endpoint {
                                        remote-endpoint = <&vga_con_in>;
                                };
                        };
@@ -502,8 +494,7 @@
 };
 
 &tcon0_out {
-       tcon0_out_vga: endpoint@0 {
-               reg = <0>;
+       tcon0_out_vga: endpoint {
                remote-endpoint = <&vga_dac_in>;
        };
 };

diff --git a/arch/arm/boot/dts/sun9i-a80-optimus.dts b/arch/arm/boot/dts/sun9i-a80-optimus.dts
index 864715e..2ed28d9 100644 (file)
--- a/arch/arm/boot/dts/sun9i-a80-optimus.dts
+++ b/arch/arm/boot/dts/sun9i-a80-optimus.dts
@@ -82,7 +82,7 @@
 
        reg_usb1_vbus: usb1-vbus {
                compatible = "regulator-fixed";
-               pinctrl-names = "default";
+               regulator-name = "usb1-vbus";
                regulator-min-microvolt = <5000000>;
                regulator-max-microvolt = <5000000>;
                enable-active-high;
@@ -91,7 +91,7 @@
 
        reg_usb3_vbus: usb3-vbus {
                compatible = "regulator-fixed";
-               pinctrl-names = "default";
+               regulator-name = "usb3-vbus";
                regulator-min-microvolt = <5000000>;
                regulator-max-microvolt = <5000000>;
                enable-active-high;

diff --git a/arch/arm/boot/dts/sun9i-a80.dtsi b/arch/arm/boot/dts/sun9i-a80.dtsi
index 6fb292e..0c1eec9 100644 (file)
--- a/arch/arm/boot/dts/sun9i-a80.dtsi
+++ b/arch/arm/boot/dts/sun9i-a80.dtsi
@@ -289,7 +289,7 @@
                status = "disabled";
        };
 
-       soc {
+       soc@20000 {
                compatible = "simple-bus";
                #address-cells = <1>;
                #size-cells = <1>;
@@ -342,7 +342,6 @@
                        clocks = <&usb_clocks CLK_BUS_HCI0>;
                        resets = <&usb_clocks RST_USB0_HCI>;
                        phys = <&usbphy1>;
-                       phy-names = "usb";
                        status = "disabled";
                };
 
@@ -354,7 +353,6 @@
                                 <&usb_clocks CLK_USB_OHCI0>;
                        resets = <&usb_clocks RST_USB0_HCI>;
                        phys = <&usbphy1>;
-                       phy-names = "usb";
                        status = "disabled";
                };
 
@@ -376,7 +374,6 @@
                        clocks = <&usb_clocks CLK_BUS_HCI1>;
                        resets = <&usb_clocks RST_USB1_HCI>;
                        phys = <&usbphy2>;
-                       phy-names = "usb";
                        status = "disabled";
                };
 
@@ -406,7 +403,6 @@
                        clocks = <&usb_clocks CLK_BUS_HCI2>;
                        resets = <&usb_clocks RST_USB2_HCI>;
                        phys = <&usbphy3>;
-                       phy-names = "usb";
                        status = "disabled";
                };
 
@@ -418,7 +414,6 @@
                                 <&usb_clocks CLK_USB_OHCI2>;
                        resets = <&usb_clocks RST_USB2_HCI>;
                        phys = <&usbphy3>;
-                       phy-names = "usb";
                        status = "disabled";
                };
 
@@ -527,7 +522,7 @@
                };
 
                gic: interrupt-controller@1c41000 {
-                       compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
+                       compatible = "arm,gic-400";
                        reg = <0x01c41000 0x1000>,
                              <0x01c42000 0x2000>,
                              <0x01c44000 0x2000>,
@@ -596,12 +591,9 @@
                                #size-cells = <0>;
 
                                fe0_out: port@1 {
-                                       #address-cells = <1>;
-                                       #size-cells = <0>;
                                        reg = <1>;
 
-                                       fe0_out_deu0: endpoint@0 {
-                                               reg = <0>;
+                                       fe0_out_deu0: endpoint {
                                                remote-endpoint = <&deu0_in_fe0>;
                                        };
                                };
@@ -623,12 +615,9 @@
                                #size-cells = <0>;
 
                                fe1_out: port@1 {
-                                       #address-cells = <1>;
-                                       #size-cells = <0>;
                                        reg = <1>;
 
-                                       fe1_out_deu1: endpoint@0 {
-                                               reg = <0>;
+                                       fe1_out_deu1: endpoint {
                                                remote-endpoint = <&deu1_in_fe1>;
                                        };
                                };
@@ -666,12 +655,9 @@
                                };
 
                                be0_out: port@1 {
-                                       #address-cells = <1>;
-                                       #size-cells = <0>;
                                        reg = <1>;
 
-                                       be0_out_drc0: endpoint@0 {
-                                               reg = <0>;
+                                       be0_out_drc0: endpoint {
                                                remote-endpoint = <&drc0_in_be0>;
                                        };
                                };
@@ -709,12 +695,9 @@
                                };
 
                                be1_out: port@1 {
-                                       #address-cells = <1>;
-                                       #size-cells = <0>;
                                        reg = <1>;
 
-                                       be1_out_drc1: endpoint@0 {
-                                               reg = <0>;
+                                       be1_out_drc1: endpoint {
                                                remote-endpoint = <&drc1_in_be1>;
                                        };
                                };
@@ -738,12 +721,9 @@
                                #size-cells = <0>;
 
                                deu0_in: port@0 {
-                                       #address-cells = <1>;
-                                       #size-cells = <0>;
                                        reg = <0>;
 
-                                       deu0_in_fe0: endpoint@0 {
-                                               reg = <0>;
+                                       deu0_in_fe0: endpoint {
                                                remote-endpoint = <&fe0_out_deu0>;
                                        };
                                };
@@ -783,12 +763,9 @@
                                #size-cells = <0>;
 
                                deu1_in: port@0 {
-                                       #address-cells = <1>;
-                                       #size-cells = <0>;
                                        reg = <0>;
 
-                                       deu1_in_fe1: endpoint@0 {
-                                               reg = <0>;
+                                       deu1_in_fe1: endpoint {
                                                remote-endpoint = <&fe1_out_deu1>;
                                        };
                                };
@@ -828,23 +805,17 @@
                                #size-cells = <0>;
 
                                drc0_in: port@0 {
-                                       #address-cells = <1>;
-                                       #size-cells = <0>;
                                        reg = <0>;
 
-                                       drc0_in_be0: endpoint@0 {
-                                               reg = <0>;
+                                       drc0_in_be0: endpoint {
                                                remote-endpoint = <&be0_out_drc0>;
                                        };
                                };
 
                                drc0_out: port@1 {
-                                       #address-cells = <1>;
-                                       #size-cells = <0>;
                                        reg = <1>;
 
-                                       drc0_out_tcon0: endpoint@0 {
-                                               reg = <0>;
+                                       drc0_out_tcon0: endpoint {
                                                remote-endpoint = <&tcon0_in_drc0>;
                                        };
                                };
@@ -868,23 +839,17 @@
                                #size-cells = <0>;
 
                                drc1_in: port@0 {
-                                       #address-cells = <1>;
-                                       #size-cells = <0>;
                                        reg = <0>;
 
-                                       drc1_in_be1: endpoint@0 {
-                                               reg = <0>;
+                                       drc1_in_be1: endpoint {
                                                remote-endpoint = <&be1_out_drc1>;
                                        };
                                };
 
                                drc1_out: port@1 {
-                                       #address-cells = <1>;
-                                       #size-cells = <0>;
                                        reg = <1>;
 
-                                       drc1_out_tcon1: endpoint@0 {
-                                               reg = <0>;
+                                       drc1_out_tcon1: endpoint {
                                                remote-endpoint = <&tcon1_in_drc1>;
                                        };
                                };
@@ -900,25 +865,21 @@
                        resets = <&ccu RST_BUS_LCD0>, <&ccu RST_BUS_EDP>;
                        reset-names = "lcd", "edp";
                        clock-output-names = "tcon0-pixel-clock";
+                       #clock-cells = <0>;
 
                        ports {
                                #address-cells = <1>;
                                #size-cells = <0>;
 
                                tcon0_in: port@0 {
-                                       #address-cells = <1>;
-                                       #size-cells = <0>;
                                        reg = <0>;
 
-                                       tcon0_in_drc0: endpoint@0 {
-                                               reg = <0>;
+                                       tcon0_in_drc0: endpoint {
                                                remote-endpoint = <&drc0_out_tcon0>;
                                        };
                                };
 
                                tcon0_out: port@1 {
-                                       #address-cells = <1>;
-                                       #size-cells = <0>;
                                        reg = <1>;
                                };
                        };
@@ -938,19 +899,14 @@
                                #size-cells = <0>;
 
                                tcon1_in: port@0 {
-                                       #address-cells = <1>;
-                                       #size-cells = <0>;
                                        reg = <0>;
 
-                                       tcon1_in_drc1: endpoint@0 {
-                                               reg = <0>;
+                                       tcon1_in_drc1: endpoint {
                                                remote-endpoint = <&drc1_out_tcon1>;
                                        };
                                };
 
                                tcon1_out: port@1 {
-                                       #address-cells = <1>;
-                                       #size-cells = <0>;
                                        reg = <1>;
                                };
                        };
@@ -997,15 +953,13 @@
                        gpio-controller;
                        interrupt-controller;
                        #interrupt-cells = <3>;
-                       #size-cells = <0>;
                        #gpio-cells = <3>;
 
                        gmac_rgmii_pins: gmac-rgmii-pins {
-                               allwinner,pins = "PA0", "PA1", "PA2", "PA3",
-                                                "PA4", "PA5", "PA7", "PA8",
-                                                "PA9", "PA10", "PA12", "PA13",
-                                                "PA15", "PA16", "PA17";
-                               allwinner,function = "gmac";
+                               pins = "PA0", "PA1", "PA2", "PA3", "PA4", "PA5",
+                                      "PA7", "PA8", "PA9", "PA10", "PA12",
+                                      "PA13", "PA15", "PA16", "PA17";
+                               function = "gmac";
                                /*
                                 * data lines in RGMII mode use DDR mode
                                 * and need a higher signal drive strength

diff --git a/arch/arm/boot/dts/sunxi-bananapi-m2-plus.dtsi b/arch/arm/boot/dts/sunxi-bananapi-m2-plus.dtsi
index 3bed375..39263e7 100644 (file)
--- a/arch/arm/boot/dts/sunxi-bananapi-m2-plus.dtsi
+++ b/arch/arm/boot/dts/sunxi-bananapi-m2-plus.dtsi
@@ -69,7 +69,6 @@
 
        leds {
                compatible = "gpio-leds";
-               pinctrl-names = "default";
 
                pwr_led {
                        label = "bananapi-m2-plus:red:pwr";
@@ -80,7 +79,6 @@
 
        gpio_keys {
                compatible = "gpio-keys";
-               pinctrl-names = "default";
 
                sw4 {
                        label = "power";
@@ -101,7 +99,6 @@
 
        wifi_pwrseq: wifi_pwrseq {
                compatible = "mmc-pwrseq-simple";
-               pinctrl-names = "default";
                reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */
                clocks = <&rtc 1>;
                clock-names = "ext_clock";
@@ -153,7 +150,7 @@
 
 &ir {
        pinctrl-names = "default";
-       pinctrl-0 = <&ir_pins_a>;
+       pinctrl-0 = <&r_ir_rx_pin>;
        status = "okay";
 };
 
@@ -210,7 +207,7 @@
 
 &uart0 {
        pinctrl-names = "default";
-       pinctrl-0 = <&uart0_pins_a>;
+       pinctrl-0 = <&uart0_pa_pins>;
        status = "okay";
 };
 

diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
index d74a6cb..84977d4 100644 (file)
--- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi
+++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
@@ -227,6 +227,11 @@
                        #size-cells = <0>;
                };
 
+               sid: eeprom@1c14000 {
+                       /* compatible is in per SoC .dtsi file */
+                       reg = <0x1c14000 0x400>;
+               };
+
                usb_otg: usb@1c19000 {
                        compatible = "allwinner,sun8i-h3-musb";
                        reg = <0x01c19000 0x400>;
@@ -237,6 +242,7 @@
                        phys = <&usbphy 0>;
                        phy-names = "usb";
                        extcon = <&usbphy 0>;
+                       dr_mode = "otg";
                        status = "disabled";
                };
 
@@ -298,7 +304,6 @@
                        clocks = <&ccu CLK_BUS_EHCI1>, <&ccu CLK_BUS_OHCI1>;
                        resets = <&ccu RST_BUS_EHCI1>, <&ccu RST_BUS_OHCI1>;
                        phys = <&usbphy 1>;
-                       phy-names = "usb";
                        status = "disabled";
                };
 
@@ -310,7 +315,6 @@
                                 <&ccu CLK_USB_OHCI1>;
                        resets = <&ccu RST_BUS_EHCI1>, <&ccu RST_BUS_OHCI1>;
                        phys = <&usbphy 1>;
-                       phy-names = "usb";
                        status = "disabled";
                };
 
@@ -321,7 +325,6 @@
                        clocks = <&ccu CLK_BUS_EHCI2>, <&ccu CLK_BUS_OHCI2>;
                        resets = <&ccu RST_BUS_EHCI2>, <&ccu RST_BUS_OHCI2>;
                        phys = <&usbphy 2>;
-                       phy-names = "usb";
                        status = "disabled";
                };
 
@@ -333,7 +336,6 @@
                                 <&ccu CLK_USB_OHCI2>;
                        resets = <&ccu RST_BUS_EHCI2>, <&ccu RST_BUS_OHCI2>;
                        phys = <&usbphy 2>;
-                       phy-names = "usb";
                        status = "disabled";
                };
 
@@ -344,7 +346,6 @@
                        clocks = <&ccu CLK_BUS_EHCI3>, <&ccu CLK_BUS_OHCI3>;
                        resets = <&ccu RST_BUS_EHCI3>, <&ccu RST_BUS_OHCI3>;
                        phys = <&usbphy 3>;
-                       phy-names = "usb";
                        status = "disabled";
                };
 
@@ -356,7 +357,6 @@
                                 <&ccu CLK_USB_OHCI3>;
                        resets = <&ccu RST_BUS_EHCI3>, <&ccu RST_BUS_OHCI3>;
                        phys = <&usbphy 3>;
-                       phy-names = "usb";
                        status = "disabled";
                };
 
@@ -381,14 +381,14 @@
                        interrupt-controller;
                        #interrupt-cells = <3>;
 
-                       csi_pins: csi {
+                       csi_pins: csi-pins {
                                pins = "PE0", "PE2", "PE3", "PE4", "PE5",
                                       "PE6", "PE7", "PE8", "PE9", "PE10",
                                       "PE11";
                                function = "csi";
                        };
 
-                       emac_rgmii_pins: emac0 {
+                       emac_rgmii_pins: emac-rgmii-pins {
                                pins = "PD0", "PD1", "PD2", "PD3", "PD4",
                                       "PD5", "PD7", "PD8", "PD9", "PD10",
                                       "PD12", "PD13", "PD15", "PD16", "PD17";
@@ -396,22 +396,22 @@
                                drive-strength = <40>;
                        };
 
-                       i2c0_pins: i2c0 {
+                       i2c0_pins: i2c0-pins {
                                pins = "PA11", "PA12";
                                function = "i2c0";
                        };
 
-                       i2c1_pins: i2c1 {
+                       i2c1_pins: i2c1-pins {
                                pins = "PA18", "PA19";
                                function = "i2c1";
                        };
 
-                       i2c2_pins: i2c2 {
+                       i2c2_pins: i2c2-pins {
                                pins = "PE12", "PE13";
                                function = "i2c2";
                        };
 
-                       mmc0_pins: mmc0 {
+                       mmc0_pins: mmc0-pins {
                                pins = "PF0", "PF1", "PF2", "PF3",
                                       "PF4", "PF5";
                                function = "mmc0";
@@ -419,7 +419,7 @@
                                bias-pull-up;
                        };
 
-                       mmc1_pins: mmc1 {
+                       mmc1_pins: mmc1-pins {
                                pins = "PG0", "PG1", "PG2", "PG3",
                                       "PG4", "PG5";
                                function = "mmc1";
@@ -427,7 +427,7 @@
                                bias-pull-up;
                        };
 
-                       mmc2_8bit_pins: mmc2_8bit {
+                       mmc2_8bit_pins: mmc2-8bit-pins {
                                pins = "PC5", "PC6", "PC8",
                                       "PC9", "PC10", "PC11",
                                       "PC12", "PC13", "PC14",
@@ -437,47 +437,47 @@
                                bias-pull-up;
                        };
 
-                       spdif_tx_pins_a: spdif {
+                       spdif_tx_pin: spdif-tx-pin {
                                pins = "PA17";
                                function = "spdif";
                        };
 
-                       spi0_pins: spi0 {
+                       spi0_pins: spi0-pins {
                                pins = "PC0", "PC1", "PC2", "PC3";
                                function = "spi0";
                        };
 
-                       spi1_pins: spi1 {
+                       spi1_pins: spi1-pins {
                                pins = "PA15", "PA16", "PA14", "PA13";
                                function = "spi1";
                        };
 
-                       uart0_pins_a: uart0 {
+                       uart0_pa_pins: uart0-pa-pins {
                                pins = "PA4", "PA5";
                                function = "uart0";
                        };
 
-                       uart1_pins: uart1 {
+                       uart1_pins: uart1-pins {
                                pins = "PG6", "PG7";
                                function = "uart1";
                        };
 
-                       uart1_rts_cts_pins: uart1_rts_cts {
+                       uart1_rts_cts_pins: uart1-rts-cts-pins {
                                pins = "PG8", "PG9";
                                function = "uart1";
                        };
 
-                       uart2_pins: uart2 {
+                       uart2_pins: uart2-pins {
                                pins = "PA0", "PA1";
                                function = "uart2";
                        };
 
-                       uart3_pins: uart3 {
+                       uart3_pins: uart3-pins {
                                pins = "PA13", "PA14";
                                function = "uart3";
                        };
 
-                       uart3_rts_cts_pins: uart3_rts_cts {
+                       uart3_rts_cts_pins: uart3-rts-cts-pins {
                                pins = "PA15", "PA16";
                                function = "uart3";
                        };
@@ -855,12 +855,12 @@
                        interrupt-controller;
                        #interrupt-cells = <3>;
 
-                       ir_pins_a: ir {
+                       r_ir_rx_pin: r-ir-rx-pin {
                                pins = "PL11";
                                function = "s_cir_rx";
                        };
 
-                       r_i2c_pins: r-i2c {
+                       r_i2c_pins: r-i2c-pins {
                                pins = "PL0", "PL1";
                                function = "s_i2c";
                        };

diff --git a/arch/arm/boot/dts/sunxi-libretech-all-h3-cc.dtsi b/arch/arm/boot/dts/sunxi-libretech-all-h3-cc.dtsi
index 1eadc13..19b3b23 100644 (file)
--- a/arch/arm/boot/dts/sunxi-libretech-all-h3-cc.dtsi
+++ b/arch/arm/boot/dts/sunxi-libretech-all-h3-cc.dtsi
@@ -167,7 +167,7 @@
 
 &ir {
        pinctrl-names = "default";
-       pinctrl-0 = <&ir_pins_a>;
+       pinctrl-0 = <&r_ir_rx_pin>;
        status = "okay";
 };
 
@@ -205,7 +205,7 @@
 
 &uart0 {
        pinctrl-names = "default";
-       pinctrl-0 = <&uart0_pins_a>;
+       pinctrl-0 = <&uart0_pa_pins>;
        status = "okay";
 };
 

diff --git a/arch/arm/boot/dts/tegra124-apalis-emc.dtsi b/arch/arm/boot/dts/tegra124-apalis-emc.dtsi
index ca2c3a5..d18eaf4 100644 (file)
--- a/arch/arm/boot/dts/tegra124-apalis-emc.dtsi
+++ b/arch/arm/boot/dts/tegra124-apalis-emc.dtsi
@@ -1,42 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0 OR X11
 /*
- * Copyright 2016 Toradex AG
+ * Copyright 2016-2019 Toradex AG
  *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- *  a) This file is free software; you can redistribute it and/or
- *     modify it under the terms of the GNU General Public License
- *     version 2 as published by the Free Software Foundation.
- *
- *     This file is distributed in the hope that it will be useful
- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *     GNU General Public License for more details.
- *
- * Or, alternatively
- *
- *  b) Permission is hereby granted, free of charge, to any person
- *     obtaining a copy of this software and associated documentation
- *     files (the "Software"), to deal in the Software without
- *     restriction, including without limitation the rights to use
- *     copy, modify, merge, publish, distribute, sublicense, and/or
- *     sell copies of the Software, and to permit persons to whom the
- *     Software is furnished to do so, subject to the following
- *     conditions:
- *
- *     The above copyright notice and this permission notice shall be
- *     included in all copies or substantial portions of the Software.
- *
- *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- *     OTHER DEALINGS IN THE SOFTWARE.
  */
 
 / {

diff --git a/arch/arm/boot/dts/tegra124-apalis-eval.dts b/arch/arm/boot/dts/tegra124-apalis-eval.dts
index eaee10e..ceb3f63 100644 (file)
--- a/arch/arm/boot/dts/tegra124-apalis-eval.dts
+++ b/arch/arm/boot/dts/tegra124-apalis-eval.dts
@@ -1,42 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0 OR X11
 /*
- * Copyright 2016-2018 Toradex AG
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- *  a) This file is free software; you can redistribute it and/or
- *     modify it under the terms of the GNU General Public License
- *     version 2 as published by the Free Software Foundation.
- *
- *     This file is distributed in the hope that it will be useful
- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *     GNU General Public License for more details.
- *
- * Or, alternatively
- *
- *  b) Permission is hereby granted, free of charge, to any person
- *     obtaining a copy of this software and associated documentation
- *     files (the "Software"), to deal in the Software without
- *     restriction, including without limitation the rights to use
- *     copy, modify, merge, publish, distribute, sublicense, and/or
- *     sell copies of the Software, and to permit persons to whom the
- *     Software is furnished to do so, subject to the following
- *     conditions:
- *
- *     The above copyright notice and this permission notice shall be
- *     included in all copies or substantial portions of the Software.
- *
- *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- *     OTHER DEALINGS IN THE SOFTWARE.
+ * Copyright 2016-2019 Toradex AG
  */
 
 /dts-v1/;

diff --git a/arch/arm/boot/dts/tegra124-apalis-v1.2-eval.dts b/arch/arm/boot/dts/tegra124-apalis-v1.2-eval.dts
index 7961eb4..826b776 100644 (file)
--- a/arch/arm/boot/dts/tegra124-apalis-v1.2-eval.dts
+++ b/arch/arm/boot/dts/tegra124-apalis-v1.2-eval.dts
@@ -1,4 +1,4 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+// SPDX-License-Identifier: GPL-2.0 OR MIT
 /*
  * Copyright 2016-2018 Toradex AG
  */

diff --git a/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi b/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi
index 367eb8c..0462ed2 100644 (file)
--- a/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi
+++ b/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi
@@ -1,4 +1,4 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+// SPDX-License-Identifier: GPL-2.0 OR MIT
 /*
  * Copyright 2016-2018 Toradex AG
  */
@@ -17,6 +17,7 @@
 
        pcie@1003000 {
                status = "okay";
+
                avddio-pex-supply = <&reg_1v05_vdd>;
                avdd-pex-pll-supply = <&reg_1v05_vdd>;
                avdd-pll-erefe-supply = <&reg_1v05_avdd>;
@@ -1796,6 +1797,7 @@
                       <&{/padctl@7009f000/pads/usb2/lanes/usb2-2}>,
                       <&{/padctl@7009f000/pads/pcie/lanes/pcie-0}>;
                phy-names = "usb2-0", "usb3-1", "usb2-1", "usb2-2", "usb3-0";
+
                avddio-pex-supply = <&reg_1v05_vdd>;
                avdd-pll-erefe-supply = <&reg_1v05_avdd>;
                avdd-pll-utmip-supply = <&reg_1v8_vddio>;
@@ -1807,6 +1809,11 @@
        };
 
        padctl@7009f000 {
+               avdd-pll-utmip-supply = <&reg_1v8_vddio>;
+               avdd-pll-erefe-supply = <&reg_1v05_avdd>;
+               avdd-pex-pll-supply = <&reg_1v05_vdd>;
+               hvdd-pex-pll-e-supply = <&reg_module_3v3>;
+
                pads {
                        usb2 {
                                status = "okay";

diff --git a/arch/arm/boot/dts/tegra124-apalis.dtsi b/arch/arm/boot/dts/tegra124-apalis.dtsi
index 13c93cd..d1e8593 100644 (file)
--- a/arch/arm/boot/dts/tegra124-apalis.dtsi
+++ b/arch/arm/boot/dts/tegra124-apalis.dtsi
@@ -1,42 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0 OR X11
 /*
- * Copyright 2016-2018 Toradex AG
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- *  a) This file is free software; you can redistribute it and/or
- *     modify it under the terms of the GNU General Public License
- *     version 2 as published by the Free Software Foundation.
- *
- *     This file is distributed in the hope that it will be useful
- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *     GNU General Public License for more details.
- *
- * Or, alternatively
- *
- *  b) Permission is hereby granted, free of charge, to any person
- *     obtaining a copy of this software and associated documentation
- *     files (the "Software"), to deal in the Software without
- *     restriction, including without limitation the rights to use
- *     copy, modify, merge, publish, distribute, sublicense, and/or
- *     sell copies of the Software, and to permit persons to whom the
- *     Software is furnished to do so, subject to the following
- *     conditions:
- *
- *     The above copyright notice and this permission notice shall be
- *     included in all copies or substantial portions of the Software.
- *
- *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- *     OTHER DEALINGS IN THE SOFTWARE.
+ * Copyright 2016-2019 Toradex AG
  */
 
 #include "tegra124.dtsi"
@@ -1837,6 +1801,11 @@
        };
 
        padctl@7009f000 {
+               avdd-pll-utmip-supply = <&reg_1v8_vddio>;
+               avdd-pll-erefe-supply = <&reg_1v05_avdd>;
+               avdd-pex-pll-supply = <&reg_1v05_vdd>;
+               hvdd-pex-pll-e-supply = <&reg_module_3v3>;
+
                pads {
                        usb2 {
                                status = "okay";

diff --git a/arch/arm/boot/dts/tegra124-jetson-tk1.dts b/arch/arm/boot/dts/tegra124-jetson-tk1.dts
index 33bbb1c..d5fd642 100644 (file)
--- a/arch/arm/boot/dts/tegra124-jetson-tk1.dts
+++ b/arch/arm/boot/dts/tegra124-jetson-tk1.dts
@@ -1721,6 +1721,11 @@
        padctl@7009f000 {
                status = "okay";
 
+               avdd-pll-utmip-supply = <&vddio_1v8>;
+               avdd-pll-erefe-supply = <&avdd_1v05_run>;
+               avdd-pex-pll-supply = <&vdd_1v05_run>;
+               hvdd-pex-pll-e-supply = <&vdd_3v3_lp0>;
+
                pads {
                        usb2 {
                                status = "okay";

diff --git a/arch/arm/boot/dts/tegra124-nyan.dtsi b/arch/arm/boot/dts/tegra124-nyan.dtsi
index a1acd87..3b10f47 100644 (file)
--- a/arch/arm/boot/dts/tegra124-nyan.dtsi
+++ b/arch/arm/boot/dts/tegra124-nyan.dtsi
@@ -414,6 +414,11 @@
        padctl@7009f000 {
                status = "okay";
 
+               avdd-pll-utmip-supply = <&vddio_1v8>;
+               avdd-pll-erefe-supply = <&avdd_1v05_run>;
+               avdd-pex-pll-supply = <&vdd_1v05_run>;
+               hvdd-pex-pll-e-supply = <&vdd_3v3_lp0>;
+
                pads {
                        usb2 {
                                status = "okay";

diff --git a/arch/arm/boot/dts/tegra124-venice2.dts b/arch/arm/boot/dts/tegra124-venice2.dts
index 4882b61..5d5e6e1 100644 (file)
--- a/arch/arm/boot/dts/tegra124-venice2.dts
+++ b/arch/arm/boot/dts/tegra124-venice2.dts
@@ -921,6 +921,11 @@
        };
 
        padctl@7009f000 {
+               avdd-pll-utmip-supply = <&vddio_1v8>;
+               avdd-pll-erefe-supply = <&avdd_1v05_run>;
+               avdd-pex-pll-supply = <&vdd_1v05_run>;
+               hvdd-pex-pll-e-supply = <&vdd_3v3_lp0>;
+
                pads {
                        usb2 {
                                status = "okay";

diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
index d2b553f..e074258 100644 (file)
--- a/arch/arm/boot/dts/tegra30.dtsi
+++ b/arch/arm/boot/dts/tegra30.dtsi
@@ -370,6 +370,17 @@
                reg = <0x6000c000 0x150>; /* AHB Arbitration + Gizmo Controller */
        };
 
+       actmon@6000c800 {
+               compatible = "nvidia,tegra30-actmon";
+               reg = <0x6000c800 0x400>;
+               interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&tegra_car TEGRA30_CLK_ACTMON>,
+                        <&tegra_car TEGRA30_CLK_EMC>;
+               clock-names = "actmon", "emc";
+               resets = <&tegra_car TEGRA30_CLK_ACTMON>;
+               reset-names = "actmon";
+       };
+
        gpio: gpio@6000d000 {
                compatible = "nvidia,tegra30-gpio";
                reg = <0x6000d000 0x1000>;

diff --git a/arch/arm/boot/dts/vf610-zii-cfu1.dts b/arch/arm/boot/dts/vf610-zii-cfu1.dts
index 445c7dc..9466913 100644 (file)
--- a/arch/arm/boot/dts/vf610-zii-cfu1.dts
+++ b/arch/arm/boot/dts/vf610-zii-cfu1.dts
@@ -29,35 +29,30 @@
                        label = "zii:green:debug1";
                        gpios = <&gpio2 18 GPIO_ACTIVE_HIGH>;
                        linux,default-trigger = "heartbeat";
-                       max-brightness = <1>;
                };
 
                led-fail {
                        label = "zii:red:fail";
                        gpios = <&gpio3 12 GPIO_ACTIVE_LOW>;
                        default-state = "off";
-                       max-brightness = <1>;
                };
 
                led-status {
                        label = "zii:green:status";
                        gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;
                        default-state = "off";
-                       max-brightness = <1>;
                };
 
                led-debug-a {
                        label = "zii:green:debug_a";
                        gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>;
                        default-state = "off";
-                       max-brightness = <1>;
                };
 
                led-debug-b {
                        label = "zii:green:debug_b";
                        gpios = <&gpio3 15 GPIO_ACTIVE_HIGH>;
                        default-state = "off";
-                       max-brightness = <1>;
                };
        };
 
@@ -92,9 +87,14 @@
        bus-num = <1>;
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_dspi1>;
-       status = "okay";
-
-       m25p128@0 {
+       /*
+        * Some CFU1s come with SPI-NOR chip DNPed, so we leave this
+        * node disabled by default and rely on bootloader to enable
+        * it when appropriate.
+        */
+       status = "disabled";
+
+       flash@0 {
                #address-cells = <1>;
                #size-cells = <1>;
                compatible = "m25p128", "jedec,spi-nor";
@@ -212,7 +212,7 @@
        pinctrl-0 = <&pinctrl_i2c0>;
        status = "okay";
 
-       pca9554@22 {
+       io-expander@22 {
                compatible = "nxp,pca9554";
                reg = <0x22>;
                gpio-controller;
@@ -223,19 +223,23 @@
                reg = <0x48>;
        };
 
-       at24c04@52 {
+       eeprom@52 {
                compatible = "atmel,24c04";
                reg = <0x52>;
                label = "nvm";
        };
 
-       at24c04@54 {
+       eeprom@54 {
                compatible = "atmel,24c04";
                reg = <0x54>;
                label = "nameplate";
        };
 };
 
+&snvsrtc {
+       status = "disabled";
+};
+
 &uart0 {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_uart0>;

diff --git a/arch/arm/boot/dts/vf610-zii-dev-rev-b.dts b/arch/arm/boot/dts/vf610-zii-dev-rev-b.dts
index bd79e00..48086c5 100644 (file)
--- a/arch/arm/boot/dts/vf610-zii-dev-rev-b.dts
+++ b/arch/arm/boot/dts/vf610-zii-dev-rev-b.dts
@@ -1,45 +1,6 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
 /*
  * Copyright (C) 2015, 2016 Zodiac Inflight Innovations
- *
- * Based on an original 'vf610-twr.dts' which is Copyright 2015,
- * Freescale Semiconductor, Inc.
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- *  a) This file is free software; you can redistribute it and/or
- *     modify it under the terms of the GNU General Public License
- *     version 2 as published by the Free Software Foundation.
- *
- *     This file is distributed in the hope that it will be useful,
- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *     GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- *  b) Permission is hereby granted, free of charge, to any person
- *     obtaining a copy of this software and associated documentation
- *     files (the "Software"), to deal in the Software without
- *     restriction, including without limitation the rights to use,
- *     copy, modify, merge, publish, distribute, sublicense, and/or
- *     sell copies of the Software, and to permit persons to whom the
- *     Software is furnished to do so, subject to the following
- *     conditions:
- *
- *     The above copyright notice and this permission notice shall be
- *     included in all copies or substantial portions of the Software.
- *
- *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- *     OTHER DEALINGS IN THE SOFTWARE.
  */
 
 /dts-v1/;
@@ -334,11 +295,11 @@
                gpio-sck  = <&gpio1 12 GPIO_ACTIVE_HIGH>;
                gpio-mosi = <&gpio1 11 GPIO_ACTIVE_HIGH>;
                gpio-miso = <&gpio1 10 GPIO_ACTIVE_HIGH>;
-               cs-gpios  = <&gpio1  9 GPIO_ACTIVE_HIGH
+               cs-gpios  = <&gpio1  9 GPIO_ACTIVE_LOW
                             &gpio1  8 GPIO_ACTIVE_HIGH>;
                num-chipselects = <2>;
 
-               m25p128@0 {
+               flash@0 {
                        compatible = "m25p128", "jedec,spi-nor";
                        #address-cells = <1>;
                        #size-cells = <1>;
@@ -367,7 +328,7 @@
        pinctrl-0 = <&pinctrl_i2c0>;
        status = "okay";
 
-       gpio5: pca9554@20 {
+       gpio5: io-expander@20 {
                compatible = "nxp,pca9554";
                reg = <0x20>;
                gpio-controller;
@@ -375,7 +336,7 @@
 
        };
 
-       gpio6: pca9554@22 {
+       gpio6: io-expander@22 {
                compatible = "nxp,pca9554";
                pinctrl-names = "default";
                pinctrl-0 = <&pinctrl_pca9554_22>;
@@ -408,7 +369,7 @@
                        #size-cells = <0>;
                        reg = <0>;
 
-                       sfp1: at24c04@50 {
+                       sfp1: eeprom@50 {
                                compatible = "atmel,24c02";
                                reg = <0x50>;
                        };
@@ -419,7 +380,7 @@
                        #size-cells = <0>;
                        reg = <1>;
 
-                       sfp2: at24c04@50 {
+                       sfp2: eeprom@50 {
                                compatible = "atmel,24c02";
                                reg = <0x50>;
                        };
@@ -430,7 +391,7 @@
                        #size-cells = <0>;
                        reg = <2>;
 
-                       sfp3: at24c04@50 {
+                       sfp3: eeprom@50 {
                                compatible = "atmel,24c02";
                                reg = <0x50>;
                        };
@@ -441,7 +402,7 @@
                        #size-cells = <0>;
                        reg = <3>;
 
-                       sfp4: at24c04@50 {
+                       sfp4: eeprom@50 {
                                compatible = "atmel,24c02";
                                reg = <0x50>;
                        };

diff --git a/arch/arm/boot/dts/vf610-zii-dev-rev-c.dts b/arch/arm/boot/dts/vf610-zii-dev-rev-c.dts
index 6f4a560..778e02c 100644 (file)
--- a/arch/arm/boot/dts/vf610-zii-dev-rev-c.dts
+++ b/arch/arm/boot/dts/vf610-zii-dev-rev-c.dts
@@ -1,45 +1,6 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
 /*
  * Copyright (C) 2015, 2016 Zodiac Inflight Innovations
- *
- * Based on an original 'vf610-twr.dts' which is Copyright 2015,
- * Freescale Semiconductor, Inc.
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- *  a) This file is free software; you can redistribute it and/or
- *     modify it under the terms of the GNU General Public License
- *     version 2 as published by the Free Software Foundation.
- *
- *     This file is distributed in the hope that it will be useful,
- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *     GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- *  b) Permission is hereby granted, free of charge, to any person
- *     obtaining a copy of this software and associated documentation
- *     files (the "Software"), to deal in the Software without
- *     restriction, including without limitation the rights to use,
- *     copy, modify, merge, publish, distribute, sublicense, and/or
- *     sell copies of the Software, and to permit persons to whom the
- *     Software is furnished to do so, subject to the following
- *     conditions:
- *
- *     The above copyright notice and this permission notice shall be
- *     included in all copies or substantial portions of the Software.
- *
- *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND,
- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- *     OTHER DEALINGS IN THE SOFTWARE.
  */
 
 /dts-v1/;
@@ -277,7 +238,7 @@
        status = "okay";
        spi-num-chipselects = <2>;
 
-       m25p128@0 {
+       flash@0 {
                compatible = "m25p128", "jedec,spi-nor";
                #address-cells = <1>;
                #size-cells = <1>;
@@ -313,7 +274,7 @@
         *    P1 - WE2_CMD
         *    P2 - WE2_CLK
         */
-       gpio5: pca9557@18 {
+       gpio5: io-expander@18 {
                compatible = "nxp,pca9557";
                reg = <0x18>;
                gpio-controller;
@@ -361,7 +322,7 @@
         *     IO0 - WE1_CLK
         *     IO1 - WE1_CMD
         */
-       gpio7: pca9554@22 {
+       gpio7: io-expander@22 {
                compatible = "nxp,pca9554";
                reg = <0x22>;
                gpio-controller;
@@ -371,7 +332,7 @@
 };
 
 &i2c1 {
-       at24mac602@50 {
+       eeprom@50 {
                compatible = "atmel,24c02";
                reg = <0x50>;
                read-only;

diff --git a/arch/arm/boot/dts/vf610-zii-dev.dtsi b/arch/arm/boot/dts/vf610-zii-dev.dtsi
index 19eb4a8..0507e6d 100644 (file)
--- a/arch/arm/boot/dts/vf610-zii-dev.dtsi
+++ b/arch/arm/boot/dts/vf610-zii-dev.dtsi
@@ -138,7 +138,7 @@
        pinctrl-names = "default", "gpio";
        pinctrl-0 = <&pinctrl_i2c0>;
        pinctrl-1 = <&pinctrl_i2c0_gpio>;
-       scl-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
+       scl-gpios = <&gpio1 4 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
        sda-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;
        status = "okay";
 
@@ -147,12 +147,12 @@
                reg = <0x48>;
        };
 
-       at24c04@50 {
+       eeprom@50 {
                compatible = "atmel,24c04";
                reg = <0x50>;
        };
 
-       at24c04@52 {
+       eeprom@52 {
                compatible = "atmel,24c04";
                reg = <0x52>;
        };

diff --git a/arch/arm/boot/dts/vf610-zii-scu4-aib.dts b/arch/arm/boot/dts/vf610-zii-scu4-aib.dts
index de6dfa5..d7019e8 100644 (file)
--- a/arch/arm/boot/dts/vf610-zii-scu4-aib.dts
+++ b/arch/arm/boot/dts/vf610-zii-scu4-aib.dts
@@ -505,14 +505,14 @@
        pinctrl-0 = <&pinctrl_i2c0>;
        status = "okay";
 
-       gpio5: pca9554@20 {
+       gpio5: io-expander@20 {
                compatible = "nxp,pca9554";
                reg = <0x20>;
                gpio-controller;
                #gpio-cells = <2>;
        };
 
-       gpio6: pca9554@22 {
+       gpio6: io-expander@22 {
                compatible = "nxp,pca9554";
                reg = <0x22>;
                gpio-controller;
@@ -524,12 +524,12 @@
                reg = <0x48>;
        };
 
-       at24c04@50 {
+       eeprom@50 {
                compatible = "atmel,24c04";
                reg = <0x50>;
        };
 
-       at24c04@52 {
+       eeprom@52 {
                compatible = "atmel,24c04";
                reg = <0x52>;
        };
@@ -577,7 +577,7 @@
                reg = <0x4f>;
        };
 
-       gpio7: pca9555@23 {
+       gpio7: io-expander@23 {
                compatible = "nxp,pca9555";
                gpio-controller;
                #gpio-cells = <2>;
@@ -671,6 +671,10 @@
        };
 };
 
+&snvsrtc {
+       status = "disabled";
+};
+
 &uart0 {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_uart0>;

diff --git a/arch/arm/boot/dts/vf610-zii-spb4.dts b/arch/arm/boot/dts/vf610-zii-spb4.dts
new file mode 100644 (file)
index 0000000..9dde83c
--- /dev/null
+++ b/arch/arm/boot/dts/vf610-zii-spb4.dts
@@ -0,0 +1,359 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+
+/*
+ * Device tree file for ZII's SPB4 board
+ *
+ * SPB - Seat Power Box
+ *
+ * Copyright (C) 2019 Zodiac Inflight Innovations
+ */
+
+/dts-v1/;
+#include "vf610.dtsi"
+
+/ {
+       model = "ZII VF610 SPB4 Board";
+       compatible = "zii,vf610spb4", "zii,vf610dev", "fsl,vf610";
+
+       chosen {
+               stdout-path = &uart0;
+       };
+
+       memory@80000000 {
+               device_type = "memory";
+               reg = <0x80000000 0x20000000>;
+       };
+
+       gpio-leds {
+               compatible = "gpio-leds";
+               pinctrl-0 = <&pinctrl_leds_debug>;
+               pinctrl-names = "default";
+
+               led-debug {
+                       label = "zii:green:debug1";
+                       gpios = <&gpio2 18 GPIO_ACTIVE_HIGH>;
+                       linux,default-trigger = "heartbeat";
+               };
+       };
+
+       reg_vcc_3v3_mcu: regulator-vcc-3v3-mcu {
+               compatible = "regulator-fixed";
+               regulator-name = "vcc_3v3_mcu";
+               regulator-min-microvolt = <3300000>;
+               regulator-max-microvolt = <3300000>;
+       };
+};
+
+&adc0 {
+       vref-supply = <&reg_vcc_3v3_mcu>;
+       status = "okay";
+};
+
+&adc1 {
+       vref-supply = <&reg_vcc_3v3_mcu>;
+       status = "okay";
+};
+
+&dspi1 {
+       bus-num = <1>;
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_dspi1>;
+       status = "okay";
+
+       flash@0 {
+               #address-cells = <1>;
+               #size-cells = <1>;
+               compatible = "m25p128", "jedec,spi-nor";
+               reg = <0>;
+               spi-max-frequency = <50000000>;
+       };
+};
+
+&edma0 {
+       status = "okay";
+};
+
+&edma1 {
+       status = "okay";
+};
+
+&esdhc0 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_esdhc0>;
+       bus-width = <8>;
+       non-removable;
+       no-1-8-v;
+       keep-power-in-suspend;
+       no-sdio;
+       no-sd;
+       status = "okay";
+};
+
+&esdhc1 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_esdhc1>;
+       bus-width = <4>;
+       no-sdio;
+       status = "okay";
+};
+
+&fec1 {
+       phy-mode = "rmii";
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_fec1>;
+       status = "okay";
+
+       fixed-link {
+               speed = <100>;
+               full-duplex;
+       };
+
+       mdio1: mdio {
+               #address-cells = <1>;
+               #size-cells = <0>;
+               status = "okay";
+
+               switch0: switch0@0 {
+                       compatible = "marvell,mv88e6190";
+                       pinctrl-0 = <&pinctrl_gpio_switch0>;
+                       pinctrl-names = "default";
+                       reg = <0>;
+                       eeprom-length = <65536>;
+                       reset-gpios = <&gpio3 11 GPIO_ACTIVE_LOW>;
+                       interrupt-parent = <&gpio3>;
+                       interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+
+                       ports {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+
+                               port@0 {
+                                       reg = <0>;
+                                       label = "cpu";
+                                       ethernet = <&fec1>;
+
+                                       fixed-link {
+                                               speed = <100>;
+                                               full-duplex;
+                                       };
+                               };
+
+                               port@1 {
+                                       reg = <1>;
+                                       label = "eth_cu_1000_1";
+                               };
+
+                               port@2 {
+                                       reg = <2>;
+                                       label = "eth_cu_1000_2";
+                               };
+
+                               port@3 {
+                                       reg = <3>;
+                                       label = "eth_cu_1000_3";
+                               };
+
+                               port@4 {
+                                       reg = <4>;
+                                       label = "eth_cu_1000_4";
+                               };
+
+                               port@5 {
+                                       reg = <5>;
+                                       label = "eth_cu_1000_5";
+                               };
+
+                               port@6 {
+                                       reg = <6>;
+                                       label = "eth_cu_1000_6";
+                               };
+                       };
+               };
+       };
+};
+
+&i2c0 {
+       clock-frequency = <100000>;
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_i2c0>;
+       status = "okay";
+
+       io-expander@22 {
+               compatible = "nxp,pca9554";
+               reg = <0x22>;
+               gpio-controller;
+               #gpio-cells = <2>;
+       };
+
+       eeprom@50 {
+               compatible = "atmel,24c04";
+               reg = <0x50>;
+               label = "nameplate";
+       };
+
+       eeprom@52 {
+               compatible = "atmel,24c04";
+               reg = <0x52>;
+       };
+};
+
+&snvsrtc {
+       status = "disabled";
+};
+
+&uart0 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_uart0>;
+       status = "okay";
+};
+
+&uart1 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_uart1>;
+       status = "okay";
+};
+
+&uart2 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_uart2>;
+       status = "okay";
+
+       rave-sp {
+               compatible = "zii,rave-sp-rdu2";
+               current-speed = <1000000>;
+               #address-cells = <1>;
+               #size-cells = <1>;
+
+               watchdog {
+                       compatible = "zii,rave-sp-watchdog";
+               };
+
+               eeprom@a3 {
+                       compatible = "zii,rave-sp-eeprom";
+                       reg = <0xa3 0x4000>;
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       zii,eeprom-name = "main-eeprom";
+               };
+       };
+};
+
+&uart3 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_uart3>;
+       status = "okay";
+};
+
+&wdoga5 {
+       status = "disabled";
+};
+
+&iomuxc {
+       pinctrl_dspi1: dspi1grp {
+               fsl,pins = <
+                       VF610_PAD_PTD5__DSPI1_CS0               0x1182
+                       VF610_PAD_PTD4__DSPI1_CS1               0x1182
+                       VF610_PAD_PTC6__DSPI1_SIN               0x1181
+                       VF610_PAD_PTC7__DSPI1_SOUT              0x1182
+                       VF610_PAD_PTC8__DSPI1_SCK               0x1182
+               >;
+       };
+
+       pinctrl_esdhc0: esdhc0grp {
+               fsl,pins = <
+                       VF610_PAD_PTC0__ESDHC0_CLK              0x31ef
+                       VF610_PAD_PTC1__ESDHC0_CMD              0x31ef
+                       VF610_PAD_PTC2__ESDHC0_DAT0             0x31ef
+                       VF610_PAD_PTC3__ESDHC0_DAT1             0x31ef
+                       VF610_PAD_PTC4__ESDHC0_DAT2             0x31ef
+                       VF610_PAD_PTC5__ESDHC0_DAT3             0x31ef
+                       VF610_PAD_PTD23__ESDHC0_DAT4            0x31ef
+                       VF610_PAD_PTD22__ESDHC0_DAT5            0x31ef
+                       VF610_PAD_PTD21__ESDHC0_DAT6            0x31ef
+                       VF610_PAD_PTD20__ESDHC0_DAT7            0x31ef
+               >;
+       };
+
+       pinctrl_esdhc1: esdhc1grp {
+               fsl,pins = <
+                       VF610_PAD_PTA24__ESDHC1_CLK             0x31ef
+                       VF610_PAD_PTA25__ESDHC1_CMD             0x31ef
+                       VF610_PAD_PTA26__ESDHC1_DAT0            0x31ef
+                       VF610_PAD_PTA27__ESDHC1_DAT1            0x31ef
+                       VF610_PAD_PTA28__ESDHC1_DATA2           0x31ef
+                       VF610_PAD_PTA29__ESDHC1_DAT3            0x31ef
+               >;
+       };
+
+       pinctrl_fec1: fec1grp {
+               fsl,pins = <
+                       VF610_PAD_PTA6__RMII_CLKIN              0x30d1
+                       VF610_PAD_PTC9__ENET_RMII1_MDC          0x30d2
+                       VF610_PAD_PTC10__ENET_RMII1_MDIO        0x30d3
+                       VF610_PAD_PTC11__ENET_RMII1_CRS         0x30d1
+                       VF610_PAD_PTC12__ENET_RMII1_RXD1        0x30d1
+                       VF610_PAD_PTC13__ENET_RMII1_RXD0        0x30d1
+                       VF610_PAD_PTC14__ENET_RMII1_RXER        0x30d1
+                       VF610_PAD_PTC15__ENET_RMII1_TXD1        0x30d2
+                       VF610_PAD_PTC16__ENET_RMII1_TXD0        0x30d2
+                       VF610_PAD_PTC17__ENET_RMII1_TXEN        0x30d2
+               >;
+       };
+
+       pinctrl_gpio_switch0: pinctrl-gpio-switch0 {
+               fsl,pins = <
+                       VF610_PAD_PTE2__GPIO_107                0x31c2
+                       VF610_PAD_PTB28__GPIO_98                0x219d
+               >;
+       };
+
+       pinctrl_i2c0: i2c0grp {
+               fsl,pins = <
+                       VF610_PAD_PTB14__I2C0_SCL               0x37ff
+                       VF610_PAD_PTB15__I2C0_SDA               0x37ff
+               >;
+       };
+
+       pinctrl_i2c1: i2c1grp {
+               fsl,pins = <
+                       VF610_PAD_PTB16__I2C1_SCL               0x37ff
+                       VF610_PAD_PTB17__I2C1_SDA               0x37ff
+               >;
+       };
+
+       pinctrl_leds_debug: pinctrl-leds-debug {
+               fsl,pins = <
+                       VF610_PAD_PTD3__GPIO_82                 0x31c2
+               >;
+       };
+
+       pinctrl_uart0: uart0grp {
+               fsl,pins = <
+                       VF610_PAD_PTB10__UART0_TX               0x21a2
+                       VF610_PAD_PTB11__UART0_RX               0x21a1
+               >;
+       };
+
+       pinctrl_uart1: uart1grp {
+               fsl,pins = <
+                       VF610_PAD_PTB23__UART1_TX               0x21a2
+                       VF610_PAD_PTB24__UART1_RX               0x21a1
+               >;
+       };
+
+       pinctrl_uart2: uart2grp {
+               fsl,pins = <
+                       VF610_PAD_PTD0__UART2_TX                0x21a2
+                       VF610_PAD_PTD1__UART2_RX                0x21a1
+               >;
+       };
+
+       pinctrl_uart3: uart3grp {
+               fsl,pins = <
+                       VF610_PAD_PTA30__UART3_TX               0x21a2
+                       VF610_PAD_PTA31__UART3_RX               0x21a1
+               >;
+       };
+};

diff --git a/arch/arm/boot/dts/vf610-zii-ssmb-dtu.dts b/arch/arm/boot/dts/vf610-zii-ssmb-dtu.dts
index 2b10672..847c585 100644 (file)
--- a/arch/arm/boot/dts/vf610-zii-ssmb-dtu.dts
+++ b/arch/arm/boot/dts/vf610-zii-ssmb-dtu.dts
@@ -37,7 +37,6 @@
                        label = "zii:green:debug1";
                        gpios = <&gpio2 18 GPIO_ACTIVE_HIGH>;
                        linux,default-trigger = "heartbeat";
-                       max-brightness = <1>;
                };
        };
 
@@ -211,6 +210,10 @@
        };
 };
 
+&snvsrtc {
+       status = "disabled";
+};
+
 &uart0 {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_uart0>;

diff --git a/arch/arm/boot/dts/vf610-zii-ssmb-spu3.dts b/arch/arm/boot/dts/vf610-zii-ssmb-spu3.dts
index 0d9fe5a..453fce8 100644 (file)
--- a/arch/arm/boot/dts/vf610-zii-ssmb-spu3.dts
+++ b/arch/arm/boot/dts/vf610-zii-ssmb-spu3.dts
@@ -37,7 +37,6 @@
                        label = "zii:green:debug1";
                        gpios = <&gpio2 18 GPIO_ACTIVE_HIGH>;
                        linux,default-trigger = "heartbeat";
-                       max-brightness = <1>;
                };
        };
 
@@ -70,7 +69,7 @@
         */
        status = "disabled";
 
-       m25p128@0 {
+       flash@0 {
                #address-cells = <1>;
                #size-cells = <1>;
                compatible = "m25p128", "jedec,spi-nor";
@@ -195,7 +194,7 @@
        pinctrl-0 = <&pinctrl_i2c0>;
        status = "okay";
 
-       gpio6: pca9505@22 {
+       gpio6: io-expander@22 {
                compatible = "nxp,pca9554";
                reg = <0x22>;
                gpio-controller;
@@ -207,18 +206,22 @@
                reg = <0x48>;
        };
 
-       at24c04@50 {
+       eeprom@50 {
                compatible = "atmel,24c04";
                reg = <0x50>;
                label = "nameplate";
        };
 
-       at24c04@52 {
+       eeprom@52 {
                compatible = "atmel,24c04";
                reg = <0x52>;
        };
 };
 
+&snvsrtc {
+       status = "disabled";
+};
+
 &uart0 {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_uart0>;
@@ -250,6 +253,10 @@
        };
 };
 
+&wdoga5 {
+       status = "disabled";
+};
+
 &iomuxc {
        pinctrl_dspi1: dspi1grp {
                fsl,pins = <

diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
index b5ca9c5..0f4d918 100644 (file)
--- a/arch/arm64/Kconfig.platforms
+++ b/arch/arm64/Kconfig.platforms
@@ -7,6 +7,11 @@ config ARCH_ACTIONS
        help
          This enables support for the Actions Semiconductor S900 SoC family.
 
+config ARCH_AGILEX
+       bool "Intel's Agilex SoCFPGA Family"
+       help
+         This enables support for Intel's Agilex SoCFPGA Family.
+
 config ARCH_SUNXI
        bool "Allwinner sunxi 64-bit SoC Family"
        select ARCH_HAS_RESET_CONTROLLER

diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
index 5bc7533..f19b762 100644 (file)
--- a/arch/arm64/boot/dts/Makefile
+++ b/arch/arm64/boot/dts/Makefile
@@ -13,6 +13,7 @@ subdir-y += cavium
 subdir-y += exynos
 subdir-y += freescale
 subdir-y += hisilicon
+subdir-y += intel
 subdir-y += lg
 subdir-y += marvell
 subdir-y += mediatek

diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/allwinner/Makefile
index 0b09171..f6db061 100644 (file)
--- a/arch/arm64/boot/dts/allwinner/Makefile
+++ b/arch/arm64/boot/dts/allwinner/Makefile
@@ -2,6 +2,7 @@
 dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-amarula-relic.dtb
 dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-bananapi-m64.dtb
 dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-nanopi-a64.dtb
+dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-oceanic-5205-5inmfd.dtb
 dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-olinuxino.dtb
 dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-orangepi-win.dtb
 dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pine64-lts.dtb
@@ -19,6 +20,8 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-orangepi-pc2.dtb
 dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-orangepi-prime.dtb
 dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-orangepi-zero-plus.dtb
 dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-orangepi-zero-plus2.dtb
+dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-beelink-gs1.dtb
+dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-orangepi-3.dtb
 dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-orangepi-lite2.dtb
 dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-orangepi-one-plus.dtb
 dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-pine-h64.dtb

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-amarula-relic.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-amarula-relic.dts
index 6cb2b7f..019ae09 100644 (file)
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-amarula-relic.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-amarula-relic.dts
@@ -22,6 +22,41 @@
                stdout-path = "serial0:115200n8";
        };
 
+       i2c {
+               compatible = "i2c-gpio";
+               sda-gpios = <&pio 4 13 GPIO_ACTIVE_HIGH>;
+               scl-gpios = <&pio 4 12 GPIO_ACTIVE_HIGH>;
+               i2c-gpio,delay-us = <5>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               ov5640: camera@3c {
+                       compatible = "ovti,ov5640";
+                       reg = <0x3c>;
+                       pinctrl-names = "default";
+                       pinctrl-0 = <&csi_mclk_pin>;
+                       clocks = <&ccu CLK_CSI_MCLK>;
+                       clock-names = "xclk";
+
+                       AVDD-supply = <&reg_aldo1>;
+                       DOVDD-supply = <&reg_dldo3>;
+                       DVDD-supply = <&reg_eldo3>;
+                       reset-gpios = <&pio 4 14 GPIO_ACTIVE_LOW>; /* CSI-RST-R: PE14 */
+                       powerdown-gpios = <&pio 4 15 GPIO_ACTIVE_HIGH>; /* CSI-STBY-R: PE15 */
+
+                       port {
+                               ov5640_ep: endpoint {
+                                       remote-endpoint = <&csi_ep>;
+                                       bus-width = <8>;
+                                       hsync-active = <1>; /* Active high */
+                                       vsync-active = <0>; /* Active low */
+                                       data-active = <1>;  /* Active high */
+                                       pclk-sample = <1>;  /* Rising */
+                               };
+                       };
+               };
+       };
+
        wifi_pwrseq: wifi-pwrseq {
                compatible = "mmc-pwrseq-simple";
                clocks = <&rtc 1>;
@@ -30,10 +65,40 @@
        };
 };
 
+&csi {
+       status = "okay";
+
+       port {
+               csi_ep: endpoint {
+                       remote-endpoint = <&ov5640_ep>;
+                       bus-width = <8>;
+                       hsync-active = <1>; /* Active high */
+                       vsync-active = <0>; /* Active low */
+                       data-active = <1>;  /* Active high */
+                       pclk-sample = <1>;  /* Rising */
+               };
+       };
+};
+
 &ehci0 {
        status = "okay";
 };
 
+&i2c0 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&i2c0_pins>;
+       status = "okay";
+
+       sensor@48 {
+               compatible = "st,stlm75";
+               reg = <0x48>;
+       };
+};
+
+&i2c0_pins {
+       bias-pull-up;
+};
+
 &mmc1 {
        pinctrl-names = "default";
        pinctrl-0 = <&mmc1_pins>;

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-oceanic-5205-5inmfd.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-oceanic-5205-5inmfd.dts
new file mode 100644 (file)
index 0000000..6a21545
--- /dev/null
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-oceanic-5205-5inmfd.dts
@@ -0,0 +1,68 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2019 Oceanic Systems (UK) Ltd.
+ * Copyright (C) 2019 Amarula Solutions B.V.
+ * Author: Jagan Teki <jagan@amarulasolutions.com>
+ */
+
+/dts-v1/;
+
+#include "sun50i-a64-sopine.dtsi"
+
+/ {
+       model = "Oceanic 5205 5inMFD";
+       compatible = "oceanic,5205-5inmfd", "allwinner,sun50i-a64";
+
+       aliases {
+               ethernet0 = &emac;
+               serial0 = &uart0;
+       };
+
+       chosen {
+               stdout-path = "serial0:115200n8";
+       };
+};
+
+&ehci0 {
+       status = "okay";
+};
+
+&emac {
+       pinctrl-names = "default";
+       pinctrl-0 = <&rgmii_pins>;
+       phy-mode = "rgmii";
+       phy-handle = <&ext_rgmii_phy>;
+       phy-supply = <&reg_dc1sw>;
+       allwinner,tx-delay-ps = <600>;
+       status = "okay";
+};
+
+&mdio {
+       ext_rgmii_phy: ethernet-phy@1 {
+               compatible = "ethernet-phy-ieee802.3-c22";
+               reg = <1>;
+       };
+};
+
+&ohci0 {
+       status = "okay";
+};
+
+&reg_dc1sw {
+       regulator-name = "vcc-phy";
+};
+
+&uart0 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&uart0_pb_pins>;
+       status = "okay";
+};
+
+&usb_otg {
+       dr_mode = "host";
+       status = "okay";
+};
+
+&usbphy {
+       status = "okay";
+};

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts
index 78c82a6..2b6345d 100644 (file)
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts
@@ -104,7 +104,6 @@
 
 &ehci0 {
        phys = <&usbphy 0>;
-       phy-names = "usb";
        status = "okay";
 };
 
@@ -151,7 +150,6 @@
 
 &ohci0 {
        phys = <&usbphy 0>;
-       phy-names = "usb";
        status = "okay";
 };
 

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-teres-i.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-teres-i.dts
index 7b7b14b..0ec46b9 100644 (file)
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-teres-i.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-teres-i.dts
@@ -21,6 +21,15 @@
                serial0 = &uart0;
        };
 
+       backlight: backlight {
+               compatible = "pwm-backlight";
+               pwms = <&pwm 0 50000 0>;
+               power-supply = <&reg_dcdc1>;
+               brightness-levels = <0 5 7 10 14 20 28 40 56 80 112>;
+               default-brightness-level = <5>;
+               enable-gpios = <&pio 3 23 GPIO_ACTIVE_HIGH>; /* PD23 */
+       };
+
        chosen {
                stdout-path = "serial0:115200n8";
 
@@ -131,6 +140,10 @@
        status = "okay";
 };
 
+&pwm {
+       status = "okay";
+};
+
 &r_rsb {
        status = "okay";
 

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
index e628d06..8c5b521 100644 (file)
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
@@ -217,7 +217,7 @@
                #size-cells = <1>;
                ranges;
 
-               de2@1000000 {
+               bus@1000000 {
                        compatible = "allwinner,sun50i-a64-de2";
                        reg = <0x1000000 0x400000>;
                        allwinner,sram = <&de2_sram 1>;
@@ -251,11 +251,19 @@
                                        #size-cells = <0>;
 
                                        mixer0_out: port@1 {
+                                               #address-cells = <1>;
+                                               #size-cells = <0>;
                                                reg = <1>;
 
-                                               mixer0_out_tcon0: endpoint {
+                                               mixer0_out_tcon0: endpoint@0 {
+                                                       reg = <0>;
                                                        remote-endpoint = <&tcon0_in_mixer0>;
                                                };
+
+                                               mixer0_out_tcon1: endpoint@1 {
+                                                       reg = <1>;
+                                                       remote-endpoint = <&tcon1_in_mixer0>;
+                                               };
                                        };
                                };
                        };
@@ -274,9 +282,17 @@
                                        #size-cells = <0>;
 
                                        mixer1_out: port@1 {
+                                               #address-cells = <1>;
+                                               #size-cells = <0>;
                                                reg = <1>;
 
-                                               mixer1_out_tcon1: endpoint {
+                                               mixer1_out_tcon0: endpoint@0 {
+                                                       reg = <0>;
+                                                       remote-endpoint = <&tcon0_in_mixer1>;
+                                               };
+
+                                               mixer1_out_tcon1: endpoint@1 {
+                                                       reg = <1>;
                                                        remote-endpoint = <&tcon1_in_mixer1>;
                                                };
                                        };
@@ -338,6 +354,7 @@
                        clocks = <&ccu CLK_BUS_TCON0>, <&ccu CLK_TCON0>;
                        clock-names = "ahb", "tcon-ch0";
                        clock-output-names = "tcon-pixel-clock";
+                       #clock-cells = <0>;
                        resets = <&ccu RST_BUS_TCON0>, <&ccu RST_BUS_LVDS>;
                        reset-names = "lcd", "lvds";
 
@@ -354,6 +371,11 @@
                                                reg = <0>;
                                                remote-endpoint = <&mixer0_out_tcon0>;
                                        };
+
+                                       tcon0_in_mixer1: endpoint@1 {
+                                               reg = <1>;
+                                               remote-endpoint = <&mixer1_out_tcon0>;
+                                       };
                                };
 
                                tcon0_out: port@1 {
@@ -379,9 +401,17 @@
                                #size-cells = <0>;
 
                                tcon1_in: port@0 {
+                                       #address-cells = <1>;
+                                       #size-cells = <0>;
                                        reg = <0>;
 
-                                       tcon1_in_mixer1: endpoint {
+                                       tcon1_in_mixer0: endpoint@0 {
+                                               reg = <0>;
+                                               remote-endpoint = <&mixer0_out_tcon1>;
+                                       };
+
+                                       tcon1_in_mixer1: endpoint@1 {
+                                               reg = <1>;
                                                remote-endpoint = <&mixer1_out_tcon1>;
                                        };
                                };
@@ -467,6 +497,7 @@
                        phys = <&usbphy 0>;
                        phy-names = "usb";
                        extcon = <&usbphy 0>;
+                       dr_mode = "otg";
                        status = "disabled";
                };
 
@@ -522,7 +553,6 @@
                        resets = <&ccu RST_BUS_OHCI1>,
                                 <&ccu RST_BUS_EHCI1>;
                        phys = <&usbphy 1>;
-                       phy-names = "usb";
                        status = "disabled";
                };
 
@@ -534,7 +564,6 @@
                                 <&ccu CLK_USB_OHCI1>;
                        resets = <&ccu RST_BUS_OHCI1>;
                        phys = <&usbphy 1>;
-                       phy-names = "usb";
                        status = "disabled";
                };
 
@@ -553,7 +582,8 @@
                        interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
                                     <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
                                     <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
-                       clocks = <&ccu 58>;
+                       clocks = <&ccu 58>, <&osc24M>, <&rtc 0>;
+                       clock-names = "apb", "hosc", "losc";
                        gpio-controller;
                        #gpio-cells = <3>;
                        interrupt-controller;
@@ -565,12 +595,18 @@
                                function = "csi";
                        };
 
-                       i2c0_pins: i2c0_pins {
+                       /omit-if-no-ref/
+                       csi_mclk_pin: csi-mclk-pin {
+                               pins = "PE1";
+                               function = "csi";
+                       };
+
+                       i2c0_pins: i2c0-pins {
                                pins = "PH0", "PH1";
                                function = "i2c0";
                        };
 
-                       i2c1_pins: i2c1_pins {
+                       i2c1_pins: i2c1-pins {
                                pins = "PH2", "PH3";
                                function = "i2c1";
                        };
@@ -607,19 +643,19 @@
                                bias-pull-up;
                        };
 
-                       pwm_pin: pwm_pin {
+                       pwm_pin: pwm-pin {
                                pins = "PD22";
                                function = "pwm";
                        };
 
-                       rmii_pins: rmii_pins {
+                       rmii_pins: rmii-pins {
                                pins = "PD10", "PD11", "PD13", "PD14", "PD17",
                                       "PD18", "PD19", "PD20", "PD22", "PD23";
                                function = "emac";
                                drive-strength = <40>;
                        };
 
-                       rgmii_pins: rgmii_pins {
+                       rgmii_pins: rgmii-pins {
                                pins = "PD8", "PD9", "PD10", "PD11", "PD12",
                                       "PD13", "PD15", "PD16", "PD17", "PD18",
                                       "PD19", "PD20", "PD21", "PD22", "PD23";
@@ -627,17 +663,17 @@
                                drive-strength = <40>;
                        };
 
-                       spdif_tx_pin: spdif {
+                       spdif_tx_pin: spdif-tx-pin {
                                pins = "PH8";
                                function = "spdif";
                        };
 
-                       spi0_pins: spi0 {
+                       spi0_pins: spi0-pins {
                                pins = "PC0", "PC1", "PC2", "PC3";
                                function = "spi0";
                        };
 
-                       spi1_pins: spi1 {
+                       spi1_pins: spi1-pins {
                                pins = "PD0", "PD1", "PD2", "PD3";
                                function = "spi1";
                        };
@@ -647,12 +683,12 @@
                                function = "uart0";
                        };
 
-                       uart1_pins: uart1_pins {
+                       uart1_pins: uart1-pins {
                                pins = "PG6", "PG7";
                                function = "uart1";
                        };
 
-                       uart1_rts_cts_pins: uart1_rts_cts_pins {
+                       uart1_rts_cts_pins: uart1-rts-cts-pins {
                                pins = "PG8", "PG9";
                                function = "uart1";
                        };
@@ -730,7 +766,6 @@
                        clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>;
                        clock-names = "apb", "mod";
                        resets = <&ccu RST_BUS_CODEC>;
-                       reset-names = "rst";
                        dmas = <&dma 15>, <&dma 15>;
                        dma-names = "rx", "tx";
                        status = "disabled";
@@ -1064,12 +1099,12 @@
                                function = "s_i2c";
                        };
 
-                       r_pwm_pin: pwm {
+                       r_pwm_pin: r-pwm-pin {
                                pins = "PL10";
                                function = "s_pwm";
                        };
 
-                       r_rsb_pins: rsb {
+                       r_rsb_pins: r-rsb-pins {
                                pins = "PL0", "PL1";
                                function = "s_rsb";
                        };

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-emlid-neutis-n5-devboard.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-emlid-neutis-n5-devboard.dts
index 85e7993..62409af 100644 (file)
--- a/arch/arm64/boot/dts/allwinner/sun50i-h5-emlid-neutis-n5-devboard.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-emlid-neutis-n5-devboard.dts
@@ -46,7 +46,6 @@
 
        vdd_cpux: gpio-regulator {
                compatible = "regulator-gpio";
-               pinctrl-names = "default";
                regulator-name = "vdd-cpux";
                regulator-type = "voltage";
                regulator-boot-on;
@@ -133,7 +132,7 @@
 
 &uart0 {
        pinctrl-names = "default";
-       pinctrl-0 = <&uart0_pins_a>;
+       pinctrl-0 = <&uart0_pa_pins>;
        status = "okay";
 };
 

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-emlid-neutis-n5.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h5-emlid-neutis-n5.dtsi
index e4d5037..82f4b44 100644 (file)
--- a/arch/arm64/boot/dts/allwinner/sun50i-h5-emlid-neutis-n5.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-emlid-neutis-n5.dtsi
@@ -21,7 +21,6 @@
 
        wifi_pwrseq: wifi_pwrseq {
                compatible = "mmc-pwrseq-simple";
-               pinctrl-names = "default";
                reset-gpios = <&pio 2 7 GPIO_ACTIVE_LOW>; /* PC7 */
                post-power-on-delay-ms = <200>;
        };

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo-plus2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo-plus2.dts
index 506e25b..9887948 100644 (file)
--- a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo-plus2.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo-plus2.dts
@@ -78,7 +78,6 @@
 
        reg_gmac_3v3: gmac-3v3 {
                compatible = "regulator-fixed";
-               pinctrl-names = "default";
                regulator-name = "gmac-3v3";
                regulator-min-microvolt = <3300000>;
                regulator-max-microvolt = <3300000>;
@@ -96,7 +95,6 @@
 
        vdd_cpux: gpio-regulator {
                compatible = "regulator-gpio";
-               pinctrl-names = "default";
                regulator-name = "vdd-cpux";
                regulator-type = "voltage";
                regulator-boot-on;
@@ -112,7 +110,6 @@
 
        wifi_pwrseq: wifi_pwrseq {
                compatible = "mmc-pwrseq-simple";
-               pinctrl-names = "default";
                reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */
                post-power-on-delay-ms = <200>;
        };
@@ -191,7 +188,7 @@
 
 &uart0 {
        pinctrl-names = "default";
-       pinctrl-0 = <&uart0_pins_a>;
+       pinctrl-0 = <&uart0_pa_pins>;
        status = "okay";
 };
 

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2.dts
index cc268a6..57a6f45 100644 (file)
--- a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2.dts
@@ -142,7 +142,7 @@
 
 &uart0 {
        pinctrl-names = "default";
-       pinctrl-0 = <&uart0_pins_a>;
+       pinctrl-0 = <&uart0_pa_pins>;
        status = "okay";
 };
 

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts
index 3e0d5a9..e126c1c 100644 (file)
--- a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts
@@ -180,7 +180,7 @@
 
 &ir {
        pinctrl-names = "default";
-       pinctrl-0 = <&ir_pins_a>;
+       pinctrl-0 = <&r_ir_rx_pin>;
        status = "okay";
 };
 
@@ -221,7 +221,7 @@
 
 &uart0 {
        pinctrl-names = "default";
-       pinctrl-0 = <&uart0_pins_a>;
+       pinctrl-0 = <&uart0_pa_pins>;
        status = "okay";
 };
 

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts
index b75ca4d..d9b3ed2 100644 (file)
--- a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts
@@ -187,7 +187,7 @@
 
 &ir {
        pinctrl-names = "default";
-       pinctrl-0 = <&ir_pins_a>;
+       pinctrl-0 = <&r_ir_rx_pin>;
        status = "okay";
 };
 
@@ -224,7 +224,7 @@
 
 &uart0 {
        pinctrl-names = "default";
-       pinctrl-0 = <&uart0_pins_a>;
+       pinctrl-0 = <&uart0_pa_pins>;
        status = "okay";
 };
 

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-zero-plus.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-zero-plus.dts
index 1238de2..db6ea7b 100644 (file)
--- a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-zero-plus.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-zero-plus.dts
@@ -127,7 +127,7 @@
 
 &uart0 {
        pinctrl-names = "default";
-       pinctrl-0 = <&uart0_pins_a>;
+       pinctrl-0 = <&uart0_pa_pins>;
        status = "okay";
 };
 

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-zero-plus2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-zero-plus2.dts
index 53c8c11..dacf613 100644 (file)
--- a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-zero-plus2.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-zero-plus2.dts
@@ -78,7 +78,6 @@
 
        wifi_pwrseq: wifi_pwrseq {
                compatible = "mmc-pwrseq-simple";
-               pinctrl-names = "default";
                reset-gpios = <&pio 0 9 GPIO_ACTIVE_LOW>; /* PA9 */
                post-power-on-delay-ms = <200>;
        };
@@ -134,7 +133,7 @@
 
 &uart0 {
        pinctrl-names = "default";
-       pinctrl-0 = <&uart0_pins_a>;
+       pinctrl-0 = <&uart0_pa_pins>;
        status = "okay";
 };
 

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi
index 96acafd..f002a49 100644 (file)
--- a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi
@@ -209,3 +209,7 @@
 &rtc {
        compatible = "allwinner,sun50i-h5-rtc";
 };
+
+&sid {
+       compatible = "allwinner,sun50i-h5-sid";
+};

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts
new file mode 100644 (file)
index 0000000..0dc33c9
--- /dev/null
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts
@@ -0,0 +1,260 @@
+// SPDX-License-Identifier: (GPL-2.0+ or MIT)
+/*
+ * Copyright (C) 2019 Clément Péron <peron.clem@gmail.com>
+ */
+
+/dts-v1/;
+
+#include "sun50i-h6.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+       model = "Beelink GS1";
+       compatible = "azw,beelink-gs1", "allwinner,sun50i-h6";
+
+       aliases {
+               ethernet0 = &emac;
+               serial0 = &uart0;
+       };
+
+       chosen {
+               stdout-path = "serial0:115200n8";
+       };
+
+       connector {
+               compatible = "hdmi-connector";
+               type = "a";
+
+               port {
+                       hdmi_con_in: endpoint {
+                               remote-endpoint = <&hdmi_out_con>;
+                       };
+               };
+       };
+
+       leds {
+               compatible = "gpio-leds";
+
+               power {
+                       label = "beelink:white:power";
+                       gpios = <&r_pio 0 4 GPIO_ACTIVE_HIGH>; /* PL4 */
+                       default-state = "on";
+               };
+       };
+
+       reg_vcc5v: vcc5v {
+               /* board wide 5V supply directly from the DC jack */
+               compatible = "regulator-fixed";
+               regulator-name = "vcc-5v";
+               regulator-min-microvolt = <5000000>;
+               regulator-max-microvolt = <5000000>;
+               regulator-always-on;
+       };
+};
+
+&de {
+       status = "okay";
+};
+
+&ehci0 {
+       status = "okay";
+};
+
+&emac {
+       pinctrl-names = "default";
+       pinctrl-0 = <&ext_rgmii_pins>;
+       phy-mode = "rgmii";
+       phy-handle = <&ext_rgmii_phy>;
+       phy-supply = <&reg_aldo2>;
+       status = "okay";
+};
+
+&hdmi {
+       status = "okay";
+};
+
+&hdmi_out {
+       hdmi_out_con: endpoint {
+               remote-endpoint = <&hdmi_con_in>;
+       };
+};
+
+&mdio {
+       ext_rgmii_phy: ethernet-phy@1 {
+               compatible = "ethernet-phy-ieee802.3-c22";
+               reg = <1>;
+       };
+};
+
+&mmc0 {
+       vmmc-supply = <&reg_cldo1>;
+       cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>;
+       bus-width = <4>;
+       status = "okay";
+};
+
+&mmc2 {
+       vmmc-supply = <&reg_cldo1>;
+       vqmmc-supply = <&reg_bldo2>;
+       non-removable;
+       cap-mmc-hw-reset;
+       bus-width = <8>;
+       status = "okay";
+};
+
+&ohci0 {
+       status = "okay";
+};
+
+&pio {
+       vcc-pd-supply = <&reg_cldo1>;
+       vcc-pg-supply = <&reg_aldo1>;
+};
+
+&r_i2c {
+       status = "okay";
+
+       axp805: pmic@36 {
+               compatible = "x-powers,axp805", "x-powers,axp806";
+               reg = <0x36>;
+               interrupt-parent = <&r_intc>;
+               interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+               interrupt-controller;
+               #interrupt-cells = <1>;
+               x-powers,self-working-mode;
+               vina-supply = <&reg_vcc5v>;
+               vinb-supply = <&reg_vcc5v>;
+               vinc-supply = <&reg_vcc5v>;
+               vind-supply = <&reg_vcc5v>;
+               vine-supply = <&reg_vcc5v>;
+               aldoin-supply = <&reg_vcc5v>;
+               bldoin-supply = <&reg_vcc5v>;
+               cldoin-supply = <&reg_vcc5v>;
+
+               regulators {
+                       reg_aldo1: aldo1 {
+                               regulator-always-on;
+                               regulator-min-microvolt = <3300000>;
+                               regulator-max-microvolt = <3300000>;
+                               regulator-name = "vcc-pl";
+                       };
+
+                       reg_aldo2: aldo2 {
+                               regulator-min-microvolt = <3300000>;
+                               regulator-max-microvolt = <3300000>;
+                               regulator-name = "vcc-ac200";
+                               regulator-enable-ramp-delay = <100000>;
+                       };
+
+                       reg_aldo3: aldo3 {
+                               regulator-always-on;
+                               regulator-min-microvolt = <3300000>;
+                               regulator-max-microvolt = <3300000>;
+                               regulator-name = "vcc25-dram";
+                       };
+
+                       reg_bldo1: bldo1 {
+                               regulator-always-on;
+                               regulator-min-microvolt = <1800000>;
+                               regulator-max-microvolt = <1800000>;
+                               regulator-name = "vcc-bias-pll";
+                       };
+
+                       reg_bldo2: bldo2 {
+                               regulator-always-on;
+                               regulator-min-microvolt = <1800000>;
+                               regulator-max-microvolt = <1800000>;
+                               regulator-name = "vcc-efuse-pcie-hdmi-io";
+                       };
+
+                       reg_bldo3: bldo3 {
+                               regulator-always-on;
+                               regulator-min-microvolt = <1800000>;
+                               regulator-max-microvolt = <1800000>;
+                               regulator-name = "vcc-dcxoio";
+                       };
+
+                       bldo4 {
+                               /* unused */
+                       };
+
+                       reg_cldo1: cldo1 {
+                               regulator-always-on;
+                               regulator-min-microvolt = <3300000>;
+                               regulator-max-microvolt = <3300000>;
+                               regulator-name = "vcc-3v3";
+                       };
+
+                       reg_cldo2: cldo2 {
+                               regulator-min-microvolt = <3300000>;
+                               regulator-max-microvolt = <3300000>;
+                               regulator-name = "vcc-wifi-1";
+                       };
+
+                       reg_cldo3: cldo3 {
+                               regulator-min-microvolt = <3300000>;
+                               regulator-max-microvolt = <3300000>;
+                               regulator-name = "vcc-wifi-2";
+                       };
+
+                       reg_dcdca: dcdca {
+                               regulator-always-on;
+                               regulator-min-microvolt = <810000>;
+                               regulator-max-microvolt = <1080000>;
+                               regulator-name = "vdd-cpu";
+                       };
+
+                       reg_dcdcc: dcdcc {
+                               regulator-min-microvolt = <810000>;
+                               regulator-max-microvolt = <1080000>;
+                               regulator-name = "vdd-gpu";
+                       };
+
+                       reg_dcdcd: dcdcd {
+                               regulator-always-on;
+                               regulator-min-microvolt = <960000>;
+                               regulator-max-microvolt = <960000>;
+                               regulator-name = "vdd-sys";
+                       };
+
+                       reg_dcdce: dcdce {
+                               regulator-always-on;
+                               regulator-min-microvolt = <1200000>;
+                               regulator-max-microvolt = <1200000>;
+                               regulator-name = "vcc-dram";
+                       };
+
+                       sw {
+                               /* unused */
+                       };
+               };
+       };
+};
+
+&r_pio {
+       /*
+        * PL0 and PL1 are used for PMIC I2C
+        * don't enable the pl-supply else
+        * it will fail at boot
+        *
+        * vcc-pl-supply = <&reg_aldo1>;
+        */
+       vcc-pm-supply = <&reg_aldo1>;
+};
+
+&uart0 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&uart0_ph_pins>;
+       status = "okay";
+};
+
+&usb2otg {
+       dr_mode = "host";
+       status = "okay";
+};
+
+&usb2phy {
+       usb0_vbus-supply = <&reg_vcc5v>;
+       status = "okay";
+};

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts
new file mode 100644 (file)
index 0000000..17d4969
--- /dev/null
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts
@@ -0,0 +1,215 @@
+// SPDX-License-Identifier: (GPL-2.0+ or MIT)
+/*
+ * Copyright (C) 2019 Ondřej Jirman <megous@megous.com>
+ */
+
+/dts-v1/;
+
+#include "sun50i-h6.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+       model = "OrangePi 3";
+       compatible = "xunlong,orangepi-3", "allwinner,sun50i-h6";
+
+       aliases {
+               serial0 = &uart0;
+       };
+
+       chosen {
+               stdout-path = "serial0:115200n8";
+       };
+
+       leds {
+               compatible = "gpio-leds";
+
+               power {
+                       label = "orangepi:red:power";
+                       gpios = <&r_pio 0 4 GPIO_ACTIVE_HIGH>; /* PL4 */
+                       default-state = "on";
+               };
+
+               status {
+                       label = "orangepi:green:status";
+                       gpios = <&r_pio 0 7 GPIO_ACTIVE_HIGH>; /* PL7 */
+               };
+       };
+
+       reg_vcc5v: vcc5v {
+               /* board wide 5V supply directly from the DC jack */
+               compatible = "regulator-fixed";
+               regulator-name = "vcc-5v";
+               regulator-min-microvolt = <5000000>;
+               regulator-max-microvolt = <5000000>;
+               regulator-always-on;
+       };
+};
+
+&cpu0 {
+       cpu-supply = <&reg_dcdca>;
+};
+
+&ehci0 {
+       status = "okay";
+};
+
+&ehci3 {
+       status = "okay";
+};
+
+&mmc0 {
+       vmmc-supply = <&reg_cldo1>;
+       cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
+       bus-width = <4>;
+       status = "okay";
+};
+
+&ohci0 {
+       status = "okay";
+};
+
+&ohci3 {
+       status = "okay";
+};
+
+&pio {
+       vcc-pc-supply = <&reg_bldo2>;
+       vcc-pd-supply = <&reg_cldo1>;
+};
+
+&r_i2c {
+       status = "okay";
+
+       axp805: pmic@36 {
+               compatible = "x-powers,axp805", "x-powers,axp806";
+               reg = <0x36>;
+               interrupt-parent = <&r_intc>;
+               interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+               interrupt-controller;
+               #interrupt-cells = <1>;
+               x-powers,self-working-mode;
+               vina-supply = <&reg_vcc5v>;
+               vinb-supply = <&reg_vcc5v>;
+               vinc-supply = <&reg_vcc5v>;
+               vind-supply = <&reg_vcc5v>;
+               vine-supply = <&reg_vcc5v>;
+               aldoin-supply = <&reg_vcc5v>;
+               bldoin-supply = <&reg_vcc5v>;
+               cldoin-supply = <&reg_vcc5v>;
+
+               regulators {
+                       reg_aldo1: aldo1 {
+                               regulator-always-on;
+                               regulator-min-microvolt = <3300000>;
+                               regulator-max-microvolt = <3300000>;
+                               regulator-name = "vcc-pl-led-ir";
+                       };
+
+                       reg_aldo2: aldo2 {
+                               regulator-min-microvolt = <3300000>;
+                               regulator-max-microvolt = <3300000>;
+                               regulator-name = "vcc33-audio-tv-ephy-mac";
+                       };
+
+                       /* ALDO3 is shorted to CLDO1 */
+                       reg_aldo3: aldo3 {
+                               regulator-always-on;
+                               regulator-min-microvolt = <3300000>;
+                               regulator-max-microvolt = <3300000>;
+                               regulator-name = "vcc33-io-pd-emmc-sd-usb-uart-1";
+                       };
+
+                       reg_bldo1: bldo1 {
+                               regulator-always-on;
+                               regulator-min-microvolt = <1800000>;
+                               regulator-max-microvolt = <1800000>;
+                               regulator-name = "vcc18-dram-bias-pll";
+                       };
+
+                       reg_bldo2: bldo2 {
+                               regulator-always-on;
+                               regulator-min-microvolt = <1800000>;
+                               regulator-max-microvolt = <1800000>;
+                               regulator-name = "vcc-efuse-pcie-hdmi-pc";
+                       };
+
+                       bldo3 {
+                               /* unused */
+                       };
+
+                       bldo4 {
+                               /* unused */
+                       };
+
+                       reg_cldo1: cldo1 {
+                               regulator-always-on;
+                               regulator-min-microvolt = <3300000>;
+                               regulator-max-microvolt = <3300000>;
+                               regulator-name = "vcc33-io-pd-emmc-sd-usb-uart-2";
+                       };
+
+                       cldo2 {
+                               /* unused */
+                       };
+
+                       cldo3 {
+                               /* unused */
+                       };
+
+                       reg_dcdca: dcdca {
+                               regulator-always-on;
+                               regulator-min-microvolt = <800000>;
+                               regulator-max-microvolt = <1160000>;
+                               regulator-name = "vdd-cpu";
+                       };
+
+                       reg_dcdcc: dcdcc {
+                               regulator-min-microvolt = <810000>;
+                               regulator-max-microvolt = <1080000>;
+                               regulator-name = "vdd-gpu";
+                       };
+
+                       reg_dcdcd: dcdcd {
+                               regulator-always-on;
+                               regulator-min-microvolt = <960000>;
+                               regulator-max-microvolt = <960000>;
+                               regulator-name = "vdd-sys";
+                       };
+
+                       reg_dcdce: dcdce {
+                               regulator-always-on;
+                               regulator-min-microvolt = <1200000>;
+                               regulator-max-microvolt = <1200000>;
+                               regulator-name = "vcc-dram";
+                       };
+
+                       sw {
+                               /* unused */
+                       };
+               };
+       };
+};
+
+&uart0 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&uart0_ph_pins>;
+       status = "okay";
+};
+
+&usb2otg {
+       /*
+        * This board doesn't have a controllable VBUS even though it
+        * does have an ID pin. Using it as anything but a USB host is
+        * unsafe.
+        */
+       dr_mode = "host";
+       status = "okay";
+};
+
+&usb2phy {
+       usb0_id_det-gpios = <&pio 2 15 GPIO_ACTIVE_HIGH>; /* PC15 */
+       usb0_vbus-supply = <&reg_vcc5v>;
+       usb3_vbus-supply = <&reg_vcc5v>;
+       status = "okay";
+};

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi
index b2526da..62e2794 100644 (file)
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi
@@ -56,8 +56,6 @@
 };
 
 &mmc0 {
-       pinctrl-names = "default";
-       pinctrl-0 = <&mmc0_pins>;
        vmmc-supply = <&reg_cldo1>;
        cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>;
        bus-width = <4>;

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts
index bdb8470..4802902 100644 (file)
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts
@@ -104,8 +104,6 @@
 };
 
 &mmc0 {
-       pinctrl-names = "default";
-       pinctrl-0 = <&mmc0_pins>;
        vmmc-supply = <&reg_cldo1>;
        cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>;
        bus-width = <4>;
@@ -113,8 +111,6 @@
 };
 
 &mmc2 {
-       pinctrl-names = "default";
-       pinctrl-0 = <&mmc2_pins>;
        vmmc-supply = <&reg_cldo1>;
        vqmmc-supply = <&reg_bldo2>;
        non-removable;

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
index c9e861a..16c5c3d 100644 (file)
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
@@ -101,7 +101,7 @@
                #size-cells = <1>;
                ranges;
 
-               display-engine@1000000 {
+               bus@1000000 {
                        compatible = "allwinner,sun50i-h6-de3",
                                     "allwinner,sun50i-a64-de2";
                        reg = <0x1000000 0x400000>;
@@ -146,6 +146,17 @@
                        };
                };
 
+               video-codec@1c0e000 {
+                       compatible = "allwinner,sun50i-h6-video-engine";
+                       reg = <0x01c0e000 0x2000>;
+                       clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>,
+                                <&ccu CLK_MBUS_VE>;
+                       clock-names = "ahb", "mod", "ram";
+                       resets = <&ccu RST_BUS_VE>;
+                       interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
+                       allwinner,sram = <&ve_sram 1>;
+               };
+
                syscon: syscon@3000000 {
                        compatible = "allwinner,sun50i-h6-system-control",
                                     "allwinner,sun50i-a64-system-control";
@@ -192,6 +203,11 @@
                        #reset-cells = <1>;
                };
 
+               sid: sid@3006000 {
+                       compatible = "allwinner,sun50i-h6-sid";
+                       reg = <0x03006000 0x400>;
+               };
+
                pio: pinctrl@300b000 {
                        compatible = "allwinner,sun50i-h6-pinctrl";
                        reg = <0x0300b000 0x400>;
@@ -206,7 +222,7 @@
                        interrupt-controller;
                        #interrupt-cells = <3>;
 
-                       ext_rgmii_pins: rgmii_pins {
+                       ext_rgmii_pins: rgmii-pins {
                                pins = "PD0", "PD1", "PD2", "PD3", "PD4",
                                       "PD5", "PD7", "PD8", "PD9", "PD10",
                                       "PD11", "PD12", "PD13", "PD19", "PD20";
@@ -227,6 +243,15 @@
                                bias-pull-up;
                        };
 
+                       /omit-if-no-ref/
+                       mmc1_pins: mmc1-pins {
+                               pins = "PG0", "PG1", "PG2", "PG3",
+                                      "PG4", "PG5";
+                               function = "mmc1";
+                               drive-strength = <30>;
+                               bias-pull-up;
+                       };
+
                        mmc2_pins: mmc2-pins {
                                pins = "PC1", "PC4", "PC5", "PC6",
                                       "PC7", "PC8", "PC9", "PC10",
@@ -236,7 +261,7 @@
                                bias-pull-up;
                        };
 
-                       uart0_ph_pins: uart0-ph {
+                       uart0_ph_pins: uart0-ph-pins {
                                pins = "PH0", "PH1";
                                function = "uart0";
                        };
@@ -262,6 +287,8 @@
                        resets = <&ccu RST_BUS_MMC0>;
                        reset-names = "ahb";
                        interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+                       pinctrl-names = "default";
+                       pinctrl-0 = <&mmc0_pins>;
                        status = "disabled";
                        #address-cells = <1>;
                        #size-cells = <0>;
@@ -276,6 +303,8 @@
                        resets = <&ccu RST_BUS_MMC1>;
                        reset-names = "ahb";
                        interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+                       pinctrl-names = "default";
+                       pinctrl-0 = <&mmc1_pins>;
                        status = "disabled";
                        #address-cells = <1>;
                        #size-cells = <0>;
@@ -290,6 +319,8 @@
                        resets = <&ccu RST_BUS_MMC2>;
                        reset-names = "ahb";
                        interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+                       pinctrl-names = "default";
+                       pinctrl-0 = <&mmc2_pins>;
                        status = "disabled";
                        #address-cells = <1>;
                        #size-cells = <0>;
@@ -425,7 +456,6 @@
                        resets = <&ccu RST_BUS_OHCI3>,
                                 <&ccu RST_BUS_EHCI3>;
                        phys = <&usb2phy 3>;
-                       phy-names = "usb";
                        status = "disabled";
                };
 
@@ -437,7 +467,6 @@
                                 <&ccu CLK_USB_OHCI3>;
                        resets = <&ccu RST_BUS_OHCI3>;
                        phys = <&usb2phy 3>;
-                       phy-names = "usb";
                        status = "disabled";
                };
 
@@ -614,7 +643,7 @@
                        interrupt-controller;
                        #interrupt-cells = <3>;
 
-                       r_i2c_pins: r-i2c {
+                       r_i2c_pins: r-i2c-pins {
                                pins = "PL0", "PL1";
                                function = "s_i2c";
                        };

diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts
index 2e3863e..d037563 100644 (file)
--- a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts
+++ b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts
@@ -107,6 +107,7 @@
 &mmc {
        status = "okay";
        cap-sd-highspeed;
+       cap-mmc-highspeed;
        broken-cd;
        bus-width = <4>;
 };
@@ -159,7 +160,7 @@
                #size-cells = <1>;
                compatible = "n25q00a";
                reg = <0>;
-               spi-max-frequency = <50000000>;
+               spi-max-frequency = <100000000>;
 
                m25p,fast-read;
                cdns,page-size = <256>;

diff --git a/arch/arm64/boot/dts/amlogic/Makefile b/arch/arm64/boot/dts/amlogic/Makefile
index 0821fed..e129c03 100644 (file)
--- a/arch/arm64/boot/dts/amlogic/Makefile
+++ b/arch/arm64/boot/dts/amlogic/Makefile
@@ -1,5 +1,6 @@
 # SPDX-License-Identifier: GPL-2.0
 dtb-$(CONFIG_ARCH_MESON) += meson-axg-s400.dtb
+dtb-$(CONFIG_ARCH_MESON) += meson-g12a-sei510.dtb
 dtb-$(CONFIG_ARCH_MESON) += meson-g12a-u200.dtb
 dtb-$(CONFIG_ARCH_MESON) += meson-g12a-x96-max.dtb
 dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-nanopi-k2.dtb

diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a-sei510.dts b/arch/arm64/boot/dts/amlogic/meson-g12a-sei510.dts
new file mode 100644 (file)
index 0000000..34b4058
--- /dev/null
+++ b/arch/arm64/boot/dts/amlogic/meson-g12a-sei510.dts
@@ -0,0 +1,185 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 BayLibre SAS. All rights reserved.
+ */
+
+/dts-v1/;
+
+#include "meson-g12a.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/meson-g12a-gpio.h>
+
+/ {
+       compatible = "seirobotics,sei510", "amlogic,g12a";
+       model = "SEI Robotics SEI510";
+
+       aliases {
+               serial0 = &uart_AO;
+       };
+
+       adc_keys {
+               compatible = "adc-keys";
+               io-channels = <&saradc 0>;
+               io-channel-names = "buttons";
+               keyup-threshold-microvolt = <1800000>;
+
+               button-onoff {
+                       label = "On/Off";
+                       linux,code = <KEY_POWER>;
+                       press-threshold-microvolt = <1700000>;
+               };
+       };
+
+       ao_5v: regulator-ao_5v {
+               compatible = "regulator-fixed";
+               regulator-name = "AO_5V";
+               regulator-min-microvolt = <5000000>;
+               regulator-max-microvolt = <5000000>;
+               vin-supply = <&dc_in>;
+               regulator-always-on;
+       };
+
+       chosen {
+               stdout-path = "serial0:115200n8";
+       };
+
+       cvbs-connector {
+               compatible = "composite-video-connector";
+
+               port {
+                       cvbs_connector_in: endpoint {
+                               remote-endpoint = <&cvbs_vdac_out>;
+                       };
+               };
+       };
+
+       dc_in: regulator-dc_in {
+               compatible = "regulator-fixed";
+               regulator-name = "DC_IN";
+               regulator-min-microvolt = <5000000>;
+               regulator-max-microvolt = <5000000>;
+               regulator-always-on;
+       };
+
+       emmc_1v8: regulator-emmc_1v8 {
+               compatible = "regulator-fixed";
+               regulator-name = "EMMC_1V8";
+               regulator-min-microvolt = <1800000>;
+               regulator-max-microvolt = <1800000>;
+               vin-supply = <&vddao_3v3>;
+               regulator-always-on;
+       };
+
+       hdmi-connector {
+               compatible = "hdmi-connector";
+               type = "a";
+
+               port {
+                       hdmi_connector_in: endpoint {
+                               remote-endpoint = <&hdmi_tx_tmds_out>;
+                       };
+               };
+       };
+
+       memory@0 {
+               device_type = "memory";
+               reg = <0x0 0x0 0x0 0x40000000>;
+       };
+
+       reserved-memory {
+               /* TEE Reserved Memory */
+               bl32_reserved: bl32@5000000 {
+                       reg = <0x0 0x05300000 0x0 0x2000000>;
+                       no-map;
+               };
+       };
+
+       vddao_3v3: regulator-vddao_3v3 {
+               compatible = "regulator-fixed";
+               regulator-name = "VDDAO_3V3";
+               regulator-min-microvolt = <3300000>;
+               regulator-max-microvolt = <3300000>;
+               vin-supply = <&dc_in>;
+               regulator-always-on;
+       };
+
+       vddao_3v3_t: regultor-vddao_3v3_t {
+               compatible = "regulator-fixed";
+               regulator-name = "VDDAO_3V3_T";
+               regulator-min-microvolt = <3300000>;
+               regulator-max-microvolt = <3300000>;
+               vin-supply = <&vddao_3v3>;
+               gpio = <&gpio GPIOH_8 GPIO_OPEN_DRAIN>;
+               enable-active-high;
+       };
+
+       vddio_ao1v8: regulator-vddio_ao1v8 {
+               compatible = "regulator-fixed";
+               regulator-name = "VDDIO_AO1V8";
+               regulator-min-microvolt = <1800000>;
+               regulator-max-microvolt = <1800000>;
+               vin-supply = <&vddao_3v3>;
+               regulator-always-on;
+       };
+};
+
+&cec_AO {
+       pinctrl-0 = <&cec_ao_a_h_pins>;
+       pinctrl-names = "default";
+       status = "disabled";
+       hdmi-phandle = <&hdmi_tx>;
+};
+
+&cecb_AO {
+       pinctrl-0 = <&cec_ao_b_h_pins>;
+       pinctrl-names = "default";
+       status = "okay";
+       hdmi-phandle = <&hdmi_tx>;
+};
+
+&cvbs_vdac_port {
+       cvbs_vdac_out: endpoint {
+               remote-endpoint = <&cvbs_connector_in>;
+       };
+};
+
+&saradc {
+       status = "okay";
+       vref-supply = <&vddio_ao1v8>;
+};
+
+&uart_A {
+       status = "okay";
+       pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>;
+       pinctrl-names = "default";
+       uart-has-rtscts;
+
+       bluetooth {
+               compatible = "brcm,bcm43438-bt";
+               shutdown-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>;
+       };
+};
+
+&hdmi_tx {
+       status = "okay";
+       pinctrl-0 = <&hdmitx_hpd_pins>, <&hdmitx_ddc_pins>;
+       pinctrl-names = "default";
+};
+
+&hdmi_tx_tmds_port {
+       hdmi_tx_tmds_out: endpoint {
+               remote-endpoint = <&hdmi_connector_in>;
+       };
+};
+
+&uart_AO {
+       status = "okay";
+       pinctrl-0 = <&uart_ao_a_pins>;
+       pinctrl-names = "default";
+};
+
+&usb {
+       status = "okay";
+       dr_mode = "host";
+};

diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a-u200.dts b/arch/arm64/boot/dts/amlogic/meson-g12a-u200.dts
index c44dbdd..0e8045b 100644 (file)
--- a/arch/arm64/boot/dts/amlogic/meson-g12a-u200.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-g12a-u200.dts
@@ -6,6 +6,8 @@
 /dts-v1/;
 
 #include "meson-g12a.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/gpio/meson-g12a-gpio.h>
 
 / {
        compatible = "amlogic,u200", "amlogic,g12a";
@@ -21,9 +23,154 @@
                device_type = "memory";
                reg = <0x0 0x0 0x0 0x40000000>;
        };
+
+       cvbs-connector {
+               compatible = "composite-video-connector";
+
+               port {
+                       cvbs_connector_in: endpoint {
+                               remote-endpoint = <&cvbs_vdac_out>;
+                       };
+               };
+       };
+
+       flash_1v8: regulator-flash_1v8 {
+               compatible = "regulator-fixed";
+               regulator-name = "FLASH_1V8";
+               regulator-min-microvolt = <1800000>;
+               regulator-max-microvolt = <1800000>;
+               vin-supply = <&vcc_3v3>;
+               regulator-always-on;
+       };
+
+       hdmi-connector {
+               compatible = "hdmi-connector";
+               type = "a";
+
+               port {
+                       hdmi_connector_in: endpoint {
+                               remote-endpoint = <&hdmi_tx_tmds_out>;
+                       };
+               };
+       };
+
+       main_12v: regulator-main_12v {
+               compatible = "regulator-fixed";
+               regulator-name = "12V";
+               regulator-min-microvolt = <12000000>;
+               regulator-max-microvolt = <12000000>;
+               regulator-always-on;
+       };
+
+       vcc_1v8: regulator-vcc_1v8 {
+               compatible = "regulator-fixed";
+               regulator-name = "VCC_1V8";
+               regulator-min-microvolt = <1800000>;
+               regulator-max-microvolt = <1800000>;
+               vin-supply = <&vcc_3v3>;
+               regulator-always-on;
+       };
+
+       vcc_3v3: regulator-vcc_3v3 {
+               compatible = "regulator-fixed";
+               regulator-name = "VCC_3V3";
+               regulator-min-microvolt = <3300000>;
+               regulator-max-microvolt = <3300000>;
+               vin-supply = <&vddao_3v3>;
+               regulator-always-on;
+               /* FIXME: actually controlled by VDDCPU_B_EN */
+       };
+
+       vcc_5v: regulator-vcc_5v {
+               compatible = "regulator-fixed";
+               regulator-name = "VCC_5V";
+               regulator-min-microvolt = <5000000>;
+               regulator-max-microvolt = <5000000>;
+               vin-supply = <&main_12v>;
+
+               gpio = <&gpio GPIOH_8 GPIO_OPEN_DRAIN>;
+               enable-active-high;
+       };
+
+       usb_pwr_en: regulator-usb_pwr_en {
+               compatible = "regulator-fixed";
+               regulator-name = "USB_PWR_EN";
+               regulator-min-microvolt = <5000000>;
+               regulator-max-microvolt = <5000000>;
+               vin-supply = <&vcc_5v>;
+
+               gpio = <&gpio GPIOH_6 GPIO_ACTIVE_HIGH>;
+               enable-active-high;
+       };
+
+       vddao_1v8: regulator-vddao_1v8 {
+               compatible = "regulator-fixed";
+               regulator-name = "VDDAO_1V8";
+               regulator-min-microvolt = <1800000>;
+               regulator-max-microvolt = <1800000>;
+               vin-supply = <&vddao_3v3>;
+               regulator-always-on;
+       };
+
+       vddao_3v3: regulator-vddao_3v3 {
+               compatible = "regulator-fixed";
+               regulator-name = "VDDAO_3V3";
+               regulator-min-microvolt = <3300000>;
+               regulator-max-microvolt = <3300000>;
+               vin-supply = <&main_12v>;
+               regulator-always-on;
+       };
+
+};
+
+&cec_AO {
+       pinctrl-0 = <&cec_ao_a_h_pins>;
+       pinctrl-names = "default";
+       status = "disabled";
+       hdmi-phandle = <&hdmi_tx>;
+};
+
+&cecb_AO {
+       pinctrl-0 = <&cec_ao_b_h_pins>;
+       pinctrl-names = "default";
+       status = "okay";
+       hdmi-phandle = <&hdmi_tx>;
+};
+
+&cvbs_vdac_port {
+       cvbs_vdac_out: endpoint {
+               remote-endpoint = <&cvbs_connector_in>;
+       };
+};
+
+&hdmi_tx {
+       status = "okay";
+       pinctrl-0 = <&hdmitx_hpd_pins>, <&hdmitx_ddc_pins>;
+       pinctrl-names = "default";
+       hdmi-supply = <&vcc_5v>;
+};
+
+&hdmi_tx_tmds_port {
+       hdmi_tx_tmds_out: endpoint {
+               remote-endpoint = <&hdmi_connector_in>;
+       };
 };
 
 &uart_AO {
        status = "okay";
+       pinctrl-0 = <&uart_ao_a_pins>;
+       pinctrl-names = "default";
 };
 
+&usb {
+       status = "okay";
+       vbus-supply = <&usb_pwr_en>;
+};
+
+&usb2_phy0 {
+       phy-supply = <&vcc_5v>;
+};
+
+&usb2_phy1 {
+       phy-supply = <&vcc_5v>;
+};

diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a-x96-max.dts b/arch/arm64/boot/dts/amlogic/meson-g12a-x96-max.dts
index c62d3d5..b3d913f 100644 (file)
--- a/arch/arm64/boot/dts/amlogic/meson-g12a-x96-max.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-g12a-x96-max.dts
@@ -6,6 +6,8 @@
 /dts-v1/;
 
 #include "meson-g12a.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/gpio/meson-g12a-gpio.h>
 
 / {
        compatible = "amediatech,x96-max", "amlogic,u200", "amlogic,g12a";
@@ -21,8 +23,146 @@
                device_type = "memory";
                reg = <0x0 0x0 0x0 0x40000000>;
        };
+
+       cvbs-connector {
+               compatible = "composite-video-connector";
+
+               port {
+                       cvbs_connector_in: endpoint {
+                               remote-endpoint = <&cvbs_vdac_out>;
+                       };
+               };
+       };
+
+       hdmi-connector {
+               compatible = "hdmi-connector";
+               type = "a";
+
+               port {
+                       hdmi_connector_in: endpoint {
+                               remote-endpoint = <&hdmi_tx_tmds_out>;
+                       };
+               };
+       };
+
+       flash_1v8: regulator-flash_1v8 {
+               compatible = "regulator-fixed";
+               regulator-name = "FLASH_1V8";
+               regulator-min-microvolt = <1800000>;
+               regulator-max-microvolt = <1800000>;
+               vin-supply = <&vcc_3v3>;
+               regulator-always-on;
+       };
+
+       dc_in: regulator-dc_in {
+               compatible = "regulator-fixed";
+               regulator-name = "DC_IN";
+               regulator-min-microvolt = <5000000>;
+               regulator-max-microvolt = <5000000>;
+               regulator-always-on;
+       };
+
+       vcc_1v8: regulator-vcc_1v8 {
+               compatible = "regulator-fixed";
+               regulator-name = "VCC_1V8";
+               regulator-min-microvolt = <1800000>;
+               regulator-max-microvolt = <1800000>;
+               vin-supply = <&vcc_3v3>;
+               regulator-always-on;
+       };
+
+       vcc_3v3: regulator-vcc_3v3 {
+               compatible = "regulator-fixed";
+               regulator-name = "VCC_3V3";
+               regulator-min-microvolt = <3300000>;
+               regulator-max-microvolt = <3300000>;
+               vin-supply = <&vddao_3v3>;
+               regulator-always-on;
+               /* FIXME: actually controlled by VDDCPU_B_EN */
+       };
+
+       vcc_5v: regulator-vcc_5v {
+               compatible = "regulator-fixed";
+               regulator-name = "VCC_5V";
+               regulator-min-microvolt = <5000000>;
+               regulator-max-microvolt = <5000000>;
+               vin-supply = <&dc_in>;
+
+               gpio = <&gpio GPIOH_8 GPIO_OPEN_DRAIN>;
+               enable-active-low;
+       };
+
+       vddao_1v8: regulator-vddao_1v8 {
+               compatible = "regulator-fixed";
+               regulator-name = "VDDAO_1V8";
+               regulator-min-microvolt = <1800000>;
+               regulator-max-microvolt = <1800000>;
+               vin-supply = <&vddao_3v3>;
+               regulator-always-on;
+       };
+
+       vddao_3v3: regulator-vddao_3v3 {
+               compatible = "regulator-fixed";
+               regulator-name = "VDDAO_3V3";
+               regulator-min-microvolt = <3300000>;
+               regulator-max-microvolt = <3300000>;
+               vin-supply = <&dc_in>;
+               regulator-always-on;
+       };
+};
+
+&cec_AO {
+       pinctrl-0 = <&cec_ao_a_h_pins>;
+       pinctrl-names = "default";
+       status = "disabled";
+       hdmi-phandle = <&hdmi_tx>;
+};
+
+&cecb_AO {
+       pinctrl-0 = <&cec_ao_b_h_pins>;
+       pinctrl-names = "default";
+       status = "okay";
+       hdmi-phandle = <&hdmi_tx>;
+};
+
+&cvbs_vdac_port {
+       cvbs_vdac_out: endpoint {
+               remote-endpoint = <&cvbs_connector_in>;
+       };
+};
+
+&hdmi_tx {
+       status = "okay";
+       pinctrl-0 = <&hdmitx_hpd_pins>, <&hdmitx_ddc_pins>;
+       pinctrl-names = "default";
+       hdmi-supply = <&vcc_5v>;
+};
+
+&hdmi_tx_tmds_port {
+       hdmi_tx_tmds_out: endpoint {
+               remote-endpoint = <&hdmi_connector_in>;
+       };
+};
+
+&uart_A {
+       status = "okay";
+       pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>;
+       pinctrl-names = "default";
+       uart-has-rtscts;
+
+       bluetooth {
+               compatible = "brcm,bcm43438-bt";
+               shutdown-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>;
+       };
 };
 
 &uart_AO {
        status = "okay";
+       pinctrl-0 = <&uart_ao_a_pins>;
+       pinctrl-names = "default";
+};
+
+&usb {
+       status = "okay";
+       dr_mode = "host";
 };

diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
index 17c6217..9f72396 100644 (file)
--- a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
@@ -3,9 +3,13 @@
  * Copyright (c) 2018 Amlogic, Inc. All rights reserved.
  */
 
+#include <dt-bindings/phy/phy.h>
 #include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/clock/g12a-clkc.h>
+#include <dt-bindings/clock/g12a-aoclkc.h>
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/reset/amlogic,meson-g12a-reset.h>
 
 / {
        compatible = "amlogic,g12a";
@@ -55,6 +59,14 @@
                };
        };
 
+       efuse: efuse {
+               compatible = "amlogic,meson-gxbb-efuse";
+               clocks = <&clkc CLKID_EFUSE>;
+               #address-cells = <1>;
+               #size-cells = <1>;
+               read-only;
+       };
+
        psci {
                compatible = "arm,psci-1.0";
                method = "smc";
@@ -70,6 +82,18 @@
                        reg = <0x0 0x05000000 0x0 0x300000>;
                        no-map;
                };
+
+               linux,cma {
+                       compatible = "shared-dma-pool";
+                       reusable;
+                       size = <0x0 0x10000000>;
+                       alignment = <0x0 0x400000>;
+                       linux,cma-default;
+               };
+       };
+
+       sm: secure-monitor {
+               compatible = "amlogic,meson-gxbb-sm";
        };
 
        soc {
@@ -85,12 +109,177 @@
                        #size-cells = <2>;
                        ranges = <0x0 0x0 0x0 0xff600000 0x0 0x200000>;
 
+                       hdmi_tx: hdmi-tx@0 {
+                               compatible = "amlogic,meson-g12a-dw-hdmi";
+                               reg = <0x0 0x0 0x0 0x10000>;
+                               interrupts = <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>;
+                               resets = <&reset RESET_HDMITX_CAPB3>,
+                                        <&reset RESET_HDMITX_PHY>,
+                                        <&reset RESET_HDMITX>;
+                               reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy";
+                               clocks = <&clkc CLKID_HDMI>,
+                                        <&clkc CLKID_HTX_PCLK>,
+                                        <&clkc CLKID_VPU_INTR>;
+                               clock-names = "isfr", "iahb", "venci";
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                               status = "disabled";
+
+                               /* VPU VENC Input */
+                               hdmi_tx_venc_port: port@0 {
+                                       reg = <0>;
+
+                                       hdmi_tx_in: endpoint {
+                                               remote-endpoint = <&hdmi_tx_out>;
+                                       };
+                               };
+
+                               /* TMDS Output */
+                               hdmi_tx_tmds_port: port@1 {
+                                       reg = <1>;
+                               };
+                       };
+
                        periphs: bus@34400 {
                                compatible = "simple-bus";
                                reg = <0x0 0x34400 0x0 0x400>;
                                #address-cells = <2>;
                                #size-cells = <2>;
                                ranges = <0x0 0x0 0x0 0x34400 0x0 0x400>;
+
+                               periphs_pinctrl: pinctrl@40 {
+                                       compatible = "amlogic,meson-g12a-periphs-pinctrl";
+                                       #address-cells = <2>;
+                                       #size-cells = <2>;
+                                       ranges;
+
+                                       gpio: bank@40 {
+                                               reg = <0x0 0x40  0x0 0x4c>,
+                                                     <0x0 0xe8  0x0 0x18>,
+                                                     <0x0 0x120 0x0 0x18>,
+                                                     <0x0 0x2c0 0x0 0x40>,
+                                                     <0x0 0x340 0x0 0x1c>;
+                                               reg-names = "gpio",
+                                                           "pull",
+                                                           "pull-enable",
+                                                           "mux",
+                                                           "ds";
+                                               gpio-controller;
+                                               #gpio-cells = <2>;
+                                               gpio-ranges = <&periphs_pinctrl 0 0 86>;
+                                       };
+
+                                       cec_ao_a_h_pins: cec_ao_a_h {
+                                               mux {
+                                                       groups = "cec_ao_a_h";
+                                                       function = "cec_ao_a_h";
+                                                       bias-disable;
+                                               };
+                                       };
+
+                                       cec_ao_b_h_pins: cec_ao_b_h {
+                                               mux {
+                                                       groups = "cec_ao_b_h";
+                                                       function = "cec_ao_b_h";
+                                                       bias-disable;
+                                               };
+                                       };
+
+                                       hdmitx_ddc_pins: hdmitx_ddc {
+                                               mux {
+                                                       groups = "hdmitx_sda",
+                                                                "hdmitx_sck";
+                                                       function = "hdmitx";
+                                                       bias-disable;
+                                               };
+                                       };
+
+                                       hdmitx_hpd_pins: hdmitx_hpd {
+                                               mux {
+                                                       groups = "hdmitx_hpd_in";
+                                                       function = "hdmitx";
+                                                       bias-disable;
+                                               };
+                                       };
+
+                                       uart_a_pins: uart-a {
+                                               mux {
+                                                       groups = "uart_a_tx",
+                                                                "uart_a_rx";
+                                                       function = "uart_a";
+                                                       bias-disable;
+                                               };
+                                       };
+
+                                       uart_a_cts_rts_pins: uart-a-cts-rts {
+                                               mux {
+                                                       groups = "uart_a_cts",
+                                                                "uart_a_rts";
+                                                       function = "uart_a";
+                                                       bias-disable;
+                                               };
+                                       };
+
+                                       uart_b_pins: uart-b {
+                                               mux {
+                                                       groups = "uart_b_tx",
+                                                                "uart_b_rx";
+                                                       function = "uart_b";
+                                                       bias-disable;
+                                               };
+                                       };
+
+                                       uart_c_pins: uart-c {
+                                               mux {
+                                                       groups = "uart_c_tx",
+                                                                "uart_c_rx";
+                                                       function = "uart_c";
+                                                       bias-disable;
+                                               };
+                                       };
+
+                                       uart_c_cts_rts_pins: uart-c-cts-rts {
+                                               mux {
+                                                       groups = "uart_c_cts",
+                                                                "uart_c_rts";
+                                                       function = "uart_c";
+                                                       bias-disable;
+                                               };
+                                       };
+                               };
+                       };
+
+                       usb2_phy0: phy@36000 {
+                               compatible = "amlogic,g12a-usb2-phy";
+                               reg = <0x0 0x36000 0x0 0x2000>;
+                               clocks = <&xtal>;
+                               clock-names = "xtal";
+                               resets = <&reset RESET_USB_PHY20>;
+                               reset-names = "phy";
+                               #phy-cells = <0>;
+                       };
+
+                       dmc: bus@38000 {
+                               compatible = "simple-bus";
+                               reg = <0x0 0x38000 0x0 0x400>;
+                               #address-cells = <2>;
+                               #size-cells = <2>;
+                               ranges = <0x0 0x0 0x0 0x38000 0x0 0x400>;
+
+                               canvas: video-lut@48 {
+                                       compatible = "amlogic,canvas";
+                                       reg = <0x0 0x48 0x0 0x14>;
+                               };
+                       };
+
+                       usb2_phy1: phy@3a000 {
+                               compatible = "amlogic,g12a-usb2-phy";
+                               reg = <0x0 0x3a000 0x0 0x2000>;
+                               clocks = <&xtal>;
+                               clock-names = "xtal";
+                               resets = <&reset RESET_USB_PHY21>;
+                               reset-names = "phy";
+                               #phy-cells = <0>;
                        };
 
                        hiu: bus@3c000 {
@@ -113,6 +302,18 @@
                                        };
                                };
                        };
+
+                       usb3_pcie_phy: phy@46000 {
+                               compatible = "amlogic,g12a-usb3-pcie-phy";
+                               reg = <0x0 0x46000 0x0 0x2000>;
+                               clocks = <&clkc CLKID_PCIE_PLL>;
+                               clock-names = "ref_clk";
+                               resets = <&reset RESET_PCIE_PHY>;
+                               reset-names = "phy";
+                               assigned-clocks = <&clkc CLKID_PCIE_PLL>;
+                               assigned-clock-rates = <100000000>;
+                               #phy-cells = <1>;
+                       };
                };
 
                aobus: bus@ff800000 {
@@ -122,6 +323,128 @@
                        #size-cells = <2>;
                        ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>;
 
+                       rti: sys-ctrl@0 {
+                               compatible = "amlogic,meson-gx-ao-sysctrl",
+                                            "simple-mfd", "syscon";
+                               reg = <0x0 0x0 0x0 0x100>;
+                               #address-cells = <2>;
+                               #size-cells = <2>;
+                               ranges = <0x0 0x0 0x0 0x0 0x0 0x100>;
+
+                               clkc_AO: clock-controller {
+                                       compatible = "amlogic,meson-g12a-aoclkc";
+                                       #clock-cells = <1>;
+                                       #reset-cells = <1>;
+                                       clocks = <&xtal>, <&clkc CLKID_CLK81>;
+                                       clock-names = "xtal", "mpeg-clk";
+                               };
+
+                               pwrc_vpu: power-controller-vpu {
+                                       compatible = "amlogic,meson-g12a-pwrc-vpu";
+                                       #power-domain-cells = <0>;
+                                       amlogic,hhi-sysctrl = <&hhi>;
+                                       resets = <&reset RESET_VIU>,
+                                                <&reset RESET_VENC>,
+                                                <&reset RESET_VCBUS>,
+                                                <&reset RESET_BT656>,
+                                                <&reset RESET_RDMA>,
+                                                <&reset RESET_VENCI>,
+                                                <&reset RESET_VENCP>,
+                                                <&reset RESET_VDAC>,
+                                                <&reset RESET_VDI6>,
+                                                <&reset RESET_VENCL>,
+                                                <&reset RESET_VID_LOCK>;
+                                       clocks = <&clkc CLKID_VPU>,
+                                                <&clkc CLKID_VAPB>;
+                                       clock-names = "vpu", "vapb";
+                                       /*
+                                        * VPU clocking is provided by two identical clock paths
+                                        * VPU_0 and VPU_1 muxed to a single clock by a glitch
+                                        * free mux to safely change frequency while running.
+                                        * Same for VAPB but with a final gate after the glitch free mux.
+                                        */
+                                       assigned-clocks = <&clkc CLKID_VPU_0_SEL>,
+                                                         <&clkc CLKID_VPU_0>,
+                                                         <&clkc CLKID_VPU>, /* Glitch free mux */
+                                                         <&clkc CLKID_VAPB_0_SEL>,
+                                                         <&clkc CLKID_VAPB_0>,
+                                                         <&clkc CLKID_VAPB_SEL>; /* Glitch free mux */
+                                       assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
+                                                                <0>, /* Do Nothing */
+                                                                <&clkc CLKID_VPU_0>,
+                                                                <&clkc CLKID_FCLK_DIV4>,
+                                                                <0>, /* Do Nothing */
+                                                                <&clkc CLKID_VAPB_0>;
+                                       assigned-clock-rates = <0>, /* Do Nothing */
+                                                              <666666666>,
+                                                              <0>, /* Do Nothing */
+                                                              <0>, /* Do Nothing */
+                                                              <250000000>,
+                                                              <0>; /* Do Nothing */
+                               };
+
+                               ao_pinctrl: pinctrl@14 {
+                                       compatible = "amlogic,meson-g12a-aobus-pinctrl";
+                                       #address-cells = <2>;
+                                       #size-cells = <2>;
+                                       ranges;
+
+                                       gpio_ao: bank@14 {
+                                               reg = <0x0 0x14 0x0 0x8>,
+                                                     <0x0 0x1c 0x0 0x8>,
+                                                     <0x0 0x24 0x0 0x14>;
+                                               reg-names = "mux",
+                                                           "ds",
+                                                           "gpio";
+                                               gpio-controller;
+                                               #gpio-cells = <2>;
+                                               gpio-ranges = <&ao_pinctrl 0 0 15>;
+                                       };
+
+                                       uart_ao_a_pins: uart-a-ao {
+                                               mux {
+                                                       groups = "uart_ao_a_tx",
+                                                                "uart_ao_a_rx";
+                                                       function = "uart_ao_a";
+                                                       bias-disable;
+                                               };
+                                       };
+
+                                       uart_ao_a_cts_rts_pins: uart-ao-a-cts-rts {
+                                               mux {
+                                                       groups = "uart_ao_a_cts",
+                                                                "uart_ao_a_rts";
+                                                       function = "uart_ao_a";
+                                                       bias-disable;
+                                               };
+                                       };
+                               };
+                       };
+
+                       cec_AO: cec@100 {
+                               compatible = "amlogic,meson-gx-ao-cec";
+                               reg = <0x0 0x00100 0x0 0x14>;
+                               interrupts = <GIC_SPI 199 IRQ_TYPE_EDGE_RISING>;
+                               clocks = <&clkc_AO CLKID_AO_CEC>;
+                               clock-names = "core";
+                               status = "disabled";
+                       };
+
+                       sec_AO: ao-secure@140 {
+                               compatible = "amlogic,meson-gx-ao-secure", "syscon";
+                               reg = <0x0 0x140 0x0 0x140>;
+                               amlogic,has-chip-id;
+                       };
+
+                       cecb_AO: cec@280 {
+                               compatible = "amlogic,meson-g12a-ao-cec";
+                               reg = <0x0 0x00280 0x0 0x1c>;
+                               interrupts = <GIC_SPI 203 IRQ_TYPE_EDGE_RISING>;
+                               clocks = <&clkc_AO CLKID_AO_CTS_OSCIN>;
+                               clock-names = "oscin";
+                               status = "disabled";
+                       };
+
                        uart_AO: serial@3000 {
                                compatible = "amlogic,meson-gx-uart",
                                             "amlogic,meson-ao-uart";
@@ -141,6 +464,46 @@
                                clock-names = "xtal", "pclk", "baud";
                                status = "disabled";
                        };
+
+                       saradc: adc@9000 {
+                               compatible = "amlogic,meson-g12a-saradc",
+                                            "amlogic,meson-saradc";
+                               reg = <0x0 0x9000 0x0 0x48>;
+                               #io-channel-cells = <1>;
+                               interrupts = <GIC_SPI 200 IRQ_TYPE_EDGE_RISING>;
+                               clocks = <&xtal>,
+                                        <&clkc_AO CLKID_AO_SAR_ADC>,
+                                        <&clkc_AO CLKID_AO_SAR_ADC_CLK>,
+                                        <&clkc_AO CLKID_AO_SAR_ADC_SEL>;
+                               clock-names = "clkin", "core", "adc_clk", "adc_sel";
+                               status = "disabled";
+                       };
+               };
+
+               vpu: vpu@ff900000 {
+                       compatible = "amlogic,meson-g12a-vpu";
+                       reg = <0x0 0xff900000 0x0 0x100000>,
+                             <0x0 0xff63c000 0x0 0x1000>;
+                       reg-names = "vpu", "hhi";
+                       interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       amlogic,canvas = <&canvas>;
+                       power-domains = <&pwrc_vpu>;
+
+                       /* CVBS VDAC output port */
+                       cvbs_vdac_port: port@0 {
+                               reg = <0>;
+                       };
+
+                       /* HDMI-TX output port */
+                       hdmi_tx_port: port@1 {
+                               reg = <1>;
+
+                               hdmi_tx_out: endpoint {
+                                       remote-endpoint = <&hdmi_tx_in>;
+                               };
+                       };
                };
 
                gic: interrupt-controller@ffc01000 {
@@ -163,10 +526,112 @@
                        #size-cells = <2>;
                        ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x100000>;
 
+                       reset: reset-controller@1004 {
+                               compatible = "amlogic,meson-g12a-reset",
+                                            "amlogic,meson-axg-reset";
+                               reg = <0x0 0x1004 0x0 0x9c>;
+                               #reset-cells = <1>;
+                       };
+
                        clk_msr: clock-measure@18000 {
                                compatible = "amlogic,meson-g12a-clk-measure";
                                reg = <0x0 0x18000 0x0 0x10>;
                        };
+
+                       uart_C: serial@22000 {
+                               compatible = "amlogic,meson-gx-uart";
+                               reg = <0x0 0x22000 0x0 0x18>;
+                               interrupts = <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>;
+                               clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>;
+                               clock-names = "xtal", "pclk", "baud";
+                               status = "disabled";
+                       };
+
+                       uart_B: serial@23000 {
+                               compatible = "amlogic,meson-gx-uart";
+                               reg = <0x0 0x23000 0x0 0x18>;
+                               interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
+                               clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
+                               clock-names = "xtal", "pclk", "baud";
+                               status = "disabled";
+                       };
+
+                       uart_A: serial@24000 {
+                               compatible = "amlogic,meson-gx-uart";
+                               reg = <0x0 0x24000 0x0 0x18>;
+                               interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
+                               clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
+                               clock-names = "xtal", "pclk", "baud";
+                               status = "disabled";
+                       };
+               };
+
+               usb: usb@ffe09000 {
+                       status = "disabled";
+                       compatible = "amlogic,meson-g12a-usb-ctrl";
+                       reg = <0x0 0xffe09000 0x0 0xa0>;
+                       interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+                       #address-cells = <2>;
+                       #size-cells = <2>;
+                       ranges;
+
+                       clocks = <&clkc CLKID_USB>;
+                       resets = <&reset RESET_USB>;
+
+                       dr_mode = "otg";
+
+                       phys = <&usb2_phy0>, <&usb2_phy1>,
+                              <&usb3_pcie_phy PHY_TYPE_USB3>;
+                       phy-names = "usb2-phy0", "usb2-phy1", "usb3-phy0";
+
+                       dwc2: usb@ff400000 {
+                               compatible = "amlogic,meson-g12a-usb", "snps,dwc2";
+                               reg = <0x0 0xff400000 0x0 0x40000>;
+                               interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+                               clocks = <&clkc CLKID_USB1_DDR_BRIDGE>;
+                               clock-names = "ddr";
+                               phys = <&usb2_phy1>;
+                               dr_mode = "peripheral";
+                               g-rx-fifo-size = <192>;
+                               g-np-tx-fifo-size = <128>;
+                               g-tx-fifo-size = <128 128 16 16 16>;
+                       };
+
+                       dwc3: usb@ff500000 {
+                               compatible = "snps,dwc3";
+                               reg = <0x0 0xff500000 0x0 0x100000>;
+                               interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+                               dr_mode = "host";
+                               snps,dis_u2_susphy_quirk;
+                               snps,quirk-frame-length-adjustment;
+                       };
+               };
+
+               mali: gpu@ffe40000 {
+                       compatible = "amlogic,meson-g12a-mali", "arm,mali-bifrost";
+                       reg = <0x0 0xffe40000 0x0 0x40000>;
+                       interrupt-parent = <&gic>;
+                       interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-names = "gpu", "mmu", "job";
+                       clocks = <&clkc CLKID_MALI>;
+                       resets = <&reset RESET_DVALIN_CAPB3>, <&reset RESET_DVALIN>;
+
+                       /*
+                        * Mali clocking is provided by two identical clock paths
+                        * MALI_0 and MALI_1 muxed to a single clock by a glitch
+                        * free mux to safely change frequency while running.
+                        */
+                       assigned-clocks = <&clkc CLKID_MALI_0_SEL>,
+                                         <&clkc CLKID_MALI_0>,
+                                         <&clkc CLKID_MALI>; /* Glitch free mux */
+                       assigned-clock-parents = <&clkc CLKID_FCLK_DIV2P5>,
+                                                <0>, /* Do Nothing */
+                                                <&clkc CLKID_MALI_0>;
+                       assigned-clock-rates = <0>, /* Do Nothing */
+                                              <800000000>,
+                                              <0>; /* Do Nothing */
                };
        };
 

diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-phicomm-n1.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-phicomm-n1.dts
index 9a8a8a7..b5667f1 100644 (file)
--- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-phicomm-n1.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-phicomm-n1.dts
@@ -14,6 +14,16 @@
        cvbs-connector {
                status = "disabled";
        };
+
+       leds {
+               compatible = "gpio-leds";
+
+               status {
+                       label = "n1:white:status";
+                       gpios = <&gpio_ao GPIOAO_9 GPIO_ACTIVE_HIGH>;
+                       default-state = "on";
+               };
+       };
 };
 
 &cvbs_vdac_port {

diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts b/arch/arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts
index 8acfd40..25f3b6b 100644 (file)
--- a/arch/arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts
@@ -178,3 +178,7 @@
        pinctrl-0 = <&uart_ao_a_pins>;
        pinctrl-names = "default";
 };
+
+&usb0 {
+       status = "okay";
+};

diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxm.dtsi
index ed3a3d5..7a85a82 100644 (file)
--- a/arch/arm64/boot/dts/amlogic/meson-gxm.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gxm.dtsi
@@ -91,6 +91,33 @@
                reset-names = "phy";
                status = "okay";
        };
+
+       mali: gpu@c0000 {
+               compatible = "amlogic,meson-gxm-mali", "arm,mali-t820";
+               reg = <0x0 0xc0000 0x0 0x40000>;
+               interrupt-parent = <&gic>;
+               interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
+               interrupt-names = "gpu", "mmu", "job";
+               clocks = <&clkc CLKID_MALI>;
+               resets = <&reset RESET_MALI_CAPB3>, <&reset RESET_MALI>;
+
+               /*
+                * Mali clocking is provided by two identical clock paths
+                * MALI_0 and MALI_1 muxed to a single clock by a glitch
+                * free mux to safely change frequency while running.
+                */
+               assigned-clocks = <&clkc CLKID_MALI_0_SEL>,
+                                 <&clkc CLKID_MALI_0>,
+                                 <&clkc CLKID_MALI>; /* Glitch free mux */
+               assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
+                                        <0>, /* Do Nothing */
+                                        <&clkc CLKID_MALI_0>;
+               assigned-clock-rates = <0>, /* Do Nothing */
+                                      <666666666>,
+                                      <0>; /* Do Nothing */
+       };
 };
 
 &clkc_AO {

diff --git a/arch/arm64/boot/dts/bitmain/bm1880-sophon-edge.dts b/arch/arm64/boot/dts/bitmain/bm1880-sophon-edge.dts
index 6a32555..3e8c707 100644 (file)
--- a/arch/arm64/boot/dts/bitmain/bm1880-sophon-edge.dts
+++ b/arch/arm64/boot/dts/bitmain/bm1880-sophon-edge.dts
@@ -8,6 +8,28 @@
 
 #include "bm1880.dtsi"
 
+/*
+ * GPIO name legend: proper name = the GPIO line is used as GPIO
+ *         NC = not connected (pin out but not routed from the chip to
+ *              anything the board)
+ *         "[PER]" = pin is muxed for [peripheral] (not GPIO)
+ *         LSEC = Low Speed External Connector
+ *         HSEC = High Speed External Connector
+ *
+ * Line names are taken from the schematic "sophon-edge-schematics"
+ * version, 1.0210.
+ *
+ * For the lines routed to the external connectors the
+ * lines are named after the 96Boards CE Specification 1.0,
+ * Appendix "Expansion Connector Signal Description".
+ *
+ * When the 96Board naming of a line and the schematic name of
+ * the same line are in conflict, the 96Board specification
+ * takes precedence. This is only for the informational
+ * lines i.e. "[FOO]", the GPIO named lines "GPIO-A" thru "GPIO-L"
+ * are the only ones actually used for GPIO.
+ */
+
 / {
        compatible = "bitmain,sophon-edge", "bitmain,bm1880";
        model = "Sophon Edge";
@@ -32,19 +54,140 @@
                clock-frequency = <500000000>;
                #clock-cells = <0>;
        };
+
+       soc {
+               gpio0: gpio@50027000 {
+                       porta: gpio-controller@0 {
+                               gpio-line-names =
+                                       "GPIO-A", /* GPIO0, LSEC pin 23 */
+                                       "GPIO-C", /* GPIO1, LSEC pin 25 */
+                                       "[GPIO2_PHY0_RST]", /* GPIO2 */
+                                       "GPIO-E", /* GPIO3, LSEC pin 27 */
+                                       "[USB_DET]", /* GPIO4 */
+                                       "[EN_P5V]", /* GPIO5 */
+                                       "[VDDIO_MS1_SEL]", /* GPIO6 */
+                                       "GPIO-G", /* GPIO7, LSEC pin 29 */
+                                       "[BM_TUSB_RST_L]", /* GPIO8 */
+                                       "[EN_P5V_USBHUB]", /* GPIO9 */
+                                       "NC",
+                                       "LED_WIFI", /* GPIO11 */
+                                       "LED_BT", /* GPIO12 */
+                                       "[BM_BLM8221_EN_L]", /* GPIO13 */
+                                       "NC", /* GPIO14 */
+                                       "NC", /* GPIO15 */
+                                       "NC", /* GPIO16 */
+                                       "NC", /* GPIO17 */
+                                       "NC", /* GPIO18 */
+                                       "NC", /* GPIO19 */
+                                       "NC", /* GPIO20 */
+                                       "NC", /* GPIO21 */
+                                       "NC", /* GPIO22 */
+                                       "NC", /* GPIO23 */
+                                       "NC", /* GPIO24 */
+                                       "NC", /* GPIO25 */
+                                       "NC", /* GPIO26 */
+                                       "NC", /* GPIO27 */
+                                       "NC", /* GPIO28 */
+                                       "NC", /* GPIO29 */
+                                       "NC", /* GPIO30 */
+                                       "NC"; /* GPIO31 */
+                       };
+               };
+
+               gpio1: gpio@50027400 {
+                       portb: gpio-controller@0 {
+                               gpio-line-names =
+                                       "NC", /* GPIO32 */
+                                       "NC", /* GPIO33 */
+                                       "[I2C0_SDA]", /* GPIO34, LSEC pin 17 */
+                                       "[I2C0_SCL]", /* GPIO35, LSEC pin 15 */
+                                       "[JTAG0_TDO]", /* GPIO36 */
+                                       "[JTAG0_TCK]", /* GPIO37 */
+                                       "[JTAG0_TDI]", /* GPIO38 */
+                                       "[JTAG0_TMS]", /* GPIO39 */
+                                       "[JTAG0_TRST_X]", /* GPIO40 */
+                                       "[JTAG1_TDO]", /* GPIO41 */
+                                       "[JTAG1_TCK]", /* GPIO42 */
+                                       "[JTAG1_TDI]", /* GPIO43 */
+                                       "[CPU_TX]", /* GPIO44 */
+                                       "[CPU_RX]", /* GPIO45 */
+                                       "[UART1_TXD]", /* GPIO46 */
+                                       "[UART1_RXD]", /* GPIO47 */
+                                       "[UART0_TXD]", /* GPIO48 */
+                                       "[UART0_RXD]", /* GPIO49 */
+                                       "GPIO-I", /* GPIO50, LSEC pin 31 */
+                                       "GPIO-K", /* GPIO51, LSEC pin 33 */
+                                       "USER_LED2", /* GPIO52 */
+                                       "USER_LED1", /* GPIO53 */
+                                       "[UART0_RTS]", /* GPIO54 */
+                                       "[UART0_CTS]", /* GPIO55 */
+                                       "USER_LED4", /* GPIO56, JTAG1_TRST_X */
+                                       "USER_LED3", /* GPIO57, JTAG1_TMS */
+                                       "[I2S0_SCLK]", /* GPIO58 */
+                                       "[I2S0_FS]", /* GPIO59 */
+                                       "[I2S0_SDI]", /* GPIO60 */
+                                       "[I2S0_SDO]", /* GPIO61 */
+                                       "GPIO-B", /* GPIO62, LSEC pin 24 */
+                                       "GPIO-F"; /* GPIO63, I2S1_SCLK, LSEC pin 28 */
+                       };
+               };
+
+               gpio2: gpio@50027800 {
+                       portc: gpio-controller@0 {
+                               gpio-line-names =
+                                       "GPIO-D", /* GPIO64, I2S1_FS, LSEC pin 26 */
+                                       "GPIO-J", /* GPIO65, I2S1_SDI, LSEC pin 32 */
+                                       "GPIO-H", /* GPIO66, I2S1_SDO, LSEC pin 30 */
+                                       "GPIO-L", /* GPIO67, LSEC pin 34 */
+                                       "[SPI0_CS]", /* GPIO68, SPI1_CS, LSEC pin 12 */
+                                       "[SPI0_DIN]", /* GPIO69, SPI1_SDI, LSEC pin 10 */
+                                       "[SPI0_DOUT]", /* GPIO70, SPI1_SDO, LSEC pin 14 */
+                                       "[SPI0_SCLK]"; /* GPIO71, SPI1_SCK, LSEC pin 8 */
+                       };
+               };
+       };
+};
+
+&pinctrl {
+       pinctrl_uart0_default: pinctrl-uart0-default {
+               pinmux {
+                       groups = "uart0_grp";
+                       function = "uart0";
+               };
+       };
+
+       pinctrl_uart1_default: pinctrl-uart1-default {
+               pinmux {
+                       groups = "uart1_grp";
+                       function = "uart1";
+               };
+       };
+
+       pinctrl_uart2_default: pinctrl-uart2-default {
+               pinmux {
+                       groups = "uart2_grp";
+                       function = "uart2";
+               };
+       };
 };
 
 &uart0 {
        status = "okay";
        clocks = <&uart_clk>;
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_uart0_default>;
 };
 
 &uart1 {
        status = "okay";
        clocks = <&uart_clk>;
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_uart1_default>;
 };
 
 &uart2 {
        status = "okay";
        clocks = <&uart_clk>;
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_uart2_default>;
 };

diff --git a/arch/arm64/boot/dts/bitmain/bm1880.dtsi b/arch/arm64/boot/dts/bitmain/bm1880.dtsi
index 55a4769..7726fd4 100644 (file)
--- a/arch/arm64/boot/dts/bitmain/bm1880.dtsi
+++ b/arch/arm64/boot/dts/bitmain/bm1880.dtsi
@@ -80,6 +80,74 @@
                        #interrupt-cells = <3>;
                };
 
+               sctrl: system-controller@50010000 {
+                       compatible = "bitmain,bm1880-sctrl", "syscon",
+                                    "simple-mfd";
+                       reg = <0x0 0x50010000 0x0 0x1000>;
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       ranges = <0x0 0x0 0x50010000 0x1000>;
+
+                       pinctrl: pinctrl@50 {
+                               compatible = "bitmain,bm1880-pinctrl";
+                               reg = <0x50 0x4B0>;
+                       };
+               };
+
+               gpio0: gpio@50027000 {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       compatible = "snps,dw-apb-gpio";
+                       reg = <0x0 0x50027000 0x0 0x400>;
+
+                       porta: gpio-controller@0 {
+                               compatible = "snps,dw-apb-gpio-port";
+                               gpio-controller;
+                               #gpio-cells = <2>;
+                               snps,nr-gpios = <32>;
+                               reg = <0>;
+                               interrupt-controller;
+                               #interrupt-cells = <2>;
+                               interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
+                       };
+               };
+
+               gpio1: gpio@50027400 {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       compatible = "snps,dw-apb-gpio";
+                       reg = <0x0 0x50027400 0x0 0x400>;
+
+                       portb: gpio-controller@0 {
+                               compatible = "snps,dw-apb-gpio-port";
+                               gpio-controller;
+                               #gpio-cells = <2>;
+                               snps,nr-gpios = <32>;
+                               reg = <0>;
+                               interrupt-controller;
+                               #interrupt-cells = <2>;
+                               interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
+                       };
+               };
+
+               gpio2: gpio@50027800 {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       compatible = "snps,dw-apb-gpio";
+                       reg = <0x0 0x50027800 0x0 0x400>;
+
+                       portc: gpio-controller@0 {
+                               compatible = "snps,dw-apb-gpio-port";
+                               gpio-controller;
+                               #gpio-cells = <2>;
+                               snps,nr-gpios = <8>;
+                               reg = <0>;
+                               interrupt-controller;
+                               #interrupt-cells = <2>;
+                               interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
+                       };
+               };
+
                uart0: serial@58018000 {
                        compatible = "snps,dw-apb-uart";
                        reg = <0x0 0x58018000 0x0 0x2000>;

diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi b/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi
index d88e2f0..d2de166 100644 (file)
--- a/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi
@@ -289,6 +289,12 @@
        assigned-clock-parents = <&cmu_top CLK_ACLK_MFC_400>;
 };
 
+&cmu_mif {
+       assigned-clocks = <&cmu_mif CLK_MOUT_SCLK_DSD_A>, <&cmu_mif CLK_DIV_SCLK_DSD>;
+       assigned-clock-parents = <&cmu_mif CLK_MOUT_MFC_PLL_DIV2>;
+       assigned-clock-rates = <0>, <333000000>;
+};
+
 &cmu_mscl {
        assigned-clocks = <&cmu_mscl CLK_MOUT_ACLK_MSCL_400_USER>,
                          <&cmu_mscl CLK_MOUT_SCLK_JPEG_USER>,

diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts b/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts
index 3d7e0a7..dda5d27 100644 (file)
--- a/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts
+++ b/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts
@@ -33,7 +33,8 @@
                          <&cmu_disp CLK_MOUT_DISP_PLL>,
                          <&cmu_mif CLK_MOUT_SCLK_DECON_TV_ECLK_A>,
                          <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK_USER>,
-                         <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK>;
+                         <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK>,
+                         <&cmu_disp CLK_MOUT_SCLK_DSD_USER>;
        assigned-clock-parents = <0>, <0>,
                                 <&cmu_mif CLK_ACLK_DISP_333>,
                                 <&cmu_mif CLK_SCLK_DSIM0_DISP>,
@@ -45,7 +46,8 @@
                                 <&cmu_disp CLK_FOUT_DISP_PLL>,
                                 <&cmu_mif CLK_MOUT_BUS_PLL_DIV2>,
                                 <&cmu_mif CLK_SCLK_DECON_TV_ECLK_DISP>,
-                                <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK_USER>;
+                                <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK_USER>,
+                                <&cmu_mif CLK_SCLK_DSD_DISP>;
        assigned-clock-rates = <250000000>, <400000000>;
 };
 

diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
index a04e803..d29d13f 100644 (file)
--- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
@@ -23,6 +23,31 @@
 
        interrupt-parent = <&gic>;
 
+       arm_a53_pmu {
+               compatible = "arm,cortex-a53-pmu", "arm,armv8-pmuv3";
+               interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+               interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
+       };
+
+       arm_a57_pmu {
+               compatible = "arm,cortex-a57-pmu", "arm,armv8-pmuv3";
+               interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
+               interrupt-affinity = <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>;
+       };
+
+       xxti: clock {
+               /* XXTI */
+               compatible = "fixed-clock";
+               clock-output-names = "oscclk";
+               #clock-cells = <0>;
+       };
+
        cpus {
                #address-cells = <1>;
                #size-cells = <0>;
@@ -237,35 +262,11 @@
                #size-cells = <1>;
                ranges;
 
-               arm_a53_pmu {
-                       compatible = "arm,cortex-a53-pmu", "arm,armv8-pmuv3";
-                       interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
-                                    <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
-                                    <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
-                                    <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
-                       interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
-               };
-
-               arm_a57_pmu {
-                       compatible = "arm,cortex-a57-pmu", "arm,armv8-pmuv3";
-                       interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
-                                    <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
-                                    <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
-                                    <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
-                       interrupt-affinity = <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>;
-               };
-
                chipid@10000000 {
                        compatible = "samsung,exynos4210-chipid";
                        reg = <0x10000000 0x100>;
                };
 
-               xxti: xxti {
-                       compatible = "fixed-clock";
-                       clock-output-names = "oscclk";
-                       #clock-cells = <0>;
-               };
-
                cmu_top: clock-controller@10030000 {
                        compatible = "samsung,exynos5433-cmu-top";
                        reg = <0x10030000 0x1000>;
@@ -559,6 +560,15 @@
                                <&cmu_top CLK_DIV_ACLK_IMEM_200>;
                };
 
+               slim_sss: slim-sss@11140000 {
+                       compatible = "samsung,exynos5433-slim-sss";
+                       reg = <0x11140000 0x1000>;
+                       interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>;
+                       clock-names = "aclk", "pclk";
+                       clocks = <&cmu_imem CLK_ACLK_SLIMSSS>,
+                                <&cmu_imem CLK_PCLK_SLIMSSS>;
+               };
+
                pd_gscl: power-domain@105c4000 {
                        compatible = "samsung,exynos5433-pd";
                        reg = <0x105c4000 0x20>;
@@ -848,12 +858,13 @@
                                <&cmu_disp CLK_ACLK_XIU_DECON1X>,
                                <&cmu_disp CLK_PCLK_SMMU_DECON1X>,
                                <&cmu_disp CLK_SCLK_DECON_VCLK>,
-                               <&cmu_disp CLK_SCLK_DECON_ECLK>;
+                               <&cmu_disp CLK_SCLK_DECON_ECLK>,
+                               <&cmu_disp CLK_SCLK_DSD>;
                        clock-names = "pclk", "aclk_decon", "aclk_smmu_decon0x",
                                "aclk_xiu_decon0x", "pclk_smmu_decon0x",
                                "aclk_smmu_decon1x", "aclk_xiu_decon1x",
                                "pclk_smmu_decon1x", "sclk_decon_vclk",
-                               "sclk_decon_eclk";
+                               "sclk_decon_eclk", "dsd";
                        power-domains = <&pd_disp>;
                        interrupt-names = "fifo", "vsync", "lcd_sys";
                        interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
@@ -890,12 +901,13 @@
                                 <&cmu_disp CLK_ACLK_XIU_TV1X>,
                                 <&cmu_disp CLK_PCLK_SMMU_TV1X>,
                                 <&cmu_disp CLK_SCLK_DECON_TV_VCLK>,
-                                <&cmu_disp CLK_SCLK_DECON_TV_ECLK>;
+                                <&cmu_disp CLK_SCLK_DECON_TV_ECLK>,
+                                <&cmu_disp CLK_SCLK_DSD>;
                        clock-names = "pclk", "aclk_decon", "aclk_smmu_decon0x",
                                      "aclk_xiu_decon0x", "pclk_smmu_decon0x",
                                      "aclk_smmu_decon1x", "aclk_xiu_decon1x",
                                      "pclk_smmu_decon1x", "sclk_decon_vclk",
-                                     "sclk_decon_eclk";
+                                     "sclk_decon_eclk", "dsd";
                        samsung,disp-sysreg = <&syscon_disp>;
                        power-domains = <&pd_disp>;
                        interrupt-names = "fifo", "vsync", "lcd_sys";
@@ -1022,11 +1034,12 @@
                        reg = <0x13c00000 0x1000>;
                        interrupts = <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>;
                        clock-names = "pclk", "aclk", "aclk_xiu",
-                                     "aclk_gsclbend";
+                                     "aclk_gsclbend", "gsd";
                        clocks = <&cmu_gscl CLK_PCLK_GSCL0>,
                                 <&cmu_gscl CLK_ACLK_GSCL0>,
                                 <&cmu_gscl CLK_ACLK_XIU_GSCLX>,
-                                <&cmu_gscl CLK_ACLK_GSCLBEND_333>;
+                                <&cmu_gscl CLK_ACLK_GSCLBEND_333>,
+                                <&cmu_gscl CLK_ACLK_GSD>;
                        iommus = <&sysmmu_gscl0>;
                        power-domains = <&pd_gscl>;
                };
@@ -1036,11 +1049,12 @@
                        reg = <0x13c10000 0x1000>;
                        interrupts = <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
                        clock-names = "pclk", "aclk", "aclk_xiu",
-                                     "aclk_gsclbend";
+                                     "aclk_gsclbend", "gsd";
                        clocks = <&cmu_gscl CLK_PCLK_GSCL1>,
                                 <&cmu_gscl CLK_ACLK_GSCL1>,
                                 <&cmu_gscl CLK_ACLK_XIU_GSCLX>,
-                                <&cmu_gscl CLK_ACLK_GSCLBEND_333>;
+                                <&cmu_gscl CLK_ACLK_GSCLBEND_333>,
+                                <&cmu_gscl CLK_ACLK_GSD>;
                        iommus = <&sysmmu_gscl1>;
                        power-domains = <&pd_gscl>;
                };
@@ -1050,11 +1064,12 @@
                        reg = <0x13c20000 0x1000>;
                        interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
                        clock-names = "pclk", "aclk", "aclk_xiu",
-                                     "aclk_gsclbend";
+                                     "aclk_gsclbend", "gsd";
                        clocks = <&cmu_gscl CLK_PCLK_GSCL2>,
                                 <&cmu_gscl CLK_ACLK_GSCL2>,
                                 <&cmu_gscl CLK_ACLK_XIU_GSCLX>,
-                                <&cmu_gscl CLK_ACLK_GSCLBEND_333>;
+                                <&cmu_gscl CLK_ACLK_GSCLBEND_333>,
+                                <&cmu_gscl CLK_ACLK_GSD>;
                        iommus = <&sysmmu_gscl2>;
                        power-domains = <&pd_gscl>;
                };

diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi b/arch/arm64/boot/dts/exynos/exynos7.dtsi
index 967558a..077d234 100644 (file)
--- a/arch/arm64/boot/dts/exynos/exynos7.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi
@@ -28,6 +28,23 @@
                tmuctrl0 = &tmuctrl_0;
        };
 
+       arm-pmu {
+               compatible = "arm,cortex-a57-pmu", "arm,armv8-pmuv3";
+               interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
+               interrupt-affinity = <&cpu_atlas0>, <&cpu_atlas1>,
+                                    <&cpu_atlas2>, <&cpu_atlas3>;
+       };
+
+       fin_pll: clock {
+               /* XXTI */
+               compatible = "fixed-clock";
+               clock-output-names = "fin_pll";
+               #clock-cells = <0>;
+       };
+
        cpus {
                #address-cells = <1>;
                #size-cells = <0>;
@@ -77,12 +94,6 @@
                        reg = <0x10000000 0x100>;
                };
 
-               fin_pll: xxti {
-                       compatible = "fixed-clock";
-                       clock-output-names = "fin_pll";
-                       #clock-cells = <0>;
-               };
-
                gic: interrupt-controller@11001000 {
                        compatible = "arm,gic-400";
                        #interrupt-cells = <3>;
@@ -469,28 +480,6 @@
                        status = "disabled";
                };
 
-               arm-pmu {
-                       compatible = "arm,cortex-a57-pmu", "arm,armv8-pmuv3";
-                       interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
-                                    <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
-                                    <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
-                                    <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
-                       interrupt-affinity = <&cpu_atlas0>, <&cpu_atlas1>,
-                                            <&cpu_atlas2>, <&cpu_atlas3>;
-               };
-
-               timer {
-                       compatible = "arm,armv8-timer";
-                       interrupts = <GIC_PPI 13
-                                       (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
-                                    <GIC_PPI 14
-                                       (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
-                                    <GIC_PPI 11
-                                       (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
-                                    <GIC_PPI 10
-                                       (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
-               };
-
                pmu_system_controller: system-controller@105c0000 {
                        compatible = "samsung,exynos7-pmu", "syscon";
                        reg = <0x105c0000 0x5000>;
@@ -635,6 +624,18 @@
                        };
                };
        };
+
+       timer {
+               compatible = "arm,armv8-timer";
+               interrupts = <GIC_PPI 13
+                               (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+                            <GIC_PPI 14
+                               (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+                            <GIC_PPI 11
+                               (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+                            <GIC_PPI 10
+                               (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
+       };
 };
 
 #include "exynos7-pinctrl.dtsi"

diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
index 13604e5..0bd122f 100644 (file)
--- a/arch/arm64/boot/dts/freescale/Makefile
+++ b/arch/arm64/boot/dts/freescale/Makefile
@@ -20,5 +20,8 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-rdb.dtb
 dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-qds.dtb
 dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-rdb.dtb
 
+dtb-$(CONFIG_ARCH_MXC) += imx8mm-evk.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8mq-evk.dtb
+dtb-$(CONFIG_ARCH_MXC) += imx8mq-zii-ultra-rmb3.dtb
+dtb-$(CONFIG_ARCH_MXC) += imx8mq-zii-ultra-zest.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8qxp-mek.dtb

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a-oxalis.dts b/arch/arm64/boot/dts/freescale/fsl-ls1012a-oxalis.dts
index 7c72626..9927b09 100644 (file)
--- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-oxalis.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-oxalis.dts
@@ -87,6 +87,10 @@
        status = "okay";
 };
 
+&pcie {
+       status = "okay";
+};
+
 &sai2 {
        status = "okay";
 };

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
index 1ce0042..ec6257a 100644 (file)
--- a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
@@ -475,7 +475,7 @@
                        interrupts = <0 126 IRQ_TYPE_LEVEL_HIGH>;
                };
 
-               pcie@3400000 {
+               pcie: pcie@3400000 {
                        compatible = "fsl,ls1012a-pcie";
                        reg = <0x00 0x03400000 0x0 0x00100000   /* controller registers */
                               0x40 0x00000000 0x0 0x00002000>; /* configuration space */

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
index 14c79f4..b359068 100644 (file)
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
@@ -32,6 +32,49 @@
                device_type = "memory";
                reg = <0x0 0x80000000 0x1 0x00000000>;
        };
+
+       sys_mclk: clock-mclk {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               clock-frequency = <25000000>;
+       };
+
+       reg_1p8v: regulator-1p8v {
+               compatible = "regulator-fixed";
+               regulator-name = "1P8V";
+               regulator-min-microvolt = <1800000>;
+               regulator-max-microvolt = <1800000>;
+               regulator-always-on;
+       };
+
+       sound {
+               compatible = "simple-audio-card";
+               simple-audio-card,format = "i2s";
+               simple-audio-card,widgets =
+                       "Microphone", "Microphone Jack",
+                       "Headphone", "Headphone Jack",
+                       "Speaker", "Speaker Ext",
+                       "Line", "Line In Jack";
+               simple-audio-card,routing =
+                       "MIC_IN", "Microphone Jack",
+                       "Microphone Jack", "Mic Bias",
+                       "LINE_IN", "Line In Jack",
+                       "Headphone Jack", "HP_OUT",
+                       "Speaker Ext", "LINE_OUT";
+
+               simple-audio-card,cpu {
+                       sound-dai = <&sai1>;
+                       frame-master;
+                       bitclock-master;
+               };
+
+               simple-audio-card,codec {
+                       sound-dai = <&sgtl5000>;
+                       frame-master;
+                       bitclock-master;
+                       system-clock-frequency = <25000000>;
+               };
+       };
 };
 
 &duart0 {
@@ -89,5 +132,24 @@
                                reg = <0x57>;
                        };
                };
+
+               i2c@5 {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       reg = <0x5>;
+
+                       sgtl5000: audio-codec@a {
+                               #sound-dai-cells = <0>;
+                               compatible = "fsl,sgtl5000";
+                               reg = <0xa>;
+                               VDDA-supply = <&reg_1p8v>;
+                               VDDIO-supply = <&reg_1p8v>;
+                               clocks = <&sys_mclk>;
+                       };
+               };
        };
 };
+
+&sai1 {
+       status = "okay";
+};

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
index f86b054..f9c272f 100644 (file)
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
@@ -28,6 +28,49 @@
                device_type = "memory";
                reg = <0x0 0x80000000 0x1 0x0000000>;
        };
+
+       sys_mclk: clock-mclk {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               clock-frequency = <25000000>;
+       };
+
+       reg_1p8v: regulator-1p8v {
+               compatible = "regulator-fixed";
+               regulator-name = "1P8V";
+               regulator-min-microvolt = <1800000>;
+               regulator-max-microvolt = <1800000>;
+               regulator-always-on;
+       };
+
+       sound {
+               compatible = "simple-audio-card";
+               simple-audio-card,format = "i2s";
+               simple-audio-card,widgets =
+                       "Microphone", "Microphone Jack",
+                       "Headphone", "Headphone Jack",
+                       "Speaker", "Speaker Ext",
+                       "Line", "Line In Jack";
+               simple-audio-card,routing =
+                       "MIC_IN", "Microphone Jack",
+                       "Microphone Jack", "Mic Bias",
+                       "LINE_IN", "Line In Jack",
+                       "Headphone Jack", "HP_OUT",
+                       "Speaker Ext", "LINE_OUT";
+
+               simple-audio-card,cpu {
+                       sound-dai = <&sai4>;
+                       frame-master;
+                       bitclock-master;
+               };
+
+               simple-audio-card,codec {
+                       sound-dai = <&sgtl5000>;
+                       frame-master;
+                       bitclock-master;
+                       system-clock-frequency = <25000000>;
+               };
+       };
 };
 
 &i2c0 {
@@ -39,6 +82,22 @@
                #address-cells = <1>;
                #size-cells = <0>;
 
+               i2c@1 {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       reg = <0x1>;
+
+                       sgtl5000: audio-codec@a {
+                               #sound-dai-cells = <0>;
+                               compatible = "fsl,sgtl5000";
+                               reg = <0xa>;
+                               VDDA-supply = <&reg_1p8v>;
+                               VDDIO-supply = <&reg_1p8v>;
+                               clocks = <&sys_mclk>;
+                               sclk-strength = <3>;
+                       };
+               };
+
                i2c@2 {
                        #address-cells = <1>;
                        #size-cells = <0>;
@@ -88,3 +147,7 @@
 &enetc_port1 {
        status = "disabled";
 };
+
+&sai4 {
+       status = "okay";
+};

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
index 2896bbc..b045812 100644 (file)
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
@@ -89,6 +89,11 @@
                                          IRQ_TYPE_LEVEL_LOW)>;
        };
 
+       pmu {
+               compatible = "arm,cortex-a72-pmu";
+               interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
+       };
+
        gic: interrupt-controller@6000000 {
                compatible= "arm,gic-v3";
                #address-cells = <2>;
@@ -235,6 +240,21 @@
                        status = "disabled";
                };
 
+               edma0: dma-controller@22c0000 {
+                       #dma-cells = <2>;
+                       compatible = "fsl,vf610-edma";
+                       reg = <0x0 0x22c0000 0x0 0x10000>,
+                             <0x0 0x22d0000 0x0 0x10000>,
+                             <0x0 0x22e0000 0x0 0x10000>;
+                       interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-names = "edma-tx", "edma-err";
+                       dma-channels = <32>;
+                       clock-names = "dmamux0", "dmamux1";
+                       clocks = <&clockgen 4 1>,
+                                <&clockgen 4 1>;
+               };
+
                gpio1: gpio@2300000 {
                        compatible = "fsl,qoriq-gpio";
                        reg = <0x0 0x2300000 0x0 0x10000>;
@@ -277,7 +297,7 @@
                sata: sata@3200000 {
                        compatible = "fsl,ls1028a-ahci";
                        reg = <0x0 0x3200000 0x0 0x10000>,
-                               <0x0 0x20140520 0x0 0x4>;
+                               <0x7 0x100520 0x0 0x4>;
                        reg-names = "ahci", "sata-ecc";
                        interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
                        clocks = <&clockgen 4 1>;
@@ -336,6 +356,48 @@
                                     <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
                };
 
+               sai1: audio-controller@f100000 {
+                       #sound-dai-cells = <0>;
+                       compatible = "fsl,vf610-sai";
+                       reg = <0x0 0xf100000 0x0 0x10000>;
+                       interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&clockgen 4 1>, <&clockgen 4 1>,
+                                <&clockgen 4 1>, <&clockgen 4 1>;
+                       clock-names = "bus", "mclk1", "mclk2", "mclk3";
+                       dma-names = "tx", "rx";
+                       dmas = <&edma0 1 4>,
+                              <&edma0 1 3>;
+                       status = "disabled";
+               };
+
+               sai2: audio-controller@f110000 {
+                       #sound-dai-cells = <0>;
+                       compatible = "fsl,vf610-sai";
+                       reg = <0x0 0xf110000 0x0 0x10000>;
+                       interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&clockgen 4 1>, <&clockgen 4 1>,
+                                <&clockgen 4 1>, <&clockgen 4 1>;
+                       clock-names = "bus", "mclk1", "mclk2", "mclk3";
+                       dma-names = "tx", "rx";
+                       dmas = <&edma0 1 6>,
+                              <&edma0 1 5>;
+                       status = "disabled";
+               };
+
+               sai4: audio-controller@f130000 {
+                       #sound-dai-cells = <0>;
+                       compatible = "fsl,vf610-sai";
+                       reg = <0x0 0xf130000 0x0 0x10000>;
+                       interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&clockgen 4 1>, <&clockgen 4 1>,
+                                <&clockgen 4 1>, <&clockgen 4 1>;
+                       clock-names = "bus", "mclk1", "mclk2", "mclk3";
+                       dma-names = "tx", "rx";
+                       dmas = <&edma0 1 10>,
+                              <&edma0 1 9>;
+                       status = "disabled";
+               };
+
                pcie@1f0000000 { /* Integrated Endpoint Root Complex */
                        compatible = "pci-host-ecam-generic";
                        reg = <0x01 0xf0000000 0x0 0x100000>;

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts
index 17ca357..4223a23 100644 (file)
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts
@@ -15,7 +15,6 @@
        model = "LS1043A RDB Board";
 
        aliases {
-               crypto = &crypto;
                serial0 = &duart0;
                serial1 = &duart1;
                serial2 = &duart2;

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
index 6fd6116..71d9ed9 100644 (file)
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
@@ -18,6 +18,7 @@
        #size-cells = <2>;
 
        aliases {
+               crypto = &crypto;
                fman0 = &fman0;
                ethernet0 = &enet0;
                ethernet1 = &enet1;
@@ -296,7 +297,6 @@
                        interrupts = <0 99 0x4>;
                        clock-names = "qspi_en", "qspi";
                        clocks = <&clockgen 4 0>, <&clockgen 4 0>;
-                       big-endian;
                        status = "disabled";
                };
 

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
index cb71850..b0ef08b 100644 (file)
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
@@ -215,8 +215,6 @@
                        interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
                        clock-names = "qspi_en", "qspi";
                        clocks = <&clockgen 4 1>, <&clockgen 4 1>;
-                       big-endian;
-                       fsl,qspi-has-second-chip;
                        status = "disabled";
                };
 

diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts
index 99a22ab..1a5acf6 100644 (file)
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts
@@ -95,6 +95,22 @@
        };
 };
 
+&sata0 {
+       status = "okay";
+};
+
+&sata1 {
+       status = "okay";
+};
+
+&sata2 {
+       status = "okay";
+};
+
+&sata3 {
+       status = "okay";
+};
+
 &uart0 {
        status = "okay";
 };

diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
index 9df37b1..c2817b7 100644 (file)
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
@@ -128,6 +128,22 @@
        };
 };
 
+&sata0 {
+       status = "okay";
+};
+
+&sata1 {
+       status = "okay";
+};
+
+&sata2 {
+       status = "okay";
+};
+
+&sata3 {
+       status = "okay";
+};
+
 &uart0 {
        status = "okay";
 };

diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
index fe87204..125a8cc 100644 (file)
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
@@ -33,6 +33,7 @@
                        i-cache-line-size = <64>;
                        i-cache-sets = <192>;
                        next-level-cache = <&cluster0_l2>;
+                       cpu-idle-states = <&cpu_pw20>;
                };
 
                cpu@1 {
@@ -48,6 +49,7 @@
                        i-cache-line-size = <64>;
                        i-cache-sets = <192>;
                        next-level-cache = <&cluster0_l2>;
+                       cpu-idle-states = <&cpu_pw20>;
                };
 
                cpu@100 {
@@ -63,6 +65,7 @@
                        i-cache-line-size = <64>;
                        i-cache-sets = <192>;
                        next-level-cache = <&cluster1_l2>;
+                       cpu-idle-states = <&cpu_pw20>;
                };
 
                cpu@101 {
@@ -78,6 +81,7 @@
                        i-cache-line-size = <64>;
                        i-cache-sets = <192>;
                        next-level-cache = <&cluster1_l2>;
+                       cpu-idle-states = <&cpu_pw20>;
                };
 
                cpu@200 {
@@ -93,6 +97,7 @@
                        i-cache-line-size = <64>;
                        i-cache-sets = <192>;
                        next-level-cache = <&cluster2_l2>;
+                       cpu-idle-states = <&cpu_pw20>;
                };
 
                cpu@201 {
@@ -108,6 +113,7 @@
                        i-cache-line-size = <64>;
                        i-cache-sets = <192>;
                        next-level-cache = <&cluster2_l2>;
+                       cpu-idle-states = <&cpu_pw20>;
                };
 
                cpu@300 {
@@ -123,6 +129,7 @@
                        i-cache-line-size = <64>;
                        i-cache-sets = <192>;
                        next-level-cache = <&cluster3_l2>;
+                       cpu-idle-states = <&cpu_pw20>;
                };
 
                cpu@301 {
@@ -138,6 +145,7 @@
                        i-cache-line-size = <64>;
                        i-cache-sets = <192>;
                        next-level-cache = <&cluster3_l2>;
+                       cpu-idle-states = <&cpu_pw20>;
                };
 
                cpu@400 {
@@ -153,6 +161,7 @@
                        i-cache-line-size = <64>;
                        i-cache-sets = <192>;
                        next-level-cache = <&cluster4_l2>;
+                       cpu-idle-states = <&cpu_pw20>;
                };
 
                cpu@401 {
@@ -168,6 +177,7 @@
                        i-cache-line-size = <64>;
                        i-cache-sets = <192>;
                        next-level-cache = <&cluster4_l2>;
+                       cpu-idle-states = <&cpu_pw20>;
                };
 
                cpu@500 {
@@ -183,6 +193,7 @@
                        i-cache-line-size = <64>;
                        i-cache-sets = <192>;
                        next-level-cache = <&cluster5_l2>;
+                       cpu-idle-states = <&cpu_pw20>;
                };
 
                cpu@501 {
@@ -198,6 +209,7 @@
                        i-cache-line-size = <64>;
                        i-cache-sets = <192>;
                        next-level-cache = <&cluster5_l2>;
+                       cpu-idle-states = <&cpu_pw20>;
                };
 
                cpu@600 {
@@ -213,6 +225,7 @@
                        i-cache-line-size = <64>;
                        i-cache-sets = <192>;
                        next-level-cache = <&cluster6_l2>;
+                       cpu-idle-states = <&cpu_pw20>;
                };
 
                cpu@601 {
@@ -228,6 +241,7 @@
                        i-cache-line-size = <64>;
                        i-cache-sets = <192>;
                        next-level-cache = <&cluster6_l2>;
+                       cpu-idle-states = <&cpu_pw20>;
                };
 
                cpu@700 {
@@ -243,6 +257,7 @@
                        i-cache-line-size = <64>;
                        i-cache-sets = <192>;
                        next-level-cache = <&cluster7_l2>;
+                       cpu-idle-states = <&cpu_pw20>;
                };
 
                cpu@701 {
@@ -258,6 +273,7 @@
                        i-cache-line-size = <64>;
                        i-cache-sets = <192>;
                        next-level-cache = <&cluster7_l2>;
+                       cpu-idle-states = <&cpu_pw20>;
                };
 
                cluster0_l2: l2-cache0 {
@@ -323,6 +339,15 @@
                        cache-sets = <1024>;
                        cache-level = <2>;
                };
+
+               cpu_pw20: cpu-pw20 {
+                       compatible = "arm,idle-state";
+                       idle-state-name = "PW20";
+                       arm,psci-suspend-param = <0x0>;
+                       entry-latency-us = <2000>;
+                       exit-latency-us = <2000>;
+                       min-residency-us = <6000>;
+                 };
        };
 
        gic: interrupt-controller@6000000 {
@@ -687,6 +712,50 @@
                        status = "disabled";
                };
 
+               sata0: sata@3200000 {
+                       compatible = "fsl,lx2160a-ahci";
+                       reg = <0x0 0x3200000 0x0 0x10000>,
+                             <0x7 0x100520 0x0 0x4>;
+                       reg-names = "ahci", "sata-ecc";
+                       interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&clockgen 4 3>;
+                       dma-coherent;
+                       status = "disabled";
+               };
+
+               sata1: sata@3210000 {
+                       compatible = "fsl,lx2160a-ahci";
+                       reg = <0x0 0x3210000 0x0 0x10000>,
+                             <0x7 0x100520 0x0 0x4>;
+                       reg-names = "ahci", "sata-ecc";
+                       interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&clockgen 4 3>;
+                       dma-coherent;
+                       status = "disabled";
+               };
+
+               sata2: sata@3220000 {
+                       compatible = "fsl,lx2160a-ahci";
+                       reg = <0x0 0x3220000 0x0 0x10000>,
+                             <0x7 0x100520 0x0 0x4>;
+                       reg-names = "ahci", "sata-ecc";
+                       interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&clockgen 4 3>;
+                       dma-coherent;
+                       status = "disabled";
+               };
+
+               sata3: sata@3230000 {
+                       compatible = "fsl,lx2160a-ahci";
+                       reg = <0x0 0x3230000 0x0 0x10000>,
+                             <0x7 0x100520 0x0 0x4>;
+                       reg-names = "ahci", "sata-ecc";
+                       interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&clockgen 4 3>;
+                       dma-coherent;
+                       status = "disabled";
+               };
+
                smmu: iommu@5000000 {
                        compatible = "arm,mmu-500";
                        reg = <0 0x5000000 0 0x800000>;

diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dts b/arch/arm64/boot/dts/freescale/imx8mm-evk.dts
new file mode 100644 (file)
index 0000000..2d5d894
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mm-evk.dts
@@ -0,0 +1,235 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2019 NXP
+ */
+
+/dts-v1/;
+
+#include "imx8mm.dtsi"
+
+/ {
+       model = "FSL i.MX8MM EVK board";
+       compatible = "fsl,imx8mm-evk", "fsl,imx8mm";
+
+       chosen {
+               stdout-path = &uart2;
+       };
+
+       leds {
+               compatible = "gpio-leds";
+               pinctrl-names = "default";
+               pinctrl-0 = <&pinctrl_gpio_led>;
+
+               status {
+                       label = "status";
+                       gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>;
+                       default-state = "on";
+               };
+       };
+
+       reg_usdhc2_vmmc: regulator-usdhc2 {
+               compatible = "regulator-fixed";
+               pinctrl-names = "default";
+               pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
+               regulator-name = "VSD_3V3";
+               regulator-min-microvolt = <3300000>;
+               regulator-max-microvolt = <3300000>;
+               gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
+               enable-active-high;
+       };
+};
+
+&fec1 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_fec1>;
+       phy-mode = "rgmii-id";
+       phy-handle = <&ethphy0>;
+       fsl,magic-packet;
+       status = "okay";
+
+       mdio {
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               ethphy0: ethernet-phy@0 {
+                       compatible = "ethernet-phy-ieee802.3-c22";
+                       reg = <0>;
+                       at803x,led-act-blind-workaround;
+                       at803x,eee-okay;
+                       at803x,vddio-1p8v;
+               };
+       };
+};
+
+&uart2 { /* console */
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_uart2>;
+       status = "okay";
+};
+
+&usdhc2 {
+       pinctrl-names = "default", "state_100mhz", "state_200mhz";
+       pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+       pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
+       pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
+       cd-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
+       bus-width = <4>;
+       vmmc-supply = <&reg_usdhc2_vmmc>;
+       status = "okay";
+};
+
+&usdhc3 {
+       pinctrl-names = "default", "state_100mhz", "state_200mhz";
+       pinctrl-0 = <&pinctrl_usdhc3>;
+       pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
+       pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
+       bus-width = <8>;
+       non-removable;
+       status = "okay";
+};
+
+&wdog1 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_wdog>;
+       fsl,ext-reset-output;
+       status = "okay";
+};
+
+&iomuxc {
+       pinctrl-names = "default";
+
+       pinctrl_fec1: fec1grp {
+               fsl,pins = <
+                       MX8MM_IOMUXC_ENET_MDC_ENET1_MDC                 0x3
+                       MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO               0x3
+                       MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3           0x1f
+                       MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2           0x1f
+                       MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1           0x1f
+                       MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0           0x1f
+                       MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3           0x91
+                       MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2           0x91
+                       MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1           0x91
+                       MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0           0x91
+                       MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC           0x1f
+                       MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC           0x91
+                       MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL     0x91
+                       MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL     0x1f
+                       MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22                0x19
+               >;
+       };
+
+       pinctrl_gpio_led: gpioledgrp {
+               fsl,pins = <
+                       MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16    0x19
+               >;
+       };
+
+       pinctrl_reg_usdhc2_vmmc: regusdhc2vmmc {
+               fsl,pins = <
+                       MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19     0x41
+               >;
+       };
+
+       pinctrl_uart2: uart2grp {
+               fsl,pins = <
+                       MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX     0x140
+                       MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX     0x140
+               >;
+       };
+
+       pinctrl_usdhc2_gpio: usdhc2grpgpio {
+               fsl,pins = <
+                       MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15      0x1c4
+               >;
+       };
+
+       pinctrl_usdhc2: usdhc2grp {
+               fsl,pins = <
+                       MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK         0x190
+                       MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD         0x1d0
+                       MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0     0x1d0
+                       MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1     0x1d0
+                       MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2     0x1d0
+                       MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3     0x1d0
+                       MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT  0x1d0
+               >;
+       };
+
+       pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
+               fsl,pins = <
+                       MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK         0x194
+                       MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD         0x1d4
+                       MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0     0x1d4
+                       MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1     0x1d4
+                       MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2     0x1d4
+                       MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3     0x1d4
+                       MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT  0x1d0
+               >;
+       };
+
+       pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
+               fsl,pins = <
+                       MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK         0x196
+                       MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD         0x1d6
+                       MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0     0x1d6
+                       MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1     0x1d6
+                       MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2     0x1d6
+                       MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3     0x1d6
+                       MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT  0x1d0
+               >;
+       };
+
+       pinctrl_usdhc3: usdhc3grp {
+               fsl,pins = <
+                       MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK               0x190
+                       MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD               0x1d0
+                       MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0           0x1d0
+                       MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1           0x1d0
+                       MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2           0x1d0
+                       MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3           0x1d0
+                       MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4             0x1d0
+                       MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5            0x1d0
+                       MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6            0x1d0
+                       MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7              0x1d0
+                       MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE           0x190
+               >;
+       };
+
+       pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
+               fsl,pins = <
+                       MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK               0x194
+                       MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD               0x1d4
+                       MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0           0x1d4
+                       MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1           0x1d4
+                       MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2           0x1d4
+                       MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3           0x1d4
+                       MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4             0x1d4
+                       MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5            0x1d4
+                       MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6            0x1d4
+                       MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7              0x1d4
+                       MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE           0x194
+               >;
+       };
+
+       pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
+               fsl,pins = <
+                       MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK               0x196
+                       MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD               0x1d6
+                       MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0           0x1d6
+                       MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1           0x1d6
+                       MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2           0x1d6
+                       MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3           0x1d6
+                       MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4             0x1d6
+                       MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5            0x1d6
+                       MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6            0x1d6
+                       MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7              0x1d6
+                       MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE           0x196
+               >;
+       };
+
+       pinctrl_wdog: wdoggrp {
+               fsl,pins = <
+                       MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B    0xc6
+               >;
+       };
+};

diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
new file mode 100644 (file)
index 0000000..6b407a9
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
@@ -0,0 +1,733 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2019 NXP
+ */
+
+#include <dt-bindings/clock/imx8mm-clock.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/thermal/thermal.h>
+
+#include "imx8mm-pinfunc.h"
+
+/ {
+       compatible = "fsl,imx8mm";
+       interrupt-parent = <&gic>;
+       #address-cells = <2>;
+       #size-cells = <2>;
+
+       aliases {
+               ethernet0 = &fec1;
+               i2c0 = &i2c1;
+               i2c1 = &i2c2;
+               i2c2 = &i2c3;
+               i2c3 = &i2c4;
+               serial0 = &uart1;
+               serial1 = &uart2;
+               serial2 = &uart3;
+               serial3 = &uart4;
+               spi0 = &ecspi1;
+               spi1 = &ecspi2;
+               spi2 = &ecspi3;
+               mmc0 = &usdhc1;
+               mmc1 = &usdhc2;
+               mmc2 = &usdhc3;
+               gpio0 = &gpio1;
+               gpio1 = &gpio2;
+               gpio2 = &gpio3;
+               gpio3 = &gpio4;
+               gpio4 = &gpio5;
+       };
+
+       cpus {
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               A53_0: cpu@0 {
+                       device_type = "cpu";
+                       compatible = "arm,cortex-a53";
+                       reg = <0x0>;
+                       clock-latency = <61036>; /* two CLK32 periods */
+                       clocks = <&clk IMX8MM_CLK_ARM>;
+                       enable-method = "psci";
+                       next-level-cache = <&A53_L2>;
+                       operating-points-v2 = <&a53_opp_table>;
+               };
+
+               A53_1: cpu@1 {
+                       device_type = "cpu";
+                       compatible = "arm,cortex-a53";
+                       reg = <0x1>;
+                       clock-latency = <61036>; /* two CLK32 periods */
+                       clocks = <&clk IMX8MM_CLK_ARM>;
+                       enable-method = "psci";
+                       next-level-cache = <&A53_L2>;
+                       operating-points-v2 = <&a53_opp_table>;
+               };
+
+               A53_2: cpu@2 {
+                       device_type = "cpu";
+                       compatible = "arm,cortex-a53";
+                       reg = <0x2>;
+                       clock-latency = <61036>; /* two CLK32 periods */
+                       clocks = <&clk IMX8MM_CLK_ARM>;
+                       enable-method = "psci";
+                       next-level-cache = <&A53_L2>;
+                       operating-points-v2 = <&a53_opp_table>;
+               };
+
+               A53_3: cpu@3 {
+                       device_type = "cpu";
+                       compatible = "arm,cortex-a53";
+                       reg = <0x3>;
+                       clock-latency = <61036>; /* two CLK32 periods */
+                       clocks = <&clk IMX8MM_CLK_ARM>;
+                       enable-method = "psci";
+                       next-level-cache = <&A53_L2>;
+                       operating-points-v2 = <&a53_opp_table>;
+               };
+
+               A53_L2: l2-cache0 {
+                       compatible = "cache";
+               };
+       };
+
+       a53_opp_table: opp-table {
+               compatible = "operating-points-v2";
+               opp-shared;
+
+               opp-1200000000 {
+                       opp-hz = /bits/ 64 <1200000000>;
+                       opp-microvolt = <850000>;
+                       clock-latency-ns = <150000>;
+               };
+
+               opp-1600000000 {
+                       opp-hz = /bits/ 64 <1600000000>;
+                       opp-microvolt = <900000>;
+                       clock-latency-ns = <150000>;
+                       opp-suspend;
+               };
+       };
+
+       memory@40000000 {
+               device_type = "memory";
+               reg = <0x0 0x40000000 0 0x80000000>;
+       };
+
+       osc_32k: clock-osc-32k {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               clock-frequency = <32768>;
+               clock-output-names = "osc_32k";
+       };
+
+       osc_24m: clock-osc-24m {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               clock-frequency = <24000000>;
+               clock-output-names = "osc_24m";
+       };
+
+       clk_ext1: clock-ext1 {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               clock-frequency = <133000000>;
+               clock-output-names = "clk_ext1";
+       };
+
+       clk_ext2: clock-ext2 {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               clock-frequency = <133000000>;
+               clock-output-names = "clk_ext2";
+       };
+
+       clk_ext3: clock-ext3 {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               clock-frequency = <133000000>;
+               clock-output-names = "clk_ext3";
+       };
+
+       clk_ext4: clock-ext4 {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               clock-frequency= <133000000>;
+               clock-output-names = "clk_ext4";
+       };
+
+       gic: interrupt-controller@38800000 {
+               compatible = "arm,gic-v3";
+               reg = <0x0 0x38800000 0 0x10000>, /* GIC Dist */
+                     <0x0 0x38880000 0 0xC0000>; /* GICR (RD_base + SGI_base) */
+               #interrupt-cells = <3>;
+               interrupt-controller;
+               interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+       };
+
+       psci {
+               compatible = "arm,psci-1.0";
+               method = "smc";
+       };
+
+       pmu {
+               compatible = "arm,armv8-pmuv3";
+               interrupts = <GIC_PPI 7
+                            (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;
+               interrupt-affinity = <&A53_0>, <&A53_1>, <&A53_2>, <&A53_3>;
+       };
+
+       timer {
+               compatible = "arm,armv8-timer";
+               interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Secure */
+                            <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Non-Secure */
+                            <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Virtual */
+                            <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; /* Hypervisor */
+               clock-frequency = <8000000>;
+               arm,no-tick-in-suspend;
+       };
+
+       soc {
+               compatible = "simple-bus";
+               #address-cells = <1>;
+               #size-cells = <1>;
+               ranges = <0x0 0x0 0x0 0x3e000000>;
+
+               aips1: bus@30000000 {
+                       compatible = "fsl,aips-bus", "simple-bus";
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       ranges;
+
+                       gpio1: gpio@30200000 {
+                               compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
+                               reg = <0x30200000 0x10000>;
+                               interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
+                               gpio-controller;
+                               #gpio-cells = <2>;
+                               interrupt-controller;
+                               #interrupt-cells = <2>;
+                       };
+
+                       gpio2: gpio@30210000 {
+                               compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
+                               reg = <0x30210000 0x10000>;
+                               interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
+                               gpio-controller;
+                               #gpio-cells = <2>;
+                               interrupt-controller;
+                               #interrupt-cells = <2>;
+                       };
+
+                       gpio3: gpio@30220000 {
+                               compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
+                               reg = <0x30220000 0x10000>;
+                               interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
+                               gpio-controller;
+                               #gpio-cells = <2>;
+                               interrupt-controller;
+                               #interrupt-cells = <2>;
+                       };
+
+                       gpio4: gpio@30230000 {
+                               compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
+                               reg = <0x30230000 0x10000>;
+                               interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+                               gpio-controller;
+                               #gpio-cells = <2>;
+                               interrupt-controller;
+                               #interrupt-cells = <2>;
+                       };
+
+                       gpio5: gpio@30240000 {
+                               compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
+                               reg = <0x30240000 0x10000>;
+                               interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+                               gpio-controller;
+                               #gpio-cells = <2>;
+                               interrupt-controller;
+                               #interrupt-cells = <2>;
+                       };
+
+                       wdog1: watchdog@30280000 {
+                               compatible = "fsl,imx8mm-wdt", "fsl,imx21-wdt";
+                               reg = <0x30280000 0x10000>;
+                               interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
+                               clocks = <&clk IMX8MM_CLK_WDOG1_ROOT>;
+                               status = "disabled";
+                       };
+
+                       wdog2: watchdog@30290000 {
+                               compatible = "fsl,imx8mm-wdt", "fsl,imx21-wdt";
+                               reg = <0x30290000 0x10000>;
+                               interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
+                               clocks = <&clk IMX8MM_CLK_WDOG2_ROOT>;
+                               status = "disabled";
+                       };
+
+                       wdog3: watchdog@302a0000 {
+                               compatible = "fsl,imx8mm-wdt", "fsl,imx21-wdt";
+                               reg = <0x302a0000 0x10000>;
+                               interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+                               clocks = <&clk IMX8MM_CLK_WDOG3_ROOT>;
+                               status = "disabled";
+                       };
+
+                       sdma2: dma-controller@302c0000 {
+                               compatible = "fsl,imx8mm-sdma", "fsl,imx7d-sdma";
+                               reg = <0x302c0000 0x10000>;
+                               interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
+                               clocks = <&clk IMX8MM_CLK_SDMA2_ROOT>,
+                                        <&clk IMX8MM_CLK_SDMA2_ROOT>;
+                               clock-names = "ipg", "ahb";
+                               #dma-cells = <3>;
+                               fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
+                       };
+
+                       sdma3: dma-controller@302b0000 {
+                               compatible = "fsl,imx8mm-sdma", "fsl,imx7d-sdma";
+                               reg = <0x302b0000 0x10000>;
+                               interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+                               clocks = <&clk IMX8MM_CLK_SDMA3_ROOT>,
+                                <&clk IMX8MM_CLK_SDMA3_ROOT>;
+                               clock-names = "ipg", "ahb";
+                               #dma-cells = <3>;
+                               fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
+                       };
+
+                       iomuxc: pinctrl@30330000 {
+                               compatible = "fsl,imx8mm-iomuxc";
+                               reg = <0x30330000 0x10000>;
+                       };
+
+                       gpr: iomuxc-gpr@30340000 {
+                               compatible = "fsl,imx8mm-iomuxc-gpr", "syscon";
+                               reg = <0x30340000 0x10000>;
+                       };
+
+                       ocotp: ocotp-ctrl@30350000 {
+                               compatible = "fsl,imx8mm-ocotp", "fsl,imx7d-ocotp", "syscon";
+                               reg = <0x30350000 0x10000>;
+                               clocks = <&clk IMX8MM_CLK_OCOTP_ROOT>;
+                               /* For nvmem subnodes */
+                               #address-cells = <1>;
+                               #size-cells = <1>;
+                       };
+
+                       anatop: anatop@30360000 {
+                               compatible = "fsl,imx8mm-anatop", "syscon", "simple-bus";
+                               reg = <0x30360000 0x10000>;
+                       };
+
+                       snvs: snvs@30370000 {
+                               compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd";
+                               reg = <0x30370000 0x10000>;
+
+                               snvs_rtc: snvs-rtc-lp {
+                                       compatible = "fsl,sec-v4.0-mon-rtc-lp";
+                                       regmap = <&snvs>;
+                                       offset = <0x34>;
+                                       interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
+                                                    <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+                               };
+
+                               snvs_pwrkey: snvs-powerkey {
+                                       compatible = "fsl,sec-v4.0-pwrkey";
+                                       regmap = <&snvs>;
+                                       interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+                                       linux,keycode = <KEY_POWER>;
+                                       wakeup-source;
+                               };
+                       };
+
+                       clk: clock-controller@30380000 {
+                               compatible = "fsl,imx8mm-ccm";
+                               reg = <0x30380000 0x10000>;
+                               #clock-cells = <1>;
+                               clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>,
+                                        <&clk_ext3>, <&clk_ext4>;
+                               clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
+                                             "clk_ext3", "clk_ext4";
+                       };
+
+                       src: reset-controller@30390000 {
+                               compatible = "fsl,imx8mm-src", "syscon";
+                               reg = <0x30390000 0x10000>;
+                               interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
+                               #reset-cells = <1>;
+                       };
+               };
+
+               aips2: bus@30400000 {
+                       compatible = "fsl,aips-bus", "simple-bus";
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       ranges;
+
+                       pwm1: pwm@30660000 {
+                               compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm";
+                               reg = <0x30660000 0x10000>;
+                               interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
+                               clocks = <&clk IMX8MM_CLK_PWM1_ROOT>,
+                                       <&clk IMX8MM_CLK_PWM1_ROOT>;
+                               clock-names = "ipg", "per";
+                               #pwm-cells = <2>;
+                               status = "disabled";
+                       };
+
+                       pwm2: pwm@30670000 {
+                               compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm";
+                               reg = <0x30670000 0x10000>;
+                               interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
+                               clocks = <&clk IMX8MM_CLK_PWM2_ROOT>,
+                                        <&clk IMX8MM_CLK_PWM2_ROOT>;
+                               clock-names = "ipg", "per";
+                               #pwm-cells = <2>;
+                               status = "disabled";
+                       };
+
+                       pwm3: pwm@30680000 {
+                               compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm";
+                               reg = <0x30680000 0x10000>;
+                               interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+                               clocks = <&clk IMX8MM_CLK_PWM3_ROOT>,
+                                        <&clk IMX8MM_CLK_PWM3_ROOT>;
+                               clock-names = "ipg", "per";
+                               #pwm-cells = <2>;
+                               status = "disabled";
+                       };
+
+                       pwm4: pwm@30690000 {
+                               compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm";
+                               reg = <0x30690000 0x10000>;
+                               interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
+                               clocks = <&clk IMX8MM_CLK_PWM4_ROOT>,
+                                        <&clk IMX8MM_CLK_PWM4_ROOT>;
+                               clock-names = "ipg", "per";
+                               #pwm-cells = <2>;
+                               status = "disabled";
+                       };
+               };
+
+               aips3: bus@30800000 {
+                       compatible = "fsl,aips-bus", "simple-bus";
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       ranges;
+
+                       ecspi1: spi@30820000 {
+                               compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi";
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                               reg = <0x30820000 0x10000>;
+                               interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+                               clocks = <&clk IMX8MM_CLK_ECSPI1_ROOT>,
+                                        <&clk IMX8MM_CLK_ECSPI1_ROOT>;
+                               clock-names = "ipg", "per";
+                               dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;
+                               dma-names = "rx", "tx";
+                               status = "disabled";
+                       };
+
+                       ecspi2: spi@30830000 {
+                               compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi";
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                               reg = <0x30830000 0x10000>;
+                               interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+                               clocks = <&clk IMX8MM_CLK_ECSPI2_ROOT>,
+                                        <&clk IMX8MM_CLK_ECSPI2_ROOT>;
+                               clock-names = "ipg", "per";
+                               dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>;
+                               dma-names = "rx", "tx";
+                               status = "disabled";
+                       };
+
+                       ecspi3: spi@30840000 {
+                               compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi";
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                               reg = <0x30840000 0x10000>;
+                               interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+                               clocks = <&clk IMX8MM_CLK_ECSPI3_ROOT>,
+                                        <&clk IMX8MM_CLK_ECSPI3_ROOT>;
+                               clock-names = "ipg", "per";
+                               dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>;
+                               dma-names = "rx", "tx";
+                               status = "disabled";
+                       };
+
+                       uart1: serial@30860000 {
+                               compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart";
+                               reg = <0x30860000 0x10000>;
+                               interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+                               clocks = <&clk IMX8MM_CLK_UART1_ROOT>,
+                                        <&clk IMX8MM_CLK_UART1_ROOT>;
+                               clock-names = "ipg", "per";
+                               dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>;
+                               dma-names = "rx", "tx";
+                               status = "disabled";
+                       };
+
+                       uart3: serial@30880000 {
+                               compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart";
+                               reg = <0x30880000 0x10000>;
+                               interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
+                               clocks = <&clk IMX8MM_CLK_UART3_ROOT>,
+                                        <&clk IMX8MM_CLK_UART3_ROOT>;
+                               clock-names = "ipg", "per";
+                               dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>;
+                               dma-names = "rx", "tx";
+                               status = "disabled";
+                       };
+
+                       uart2: serial@30890000 {
+                               compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart";
+                               reg = <0x30890000 0x10000>;
+                               interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
+                               clocks = <&clk IMX8MM_CLK_UART2_ROOT>,
+                                        <&clk IMX8MM_CLK_UART2_ROOT>;
+                               clock-names = "ipg", "per";
+                               status = "disabled";
+                       };
+
+                       i2c1: i2c@30a20000 {
+                               compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c";
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                               reg = <0x30a20000 0x10000>;
+                               interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+                               clocks = <&clk IMX8MM_CLK_I2C1_ROOT>;
+                               status = "disabled";
+                       };
+
+                       i2c2: i2c@30a30000 {
+                               compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c";
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                               reg = <0x30a30000 0x10000>;
+                               interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+                               clocks = <&clk IMX8MM_CLK_I2C2_ROOT>;
+                               status = "disabled";
+                       };
+
+                       i2c3: i2c@30a40000 {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                               compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c";
+                               reg = <0x30a40000 0x10000>;
+                               interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+                               clocks = <&clk IMX8MM_CLK_I2C3_ROOT>;
+                               status = "disabled";
+                       };
+
+                       i2c4: i2c@30a50000 {
+                               compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c";
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                               reg = <0x30a50000 0x10000>;
+                               interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
+                               clocks = <&clk IMX8MM_CLK_I2C4_ROOT>;
+                               status = "disabled";
+                       };
+
+                       uart4: serial@30a60000 {
+                               compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart";
+                               reg = <0x30a60000 0x10000>;
+                               interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
+                               clocks = <&clk IMX8MM_CLK_UART4_ROOT>,
+                                        <&clk IMX8MM_CLK_UART4_ROOT>;
+                               clock-names = "ipg", "per";
+                               dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>;
+                               dma-names = "rx", "tx";
+                               status = "disabled";
+                       };
+
+                       usdhc1: mmc@30b40000 {
+                               compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
+                               reg = <0x30b40000 0x10000>;
+                               interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
+                               clocks = <&clk IMX8MM_CLK_DUMMY>,
+                                        <&clk IMX8MM_CLK_NAND_USDHC_BUS>,
+                                        <&clk IMX8MM_CLK_USDHC1_ROOT>;
+                               clock-names = "ipg", "ahb", "per";
+                               assigned-clocks = <&clk IMX8MM_CLK_USDHC1>;
+                               assigned-clock-rates = <400000000>;
+                               fsl,tuning-start-tap = <20>;
+                               fsl,tuning-step= <2>;
+                               bus-width = <4>;
+                               status = "disabled";
+                       };
+
+                       usdhc2: mmc@30b50000 {
+                               compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
+                               reg = <0x30b50000 0x10000>;
+                               interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+                               clocks = <&clk IMX8MM_CLK_DUMMY>,
+                                        <&clk IMX8MM_CLK_NAND_USDHC_BUS>,
+                                        <&clk IMX8MM_CLK_USDHC2_ROOT>;
+                               clock-names = "ipg", "ahb", "per";
+                               fsl,tuning-start-tap = <20>;
+                               fsl,tuning-step= <2>;
+                               bus-width = <4>;
+                               status = "disabled";
+                       };
+
+                       usdhc3: mmc@30b60000 {
+                               compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
+                               reg = <0x30b60000 0x10000>;
+                               interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
+                               clocks = <&clk IMX8MM_CLK_DUMMY>,
+                                        <&clk IMX8MM_CLK_NAND_USDHC_BUS>,
+                                        <&clk IMX8MM_CLK_USDHC3_ROOT>;
+                               clock-names = "ipg", "ahb", "per";
+                               assigned-clocks = <&clk IMX8MM_CLK_USDHC3_ROOT>;
+                               assigned-clock-rates = <400000000>;
+                               fsl,tuning-start-tap = <20>;
+                               fsl,tuning-step= <2>;
+                               bus-width = <4>;
+                               status = "disabled";
+                       };
+
+                       sdma1: dma-controller@30bd0000 {
+                               compatible = "fsl,imx8mm-sdma", "fsl,imx7d-sdma";
+                               reg = <0x30bd0000 0x10000>;
+                               interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
+                               clocks = <&clk IMX8MM_CLK_SDMA1_ROOT>,
+                                        <&clk IMX8MM_CLK_SDMA1_ROOT>;
+                               clock-names = "ipg", "ahb";
+                               #dma-cells = <3>;
+                               fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
+                       };
+
+                       fec1: ethernet@30be0000 {
+                               compatible = "fsl,imx8mm-fec", "fsl,imx6sx-fec";
+                               reg = <0x30be0000 0x10000>;
+                               interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
+                               clocks = <&clk IMX8MM_CLK_ENET1_ROOT>,
+                                        <&clk IMX8MM_CLK_ENET1_ROOT>,
+                                        <&clk IMX8MM_CLK_ENET_TIMER>,
+                                        <&clk IMX8MM_CLK_ENET_REF>,
+                                        <&clk IMX8MM_CLK_ENET_PHY_REF>;
+                               clock-names = "ipg", "ahb", "ptp",
+                                             "enet_clk_ref", "enet_out";
+                               assigned-clocks = <&clk IMX8MM_CLK_ENET_AXI>,
+                                                 <&clk IMX8MM_CLK_ENET_TIMER>,
+                                                 <&clk IMX8MM_CLK_ENET_REF>,
+                                                 <&clk IMX8MM_CLK_ENET_TIMER>;
+                               assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_266M>,
+                                                        <&clk IMX8MM_SYS_PLL2_100M>,
+                                                        <&clk IMX8MM_SYS_PLL2_125M>;
+                               assigned-clock-rates = <0>, <0>, <125000000>, <100000000>;
+                               fsl,num-tx-queues = <3>;
+                               fsl,num-rx-queues = <3>;
+                               status = "disabled";
+                       };
+
+               };
+
+               aips4: bus@32c00000 {
+                       compatible = "fsl,aips-bus", "simple-bus";
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       ranges;
+
+                       usbotg1: usb@32e40000 {
+                               compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb";
+                               reg = <0x32e40000 0x200>;
+                               interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
+                               clocks = <&clk IMX8MM_CLK_USB1_CTRL_ROOT>;
+                               clock-names = "usb1_ctrl_root_clk";
+                               assigned-clocks = <&clk IMX8MM_CLK_USB_BUS>,
+                                                 <&clk IMX8MM_CLK_USB_CORE_REF>;
+                               assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>,
+                                                        <&clk IMX8MM_SYS_PLL1_100M>;
+                               fsl,usbphy = <&usbphynop1>;
+                               fsl,usbmisc = <&usbmisc1 0>;
+                               status = "disabled";
+                       };
+
+                       usbphynop1: usbphynop1 {
+                               compatible = "usb-nop-xceiv";
+                               clocks = <&clk IMX8MM_CLK_USB_PHY_REF>;
+                               assigned-clocks = <&clk IMX8MM_CLK_USB_PHY_REF>;
+                               assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_100M>;
+                               clock-names = "main_clk";
+                       };
+
+                       usbmisc1: usbmisc@32e40200 {
+                               compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc";
+                               #index-cells = <1>;
+                               reg = <0x32e40200 0x200>;
+                       };
+
+                       usbotg2: usb@32e50000 {
+                               compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb";
+                               reg = <0x32e50000 0x200>;
+                               interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
+                               clocks = <&clk IMX8MM_CLK_USB1_CTRL_ROOT>;
+                               clock-names = "usb1_ctrl_root_clk";
+                               assigned-clocks = <&clk IMX8MM_CLK_USB_BUS>,
+                                                 <&clk IMX8MM_CLK_USB_CORE_REF>;
+                               assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>,
+                                                        <&clk IMX8MM_SYS_PLL1_100M>;
+                               fsl,usbphy = <&usbphynop2>;
+                               fsl,usbmisc = <&usbmisc2 0>;
+                               status = "disabled";
+                       };
+
+                       usbphynop2: usbphynop2 {
+                               compatible = "usb-nop-xceiv";
+                               clocks = <&clk IMX8MM_CLK_USB_PHY_REF>;
+                               assigned-clocks = <&clk IMX8MM_CLK_USB_PHY_REF>;
+                               assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_100M>;
+                               clock-names = "main_clk";
+                       };
+
+                       usbmisc2: usbmisc@32e50200 {
+                               compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc";
+                               #index-cells = <1>;
+                               reg = <0x32e50200 0x200>;
+                       };
+
+               };
+
+               dma_apbh: dma-controller@33000000 {
+                       compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh";
+                       reg = <0x33000000 0x2000>;
+                       interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
+                       #dma-cells = <1>;
+                       dma-channels = <4>;
+                       clocks = <&clk IMX8MM_CLK_NAND_USDHC_BUS_RAWNAND_CLK>;
+               };
+
+               gpmi: nand-controller@33002000{
+                       compatible = "fsl,imx8mm-gpmi-nand", "fsl,imx7d-gpmi-nand";
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       reg = <0x33002000 0x2000>, <0x33004000 0x4000>;
+                       reg-names = "gpmi-nand", "bch";
+                       interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-names = "bch";
+                       clocks = <&clk IMX8MM_CLK_NAND_ROOT>,
+                                <&clk IMX8MM_CLK_NAND_USDHC_BUS_RAWNAND_CLK>;
+                       clock-names = "gpmi_io", "gpmi_bch_apb";
+                       dmas = <&dma_apbh 0>;
+                       dma-names = "rx-tx";
+                       status = "disabled";
+               };
+       };
+};

diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
index 54737bf..b2038be 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
@@ -21,6 +21,12 @@
                reg = <0x00000000 0x40000000 0 0xc0000000>;
        };
 
+       pcie0_refclk: pcie0-refclk {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               clock-frequency = <100000000>;
+       };
+
        reg_usdhc2_vmmc: regulator-vsd-3v3 {
                pinctrl-names = "default";
                pinctrl-0 = <&pinctrl_reg_usdhc2>;
@@ -31,6 +37,63 @@
                gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
                enable-active-high;
        };
+
+       buck2_reg: regulator-buck2 {
+               pinctrl-names = "default";
+               pinctrl-0 = <&pinctrl_buck2>;
+               compatible = "regulator-gpio";
+               regulator-name = "vdd_arm";
+               regulator-min-microvolt = <900000>;
+               regulator-max-microvolt = <1000000>;
+               gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
+               states = <1000000 0x0
+                         900000 0x1>;
+       };
+
+       wm8524: audio-codec {
+               #sound-dai-cells = <0>;
+               compatible = "wlf,wm8524";
+               wlf,mute-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
+       };
+
+       sound-wm8524 {
+               compatible = "simple-audio-card";
+               simple-audio-card,name = "wm8524-audio";
+               simple-audio-card,format = "i2s";
+               simple-audio-card,frame-master = <&cpudai>;
+               simple-audio-card,bitclock-master = <&cpudai>;
+               simple-audio-card,widgets =
+                       "Line", "Left Line Out Jack",
+                       "Line", "Right Line Out Jack";
+               simple-audio-card,routing =
+                       "Left Line Out Jack", "LINEVOUTL",
+                       "Right Line Out Jack", "LINEVOUTR";
+
+               cpudai: simple-audio-card,cpu {
+                       sound-dai = <&sai2>;
+               };
+
+               link_codec: simple-audio-card,codec {
+                       sound-dai = <&wm8524>;
+                       clocks = <&clk IMX8MQ_CLK_SAI2_ROOT>;
+               };
+       };
+};
+
+&A53_0 {
+       cpu-supply = <&buck2_reg>;
+};
+
+&A53_1 {
+       cpu-supply = <&buck2_reg>;
+};
+
+&A53_2 {
+       cpu-supply = <&buck2_reg>;
+};
+
+&A53_3 {
+       cpu-supply = <&buck2_reg>;
 };
 
 &fec1 {
@@ -52,6 +115,26 @@
        };
 };
 
+&sai2 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_sai2>;
+       assigned-clocks = <&clk IMX8MQ_CLK_SAI2>;
+       assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>;
+       assigned-clock-rates = <24576000>;
+       status = "okay";
+};
+
+&gpio5 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_wifi_reset>;
+
+       wl-reg-on {
+               gpio-hog;
+               gpios = <29 GPIO_ACTIVE_HIGH>;
+               output-high;
+       };
+};
+
 &i2c1 {
        clock-frequency = <100000>;
        pinctrl-names = "default";
@@ -143,6 +226,22 @@
        };
 };
 
+&pcie0 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_pcie0>;
+       reset-gpio = <&gpio5 28 GPIO_ACTIVE_LOW>;
+       clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>,
+                <&clk IMX8MQ_CLK_PCIE1_AUX>,
+                <&clk IMX8MQ_CLK_PCIE1_PHY>,
+                <&pcie0_refclk>;
+       clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
+       status = "okay";
+};
+
+&pgc_gpu {
+       power-supply = <&sw1a_reg>;
+};
+
 &uart1 {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_uart1>;
@@ -203,6 +302,13 @@
 };
 
 &iomuxc {
+       pinctrl_buck2: vddarmgrp {
+               fsl,pins = <
+                       MX8MQ_IOMUXC_GPIO1_IO13_GPIO1_IO13              0x19
+               >;
+
+       };
+
        pinctrl_fec1: fec1grp {
                fsl,pins = <
                        MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC                 0x3
@@ -230,6 +336,13 @@
                >;
        };
 
+       pinctrl_pcie0: pcie0grp {
+               fsl,pins = <
+                       MX8MQ_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B            0x76
+                       MX8MQ_IOMUXC_UART4_RXD_GPIO5_IO28               0x16
+               >;
+       };
+
        pinctrl_qspi: qspigrp {
                fsl,pins = <
                        MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK       0x82
@@ -248,6 +361,16 @@
                >;
        };
 
+       pinctrl_sai2: sai2grp {
+               fsl,pins = <
+                       MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC     0xd6
+                       MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK      0xd6
+                       MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK        0xd6
+                       MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0    0xd6
+                       MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8       0xd6
+               >;
+       };
+
        pinctrl_uart1: uart1grp {
                fsl,pins = <
                        MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX             0x49
@@ -347,4 +470,10 @@
                        MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B            0xc6
                >;
        };
+
+       pinctrl_wifi_reset: wifiresetgrp {
+               fsl,pins = <
+                       MX8MQ_IOMUXC_UART4_TXD_GPIO5_IO29               0x16
+               >;
+       };
 };

diff --git a/arch/arm64/boot/dts/freescale/imx8mq-zii-ultra-rmb3.dts b/arch/arm64/boot/dts/freescale/imx8mq-zii-ultra-rmb3.dts
new file mode 100644 (file)
index 0000000..d2a6da4
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mq-zii-ultra-rmb3.dts
@@ -0,0 +1,95 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2019 Zodiac Inflight Innovations
+ */
+
+/dts-v1/;
+
+#include "imx8mq-zii-ultra.dtsi"
+
+/ {
+       model = "ZII i.MX8MQ Ultra RMB3 Board";
+       compatible = "zii,imx8mq-ultra-rmb3", "zii,imx8mq-ultra", "fsl,imx8mq";
+};
+
+&ecspi1 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_ecspi1>;
+       cs-gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>;
+       status = "okay";
+       #address-cells = <1>;
+       #size-cells = <0>;
+
+       nor_flash: flash@0 {
+               compatible = "st,n25q128a13", "jedec,spi-nor";
+               spi-max-frequency = <20000000>;
+               reg = <0>;
+       };
+};
+
+&i2c2 {
+       temp-sense@48 {
+               compatible = "national,lm75";
+               reg = <0x48>;
+       };
+};
+
+&i2c4 {
+       touchscreen@20 {
+               compatible = "syna,rmi4-i2c";
+               pinctrl-names = "default";
+               pinctrl-0 = <&pinctrl_ts>;
+               reg = <0x20>;
+               interrupt-parent = <&gpio1>;
+               interrupts = <12 IRQ_TYPE_LEVEL_LOW>;
+
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               rmi4-f01@1 {
+                       reg = <0x1>;
+                       syna,nosleep-mode = <2>;
+               };
+
+               rmi4-f11@11 {
+                       reg = <0x11>;
+                       touchscreen-inverted-x;
+                       touchscreen-swapped-x-y;
+                       syna,sensor-type = <1>;
+               };
+
+               rmi4-f12@12 {
+                       reg = <0x12>;
+                       touchscreen-inverted-x;
+                       touchscreen-swapped-x-y;
+                       syna,sensor-type = <1>;
+               };
+       };
+
+       touchscreen@2a {
+               compatible = "eeti,exc3000";
+               pinctrl-names = "default";
+               pinctrl-0 = <&pinctrl_ts>;
+               reg = <0x2a>;
+               interrupt-parent = <&gpio1>;
+               interrupts = <12 IRQ_TYPE_LEVEL_LOW>;
+               touchscreen-inverted-x;
+               touchscreen-swapped-x-y;
+               status = "disabled";
+       };
+};
+
+&usbhub {
+       swap-dx-lanes = <0>;
+};
+
+&iomuxc {
+       pinctrl_ecspi1: ecspi1grp {
+               fsl,pins = <
+                       MX8MQ_IOMUXC_ECSPI1_SS0_GPIO5_IO9       0x19
+                       MX8MQ_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK    0x82
+                       MX8MQ_IOMUXC_ECSPI1_MISO_ECSPI1_MISO    0x82
+                       MX8MQ_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI    0x82
+               >;
+       };
+};

diff --git a/arch/arm64/boot/dts/freescale/imx8mq-zii-ultra-zest.dts b/arch/arm64/boot/dts/freescale/imx8mq-zii-ultra-zest.dts
new file mode 100644 (file)
index 0000000..1084d93
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mq-zii-ultra-zest.dts
@@ -0,0 +1,24 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2019 Zodiac Inflight Innovations
+ */
+
+/dts-v1/;
+
+#include "imx8mq-zii-ultra.dtsi"
+
+/ {
+       model = "ZII i.MX8MQ Ultra Zest Board";
+       compatible = "zii,imx8mq-ultra-zest", "zii,imx8mq-ultra", "fsl,imx8mq";
+};
+
+&i2c4 {
+       touchscreen@4a {
+               compatible = "atmel,maxtouch";
+               pinctrl-names = "default";
+               pinctrl-0 = <&pinctrl_ts>;
+               reg = <0x4a>;
+               interrupt-parent = <&gpio1>;
+               interrupts = <12 IRQ_TYPE_LEVEL_LOW>;
+       };
+};

diff --git a/arch/arm64/boot/dts/freescale/imx8mq-zii-ultra.dtsi b/arch/arm64/boot/dts/freescale/imx8mq-zii-ultra.dtsi
new file mode 100644 (file)
index 0000000..7a1706f
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mq-zii-ultra.dtsi
@@ -0,0 +1,725 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2019 Zodiac Inflight Innovations
+ */
+
+#include "imx8mq.dtsi"
+
+/ {
+       aliases {
+               mdio-gpio0 = &mdio0;
+               rtc0 = &ds1341;
+       };
+
+       chosen {
+               stdout-path = &uart1;
+       };
+
+       mdio0: bitbang-mdio {
+               compatible = "virtual,mdio-gpio";
+               pinctrl-names = "default";
+               pinctrl-0 = <&pinctrl_mdio_bitbang>, <&pinctrl_fec1_phy_reset>;
+               gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>, /* MDC */
+                       <&gpio1 14 GPIO_ACTIVE_HIGH>; /* MDIO */
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               phy0: ethernet-phy@0 {
+                       reg = <0>;
+                       reset-gpios = <&gpio1 29 GPIO_ACTIVE_LOW>;
+               };
+       };
+
+       pcie0_refclk: clock-pcie0-refclk {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               clock-frequency = <100000000>;
+       };
+
+       pcie1_refclk: clock-pcie1-refclk {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               clock-frequency = <100000000>;
+       };
+
+       reg_12p0_main: regulator-12p0-main {
+               compatible = "regulator-fixed";
+               regulator-name = "12V_MAIN";
+               regulator-min-microvolt = <5000000>;
+               regulator-max-microvolt = <5000000>;
+               regulator-always-on;
+       };
+
+       reg_5p0_main: regulator-5p0-main {
+               compatible = "regulator-fixed";
+               vin-supply = <&reg_12p0_main>;
+               regulator-name = "5V_MAIN";
+               regulator-min-microvolt = <5000000>;
+               regulator-max-microvolt = <5000000>;
+               regulator-always-on;
+       };
+
+       reg_3p3_main: regulator-3p3-main {
+               compatible = "regulator-fixed";
+               vin-supply = <&reg_12p0_main>;
+               regulator-name = "3V3V_MAIN";
+               regulator-min-microvolt = <3300000>;
+               regulator-max-microvolt = <3300000>;
+               regulator-always-on;
+       };
+
+       reg_5p0_user_usb: regulator-5p0-user-usb {
+               compatible = "regulator-fixed";
+               pinctrl-names = "default";
+               pinctrl-0 = <&pinctrl_reg_user_usb>;
+               vin-supply = <&reg_5p0_main>;
+               regulator-name = "5V_USER_USB";
+               regulator-min-microvolt = <5000000>;
+               regulator-max-microvolt = <5000000>;
+               gpio = <&gpio3 12 GPIO_ACTIVE_LOW>;
+               startup-delay-us = <1000>;
+       };
+
+       reg_usdhc2_vmmc: regulator-vsd-3v3 {
+               pinctrl-names = "default";
+               pinctrl-0 = <&pinctrl_reg_usdhc2>;
+               compatible = "regulator-fixed";
+               vin-supply = <&reg_3p3_main>;
+               regulator-name = "3V3_SD";
+               regulator-min-microvolt = <3300000>;
+               regulator-max-microvolt = <3300000>;
+               gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
+               enable-active-high;
+       };
+
+       reg_arm: regulator-arm {
+               pinctrl-names = "default";
+               pinctrl-0 = <&pinctrl_reg_arm>;
+               compatible = "regulator-gpio";
+               vin-supply = <&reg_12p0_main>;
+               regulator-name = "0V9_ARM";
+               regulator-min-microvolt = <900000>;
+               regulator-max-microvolt = <1000000>;
+               gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>;
+               states = <1000000 0x0
+                          900000 0x1>;
+               regulator-always-on;
+       };
+};
+
+&A53_0 {
+       cpu-supply = <&reg_arm>;
+};
+
+&A53_1 {
+       cpu-supply = <&reg_arm>;
+};
+
+&A53_2 {
+       cpu-supply = <&reg_arm>;
+};
+
+&A53_3 {
+       cpu-supply = <&reg_arm>;
+};
+
+&fec1 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_fec1>;
+
+       phy-handle = <&phy0>;
+       phy-mode = "rmii";
+       status = "okay";
+
+       mdio {
+               #address-cells = <1>;
+               #size-cells = <0>;
+               status = "okay";
+
+               switch: switch@0 {
+                       compatible = "marvell,mv88e6085";
+                       pinctrl-0 = <&pinctrl_switch_irq>;
+                       pinctrl-names = "default";
+                       reg = <0>;
+                       dsa,member = <0 0>;
+                       eeprom-length = <512>;
+                       interrupt-parent = <&gpio1>;
+                       interrupts = <15 IRQ_TYPE_LEVEL_LOW>;
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+
+                       ports {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+
+                               port@0 {
+                                       reg = <0>;
+                                       label = "gigabit_proc";
+                                       phy-handle = <&switchphy0>;
+                               };
+
+                               port@1 {
+                                       reg = <1>;
+                                       label = "netaux";
+                                       phy-handle = <&switchphy1>;
+                               };
+
+                               port@2 {
+                                       reg = <2>;
+                                       label = "cpu";
+                                       ethernet = <&fec1>;
+
+                                       fixed-link {
+                                               speed = <100>;
+                                               full-duplex;
+                                       };
+                               };
+
+                               port@3 {
+                                       reg = <3>;
+                                       label = "netright";
+                                       phy-handle = <&switchphy3>;
+                               };
+
+                               port@4 {
+                                       reg = <4>;
+                                       label = "netleft";
+                                       phy-handle = <&switchphy4>;
+                               };
+                       };
+
+                       mdio {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+
+                               switchphy0: switchphy@0 {
+                                       reg = <0>;
+                                       interrupt-parent = <&switch>;
+                                       interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
+                               };
+
+                               switchphy1: switchphy@1 {
+                                       reg = <1>;
+                                       interrupt-parent = <&switch>;
+                                       interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
+                               };
+
+                               switchphy2: switchphy@2 {
+                                       reg = <2>;
+                                       interrupt-parent = <&switch>;
+                                       interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
+                               };
+
+                               switchphy3: switchphy@3 {
+                                       reg = <3>;
+                                       interrupt-parent = <&switch>;
+                                       interrupts = <3 IRQ_TYPE_LEVEL_HIGH>;
+                               };
+
+                               switchphy4: switchphy@4 {
+                                       reg = <4>;
+                                       interrupt-parent = <&switch>;
+                                       interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
+                               };
+                       };
+               };
+       };
+};
+
+&gpio3 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_gpio3_hog>;
+
+       usb-emulation {
+               gpio-hog;
+               gpios = <10 GPIO_ACTIVE_HIGH>;
+               output-low;
+               line-name = "usb-emulation";
+       };
+
+       usb-mode1 {
+               gpio-hog;
+               gpios = <11 GPIO_ACTIVE_HIGH>;
+               output-high;
+               line-name = "usb-mode1";
+       };
+
+       usb-mode2 {
+               gpio-hog;
+               gpios = <13 GPIO_ACTIVE_HIGH>;
+               output-high;
+               line-name = "usb-mode2";
+       };
+};
+
+&i2c1 {
+       clock-frequency = <400000>;
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_i2c1>;
+       status = "okay";
+};
+
+&i2c2 {
+       clock-frequency = <400000>;
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_i2c2>;
+       status = "okay";
+
+       pmic@8 {
+               compatible = "fsl,pfuze100";
+               reg = <0x8>;
+
+               regulators {
+                       sw1a_reg: sw1ab {
+                               regulator-min-microvolt = <825000>;
+                               regulator-max-microvolt = <1100000>;
+                       };
+
+                       sw1c_reg: sw1c {
+                               regulator-min-microvolt = <825000>;
+                               regulator-max-microvolt = <1100000>;
+                       };
+
+                       sw2_reg: sw2 {
+                               regulator-min-microvolt = <1100000>;
+                               regulator-max-microvolt = <1100000>;
+                               regulator-always-on;
+                       };
+
+                       sw3a_reg: sw3ab {
+                               regulator-min-microvolt = <825000>;
+                               regulator-max-microvolt = <1100000>;
+                               regulator-always-on;
+                       };
+
+                       sw4_reg: sw4 {
+                               regulator-min-microvolt = <1800000>;
+                               regulator-max-microvolt = <1800000>;
+                               regulator-always-on;
+                       };
+
+                       swbst_reg: swbst {
+                               regulator-min-microvolt = <5000000>;
+                               regulator-max-microvolt = <5150000>;
+                       };
+
+                       snvs_reg: vsnvs {
+                               regulator-min-microvolt = <1000000>;
+                               regulator-max-microvolt = <3000000>;
+                               regulator-always-on;
+                       };
+
+                       vref_reg: vrefddr {
+                               regulator-always-on;
+                       };
+
+                       vgen1_reg: vgen1 {
+                               regulator-min-microvolt = <800000>;
+                               regulator-max-microvolt = <1550000>;
+                       };
+
+                       vgen2_reg: vgen2 {
+                               regulator-min-microvolt = <850000>;
+                               regulator-max-microvolt = <975000>;
+                               regulator-always-on;
+                       };
+
+                       vgen3_reg: vgen3 {
+                               regulator-min-microvolt = <1675000>;
+                               regulator-max-microvolt = <1975000>;
+                               regulator-always-on;
+                       };
+
+                       vgen4_reg: vgen4 {
+                               regulator-min-microvolt = <1625000>;
+                               regulator-max-microvolt = <1875000>;
+                               regulator-always-on;
+                       };
+
+                       vgen5_reg: vgen5 {
+                               regulator-min-microvolt = <3075000>;
+                               regulator-max-microvolt = <3625000>;
+                               regulator-always-on;
+                       };
+
+                       vgen6_reg: vgen6 {
+                               regulator-min-microvolt = <1800000>;
+                               regulator-max-microvolt = <3300000>;
+                       };
+               };
+       };
+
+       eeprom@54 {
+               compatible = "atmel,24c128";
+               reg = <0x54>;
+       };
+
+       ds1341: rtc@68 {
+               compatible = "dallas,ds1341";
+               reg = <0x68>;
+       };
+};
+
+&i2c3 {
+       clock-frequency = <100000>;
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_i2c3>;
+       status = "okay";
+
+       usbhub: usbhub@2c {
+               compatible ="microchip,usb2513b";
+               pinctrl-names = "default";
+               pinctrl-0 = <&pinctrl_usbhub>;
+               reg = <0x2c>;
+               reset-gpios = <&gpio3 25 GPIO_ACTIVE_LOW>;
+       };
+};
+
+&i2c4 {
+       clock-frequency = <400000>;
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_i2c4>;
+       status = "okay";
+};
+
+&uart1 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_uart1>;
+       status = "okay";
+};
+
+&uart2 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_uart2>;
+       status = "okay";
+
+       rave-sp {
+               compatible = "zii,rave-sp-rdu2";
+               current-speed = <1000000>;
+               #address-cells = <1>;
+               #size-cells = <1>;
+
+               watchdog {
+                       compatible = "zii,rave-sp-watchdog";
+               };
+
+               backlight {
+                       compatible = "zii,rave-sp-backlight";
+               };
+
+               pwrbutton {
+                       compatible = "zii,rave-sp-pwrbutton";
+               };
+
+               eeprom@a3 {
+                       compatible = "zii,rave-sp-eeprom";
+                       reg = <0xa3 0x4000>;
+                       zii,eeprom-name = "dds-eeprom";
+               };
+
+               eeprom@a4 {
+                       compatible = "zii,rave-sp-eeprom";
+                       reg = <0xa4 0x4000>;
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       zii,eeprom-name = "main-eeprom";
+               };
+       };
+};
+
+&usb3_phy0 {
+       vbus-supply = <&reg_5p0_user_usb>;
+       status = "okay";
+};
+
+&usb_dwc3_0 {
+       dr_mode = "host";
+       status = "okay";
+};
+
+&usb3_phy1 {
+       vbus-supply = <&reg_5p0_main>;
+       status = "okay";
+};
+
+&usb_dwc3_1 {
+       dr_mode = "host";
+       status = "okay";
+};
+
+&pcie0 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_pcie0>;
+       reset-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;
+       clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>,
+                <&clk IMX8MQ_CLK_PCIE1_AUX>,
+                <&clk IMX8MQ_CLK_PCIE1_PHY>,
+                <&pcie0_refclk>;
+       clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
+       status = "okay";
+};
+
+&pcie1 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_pcie1>;
+       reset-gpio = <&gpio1 6 GPIO_ACTIVE_LOW>;
+       clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>,
+                <&clk IMX8MQ_CLK_PCIE2_AUX>,
+                <&clk IMX8MQ_CLK_PCIE2_PHY>,
+                <&pcie1_refclk>;
+       clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
+       status = "okay";
+};
+
+&pgc_gpu {
+       power-supply = <&sw1a_reg>;
+};
+
+&pgc_vpu {
+       power-supply = <&sw1c_reg>;
+};
+
+&usdhc1 {
+       pinctrl-names = "default", "state_100mhz", "state_200mhz";
+       pinctrl-0 = <&pinctrl_usdhc1>;
+       pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
+       pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
+       vqmmc-supply = <&sw4_reg>;
+       bus-width = <8>;
+       non-removable;
+       no-sd;
+       no-sdio;
+       status = "okay";
+};
+
+&usdhc2 {
+       pinctrl-names = "default", "state_100mhz", "state_200mhz";
+       pinctrl-0 = <&pinctrl_usdhc2>;
+       pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
+       pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
+       cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
+       vmmc-supply = <&reg_usdhc2_vmmc>;
+       status = "okay";
+};
+
+&snvs_rtc {
+       status = "disabled";
+};
+
+&iomuxc {
+       pinctrl_fec1: fec1grp {
+               fsl,pins = <
+                       MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC                 0x3
+                       MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO               0x23
+                       MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1           0x1f
+                       MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0           0x1f
+                       MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1           0x91
+                       MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0           0x91
+                       MX8MQ_IOMUXC_ENET_TD2_ENET1_TX_CLK              0x1f
+                       MX8MQ_IOMUXC_ENET_RXC_ENET1_RX_ER               0x91
+                       MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL     0x91
+                       MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL     0x1f
+               >;
+       };
+
+       pinctrl_fec1_phy_reset: fec1phyresetgrp {
+               fsl,pins = <
+                       MX8MQ_IOMUXC_ENET_RD3_GPIO1_IO29                0x11
+               >;
+       };
+
+       pinctrl_gpio3_hog: gpio3hoggrp {
+               fsl,pins = <
+                       MX8MQ_IOMUXC_NAND_DATA04_GPIO3_IO10             0x6
+                       MX8MQ_IOMUXC_NAND_DATA05_GPIO3_IO11             0x6
+                       MX8MQ_IOMUXC_NAND_DATA07_GPIO3_IO13             0x6
+               >;
+       };
+
+       pinctrl_i2c1: i2c1grp {
+               fsl,pins = <
+                       MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL                  0x4000007f
+                       MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA                  0x4000007f
+               >;
+       };
+
+       pinctrl_i2c2: i2c2grp {
+               fsl,pins = <
+                       MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL                  0x4000007f
+                       MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA                  0x4000007f
+               >;
+       };
+
+       pinctrl_i2c3: i2c3grp {
+               fsl,pins = <
+                       MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL                  0x4000007f
+                       MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA                  0x4000007f
+               >;
+       };
+
+       pinctrl_i2c4: i2c4grp {
+               fsl,pins = <
+                       MX8MQ_IOMUXC_I2C4_SCL_I2C4_SCL                  0x4000007f
+                       MX8MQ_IOMUXC_I2C4_SDA_I2C4_SDA                  0x4000007f
+               >;
+       };
+
+       pinctrl_mdio_bitbang: bitbangmdiogrp {
+               fsl,pins = <
+                       MX8MQ_IOMUXC_GPIO1_IO13_GPIO1_IO13              0x44
+                       MX8MQ_IOMUXC_GPIO1_IO14_GPIO1_IO14              0x64
+               >;
+       };
+
+       pinctrl_pcie0: pcie0grp {
+               fsl,pins = <
+                       MX8MQ_IOMUXC_UART4_RXD_PCIE1_CLKREQ_B           0x66
+                       MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3               0x6
+               >;
+       };
+
+       pinctrl_pcie1: pcie1grp {
+               fsl,pins = <
+                       MX8MQ_IOMUXC_UART4_TXD_PCIE2_CLKREQ_B           0x66
+                       MX8MQ_IOMUXC_GPIO1_IO06_GPIO1_IO6               0x6
+               >;
+       };
+
+       pinctrl_reg_arm: regarmgrp {
+               fsl,pins = <
+                       MX8MQ_IOMUXC_NAND_READY_B_GPIO3_IO16            0x19
+               >;
+       };
+
+       pinctrl_reg_usdhc2: regusdhc2grp {
+               fsl,pins = <
+                       MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19             0x41
+               >;
+       };
+
+       pinctrl_reg_user_usb: reguserusbgrp {
+               fsl,pins = <
+                       MX8MQ_IOMUXC_NAND_DATA06_GPIO3_IO12             0x6
+               >;
+       };
+
+       pinctrl_switch_irq: switchgrp {
+               fsl,pins = <
+                       MX8MQ_IOMUXC_GPIO1_IO15_GPIO1_IO15              0x41
+               >;
+       };
+
+       pinctrl_ts: tsgrp {
+               fsl,pins = <
+                       MX8MQ_IOMUXC_GPIO1_IO11_GPIO1_IO11              0x96
+                       MX8MQ_IOMUXC_GPIO1_IO12_GPIO1_IO12              0x96
+               >;
+       };
+
+       pinctrl_uart1: uart1grp {
+               fsl,pins = <
+                       MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX             0x49
+                       MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX             0x49
+               >;
+       };
+
+       pinctrl_uart2: uart2grp {
+               fsl,pins = <
+                       MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX             0x49
+                       MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX             0x49
+               >;
+       };
+
+       pinctrl_usbhub: usbhubgrp {
+               fsl,pins = <
+                       MX8MQ_IOMUXC_SAI5_MCLK_GPIO3_IO25               0x41
+               >;
+       };
+
+       pinctrl_usdhc1: usdhc1grp {
+               fsl,pins = <
+                       MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK                 0x83
+                       MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD                 0xc3
+                       MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0             0xc3
+                       MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1             0xc3
+                       MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2             0xc3
+                       MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3             0xc3
+                       MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4             0xc3
+                       MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5             0xc3
+                       MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6             0xc3
+                       MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7             0xc3
+                       MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE           0x83
+                       MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B         0xc1
+               >;
+       };
+
+       pinctrl_usdhc1_100mhz: usdhc1-100grp {
+               fsl,pins = <
+                       MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK                 0x8d
+                       MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD                 0xcd
+                       MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0             0xcd
+                       MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1             0xcd
+                       MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2             0xcd
+                       MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3             0xcd
+                       MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4             0xcd
+                       MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5             0xcd
+                       MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6             0xcd
+                       MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7             0xcd
+                       MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE           0x8d
+                       MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B         0xc1
+               >;
+       };
+
+       pinctrl_usdhc1_200mhz: usdhc1-200grp {
+               fsl,pins = <
+                       MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK                 0x9f
+                       MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD                 0xdf
+                       MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0             0xdf
+                       MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1             0xdf
+                       MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2             0xdf
+                       MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3             0xdf
+                       MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4             0xdf
+                       MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5             0xdf
+                       MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6             0xdf
+                       MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7             0xdf
+                       MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE           0x9f
+                       MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B         0xc1
+               >;
+       };
+
+       pinctrl_usdhc2: usdhc2grp {
+               fsl,pins = <
+                       MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK                 0x83
+                       MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD                 0xc3
+                       MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0             0xc3
+                       MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1             0xc3
+                       MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2             0xc3
+                       MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3             0xc3
+                       MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT          0xc1
+               >;
+       };
+
+       pinctrl_usdhc2_100mhz: usdhc2-100grp {
+               fsl,pins = <
+                       MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK                 0x85
+                       MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD                 0xc5
+                       MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0             0xc5
+                       MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1             0xc5
+                       MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2             0xc5
+                       MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3             0xc5
+                       MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT          0xc1
+               >;
+       };
+
+       pinctrl_usdhc2_200mhz: usdhc2-200grp {
+               fsl,pins = <
+                       MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK                 0x87
+                       MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD                 0xc7
+                       MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0             0xc7
+                       MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1             0xc7
+                       MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2             0xc7
+                       MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3             0xc7
+                       MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT          0xc1
+               >;
+       };
+};

diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
index 9155bd4..6d635ba 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
@@ -6,8 +6,10 @@
 
 #include <dt-bindings/clock/imx8mq-clock.h>
 #include <dt-bindings/power/imx8mq-power.h>
+#include <dt-bindings/reset/imx8mq-reset.h>
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/thermal/thermal.h>
 #include "imx8mq-pinfunc.h"
 
 / {
@@ -87,32 +89,48 @@
                        device_type = "cpu";
                        compatible = "arm,cortex-a53";
                        reg = <0x0>;
+                       clock-latency = <61036>; /* two CLK32 periods */
+                       clocks = <&clk IMX8MQ_CLK_ARM>;
                        enable-method = "psci";
                        next-level-cache = <&A53_L2>;
+                       operating-points-v2 = <&a53_opp_table>;
+                       #cooling-cells = <2>;
                };
 
                A53_1: cpu@1 {
                        device_type = "cpu";
                        compatible = "arm,cortex-a53";
                        reg = <0x1>;
+                       clock-latency = <61036>; /* two CLK32 periods */
+                       clocks = <&clk IMX8MQ_CLK_ARM>;
                        enable-method = "psci";
                        next-level-cache = <&A53_L2>;
+                       operating-points-v2 = <&a53_opp_table>;
+                       #cooling-cells = <2>;
                };
 
                A53_2: cpu@2 {
                        device_type = "cpu";
                        compatible = "arm,cortex-a53";
                        reg = <0x2>;
+                       clock-latency = <61036>; /* two CLK32 periods */
+                       clocks = <&clk IMX8MQ_CLK_ARM>;
                        enable-method = "psci";
                        next-level-cache = <&A53_L2>;
+                       operating-points-v2 = <&a53_opp_table>;
+                       #cooling-cells = <2>;
                };
 
                A53_3: cpu@3 {
                        device_type = "cpu";
                        compatible = "arm,cortex-a53";
                        reg = <0x3>;
+                       clock-latency = <61036>; /* two CLK32 periods */
+                       clocks = <&clk IMX8MQ_CLK_ARM>;
                        enable-method = "psci";
                        next-level-cache = <&A53_L2>;
+                       operating-points-v2 = <&a53_opp_table>;
+                       #cooling-cells = <2>;
                };
 
                A53_L2: l2-cache0 {
@@ -120,6 +138,24 @@
                };
        };
 
+       a53_opp_table: opp-table {
+               compatible = "operating-points-v2";
+               opp-shared;
+
+               opp-800000000 {
+                       opp-hz = /bits/ 64 <800000000>;
+                       opp-microvolt = <900000>;
+                       clock-latency-ns = <150000>;
+               };
+
+               opp-1300000000 {
+                       opp-hz = /bits/ 64 <1300000000>;
+                       opp-microvolt = <1000000>;
+                       clock-latency-ns = <150000>;
+                       opp-suspend;
+               };
+       };
+
        pmu {
                compatible = "arm,cortex-a53-pmu";
                interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
@@ -132,6 +168,67 @@
                method = "smc";
        };
 
+       thermal-zones {
+               cpu-thermal {
+                       polling-delay-passive = <250>;
+                       polling-delay = <2000>;
+                       thermal-sensors = <&tmu 0>;
+
+                       trips {
+                               cpu_alert: cpu-alert {
+                                       temperature = <80000>;
+                                       hysteresis = <2000>;
+                                       type = "passive";
+                               };
+
+                               cpu-crit {
+                                       temperature = <90000>;
+                                       hysteresis = <2000>;
+                                       type = "critical";
+                               };
+                       };
+
+                       cooling-maps {
+                               map0 {
+                                       trip = <&cpu_alert>;
+                                       cooling-device =
+                                               <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+                                               <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+                                               <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+                                               <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+                               };
+                       };
+               };
+
+               gpu-thermal {
+                       polling-delay-passive = <250>;
+                       polling-delay = <2000>;
+                       thermal-sensors = <&tmu 1>;
+
+                       trips {
+                               gpu-crit {
+                                       temperature = <90000>;
+                                       hysteresis = <2000>;
+                                       type = "critical";
+                               };
+                       };
+               };
+
+               vpu-thermal {
+                       polling-delay-passive = <250>;
+                       polling-delay = <2000>;
+                       thermal-sensors = <&tmu 2>;
+
+                       trips {
+                               vpu-crit {
+                                       temperature = <90000>;
+                                       hysteresis = <2000>;
+                                       type = "critical";
+                               };
+                       };
+               };
+       };
+
        timer {
                compatible = "arm,armv8-timer";
                interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure */
@@ -160,6 +257,7 @@
                                reg = <0x30200000 0x10000>;
                                interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
                                             <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
+                               clocks = <&clk IMX8MQ_CLK_GPIO1_ROOT>;
                                gpio-controller;
                                #gpio-cells = <2>;
                                interrupt-controller;
@@ -171,6 +269,7 @@
                                reg = <0x30210000 0x10000>;
                                interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
                                             <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
+                               clocks = <&clk IMX8MQ_CLK_GPIO2_ROOT>;
                                gpio-controller;
                                #gpio-cells = <2>;
                                interrupt-controller;
@@ -182,6 +281,7 @@
                                reg = <0x30220000 0x10000>;
                                interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
                                             <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
+                               clocks = <&clk IMX8MQ_CLK_GPIO3_ROOT>;
                                gpio-controller;
                                #gpio-cells = <2>;
                                interrupt-controller;
@@ -193,6 +293,7 @@
                                reg = <0x30230000 0x10000>;
                                interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
                                             <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+                               clocks = <&clk IMX8MQ_CLK_GPIO4_ROOT>;
                                gpio-controller;
                                #gpio-cells = <2>;
                                interrupt-controller;
@@ -204,12 +305,65 @@
                                reg = <0x30240000 0x10000>;
                                interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
                                             <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+                               clocks = <&clk IMX8MQ_CLK_GPIO5_ROOT>;
                                gpio-controller;
                                #gpio-cells = <2>;
                                interrupt-controller;
                                #interrupt-cells = <2>;
                        };
 
+                       tmu: tmu@30260000 {
+                               compatible = "fsl,imx8mq-tmu";
+                               reg = <0x30260000 0x10000>;
+                               interrupt = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
+                               little-endian;
+                               fsl,tmu-range = <0xb0000 0xa0026 0x80048 0x70061>;
+                               fsl,tmu-calibration = <0x00000000 0x00000023
+                                                      0x00000001 0x00000029
+                                                      0x00000002 0x0000002f
+                                                      0x00000003 0x00000035
+                                                      0x00000004 0x0000003d
+                                                      0x00000005 0x00000043
+                                                      0x00000006 0x0000004b
+                                                      0x00000007 0x00000051
+                                                      0x00000008 0x00000057
+                                                      0x00000009 0x0000005f
+                                                      0x0000000a 0x00000067
+                                                      0x0000000b 0x0000006f
+
+                                                      0x00010000 0x0000001b
+                                                      0x00010001 0x00000023
+                                                      0x00010002 0x0000002b
+                                                      0x00010003 0x00000033
+                                                      0x00010004 0x0000003b
+                                                      0x00010005 0x00000043
+                                                      0x00010006 0x0000004b
+                                                      0x00010007 0x00000055
+                                                      0x00010008 0x0000005d
+                                                      0x00010009 0x00000067
+                                                      0x0001000a 0x00000070
+
+                                                      0x00020000 0x00000017
+                                                      0x00020001 0x00000023
+                                                      0x00020002 0x0000002d
+                                                      0x00020003 0x00000037
+                                                      0x00020004 0x00000041
+                                                      0x00020005 0x0000004b
+                                                      0x00020006 0x00000057
+                                                      0x00020007 0x00000063
+                                                      0x00020008 0x0000006f
+
+                                                      0x00030000 0x00000015
+                                                      0x00030001 0x00000021
+                                                      0x00030002 0x0000002d
+                                                      0x00030003 0x00000039
+                                                      0x00030004 0x00000045
+                                                      0x00030005 0x00000053
+                                                      0x00030006 0x0000005f
+                                                      0x00030007 0x00000071>;
+                               #thermal-sensor-cells =  <1>;
+                       };
+
                        wdog1: watchdog@30280000 {
                                compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt";
                                reg = <0x30280000 0x10000>;
@@ -234,16 +388,35 @@
                                status = "disabled";
                        };
 
+                       sdma2: sdma@302c0000 {
+                               compatible = "fsl,imx8mq-sdma","fsl,imx7d-sdma";
+                               reg = <0x302c0000 0x10000>;
+                               interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
+                               clocks = <&clk IMX8MQ_CLK_SDMA2_ROOT>,
+                                        <&clk IMX8MQ_CLK_SDMA2_ROOT>;
+                               clock-names = "ipg", "ahb";
+                               #dma-cells = <3>;
+                               fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
+                       };
+
                        iomuxc: iomuxc@30330000 {
                                compatible = "fsl,imx8mq-iomuxc";
                                reg = <0x30330000 0x10000>;
                        };
 
                        iomuxc_gpr: syscon@30340000 {
-                               compatible = "fsl,imx8mq-iomuxc-gpr", "syscon";
+                               compatible = "fsl,imx8mq-iomuxc-gpr", "fsl,imx6q-iomuxc-gpr", "syscon";
                                reg = <0x30340000 0x10000>;
                        };
 
+                       ocotp: ocotp-ctrl@30350000 {
+                               compatible = "fsl,imx8mq-ocotp", "syscon";
+                               reg = <0x30350000 0x10000>;
+                               clocks = <&clk IMX8MQ_CLK_OCOTP_ROOT>;
+                               #address-cells = <1>;
+                               #size-cells = <1>;
+                       };
+
                        anatop: syscon@30360000 {
                                compatible = "fsl,imx8mq-anatop", "syscon";
                                reg = <0x30360000 0x10000>;
@@ -278,6 +451,12 @@
                                              "clk_ext3", "clk_ext4";
                        };
 
+                       src: reset-controller@30390000 {
+                               compatible = "fsl,imx8mq-src", "syscon";
+                               reg = <0x30390000 0x10000>;
+                               #reset-cells = <1>;
+                       };
+
                        gpc: gpc@303a0000 {
                                compatible = "fsl,imx8mq-gpc";
                                reg = <0x303a0000 0x10000>;
@@ -294,9 +473,25 @@
                                                reg = <IMX8M_POWER_DOMAIN_MIPI>;
                                        };
 
-                                       pgc_pcie1: power-domain@1 {
+                                       /*
+                                        * As per comment in ATF source code:
+                                        *
+                                        * PCIE1 and PCIE2 share the
+                                        * same reset signal, if we
+                                        * power down PCIE2, PCIE1
+                                        * will be held in reset too.
+                                        *
+                                        * So instead of creating two
+                                        * separate power domains for
+                                        * PCIE1 and PCIE2 we create a
+                                        * link between both and use
+                                        * it as a shared PCIE power
+                                        * domain.
+                                        */
+                                       pgc_pcie: power-domain@1 {
                                                #power-domain-cells = <0>;
                                                reg = <IMX8M_POWER_DOMAIN_PCIE1>;
+                                               power-domains = <&pgc_pcie2>;
                                        };
 
                                        pgc_otg1: power-domain@2 {
@@ -478,6 +673,21 @@
                                status = "disabled";
                        };
 
+                       sai2: sai@308b0000 {
+                               #sound-dai-cells = <0>;
+                               compatible = "fsl,imx8mq-sai",
+                                            "fsl,imx6sx-sai";
+                               reg = <0x308b0000 0x10000>;
+                               interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+                               clocks = <&clk IMX8MQ_CLK_SAI2_IPG>,
+                                        <&clk IMX8MQ_CLK_SAI2_ROOT>,
+                                        <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>;
+                               clock-names = "bus", "mclk1", "mclk2", "mclk3";
+                               dmas = <&sdma1 10 24 0>, <&sdma1 11 24 0>;
+                               dma-names = "rx", "tx";
+                               status = "disabled";
+                       };
+
                        i2c1: i2c@30a20000 {
                                compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
                                reg = <0x30a20000 0x10000>;
@@ -575,6 +785,17 @@
                                status = "disabled";
                        };
 
+                       sdma1: sdma@30bd0000 {
+                               compatible = "fsl,imx8mq-sdma","fsl,imx7d-sdma";
+                               reg = <0x30bd0000 0x10000>;
+                               interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
+                               clocks = <&clk IMX8MQ_CLK_SDMA1_ROOT>,
+                                        <&clk IMX8MQ_CLK_AHB>;
+                               clock-names = "ipg", "ahb";
+                               #dma-cells = <3>;
+                               fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
+                       };
+
                        fec1: ethernet@30be0000 {
                                compatible = "fsl,imx8mq-fec", "fsl,imx6sx-fec";
                                reg = <0x30be0000 0x10000>;
@@ -594,6 +815,30 @@
                        };
                };
 
+               gpu: gpu@38000000 {
+                       compatible = "vivante,gc";
+                       reg = <0x38000000 0x40000>;
+                       interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&clk IMX8MQ_CLK_GPU_ROOT>,
+                                <&clk IMX8MQ_CLK_GPU_SHADER_DIV>,
+                                <&clk IMX8MQ_CLK_GPU_AXI>,
+                                <&clk IMX8MQ_CLK_GPU_AHB>;
+                       clock-names = "core", "shader", "bus", "reg";
+                       assigned-clocks = <&clk IMX8MQ_CLK_GPU_CORE_SRC>,
+                                         <&clk IMX8MQ_CLK_GPU_SHADER_SRC>,
+                                         <&clk IMX8MQ_CLK_GPU_AXI>,
+                                         <&clk IMX8MQ_CLK_GPU_AHB>,
+                                         <&clk IMX8MQ_GPU_PLL_BYPASS>;
+                       assigned-clock-parents = <&clk IMX8MQ_GPU_PLL_OUT>,
+                                                <&clk IMX8MQ_GPU_PLL_OUT>,
+                                                <&clk IMX8MQ_GPU_PLL_OUT>,
+                                                <&clk IMX8MQ_GPU_PLL_OUT>,
+                                                <&clk IMX8MQ_GPU_PLL>;
+                       assigned-clock-rates = <800000000>, <800000000>,
+                                              <800000000>, <800000000>, <0>;
+                       power-domains = <&pgc_gpu>;
+               };
+
                usb_dwc3_0: usb@38100000 {
                        compatible = "fsl,imx8mq-dwc3", "snps,dwc3";
                        reg = <0x38100000 0x10000>;
@@ -658,6 +903,66 @@
                        status = "disabled";
                };
 
+
+               pcie0: pcie@33800000 {
+                       compatible = "fsl,imx8mq-pcie";
+                       reg = <0x33800000 0x400000>,
+                             <0x1ff00000 0x80000>;
+                       reg-names = "dbi", "config";
+                       #address-cells = <3>;
+                       #size-cells = <2>;
+                       device_type = "pci";
+                       bus-range = <0x00 0xff>;
+                       ranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000 /* downstream I/O 64KB */
+                                 0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */
+                       num-lanes = <1>;
+                       num-viewport = <4>;
+                       interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-names = "msi";
+                       #interrupt-cells = <1>;
+                       interrupt-map-mask = <0 0 0 0x7>;
+                       interrupt-map = <0 0 0 1 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
+                                       <0 0 0 2 &gic GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
+                                       <0 0 0 3 &gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
+                                       <0 0 0 4 &gic GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
+                       fsl,max-link-speed = <2>;
+                       power-domains = <&pgc_pcie>;
+                       resets = <&src IMX8MQ_RESET_PCIEPHY>,
+                                <&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>,
+                                <&src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>;
+                       reset-names = "pciephy", "apps", "turnoff";
+                       status = "disabled";
+               };
+
+               pcie1: pcie@33c00000 {
+                       compatible = "fsl,imx8mq-pcie";
+                       reg = <0x33c00000 0x400000>,
+                             <0x27f00000 0x80000>;
+                       reg-names = "dbi", "config";
+                       #address-cells = <3>;
+                       #size-cells = <2>;
+                       device_type = "pci";
+                       ranges =  <0x81000000 0 0x00000000 0x27f80000 0 0x00010000 /* downstream I/O 64KB */
+                                  0x82000000 0 0x20000000 0x20000000 0 0x07f00000>; /* non-prefetchable memory */
+                       num-lanes = <1>;
+                       num-viewport = <4>;
+                       interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-names = "msi";
+                       #interrupt-cells = <1>;
+                       interrupt-map-mask = <0 0 0 0x7>;
+                       interrupt-map = <0 0 0 1 &gic GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
+                                       <0 0 0 2 &gic GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
+                                       <0 0 0 3 &gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
+                                       <0 0 0 4 &gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
+                       fsl,max-link-speed = <2>;
+                       power-domains = <&pgc_pcie>;
+                       resets = <&src IMX8MQ_RESET_PCIEPHY2>,
+                                <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_EN>,
+                                <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_TURNOFF>;
+                       reset-names = "pciephy", "apps", "turnoff";
+                       status = "disabled";
+               };
+
                gic: interrupt-controller@38800000 {
                        compatible = "arm,gic-v3";
                        reg = <0x38800000 0x10000>,     /* GIC Dist */

diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
index 03aad66..bfdada2 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
+++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
@@ -60,6 +60,82 @@
        };
 };
 
+&adma_i2c1 {
+       #address-cells = <1>;
+       #size-cells = <0>;
+       clock-frequency = <100000>;
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_lpi2c1 &pinctrl_ioexp_rst>;
+       status = "okay";
+
+       i2c-switch@71 {
+               compatible = "nxp,pca9646", "nxp,pca9546";
+               #address-cells = <1>;
+               #size-cells = <0>;
+               reg = <0x71>;
+               reset-gpios = <&lsio_gpio1 1 GPIO_ACTIVE_LOW>;
+
+               i2c@0 {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       reg = <0>;
+
+                       max7322: gpio@68 {
+                               compatible = "maxim,max7322";
+                               reg = <0x68>;
+                               gpio-controller;
+                               #gpio-cells = <2>;
+                       };
+               };
+
+               i2c@1 {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       reg = <1>;
+               };
+
+               i2c@2 {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       reg = <2>;
+
+                       pressure-sensor@60 {
+                               compatible = "fsl,mpl3115";
+                               reg = <0x60>;
+                       };
+               };
+
+               i2c@3 {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       reg = <3>;
+
+                       pca9557_a: gpio@1a {
+                               compatible = "nxp,pca9557";
+                               reg = <0x1a>;
+                               gpio-controller;
+                               #gpio-cells = <2>;
+                       };
+
+                       pca9557_b: gpio@1d {
+                               compatible = "nxp,pca9557";
+                               reg = <0x1d>;
+                               gpio-controller;
+                               #gpio-cells = <2>;
+                       };
+
+                       light-sensor@44 {
+                               pinctrl-names = "default";
+                               pinctrl-0 = <&pinctrl_isl29023>;
+                               compatible = "isil,isl29023";
+                               reg = <0x44>;
+                               interrupt-parent = <&lsio_gpio1>;
+                               interrupts = <2 IRQ_TYPE_EDGE_FALLING>;
+                       };
+               };
+       };
+};
+
 &usdhc1 {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_usdhc1>;
@@ -100,6 +176,25 @@
                >;
        };
 
+       pinctrl_ioexp_rst: ioexp_rst_grp {
+               fsl,pins = <
+                       IMX8QXP_SPI2_SDO_LSIO_GPIO1_IO01                        0x06000021
+               >;
+       };
+
+       pinctrl_isl29023: isl29023grp {
+               fsl,pins = <
+                       IMX8QXP_SPI2_SDI_LSIO_GPIO1_IO02                        0x00000021
+               >;
+       };
+
+       pinctrl_lpi2c1: lpi2c1grp {
+               fsl,pins = <
+                       IMX8QXP_USB_SS3_TC1_ADMA_I2C1_SCL                       0x06000021
+                       IMX8QXP_USB_SS3_TC3_ADMA_I2C1_SDA                       0x06000021
+               >;
+       };
+
        pinctrl_lpuart0: lpuart0grp {
                fsl,pins = <
                        IMX8QXP_UART0_RX_ADMA_UART0_RX                          0x06000020

diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
index 4c3dd95..0683ee2 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
@@ -21,6 +21,7 @@
                mmc1 = &usdhc2;
                mmc2 = &usdhc3;
                serial0 = &adma_lpuart0;
+               mu1 = &lsio_mu1;
        };
 
        cpus {
@@ -34,6 +35,9 @@
                        reg = <0x0 0x0>;
                        enable-method = "psci";
                        next-level-cache = <&A35_L2>;
+                       clocks = <&clk IMX_A35_CLK>;
+                       operating-points-v2 = <&a35_opp_table>;
+                       #cooling-cells = <2>;
                };
 
                A35_1: cpu@1 {
@@ -42,6 +46,9 @@
                        reg = <0x0 0x1>;
                        enable-method = "psci";
                        next-level-cache = <&A35_L2>;
+                       clocks = <&clk IMX_A35_CLK>;
+                       operating-points-v2 = <&a35_opp_table>;
+                       #cooling-cells = <2>;
                };
 
                A35_2: cpu@2 {
@@ -50,6 +57,9 @@
                        reg = <0x0 0x2>;
                        enable-method = "psci";
                        next-level-cache = <&A35_L2>;
+                       clocks = <&clk IMX_A35_CLK>;
+                       operating-points-v2 = <&a35_opp_table>;
+                       #cooling-cells = <2>;
                };
 
                A35_3: cpu@3 {
@@ -58,6 +68,9 @@
                        reg = <0x0 0x3>;
                        enable-method = "psci";
                        next-level-cache = <&A35_L2>;
+                       clocks = <&clk IMX_A35_CLK>;
+                       operating-points-v2 = <&a35_opp_table>;
+                       #cooling-cells = <2>;
                };
 
                A35_L2: l2-cache0 {
@@ -65,6 +78,24 @@
                };
        };
 
+       a35_opp_table: opp-table {
+               compatible = "operating-points-v2";
+               opp-shared;
+
+               opp-900000000 {
+                       opp-hz = /bits/ 64 <900000000>;
+                       opp-microvolt = <1000000>;
+                       clock-latency-ns = <150000>;
+               };
+
+               opp-1200000000 {
+                       opp-hz = /bits/ 64 <1200000000>;
+                       opp-microvolt = <1100000>;
+                       clock-latency-ns = <150000>;
+                       opp-suspend;
+               };
+       };
+
        gic: interrupt-controller@51a00000 {
                compatible = "arm,gic-v3";
                reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */
@@ -87,7 +118,8 @@
        scu {
                compatible = "fsl,imx-scu";
                mbox-names = "tx0", "tx1", "tx2", "tx3",
-                            "rx0", "rx1", "rx2", "rx3";
+                            "rx0", "rx1", "rx2", "rx3",
+                            "gip3";
                mboxes = <&lsio_mu1 0 0
                          &lsio_mu1 0 1
                          &lsio_mu1 0 2
@@ -95,7 +127,8 @@
                          &lsio_mu1 1 0
                          &lsio_mu1 1 1
                          &lsio_mu1 1 2
-                         &lsio_mu1 1 3>;
+                         &lsio_mu1 1 3
+                         &lsio_mu1 3 3>;
 
                clk: clock-controller {
                        compatible = "fsl,imx8qxp-clk";
@@ -163,6 +196,39 @@
                        status = "disabled";
                };
 
+               adma_lpuart1: serial@5a070000 {
+                       compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
+                       reg = <0x5a070000 0x1000>;
+                       interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-parent = <&gic>;
+                       clocks = <&adma_lpcg IMX_ADMA_LPCG_UART1_BAUD_CLK>;
+                       clock-names = "ipg";
+                       power-domains = <&pd IMX_SC_R_UART_1>;
+                       status = "disabled";
+               };
+
+               adma_lpuart2: serial@5a080000 {
+                       compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
+                       reg = <0x5a080000 0x1000>;
+                       interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-parent = <&gic>;
+                       clocks = <&adma_lpcg IMX_ADMA_LPCG_UART2_BAUD_CLK>;
+                       clock-names = "ipg";
+                       power-domains = <&pd IMX_SC_R_UART_2>;
+                       status = "disabled";
+               };
+
+               adma_lpuart3: serial@5a090000 {
+                       compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
+                       reg = <0x5a090000 0x1000>;
+                       interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-parent = <&gic>;
+                       clocks = <&adma_lpcg IMX_ADMA_LPCG_UART3_BAUD_CLK>;
+                       clock-names = "ipg";
+                       power-domains = <&pd IMX_SC_R_UART_3>;
+                       status = "disabled";
+               };
+
                adma_i2c0: i2c@5a800000 {
                        compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
                        reg = <0x5a800000 0x4000>;
@@ -328,7 +394,7 @@
                        compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
                        reg = <0x5d1b0000 0x10000>;
                        interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
-                       #mbox-cells = <0>;
+                       #mbox-cells = <2>;
                        status = "disabled";
                };
 
@@ -339,11 +405,19 @@
                        #mbox-cells = <2>;
                };
 
+               lsio_mu2: mailbox@5d1d0000 {
+                       compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
+                       reg = <0x5d1d0000 0x10000>;
+                       interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
+                       #mbox-cells = <2>;
+                       status = "disabled";
+               };
+
                lsio_mu3: mailbox@5d1e0000 {
                        compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
                        reg = <0x5d1e0000 0x10000>;
                        interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
-                       #mbox-cells = <0>;
+                       #mbox-cells = <2>;
                        status = "disabled";
                };
 
@@ -351,7 +425,7 @@
                        compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
                        reg = <0x5d1f0000 0x10000>;
                        interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
-                       #mbox-cells = <0>;
+                       #mbox-cells = <2>;
                        status = "disabled";
                };
 
@@ -443,4 +517,9 @@
                        power-domains = <&pd IMX_SC_R_GPIO_7>;
                };
        };
+
+       watchdog {
+               compatible = "fsl,imx8qxp-sc-wdt", "fsl,imx-sc-wdt";
+               timeout-sec = <60>;
+       };
 };

diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
index 2f19e0e..aa6a8ad 100644 (file)
--- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
@@ -478,6 +478,8 @@
                        compatible = "arm,pl011", "arm,primecell";
                        reg = <0x0 0xfdf00000 0x0 0x1000>;
                        interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
+                       dma-names = "rx", "tx";
+                       dmas =  <&dma0 2 &dma0 3>;
                        clocks = <&crg_ctrl HI3660_CLK_GATE_UART1>,
                                 <&crg_ctrl HI3660_CLK_GATE_UART1>;
                        clock-names = "uartclk", "apb_pclk";
@@ -490,6 +492,8 @@
                        compatible = "arm,pl011", "arm,primecell";
                        reg = <0x0 0xfdf03000 0x0 0x1000>;
                        interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
+                       dma-names = "rx", "tx";
+                       dmas =  <&dma0 4 &dma0 5>;
                        clocks = <&crg_ctrl HI3660_CLK_GATE_UART2>,
                                 <&crg_ctrl HI3660_PCLK>;
                        clock-names = "uartclk", "apb_pclk";
@@ -514,6 +518,8 @@
                        compatible = "arm,pl011", "arm,primecell";
                        reg = <0x0 0xfdf01000 0x0 0x1000>;
                        interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
+                       dma-names = "rx", "tx";
+                       dmas =  <&dma0 6 &dma0 7>;
                        clocks = <&crg_ctrl HI3660_CLK_GATE_UART4>,
                                 <&crg_ctrl HI3660_CLK_GATE_UART4>;
                        clock-names = "uartclk", "apb_pclk";
@@ -526,6 +532,8 @@
                        compatible = "arm,pl011", "arm,primecell";
                        reg = <0x0 0xfdf05000 0x0 0x1000>;
                        interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
+                       dma-names = "rx", "tx";
+                       dmas =  <&dma0 8 &dma0 9>;
                        clocks = <&crg_ctrl HI3660_CLK_GATE_UART5>,
                                 <&crg_ctrl HI3660_CLK_GATE_UART5>;
                        clock-names = "uartclk", "apb_pclk";
@@ -552,13 +560,23 @@
                        #dma-cells = <1>;
                        dma-channels = <16>;
                        dma-requests = <32>;
-                       dma-min-chan = <1>;
+                       dma-channel-mask = <0xfffe>;
                        interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
                        clocks = <&crg_ctrl HI3660_CLK_GATE_DMAC>;
                        dma-no-cci;
                        dma-type = "hi3660_dma";
                };
 
+               asp_dmac: dma-controller@e804b000 {
+                       compatible = "hisilicon,hisi-pcm-asp-dma-1.0";
+                       reg = <0x0 0xe804b000 0x0 0x1000>;
+                       #dma-cells = <1>;
+                       dma-channels = <16>;
+                       dma-requests = <32>;
+                       interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-names = "asp_dma_irq";
+               };
+
                rtc0: rtc@fff04000 {
                        compatible = "arm,pl031", "arm,primecell";
                        reg = <0x0 0Xfff04000 0x0 0x1000>;

diff --git a/arch/arm64/boot/dts/hisilicon/hi3670-hikey970.dts b/arch/arm64/boot/dts/hisilicon/hi3670-hikey970.dts
index c9775b6..7dac33d 100644 (file)
--- a/arch/arm64/boot/dts/hisilicon/hi3670-hikey970.dts
+++ b/arch/arm64/boot/dts/hisilicon/hi3670-hikey970.dts
@@ -8,6 +8,7 @@
  */
 
 /dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
 
 #include "hi3670.dtsi"
 #include "hikey970-pinctrl.dtsi"
@@ -17,6 +18,8 @@
        compatible = "hisilicon,hi3670-hikey970", "hisilicon,hi3670";
 
        aliases {
+               mshc1 = &dwmmc1;
+               mshc2 = &dwmmc2;
                serial0 = &uart0;
                serial1 = &uart1;
                serial2 = &uart2;
@@ -35,6 +38,37 @@
                /* expect bootloader to fill in this region */
                reg = <0x0 0x0 0x0 0x0>;
        };
+
+       sd_1v8: regulator-1v8 {
+               compatible = "regulator-fixed";
+               regulator-name = "fixed-1.8V";
+               regulator-min-microvolt = <1800000>;
+               regulator-max-microvolt = <1800000>;
+               regulator-always-on;
+       };
+
+       sd_3v3: regulator-3v3 {
+               compatible = "regulator-fixed";
+               regulator-name = "fixed-3.3V";
+               regulator-min-microvolt = <3300000>;
+               regulator-max-microvolt = <3300000>;
+               regulator-boot-on;
+               regulator-always-on;
+       };
+
+       wlan_en: wlan-en-1-8v {
+               compatible = "regulator-fixed";
+               regulator-name = "wlan-en-regulator";
+               regulator-min-microvolt = <1800000>;
+               regulator-max-microvolt = <1800000>;
+
+               /* GPIO_051_WIFI_EN */
+               gpio = <&gpio6 3 0>;
+
+               /* WLAN card specific delay */
+               startup-delay-us = <70000>;
+               enable-active-high;
+       };
 };
 
 /*
@@ -354,6 +388,47 @@
                "GPIO_231_HDMI_INT";
 };
 
+&dwmmc1 {
+       bus-width = <0x4>;
+       sd-uhs-sdr12;
+       sd-uhs-sdr25;
+       sd-uhs-sdr50;
+       sd-uhs-sdr104;
+       cap-sd-highspeed;
+       disable-wp;
+       cd-inverted;
+       cd-gpios = <&gpio25 5 GPIO_ACTIVE_HIGH>;
+       pinctrl-names = "default";
+       pinctrl-0 = <&sd_pmx_func
+                    &sd_clk_cfg_func
+                    &sd_cfg_func>;
+       vmmc-supply = <&sd_3v3>;
+       vqmmc-supply = <&sd_1v8>;
+       status = "okay";
+};
+
+&dwmmc2 { /* WIFI */
+       bus-width = <0x4>;
+       non-removable;
+       broken-cd;
+       cap-power-off-card;
+       pinctrl-names = "default";
+       pinctrl-0 = <&sdio_pmx_func
+                    &sdio_clk_cfg_func
+                    &sdio_cfg_func>;
+       /* WL_EN */
+       vmmc-supply = <&wlan_en>;
+       status = "ok";
+
+       wlcore: wlcore@2 {
+               compatible = "ti,wl1837";
+               reg = <2>;      /* sdio func num */
+               /* WL_IRQ, GPIO_177_WL_WAKEUP_AP */
+               interrupt-parent = <&gpio22>;
+               interrupts = <1 IRQ_TYPE_EDGE_RISING>;
+       };
+};
+
 &uart0 {
        /* On High speed expansion header */
        label = "HS-UART0";

diff --git a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi
index 2ed06e4..2dcffa3 100644 (file)
--- a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi
@@ -151,6 +151,13 @@
                        #clock-cells = <1>;
                };
 
+               crg_rst: crg_rst_controller {
+                       compatible = "hisilicon,hi3670-reset",
+                                    "hisilicon,hi3660-reset";
+                       #reset-cells = <2>;
+                       hisi,rst-syscon = <&crg_ctrl>;
+               };
+
                pctrl: pctrl@e8a09000 {
                        compatible = "hisilicon,hi3670-pctrl", "syscon";
                        reg = <0x0 0xe8a09000 0x0 0x1000>;
@@ -647,5 +654,60 @@
                        clocks = <&sctrl HI3670_PCLK_AO_GPIO6>;
                        clock-names = "apb_pclk";
                };
+
+               /* UFS */
+               ufs: ufs@ff3c0000 {
+                       compatible = "hisilicon,hi3670-ufs", "jedec,ufs-2.1";
+                       /* 0: HCI standard */
+                       /* 1: UFS SYS CTRL */
+                       reg = <0x0 0xff3c0000 0x0 0x1000>,
+                               <0x0 0xff3e0000 0x0 0x1000>;
+                       interrupt-parent = <&gic>;
+                       interrupts = <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&crg_ctrl HI3670_CLK_GATE_UFSIO_REF>,
+                               <&crg_ctrl HI3670_CLK_GATE_UFS_SUBSYS>;
+                       clock-names = "ref_clk", "phy_clk";
+                       freq-table-hz = <0 0>, <0 0>;
+                       /* offset: 0x84; bit: 12 */
+                       resets = <&crg_rst 0x84 12>;
+                       reset-names = "rst";
+               };
+
+               /* SD */
+               dwmmc1: dwmmc1@ff37f000 {
+                       compatible = "hisilicon,hi3670-dw-mshc",
+                                    "hisilicon,hi3660-dw-mshc";
+                       reg = <0x0 0xff37f000 0x0 0x1000>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&crg_ctrl HI3670_CLK_GATE_SD>,
+                               <&crg_ctrl HI3670_HCLK_GATE_SD>;
+                       clock-names = "ciu", "biu";
+                       clock-frequency = <3200000>;
+                       resets = <&crg_rst 0x94 18>;
+                       reset-names = "reset";
+                       hisilicon,peripheral-syscon = <&sctrl>;
+                       card-detect-delay = <200>;
+                       status = "disabled";
+               };
+
+               /* SDIO */
+               dwmmc2: dwmmc2@fc183000 {
+                       compatible = "hisilicon,hi3670-dw-mshc",
+                                    "hisilicon,hi3660-dw-mshc";
+                       reg = <0x0 0xfc183000 0x0 0x1000>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&crg_ctrl HI3670_CLK_GATE_SDIO>,
+                               <&crg_ctrl HI3670_HCLK_GATE_SDIO>;
+                       clock-names = "ciu", "biu";
+                       clock-frequency = <3200000>;
+                       resets = <&crg_rst 0x94 20>;
+                       reset-names = "reset";
+                       card-detect-delay = <200>;
+                       status = "disabled";
+               };
        };
 };

diff --git a/arch/arm64/boot/dts/hisilicon/hikey970-pinctrl.dtsi b/arch/arm64/boot/dts/hisilicon/hikey970-pinctrl.dtsi
index 67bb52d..d456b0a 100644 (file)
--- a/arch/arm64/boot/dts/hisilicon/hikey970-pinctrl.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hikey970-pinctrl.dtsi
@@ -196,6 +196,16 @@
                        /* pin base, nr pins & gpio function */
                        pinctrl-single,gpio-range = <&range 0 10 0>;
 
+                       sdio_pmx_func: sdio_pmx_func {
+                               pinctrl-single,pins = <
+                                       0x000 MUX_M1 /* SDIO_CLK */
+                                       0x004 MUX_M1 /* SDIO_CMD */
+                                       0x008 MUX_M1 /* SDIO_DATA0 */
+                                       0x00c MUX_M1 /* SDIO_DATA1 */
+                                       0x010 MUX_M1 /* SDIO_DATA2 */
+                                       0x014 MUX_M1 /* SDIO_DATA3 */
+                               >;
+                       };
                };
 
                pmx6: pinmux@fc182800 {
@@ -203,6 +213,52 @@
                        reg = <0x0 0xfc182800 0x0 0x028>;
                        #pinctrl-cells = <1>;
                        pinctrl-single,register-width = <0x20>;
+
+                       sdio_clk_cfg_func: sdio_clk_cfg_func {
+                               pinctrl-single,pins = <
+                                       0x000 0x0 /* SDIO_CLK */
+                               >;
+                               pinctrl-single,bias-pulldown = <
+                                       PULL_DIS
+                                       PULL_DOWN
+                                       PULL_DIS
+                                       PULL_DOWN
+                               >;
+                               pinctrl-single,bias-pullup = <
+                                       PULL_DIS
+                                       PULL_UP
+                                       PULL_DIS
+                                       PULL_UP
+                               >;
+                               pinctrl-single,drive-strength = <
+                                       DRIVE6_32MA DRIVE6_MASK
+                               >;
+                       };
+
+                       sdio_cfg_func: sdio_cfg_func {
+                               pinctrl-single,pins = <
+                                       0x004 0x0 /* SDIO_CMD */
+                                       0x008 0x0 /* SDIO_DATA0 */
+                                       0x00c 0x0 /* SDIO_DATA1 */
+                                       0x010 0x0 /* SDIO_DATA2 */
+                                       0x014 0x0 /* SDIO_DATA3 */
+                               >;
+                               pinctrl-single,bias-pulldown = <
+                                       PULL_DIS
+                                       PULL_DOWN
+                                       PULL_DIS
+                                       PULL_DOWN
+                               >;
+                               pinctrl-single,bias-pullup = <
+                                       PULL_UP
+                                       PULL_UP
+                                       PULL_DIS
+                                       PULL_UP
+                               >;
+                               pinctrl-single,drive-strength = <
+                                       DRIVE6_19MA DRIVE6_MASK
+                               >;
+                       };
                };
 
                pmx7: pinmux@ff37e000 {
@@ -214,6 +270,17 @@
                        pinctrl-single,function-mask = <7>;
                        /* pin base, nr pins & gpio function */
                        pinctrl-single,gpio-range = <&range 0 12 0>;
+
+                       sd_pmx_func: sd_pmx_func {
+                               pinctrl-single,pins = <
+                                       0x000 MUX_M1 /* SD_CLK */
+                                       0x004 MUX_M1 /* SD_CMD */
+                                       0x008 MUX_M1 /* SD_DATA0 */
+                                       0x00c MUX_M1 /* SD_DATA1 */
+                                       0x010 MUX_M1 /* SD_DATA2 */
+                                       0x014 MUX_M1 /* SD_DATA3 */
+                               >;
+                       };
                };
 
                pmx8: pinmux@ff37e800 {
@@ -221,6 +288,54 @@
                        reg = <0x0 0xff37e800 0x0 0x030>;
                        #pinctrl-cells = <1>;
                        pinctrl-single,register-width = <0x20>;
+
+                       sd_clk_cfg_func: sd_clk_cfg_func {
+                               pinctrl-single,pins = <
+                                       0x000 0x0 /* SD_CLK */
+                               >;
+                               pinctrl-single,bias-pulldown = <
+                                       PULL_DIS
+                                       PULL_DOWN
+                                       PULL_DIS
+                                       PULL_DOWN
+                               >;
+                               pinctrl-single,bias-pullup = <
+                                       PULL_DIS
+                                       PULL_UP
+                                       PULL_DIS
+                                       PULL_UP
+                               >;
+                               pinctrl-single,drive-strength = <
+                                       DRIVE6_32MA
+                                       DRIVE6_MASK
+                               >;
+                       };
+
+                       sd_cfg_func: sd_cfg_func {
+                               pinctrl-single,pins = <
+                                       0x004 0x0 /* SD_CMD */
+                                       0x008 0x0 /* SD_DATA0 */
+                                       0x00c 0x0 /* SD_DATA1 */
+                                       0x010 0x0 /* SD_DATA2 */
+                                       0x014 0x0 /* SD_DATA3 */
+                               >;
+                               pinctrl-single,bias-pulldown = <
+                                       PULL_DIS
+                                       PULL_DOWN
+                                       PULL_DIS
+                                       PULL_DOWN
+                               >;
+                               pinctrl-single,bias-pullup = <
+                                       PULL_UP
+                                       PULL_UP
+                                       PULL_DIS
+                                       PULL_UP
+                               >;
+                               pinctrl-single,drive-strength = <
+                                       DRIVE6_19MA
+                                       DRIVE6_MASK
+                               >;
+                       };
                };
 
                pmx1: pinmux@fff11000 {

diff --git a/arch/arm64/boot/dts/intel/Makefile b/arch/arm64/boot/dts/intel/Makefile
new file mode 100644 (file)
index 0000000..9606ac8
--- /dev/null
+++ b/arch/arm64/boot/dts/intel/Makefile
@@ -0,0 +1 @@
+dtb-$(CONFIG_ARCH_AGILEX) += socfpga_agilex_socdk.dtb

diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi
new file mode 100644 (file)
index 0000000..e4ceb3a
--- /dev/null
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi
@@ -0,0 +1,444 @@
+// SPDX-License-Identifier:     GPL-2.0
+/*
+ * Copyright (C) 2019, Intel Corporation
+ */
+
+/dts-v1/;
+#include <dt-bindings/reset/altr,rst-mgr-s10.h>
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+       compatible = "intel,socfpga-agilex";
+       #address-cells = <2>;
+       #size-cells = <2>;
+
+       cpus {
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               cpu0: cpu@0 {
+                       compatible = "arm,cortex-a53";
+                       device_type = "cpu";
+                       enable-method = "psci";
+                       reg = <0x0>;
+               };
+
+               cpu1: cpu@1 {
+                       compatible = "arm,cortex-a53";
+                       device_type = "cpu";
+                       enable-method = "psci";
+                       reg = <0x1>;
+               };
+
+               cpu2: cpu@2 {
+                       compatible = "arm,cortex-a53";
+                       device_type = "cpu";
+                       enable-method = "psci";
+                       reg = <0x2>;
+               };
+
+               cpu3: cpu@3 {
+                       compatible = "arm,cortex-a53";
+                       device_type = "cpu";
+                       enable-method = "psci";
+                       reg = <0x3>;
+               };
+       };
+
+       pmu {
+               compatible = "arm,armv8-pmuv3";
+               interrupts = <0 120 8>,
+                            <0 121 8>,
+                            <0 122 8>,
+                            <0 123 8>;
+               interrupt-affinity = <&cpu0>,
+                                    <&cpu1>,
+                                    <&cpu2>,
+                                    <&cpu3>;
+               interrupt-parent = <&intc>;
+       };
+
+       psci {
+               compatible = "arm,psci-0.2";
+               method = "smc";
+       };
+
+       intc: intc@fffc1000 {
+               compatible = "arm,gic-400", "arm,cortex-a15-gic";
+               #interrupt-cells = <3>;
+               interrupt-controller;
+               reg = <0x0 0xfffc1000 0x0 0x1000>,
+                     <0x0 0xfffc2000 0x0 0x2000>,
+                     <0x0 0xfffc4000 0x0 0x2000>,
+                     <0x0 0xfffc6000 0x0 0x2000>;
+       };
+
+       soc {
+               #address-cells = <1>;
+               #size-cells = <1>;
+               compatible = "simple-bus";
+               device_type = "soc";
+               interrupt-parent = <&intc>;
+               ranges = <0 0 0 0xffffffff>;
+
+               gmac0: ethernet@ff800000 {
+                       compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac";
+                       reg = <0xff800000 0x2000>;
+                       interrupts = <0 90 4>;
+                       interrupt-names = "macirq";
+                       mac-address = [00 00 00 00 00 00];
+                       resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>;
+                       reset-names = "stmmaceth", "stmmaceth-ocp";
+                       tx-fifo-depth = <16384>;
+                       rx-fifo-depth = <16384>;
+                       snps,multicast-filter-bins = <256>;
+                       iommus = <&smmu 1>;
+                       status = "disabled";
+               };
+
+               gmac1: ethernet@ff802000 {
+                       compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac";
+                       reg = <0xff802000 0x2000>;
+                       interrupts = <0 91 4>;
+                       interrupt-names = "macirq";
+                       mac-address = [00 00 00 00 00 00];
+                       resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>;
+                       reset-names = "stmmaceth", "stmmaceth-ocp";
+                       tx-fifo-depth = <16384>;
+                       rx-fifo-depth = <16384>;
+                       snps,multicast-filter-bins = <256>;
+                       iommus = <&smmu 2>;
+                       status = "disabled";
+               };
+
+               gmac2: ethernet@ff804000 {
+                       compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac";
+                       reg = <0xff804000 0x2000>;
+                       interrupts = <0 92 4>;
+                       interrupt-names = "macirq";
+                       mac-address = [00 00 00 00 00 00];
+                       resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>;
+                       reset-names = "stmmaceth", "stmmaceth-ocp";
+                       tx-fifo-depth = <16384>;
+                       rx-fifo-depth = <16384>;
+                       snps,multicast-filter-bins = <256>;
+                       iommus = <&smmu 3>;
+                       status = "disabled";
+               };
+
+               gpio0: gpio@ffc03200 {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       compatible = "snps,dw-apb-gpio";
+                       reg = <0xffc03200 0x100>;
+                       resets = <&rst GPIO0_RESET>;
+                       status = "disabled";
+
+                       porta: gpio-controller@0 {
+                               compatible = "snps,dw-apb-gpio-port";
+                               gpio-controller;
+                               #gpio-cells = <2>;
+                               snps,nr-gpios = <24>;
+                               reg = <0>;
+                               interrupt-controller;
+                               #interrupt-cells = <2>;
+                               interrupts = <0 110 4>;
+                       };
+               };
+
+               gpio1: gpio@ffc03300 {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       compatible = "snps,dw-apb-gpio";
+                       reg = <0xffc03300 0x100>;
+                       resets = <&rst GPIO1_RESET>;
+                       status = "disabled";
+
+                       portb: gpio-controller@0 {
+                               compatible = "snps,dw-apb-gpio-port";
+                               gpio-controller;
+                               #gpio-cells = <2>;
+                               snps,nr-gpios = <24>;
+                               reg = <0>;
+                               interrupt-controller;
+                               #interrupt-cells = <2>;
+                               interrupts = <0 111 4>;
+                       };
+               };
+
+               i2c0: i2c@ffc02800 {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       compatible = "snps,designware-i2c";
+                       reg = <0xffc02800 0x100>;
+                       interrupts = <0 103 4>;
+                       resets = <&rst I2C0_RESET>;
+                       status = "disabled";
+               };
+
+               i2c1: i2c@ffc02900 {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       compatible = "snps,designware-i2c";
+                       reg = <0xffc02900 0x100>;
+                       interrupts = <0 104 4>;
+                       resets = <&rst I2C1_RESET>;
+                       status = "disabled";
+               };
+
+               i2c2: i2c@ffc02a00 {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       compatible = "snps,designware-i2c";
+                       reg = <0xffc02a00 0x100>;
+                       interrupts = <0 105 4>;
+                       resets = <&rst I2C2_RESET>;
+                       status = "disabled";
+               };
+
+               i2c3: i2c@ffc02b00 {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       compatible = "snps,designware-i2c";
+                       reg = <0xffc02b00 0x100>;
+                       interrupts = <0 106 4>;
+                       resets = <&rst I2C3_RESET>;
+                       status = "disabled";
+               };
+
+               i2c4: i2c@ffc02c00 {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       compatible = "snps,designware-i2c";
+                       reg = <0xffc02c00 0x100>;
+                       interrupts = <0 107 4>;
+                       resets = <&rst I2C4_RESET>;
+                       status = "disabled";
+               };
+
+               mmc: dwmmc0@ff808000 {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       compatible = "altr,socfpga-dw-mshc";
+                       reg = <0xff808000 0x1000>;
+                       interrupts = <0 96 4>;
+                       fifo-depth = <0x400>;
+                       resets = <&rst SDMMC_RESET>;
+                       reset-names = "reset";
+                       iommus = <&smmu 5>;
+                       status = "disabled";
+               };
+
+               ocram: sram@ffe00000 {
+                       compatible = "mmio-sram";
+                       reg = <0xffe00000 0x40000>;
+               };
+
+               pdma: pdma@ffda0000 {
+                       compatible = "arm,pl330", "arm,primecell";
+                       reg = <0xffda0000 0x1000>;
+                       interrupts = <0 81 4>,
+                                    <0 82 4>,
+                                    <0 83 4>,
+                                    <0 84 4>,
+                                    <0 85 4>,
+                                    <0 86 4>,
+                                    <0 87 4>,
+                                    <0 88 4>,
+                                    <0 89 4>;
+                       #dma-cells = <1>;
+                       #dma-channels = <8>;
+                       #dma-requests = <32>;
+               };
+
+               rst: rstmgr@ffd11000 {
+                       #reset-cells = <1>;
+                       compatible = "altr,stratix10-rst-mgr";
+                       reg = <0xffd11000 0x100>;
+               };
+
+               smmu: iommu@fa000000 {
+                       compatible = "arm,mmu-500", "arm,smmu-v2";
+                       reg = <0xfa000000 0x40000>;
+                       #global-interrupts = <2>;
+                       #iommu-cells = <1>;
+                       interrupt-parent = <&intc>;
+                       interrupts = <0 128 4>, /* Global Secure Fault */
+                               <0 129 4>, /* Global Non-secure Fault */
+                               /* Non-secure Context Interrupts (32) */
+                               <0 138 4>, <0 139 4>, <0 140 4>, <0 141 4>,
+                               <0 142 4>, <0 143 4>, <0 144 4>, <0 145 4>,
+                               <0 146 4>, <0 147 4>, <0 148 4>, <0 149 4>,
+                               <0 150 4>, <0 151 4>, <0 152 4>, <0 153 4>,
+                               <0 154 4>, <0 155 4>, <0 156 4>, <0 157 4>,
+                               <0 158 4>, <0 159 4>, <0 160 4>, <0 161 4>,
+                               <0 162 4>, <0 163 4>, <0 164 4>, <0 165 4>,
+                               <0 166 4>, <0 167 4>, <0 168 4>, <0 169 4>;
+                       stream-match-mask = <0x7ff0>;
+                       status = "disabled";
+               };
+
+               spi0: spi@ffda4000 {
+                       compatible = "snps,dw-apb-ssi";
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       reg = <0xffda4000 0x1000>;
+                       interrupts = <0 99 4>;
+                       resets = <&rst SPIM0_RESET>;
+                       reg-io-width = <4>;
+                       num-cs = <4>;
+                       status = "disabled";
+               };
+
+               spi1: spi@ffda5000 {
+                       compatible = "snps,dw-apb-ssi";
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       reg = <0xffda5000 0x1000>;
+                       interrupts = <0 100 4>;
+                       resets = <&rst SPIM1_RESET>;
+                       reg-io-width = <4>;
+                       num-cs = <4>;
+                       status = "disabled";
+               };
+
+               sysmgr: sysmgr@ffd12000 {
+                       compatible = "altr,sys-mgr", "syscon";
+                       reg = <0xffd12000 0x500>;
+               };
+
+               /* Local timer */
+               timer {
+                       compatible = "arm,armv8-timer";
+                       interrupts = <1 13 0xf08>,
+                                    <1 14 0xf08>,
+                                    <1 11 0xf08>,
+                                    <1 10 0xf08>;
+               };
+
+               timer0: timer0@ffc03000 {
+                       compatible = "snps,dw-apb-timer";
+                       interrupts = <0 113 4>;
+                       reg = <0xffc03000 0x100>;
+               };
+
+               timer1: timer1@ffc03100 {
+                       compatible = "snps,dw-apb-timer";
+                       interrupts = <0 114 4>;
+                       reg = <0xffc03100 0x100>;
+               };
+
+               timer2: timer2@ffd00000 {
+                       compatible = "snps,dw-apb-timer";
+                       interrupts = <0 115 4>;
+                       reg = <0xffd00000 0x100>;
+               };
+
+               timer3: timer3@ffd00100 {
+                       compatible = "snps,dw-apb-timer";
+                       interrupts = <0 116 4>;
+                       reg = <0xffd00100 0x100>;
+               };
+
+               uart0: serial0@ffc02000 {
+                       compatible = "snps,dw-apb-uart";
+                       reg = <0xffc02000 0x100>;
+                       interrupts = <0 108 4>;
+                       reg-shift = <2>;
+                       reg-io-width = <4>;
+                       resets = <&rst UART0_RESET>;
+                       status = "disabled";
+               };
+
+               uart1: serial1@ffc02100 {
+                       compatible = "snps,dw-apb-uart";
+                       reg = <0xffc02100 0x100>;
+                       interrupts = <0 109 4>;
+                       reg-shift = <2>;
+                       reg-io-width = <4>;
+                       resets = <&rst UART1_RESET>;
+                       status = "disabled";
+               };
+
+               usbphy0: usbphy@0 {
+                       #phy-cells = <0>;
+                       compatible = "usb-nop-xceiv";
+                       status = "okay";
+               };
+
+               usb0: usb@ffb00000 {
+                       compatible = "snps,dwc2";
+                       reg = <0xffb00000 0x40000>;
+                       interrupts = <0 93 4>;
+                       phys = <&usbphy0>;
+                       phy-names = "usb2-phy";
+                       resets = <&rst USB0_RESET>, <&rst USB0_OCP_RESET>;
+                       reset-names = "dwc2", "dwc2-ecc";
+                       iommus = <&smmu 6>;
+                       status = "disabled";
+               };
+
+               usb1: usb@ffb40000 {
+                       compatible = "snps,dwc2";
+                       reg = <0xffb40000 0x40000>;
+                       interrupts = <0 94 4>;
+                       phys = <&usbphy0>;
+                       phy-names = "usb2-phy";
+                       resets = <&rst USB1_RESET>, <&rst USB1_OCP_RESET>;
+                       reset-names = "dwc2", "dwc2-ecc";
+                       iommus = <&smmu 7>;
+                       status = "disabled";
+               };
+
+               watchdog0: watchdog@ffd00200 {
+                       compatible = "snps,dw-wdt";
+                       reg = <0xffd00200 0x100>;
+                       interrupts = <0 117 4>;
+                       resets = <&rst WATCHDOG0_RESET>;
+                       status = "disabled";
+               };
+
+               watchdog1: watchdog@ffd00300 {
+                       compatible = "snps,dw-wdt";
+                       reg = <0xffd00300 0x100>;
+                       interrupts = <0 118 4>;
+                       resets = <&rst WATCHDOG1_RESET>;
+                       status = "disabled";
+               };
+
+               watchdog2: watchdog@ffd00400 {
+                       compatible = "snps,dw-wdt";
+                       reg = <0xffd00400 0x100>;
+                       interrupts = <0 125 4>;
+                       resets = <&rst WATCHDOG2_RESET>;
+                       status = "disabled";
+               };
+
+               watchdog3: watchdog@ffd00500 {
+                       compatible = "snps,dw-wdt";
+                       reg = <0xffd00500 0x100>;
+                       interrupts = <0 126 4>;
+                       resets = <&rst WATCHDOG3_RESET>;
+                       status = "disabled";
+               };
+
+               sdr: sdr@f8011100 {
+                       compatible = "altr,sdr-ctl", "syscon";
+                       reg = <0xf8011100 0xc0>;
+               };
+
+               qspi: spi@ff8d2000 {
+                       compatible = "cdns,qspi-nor";
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       reg = <0xff8d2000 0x100>,
+                             <0xff900000 0x100000>;
+                       interrupts = <0 3 4>;
+                       cdns,fifo-depth = <128>;
+                       cdns,fifo-width = <4>;
+                       cdns,trigger-address = <0x00000000>;
+
+                       status = "disabled";
+               };
+       };
+};

diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts b/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts
new file mode 100644 (file)
index 0000000..7814a9e
--- /dev/null
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts
@@ -0,0 +1,75 @@
+// SPDX-License-Identifier:     GPL-2.0
+/*
+ * Copyright (C) 2019, Intel Corporation
+ */
+#include "socfpga_agilex.dtsi"
+
+/ {
+       model = "SoCFPGA Agilex SoCDK";
+
+       aliases {
+               serial0 = &uart0;
+               ethernet0 = &gmac0;
+               ethernet1 = &gmac1;
+               ethernet2 = &gmac2;
+       };
+
+       chosen {
+               stdout-path = "serial0:115200n8";
+       };
+
+       memory {
+               device_type = "memory";
+               /* We expect the bootloader to fill in the reg */
+               reg = <0 0 0 0>;
+       };
+};
+
+&gpio1 {
+       status = "okay";
+};
+
+&gmac0 {
+       status = "okay";
+       phy-mode = "rgmii";
+       phy-handle = <&phy0>;
+
+       max-frame-size = <9000>;
+
+       mdio0 {
+               #address-cells = <1>;
+               #size-cells = <0>;
+               compatible = "snps,dwmac-mdio";
+               phy0: ethernet-phy@0 {
+                       reg = <4>;
+
+                       txd0-skew-ps = <0>; /* -420ps */
+                       txd1-skew-ps = <0>; /* -420ps */
+                       txd2-skew-ps = <0>; /* -420ps */
+                       txd3-skew-ps = <0>; /* -420ps */
+                       rxd0-skew-ps = <420>; /* 0ps */
+                       rxd1-skew-ps = <420>; /* 0ps */
+                       rxd2-skew-ps = <420>; /* 0ps */
+                       rxd3-skew-ps = <420>; /* 0ps */
+                       txen-skew-ps = <0>; /* -420ps */
+                       txc-skew-ps = <900>; /* 0ps */
+                       rxdv-skew-ps = <420>; /* 0ps */
+                       rxc-skew-ps = <1680>; /* 780ps */
+               };
+       };
+};
+
+&mmc {
+       status = "okay";
+       cap-sd-highspeed;
+       broken-cd;
+       bus-width = <4>;
+};
+
+&uart0 {
+       status = "okay";
+};
+
+&watchdog0 {
+       status = "okay";
+};

diff --git a/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts b/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts
index 2468762..9143aa1 100644 (file)
--- a/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts
+++ b/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts
@@ -226,6 +226,11 @@
                marvell,function = "gpio";
        };
 
+       cp0_wlan_disable_pins: wlan-disable-pins {
+               marvell,pins = "mpp51";
+               marvell,function = "gpio";
+       };
+
        cp0_sdhci_pins: sdhci-pins {
                marvell,pins = "mpp55", "mpp56", "mpp57", "mpp58", "mpp59",
                               "mpp60", "mpp61";
@@ -235,7 +240,7 @@
 
 &cp0_pcie0 {
        pinctrl-names = "default";
-       pinctrl-0 = <&cp0_pci0_reset_pins>;
+       pinctrl-0 = <&cp0_pci0_reset_pins &cp0_wlan_disable_pins>;
        reset-gpios = <&cp0_gpio2 0 GPIO_ACTIVE_LOW>;
        status = "okay";
 };
@@ -253,6 +258,12 @@
                output-low;
        };
 
+       wlan_disable {
+               gpio-hog;
+               gpios = <19 GPIO_ACTIVE_LOW>;
+               output-low;
+       };
+
        lte_disable {
                gpio-hog;
                gpios = <21 GPIO_ACTIVE_LOW>;

diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
index c3c3601..15f1842 100644 (file)
--- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
@@ -178,12 +178,12 @@
 
                cpu2: cpu@100 {
                        device_type = "cpu";
-                       compatible = "arm,cortex-a57";
+                       compatible = "arm,cortex-a72";
                        reg = <0x100>;
                        enable-method = "psci";
                        cpu-idle-states = <&CPU_SLEEP_0>;
                        #cooling-cells = <2>;
-                       clocks = <&infracfg CLK_INFRA_CA57SEL>,
+                       clocks = <&infracfg CLK_INFRA_CA72SEL>,
                                 <&apmixedsys CLK_APMIXED_MAINPLL>;
                        clock-names = "cpu", "intermediate";
                        operating-points-v2 = <&cluster1_opp>;
@@ -191,12 +191,12 @@
 
                cpu3: cpu@101 {
                        device_type = "cpu";
-                       compatible = "arm,cortex-a57";
+                       compatible = "arm,cortex-a72";
                        reg = <0x101>;
                        enable-method = "psci";
                        cpu-idle-states = <&CPU_SLEEP_0>;
                        #cooling-cells = <2>;
-                       clocks = <&infracfg CLK_INFRA_CA57SEL>,
+                       clocks = <&infracfg CLK_INFRA_CA72SEL>,
                                 <&apmixedsys CLK_APMIXED_MAINPLL>;
                        clock-names = "cpu", "intermediate";
                        operating-points-v2 = <&cluster1_opp>;
@@ -216,6 +216,20 @@
                };
        };
 
+       pmu_a53 {
+               compatible = "arm,cortex-a53-pmu";
+               interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_LOW>,
+                            <GIC_SPI 9 IRQ_TYPE_LEVEL_LOW>;
+               interrupt-affinity = <&cpu0>, <&cpu1>;
+       };
+
+       pmu_a72 {
+               compatible = "arm,cortex-a72-pmu";
+               interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_LOW>,
+                            <GIC_SPI 13 IRQ_TYPE_LEVEL_LOW>;
+               interrupt-affinity = <&cpu2>, <&cpu3>;
+       };
+
        psci {
                compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci";
                method = "smc";
@@ -1307,6 +1321,15 @@
                                      "vencpll",
                                      "venc_lt_sel",
                                      "vdec_bus_clk_src";
+                       assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>,
+                                         <&topckgen CLK_TOP_CCI400_SEL>,
+                                         <&topckgen CLK_TOP_VDEC_SEL>,
+                                         <&apmixedsys CLK_APMIXED_VCODECPLL>,
+                                         <&apmixedsys CLK_APMIXED_VENCPLL>;
+                       assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL_370P5>,
+                                                <&topckgen CLK_TOP_UNIVPLL_D2>,
+                                                <&topckgen CLK_TOP_VCODECPLL>;
+                       assigned-clock-rates = <0>, <0>, <0>, <1482000000>, <800000000>;
                };
 
                larb1: larb@16010000 {
@@ -1372,6 +1395,10 @@
                                      "venc_sel",
                                      "venc_lt_sel_src",
                                      "venc_lt_sel";
+                       assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>,
+                                         <&topckgen CLK_TOP_VENC_LT_SEL>;
+                       assigned-clock-parents = <&topckgen CLK_TOP_VENCPLL_D2>,
+                                                <&topckgen CLK_TOP_UNIVPLL1_D2>;
                };
 
                vencltsys: clock-controller@19000000 {

diff --git a/arch/arm64/boot/dts/mediatek/mt8183-pinfunc.h b/arch/arm64/boot/dts/mediatek/mt8183-pinfunc.h
new file mode 100644 (file)
index 0000000..6221cd7
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt8183-pinfunc.h
@@ -0,0 +1,1120 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2018 MediaTek Inc.
+ * Author: Zhiyong Tao <zhiyong.tao@mediatek.com>
+ *
+ */
+
+#ifndef __MT8183_PINFUNC_H
+#define __MT8183_PINFUNC_H
+
+#include <dt-bindings/pinctrl/mt65xx.h>
+
+#define PINMUX_GPIO0__FUNC_GPIO0 (MTK_PIN_NO(0) | 0)
+#define PINMUX_GPIO0__FUNC_MRG_SYNC (MTK_PIN_NO(0) | 1)
+#define PINMUX_GPIO0__FUNC_PCM0_SYNC (MTK_PIN_NO(0) | 2)
+#define PINMUX_GPIO0__FUNC_TP_GPIO0_AO (MTK_PIN_NO(0) | 3)
+#define PINMUX_GPIO0__FUNC_SRCLKENAI0 (MTK_PIN_NO(0) | 4)
+#define PINMUX_GPIO0__FUNC_SCP_SPI2_CS (MTK_PIN_NO(0) | 5)
+#define PINMUX_GPIO0__FUNC_I2S3_MCK (MTK_PIN_NO(0) | 6)
+#define PINMUX_GPIO0__FUNC_SPI2_CSB (MTK_PIN_NO(0) | 7)
+
+#define PINMUX_GPIO1__FUNC_GPIO1 (MTK_PIN_NO(1) | 0)
+#define PINMUX_GPIO1__FUNC_MRG_CLK (MTK_PIN_NO(1) | 1)
+#define PINMUX_GPIO1__FUNC_PCM0_CLK (MTK_PIN_NO(1) | 2)
+#define PINMUX_GPIO1__FUNC_TP_GPIO1_AO (MTK_PIN_NO(1) | 3)
+#define PINMUX_GPIO1__FUNC_CLKM3 (MTK_PIN_NO(1) | 4)
+#define PINMUX_GPIO1__FUNC_SCP_SPI2_MO (MTK_PIN_NO(1) | 5)
+#define PINMUX_GPIO1__FUNC_I2S3_BCK (MTK_PIN_NO(1) | 6)
+#define PINMUX_GPIO1__FUNC_SPI2_MO (MTK_PIN_NO(1) | 7)
+
+#define PINMUX_GPIO2__FUNC_GPIO2 (MTK_PIN_NO(2) | 0)
+#define PINMUX_GPIO2__FUNC_MRG_DO (MTK_PIN_NO(2) | 1)
+#define PINMUX_GPIO2__FUNC_PCM0_DO (MTK_PIN_NO(2) | 2)
+#define PINMUX_GPIO2__FUNC_TP_GPIO2_AO (MTK_PIN_NO(2) | 3)
+#define PINMUX_GPIO2__FUNC_SCL6 (MTK_PIN_NO(2) | 4)
+#define PINMUX_GPIO2__FUNC_SCP_SPI2_CK (MTK_PIN_NO(2) | 5)
+#define PINMUX_GPIO2__FUNC_I2S3_LRCK (MTK_PIN_NO(2) | 6)
+#define PINMUX_GPIO2__FUNC_SPI2_CLK (MTK_PIN_NO(2) | 7)
+
+#define PINMUX_GPIO3__FUNC_GPIO3 (MTK_PIN_NO(3) | 0)
+#define PINMUX_GPIO3__FUNC_MRG_DI (MTK_PIN_NO(3) | 1)
+#define PINMUX_GPIO3__FUNC_PCM0_DI (MTK_PIN_NO(3) | 2)
+#define PINMUX_GPIO3__FUNC_TP_GPIO3_AO (MTK_PIN_NO(3) | 3)
+#define PINMUX_GPIO3__FUNC_SDA6 (MTK_PIN_NO(3) | 4)
+#define PINMUX_GPIO3__FUNC_TDM_MCK (MTK_PIN_NO(3) | 5)
+#define PINMUX_GPIO3__FUNC_I2S3_DO (MTK_PIN_NO(3) | 6)
+#define PINMUX_GPIO3__FUNC_SCP_VREQ_VAO (MTK_PIN_NO(3) | 7)
+
+#define PINMUX_GPIO4__FUNC_GPIO4 (MTK_PIN_NO(4) | 0)
+#define PINMUX_GPIO4__FUNC_PWM_B (MTK_PIN_NO(4) | 1)
+#define PINMUX_GPIO4__FUNC_I2S0_MCK (MTK_PIN_NO(4) | 2)
+#define PINMUX_GPIO4__FUNC_SSPM_UTXD_AO (MTK_PIN_NO(4) | 3)
+#define PINMUX_GPIO4__FUNC_MD_URXD1 (MTK_PIN_NO(4) | 4)
+#define PINMUX_GPIO4__FUNC_TDM_BCK (MTK_PIN_NO(4) | 5)
+#define PINMUX_GPIO4__FUNC_TP_GPIO4_AO (MTK_PIN_NO(4) | 6)
+#define PINMUX_GPIO4__FUNC_DAP_MD32_SWD (MTK_PIN_NO(4) | 7)
+
+#define PINMUX_GPIO5__FUNC_GPIO5 (MTK_PIN_NO(5) | 0)
+#define PINMUX_GPIO5__FUNC_PWM_C (MTK_PIN_NO(5) | 1)
+#define PINMUX_GPIO5__FUNC_I2S0_BCK (MTK_PIN_NO(5) | 2)
+#define PINMUX_GPIO5__FUNC_SSPM_URXD_AO (MTK_PIN_NO(5) | 3)
+#define PINMUX_GPIO5__FUNC_MD_UTXD1 (MTK_PIN_NO(5) | 4)
+#define PINMUX_GPIO5__FUNC_TDM_LRCK (MTK_PIN_NO(5) | 5)
+#define PINMUX_GPIO5__FUNC_TP_GPIO5_AO (MTK_PIN_NO(5) | 6)
+#define PINMUX_GPIO5__FUNC_DAP_MD32_SWCK (MTK_PIN_NO(5) | 7)
+
+#define PINMUX_GPIO6__FUNC_GPIO6 (MTK_PIN_NO(6) | 0)
+#define PINMUX_GPIO6__FUNC_PWM_A (MTK_PIN_NO(6) | 1)
+#define PINMUX_GPIO6__FUNC_I2S0_LRCK (MTK_PIN_NO(6) | 2)
+#define PINMUX_GPIO6__FUNC_IDDIG (MTK_PIN_NO(6) | 3)
+#define PINMUX_GPIO6__FUNC_MD_URXD0 (MTK_PIN_NO(6) | 4)
+#define PINMUX_GPIO6__FUNC_TDM_DATA0 (MTK_PIN_NO(6) | 5)
+#define PINMUX_GPIO6__FUNC_TP_GPIO6_AO (MTK_PIN_NO(6) | 6)
+#define PINMUX_GPIO6__FUNC_CMFLASH (MTK_PIN_NO(6) | 7)
+
+#define PINMUX_GPIO7__FUNC_GPIO7 (MTK_PIN_NO(7) | 0)
+#define PINMUX_GPIO7__FUNC_SPI1_B_MI (MTK_PIN_NO(7) | 1)
+#define PINMUX_GPIO7__FUNC_I2S0_DI (MTK_PIN_NO(7) | 2)
+#define PINMUX_GPIO7__FUNC_USB_DRVVBUS (MTK_PIN_NO(7) | 3)
+#define PINMUX_GPIO7__FUNC_MD_UTXD0 (MTK_PIN_NO(7) | 4)
+#define PINMUX_GPIO7__FUNC_TDM_DATA1 (MTK_PIN_NO(7) | 5)
+#define PINMUX_GPIO7__FUNC_TP_GPIO7_AO (MTK_PIN_NO(7) | 6)
+#define PINMUX_GPIO7__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(7) | 7)
+
+#define PINMUX_GPIO8__FUNC_GPIO8 (MTK_PIN_NO(8) | 0)
+#define PINMUX_GPIO8__FUNC_SPI1_B_CSB (MTK_PIN_NO(8) | 1)
+#define PINMUX_GPIO8__FUNC_ANT_SEL3 (MTK_PIN_NO(8) | 2)
+#define PINMUX_GPIO8__FUNC_SCL7 (MTK_PIN_NO(8) | 3)
+#define PINMUX_GPIO8__FUNC_CONN_MCU_TRST_B (MTK_PIN_NO(8) | 4)
+#define PINMUX_GPIO8__FUNC_TDM_DATA2 (MTK_PIN_NO(8) | 5)
+#define PINMUX_GPIO8__FUNC_MD_INT0 (MTK_PIN_NO(8) | 6)
+#define PINMUX_GPIO8__FUNC_JTRSTN_SEL1 (MTK_PIN_NO(8) | 7)
+
+#define PINMUX_GPIO9__FUNC_GPIO9 (MTK_PIN_NO(9) | 0)
+#define PINMUX_GPIO9__FUNC_SPI1_B_MO (MTK_PIN_NO(9) | 1)
+#define PINMUX_GPIO9__FUNC_ANT_SEL4 (MTK_PIN_NO(9) | 2)
+#define PINMUX_GPIO9__FUNC_CMMCLK2 (MTK_PIN_NO(9) | 3)
+#define PINMUX_GPIO9__FUNC_CONN_MCU_DBGACK_N (MTK_PIN_NO(9) | 4)
+#define PINMUX_GPIO9__FUNC_SSPM_JTAG_TRSTN (MTK_PIN_NO(9) | 5)
+#define PINMUX_GPIO9__FUNC_IO_JTAG_TRSTN (MTK_PIN_NO(9) | 6)
+#define PINMUX_GPIO9__FUNC_DBG_MON_B10 (MTK_PIN_NO(9) | 7)
+
+#define PINMUX_GPIO10__FUNC_GPIO10 (MTK_PIN_NO(10) | 0)
+#define PINMUX_GPIO10__FUNC_SPI1_B_CLK (MTK_PIN_NO(10) | 1)
+#define PINMUX_GPIO10__FUNC_ANT_SEL5 (MTK_PIN_NO(10) | 2)
+#define PINMUX_GPIO10__FUNC_CMMCLK3 (MTK_PIN_NO(10) | 3)
+#define PINMUX_GPIO10__FUNC_CONN_MCU_DBGI_N (MTK_PIN_NO(10) | 4)
+#define PINMUX_GPIO10__FUNC_TDM_DATA3 (MTK_PIN_NO(10) | 5)
+#define PINMUX_GPIO10__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(10) | 6)
+#define PINMUX_GPIO10__FUNC_DBG_MON_B11 (MTK_PIN_NO(10) | 7)
+
+#define PINMUX_GPIO11__FUNC_GPIO11 (MTK_PIN_NO(11) | 0)
+#define PINMUX_GPIO11__FUNC_TP_URXD1_AO (MTK_PIN_NO(11) | 1)
+#define PINMUX_GPIO11__FUNC_IDDIG (MTK_PIN_NO(11) | 2)
+#define PINMUX_GPIO11__FUNC_SCL6 (MTK_PIN_NO(11) | 3)
+#define PINMUX_GPIO11__FUNC_UCTS1 (MTK_PIN_NO(11) | 4)
+#define PINMUX_GPIO11__FUNC_UCTS0 (MTK_PIN_NO(11) | 5)
+#define PINMUX_GPIO11__FUNC_SRCLKENAI1 (MTK_PIN_NO(11) | 6)
+#define PINMUX_GPIO11__FUNC_I2S5_MCK (MTK_PIN_NO(11) | 7)
+
+#define PINMUX_GPIO12__FUNC_GPIO12 (MTK_PIN_NO(12) | 0)
+#define PINMUX_GPIO12__FUNC_TP_UTXD1_AO (MTK_PIN_NO(12) | 1)
+#define PINMUX_GPIO12__FUNC_USB_DRVVBUS (MTK_PIN_NO(12) | 2)
+#define PINMUX_GPIO12__FUNC_SDA6 (MTK_PIN_NO(12) | 3)
+#define PINMUX_GPIO12__FUNC_URTS1 (MTK_PIN_NO(12) | 4)
+#define PINMUX_GPIO12__FUNC_URTS0 (MTK_PIN_NO(12) | 5)
+#define PINMUX_GPIO12__FUNC_I2S2_DI2 (MTK_PIN_NO(12) | 6)
+#define PINMUX_GPIO12__FUNC_I2S5_BCK (MTK_PIN_NO(12) | 7)
+
+#define PINMUX_GPIO13__FUNC_GPIO13 (MTK_PIN_NO(13) | 0)
+#define PINMUX_GPIO13__FUNC_DBPI_D0 (MTK_PIN_NO(13) | 1)
+#define PINMUX_GPIO13__FUNC_SPI5_MI (MTK_PIN_NO(13) | 2)
+#define PINMUX_GPIO13__FUNC_PCM0_SYNC (MTK_PIN_NO(13) | 3)
+#define PINMUX_GPIO13__FUNC_MD_URXD0 (MTK_PIN_NO(13) | 4)
+#define PINMUX_GPIO13__FUNC_ANT_SEL3 (MTK_PIN_NO(13) | 5)
+#define PINMUX_GPIO13__FUNC_I2S0_MCK (MTK_PIN_NO(13) | 6)
+#define PINMUX_GPIO13__FUNC_DBG_MON_B15 (MTK_PIN_NO(13) | 7)
+
+#define PINMUX_GPIO14__FUNC_GPIO14 (MTK_PIN_NO(14) | 0)
+#define PINMUX_GPIO14__FUNC_DBPI_D1 (MTK_PIN_NO(14) | 1)
+#define PINMUX_GPIO14__FUNC_SPI5_CSB (MTK_PIN_NO(14) | 2)
+#define PINMUX_GPIO14__FUNC_PCM0_CLK (MTK_PIN_NO(14) | 3)
+#define PINMUX_GPIO14__FUNC_MD_UTXD0 (MTK_PIN_NO(14) | 4)
+#define PINMUX_GPIO14__FUNC_ANT_SEL4 (MTK_PIN_NO(14) | 5)
+#define PINMUX_GPIO14__FUNC_I2S0_BCK (MTK_PIN_NO(14) | 6)
+#define PINMUX_GPIO14__FUNC_DBG_MON_B16 (MTK_PIN_NO(14) | 7)
+
+#define PINMUX_GPIO15__FUNC_GPIO15 (MTK_PIN_NO(15) | 0)
+#define PINMUX_GPIO15__FUNC_DBPI_D2 (MTK_PIN_NO(15) | 1)
+#define PINMUX_GPIO15__FUNC_SPI5_MO (MTK_PIN_NO(15) | 2)
+#define PINMUX_GPIO15__FUNC_PCM0_DO (MTK_PIN_NO(15) | 3)
+#define PINMUX_GPIO15__FUNC_MD_URXD1 (MTK_PIN_NO(15) | 4)
+#define PINMUX_GPIO15__FUNC_ANT_SEL5 (MTK_PIN_NO(15) | 5)
+#define PINMUX_GPIO15__FUNC_I2S0_LRCK (MTK_PIN_NO(15) | 6)
+#define PINMUX_GPIO15__FUNC_DBG_MON_B17 (MTK_PIN_NO(15) | 7)
+
+#define PINMUX_GPIO16__FUNC_GPIO16 (MTK_PIN_NO(16) | 0)
+#define PINMUX_GPIO16__FUNC_DBPI_D3 (MTK_PIN_NO(16) | 1)
+#define PINMUX_GPIO16__FUNC_SPI5_CLK (MTK_PIN_NO(16) | 2)
+#define PINMUX_GPIO16__FUNC_PCM0_DI (MTK_PIN_NO(16) | 3)
+#define PINMUX_GPIO16__FUNC_MD_UTXD1 (MTK_PIN_NO(16) | 4)
+#define PINMUX_GPIO16__FUNC_ANT_SEL6 (MTK_PIN_NO(16) | 5)
+#define PINMUX_GPIO16__FUNC_I2S0_DI (MTK_PIN_NO(16) | 6)
+#define PINMUX_GPIO16__FUNC_DBG_MON_B23 (MTK_PIN_NO(16) | 7)
+
+#define PINMUX_GPIO17__FUNC_GPIO17 (MTK_PIN_NO(17) | 0)
+#define PINMUX_GPIO17__FUNC_DBPI_D4 (MTK_PIN_NO(17) | 1)
+#define PINMUX_GPIO17__FUNC_SPI4_MI (MTK_PIN_NO(17) | 2)
+#define PINMUX_GPIO17__FUNC_CONN_MCU_TRST_B (MTK_PIN_NO(17) | 3)
+#define PINMUX_GPIO17__FUNC_MD_INT0 (MTK_PIN_NO(17) | 4)
+#define PINMUX_GPIO17__FUNC_ANT_SEL7 (MTK_PIN_NO(17) | 5)
+#define PINMUX_GPIO17__FUNC_I2S3_MCK (MTK_PIN_NO(17) | 6)
+#define PINMUX_GPIO17__FUNC_DBG_MON_A1 (MTK_PIN_NO(17) | 7)
+
+#define PINMUX_GPIO18__FUNC_GPIO18 (MTK_PIN_NO(18) | 0)
+#define PINMUX_GPIO18__FUNC_DBPI_D5 (MTK_PIN_NO(18) | 1)
+#define PINMUX_GPIO18__FUNC_SPI4_CSB (MTK_PIN_NO(18) | 2)
+#define PINMUX_GPIO18__FUNC_CONN_MCU_DBGI_N (MTK_PIN_NO(18) | 3)
+#define PINMUX_GPIO18__FUNC_MD_INT0 (MTK_PIN_NO(18) | 4)
+#define PINMUX_GPIO18__FUNC_SCP_VREQ_VAO (MTK_PIN_NO(18) | 5)
+#define PINMUX_GPIO18__FUNC_I2S3_BCK (MTK_PIN_NO(18) | 6)
+#define PINMUX_GPIO18__FUNC_DBG_MON_A2 (MTK_PIN_NO(18) | 7)
+
+#define PINMUX_GPIO19__FUNC_GPIO19 (MTK_PIN_NO(19) | 0)
+#define PINMUX_GPIO19__FUNC_DBPI_D6 (MTK_PIN_NO(19) | 1)
+#define PINMUX_GPIO19__FUNC_SPI4_MO (MTK_PIN_NO(19) | 2)
+#define PINMUX_GPIO19__FUNC_CONN_MCU_TDO (MTK_PIN_NO(19) | 3)
+#define PINMUX_GPIO19__FUNC_MD_INT2_C2K_UIM1_HOT_PLUG (MTK_PIN_NO(19) | 4)
+#define PINMUX_GPIO19__FUNC_URXD1 (MTK_PIN_NO(19) | 5)
+#define PINMUX_GPIO19__FUNC_I2S3_LRCK (MTK_PIN_NO(19) | 6)
+#define PINMUX_GPIO19__FUNC_DBG_MON_A3 (MTK_PIN_NO(19) | 7)
+
+#define PINMUX_GPIO20__FUNC_GPIO20 (MTK_PIN_NO(20) | 0)
+#define PINMUX_GPIO20__FUNC_DBPI_D7 (MTK_PIN_NO(20) | 1)
+#define PINMUX_GPIO20__FUNC_SPI4_CLK (MTK_PIN_NO(20) | 2)
+#define PINMUX_GPIO20__FUNC_CONN_MCU_DBGACK_N (MTK_PIN_NO(20) | 3)
+#define PINMUX_GPIO20__FUNC_MD_INT1_C2K_UIM0_HOT_PLUG (MTK_PIN_NO(20) | 4)
+#define PINMUX_GPIO20__FUNC_UTXD1 (MTK_PIN_NO(20) | 5)
+#define PINMUX_GPIO20__FUNC_I2S3_DO (MTK_PIN_NO(20) | 6)
+#define PINMUX_GPIO20__FUNC_DBG_MON_A19 (MTK_PIN_NO(20) | 7)
+
+#define PINMUX_GPIO21__FUNC_GPIO21 (MTK_PIN_NO(21) | 0)
+#define PINMUX_GPIO21__FUNC_DBPI_D8 (MTK_PIN_NO(21) | 1)
+#define PINMUX_GPIO21__FUNC_SPI3_MI (MTK_PIN_NO(21) | 2)
+#define PINMUX_GPIO21__FUNC_CONN_MCU_TMS (MTK_PIN_NO(21) | 3)
+#define PINMUX_GPIO21__FUNC_DAP_MD32_SWD (MTK_PIN_NO(21) | 4)
+#define PINMUX_GPIO21__FUNC_CONN_MCU_AICE_TMSC (MTK_PIN_NO(21) | 5)
+#define PINMUX_GPIO21__FUNC_I2S2_MCK (MTK_PIN_NO(21) | 6)
+#define PINMUX_GPIO21__FUNC_DBG_MON_B5 (MTK_PIN_NO(21) | 7)
+
+#define PINMUX_GPIO22__FUNC_GPIO22 (MTK_PIN_NO(22) | 0)
+#define PINMUX_GPIO22__FUNC_DBPI_D9 (MTK_PIN_NO(22) | 1)
+#define PINMUX_GPIO22__FUNC_SPI3_CSB (MTK_PIN_NO(22) | 2)
+#define PINMUX_GPIO22__FUNC_CONN_MCU_TCK (MTK_PIN_NO(22) | 3)
+#define PINMUX_GPIO22__FUNC_DAP_MD32_SWCK (MTK_PIN_NO(22) | 4)
+#define PINMUX_GPIO22__FUNC_CONN_MCU_AICE_TCKC (MTK_PIN_NO(22) | 5)
+#define PINMUX_GPIO22__FUNC_I2S2_BCK (MTK_PIN_NO(22) | 6)
+#define PINMUX_GPIO22__FUNC_DBG_MON_B6 (MTK_PIN_NO(22) | 7)
+
+#define PINMUX_GPIO23__FUNC_GPIO23 (MTK_PIN_NO(23) | 0)
+#define PINMUX_GPIO23__FUNC_DBPI_D10 (MTK_PIN_NO(23) | 1)
+#define PINMUX_GPIO23__FUNC_SPI3_MO (MTK_PIN_NO(23) | 2)
+#define PINMUX_GPIO23__FUNC_CONN_MCU_TDI (MTK_PIN_NO(23) | 3)
+#define PINMUX_GPIO23__FUNC_UCTS1 (MTK_PIN_NO(23) | 4)
+#define PINMUX_GPIO23__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(23) | 5)
+#define PINMUX_GPIO23__FUNC_I2S2_LRCK (MTK_PIN_NO(23) | 6)
+#define PINMUX_GPIO23__FUNC_DBG_MON_B7 (MTK_PIN_NO(23) | 7)
+
+#define PINMUX_GPIO24__FUNC_GPIO24 (MTK_PIN_NO(24) | 0)
+#define PINMUX_GPIO24__FUNC_DBPI_D11 (MTK_PIN_NO(24) | 1)
+#define PINMUX_GPIO24__FUNC_SPI3_CLK (MTK_PIN_NO(24) | 2)
+#define PINMUX_GPIO24__FUNC_SRCLKENAI0 (MTK_PIN_NO(24) | 3)
+#define PINMUX_GPIO24__FUNC_URTS1 (MTK_PIN_NO(24) | 4)
+#define PINMUX_GPIO24__FUNC_IO_JTAG_TCK (MTK_PIN_NO(24) | 5)
+#define PINMUX_GPIO24__FUNC_I2S2_DI (MTK_PIN_NO(24) | 6)
+#define PINMUX_GPIO24__FUNC_DBG_MON_B31 (MTK_PIN_NO(24) | 7)
+
+#define PINMUX_GPIO25__FUNC_GPIO25 (MTK_PIN_NO(25) | 0)
+#define PINMUX_GPIO25__FUNC_DBPI_HSYNC (MTK_PIN_NO(25) | 1)
+#define PINMUX_GPIO25__FUNC_ANT_SEL0 (MTK_PIN_NO(25) | 2)
+#define PINMUX_GPIO25__FUNC_SCL6 (MTK_PIN_NO(25) | 3)
+#define PINMUX_GPIO25__FUNC_KPCOL2 (MTK_PIN_NO(25) | 4)
+#define PINMUX_GPIO25__FUNC_IO_JTAG_TMS (MTK_PIN_NO(25) | 5)
+#define PINMUX_GPIO25__FUNC_I2S1_MCK (MTK_PIN_NO(25) | 6)
+#define PINMUX_GPIO25__FUNC_DBG_MON_B0 (MTK_PIN_NO(25) | 7)
+
+#define PINMUX_GPIO26__FUNC_GPIO26 (MTK_PIN_NO(26) | 0)
+#define PINMUX_GPIO26__FUNC_DBPI_VSYNC (MTK_PIN_NO(26) | 1)
+#define PINMUX_GPIO26__FUNC_ANT_SEL1 (MTK_PIN_NO(26) | 2)
+#define PINMUX_GPIO26__FUNC_SDA6 (MTK_PIN_NO(26) | 3)
+#define PINMUX_GPIO26__FUNC_KPROW2 (MTK_PIN_NO(26) | 4)
+#define PINMUX_GPIO26__FUNC_IO_JTAG_TDI (MTK_PIN_NO(26) | 5)
+#define PINMUX_GPIO26__FUNC_I2S1_BCK (MTK_PIN_NO(26) | 6)
+#define PINMUX_GPIO26__FUNC_DBG_MON_B1 (MTK_PIN_NO(26) | 7)
+
+#define PINMUX_GPIO27__FUNC_GPIO27 (MTK_PIN_NO(27) | 0)
+#define PINMUX_GPIO27__FUNC_DBPI_DE (MTK_PIN_NO(27) | 1)
+#define PINMUX_GPIO27__FUNC_ANT_SEL2 (MTK_PIN_NO(27) | 2)
+#define PINMUX_GPIO27__FUNC_SCL7 (MTK_PIN_NO(27) | 3)
+#define PINMUX_GPIO27__FUNC_DMIC_CLK (MTK_PIN_NO(27) | 4)
+#define PINMUX_GPIO27__FUNC_IO_JTAG_TDO (MTK_PIN_NO(27) | 5)
+#define PINMUX_GPIO27__FUNC_I2S1_LRCK (MTK_PIN_NO(27) | 6)
+#define PINMUX_GPIO27__FUNC_DBG_MON_B9 (MTK_PIN_NO(27) | 7)
+
+#define PINMUX_GPIO28__FUNC_GPIO28 (MTK_PIN_NO(28) | 0)
+#define PINMUX_GPIO28__FUNC_DBPI_CK (MTK_PIN_NO(28) | 1)
+#define PINMUX_GPIO28__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(28) | 2)
+#define PINMUX_GPIO28__FUNC_SDA7 (MTK_PIN_NO(28) | 3)
+#define PINMUX_GPIO28__FUNC_DMIC_DAT (MTK_PIN_NO(28) | 4)
+#define PINMUX_GPIO28__FUNC_IO_JTAG_TRSTN (MTK_PIN_NO(28) | 5)
+#define PINMUX_GPIO28__FUNC_I2S1_DO (MTK_PIN_NO(28) | 6)
+#define PINMUX_GPIO28__FUNC_DBG_MON_B32 (MTK_PIN_NO(28) | 7)
+
+#define PINMUX_GPIO29__FUNC_GPIO29 (MTK_PIN_NO(29) | 0)
+#define PINMUX_GPIO29__FUNC_MSDC1_CLK (MTK_PIN_NO(29) | 1)
+#define PINMUX_GPIO29__FUNC_IO_JTAG_TCK (MTK_PIN_NO(29) | 2)
+#define PINMUX_GPIO29__FUNC_UDI_TCK (MTK_PIN_NO(29) | 3)
+#define PINMUX_GPIO29__FUNC_CONN_DSP_JCK (MTK_PIN_NO(29) | 4)
+#define PINMUX_GPIO29__FUNC_SSPM_JTAG_TCK (MTK_PIN_NO(29) | 5)
+#define PINMUX_GPIO29__FUNC_PCM1_CLK (MTK_PIN_NO(29) | 6)
+#define PINMUX_GPIO29__FUNC_DBG_MON_A6 (MTK_PIN_NO(29) | 7)
+
+#define PINMUX_GPIO30__FUNC_GPIO30 (MTK_PIN_NO(30) | 0)
+#define PINMUX_GPIO30__FUNC_MSDC1_DAT3 (MTK_PIN_NO(30) | 1)
+#define PINMUX_GPIO30__FUNC_DAP_MD32_SWD (MTK_PIN_NO(30) | 2)
+#define PINMUX_GPIO30__FUNC_CONN_MCU_AICE_TMSC (MTK_PIN_NO(30) | 3)
+#define PINMUX_GPIO30__FUNC_CONN_DSP_JINTP (MTK_PIN_NO(30) | 4)
+#define PINMUX_GPIO30__FUNC_SSPM_JTAG_TRSTN (MTK_PIN_NO(30) | 5)
+#define PINMUX_GPIO30__FUNC_PCM1_DI (MTK_PIN_NO(30) | 6)
+#define PINMUX_GPIO30__FUNC_DBG_MON_A7 (MTK_PIN_NO(30) | 7)
+
+#define PINMUX_GPIO31__FUNC_GPIO31 (MTK_PIN_NO(31) | 0)
+#define PINMUX_GPIO31__FUNC_MSDC1_CMD (MTK_PIN_NO(31) | 1)
+#define PINMUX_GPIO31__FUNC_IO_JTAG_TMS (MTK_PIN_NO(31) | 2)
+#define PINMUX_GPIO31__FUNC_UDI_TMS (MTK_PIN_NO(31) | 3)
+#define PINMUX_GPIO31__FUNC_CONN_DSP_JMS (MTK_PIN_NO(31) | 4)
+#define PINMUX_GPIO31__FUNC_SSPM_JTAG_TMS (MTK_PIN_NO(31) | 5)
+#define PINMUX_GPIO31__FUNC_PCM1_SYNC (MTK_PIN_NO(31) | 6)
+#define PINMUX_GPIO31__FUNC_DBG_MON_A8 (MTK_PIN_NO(31) | 7)
+
+#define PINMUX_GPIO32__FUNC_GPIO32 (MTK_PIN_NO(32) | 0)
+#define PINMUX_GPIO32__FUNC_MSDC1_DAT0 (MTK_PIN_NO(32) | 1)
+#define PINMUX_GPIO32__FUNC_IO_JTAG_TDI (MTK_PIN_NO(32) | 2)
+#define PINMUX_GPIO32__FUNC_UDI_TDI (MTK_PIN_NO(32) | 3)
+#define PINMUX_GPIO32__FUNC_CONN_DSP_JDI (MTK_PIN_NO(32) | 4)
+#define PINMUX_GPIO32__FUNC_SSPM_JTAG_TDI (MTK_PIN_NO(32) | 5)
+#define PINMUX_GPIO32__FUNC_PCM1_DO0 (MTK_PIN_NO(32) | 6)
+#define PINMUX_GPIO32__FUNC_DBG_MON_A9 (MTK_PIN_NO(32) | 7)
+
+#define PINMUX_GPIO33__FUNC_GPIO33 (MTK_PIN_NO(33) | 0)
+#define PINMUX_GPIO33__FUNC_MSDC1_DAT2 (MTK_PIN_NO(33) | 1)
+#define PINMUX_GPIO33__FUNC_IO_JTAG_TRSTN (MTK_PIN_NO(33) | 2)
+#define PINMUX_GPIO33__FUNC_UDI_NTRST (MTK_PIN_NO(33) | 3)
+#define PINMUX_GPIO33__FUNC_DAP_MD32_SWCK (MTK_PIN_NO(33) | 4)
+#define PINMUX_GPIO33__FUNC_CONN_MCU_AICE_TCKC (MTK_PIN_NO(33) | 5)
+#define PINMUX_GPIO33__FUNC_PCM1_DO2 (MTK_PIN_NO(33) | 6)
+#define PINMUX_GPIO33__FUNC_DBG_MON_A10 (MTK_PIN_NO(33) | 7)
+
+#define PINMUX_GPIO34__FUNC_GPIO34 (MTK_PIN_NO(34) | 0)
+#define PINMUX_GPIO34__FUNC_MSDC1_DAT1 (MTK_PIN_NO(34) | 1)
+#define PINMUX_GPIO34__FUNC_IO_JTAG_TDO (MTK_PIN_NO(34) | 2)
+#define PINMUX_GPIO34__FUNC_UDI_TDO (MTK_PIN_NO(34) | 3)
+#define PINMUX_GPIO34__FUNC_CONN_DSP_JDO (MTK_PIN_NO(34) | 4)
+#define PINMUX_GPIO34__FUNC_SSPM_JTAG_TDO (MTK_PIN_NO(34) | 5)
+#define PINMUX_GPIO34__FUNC_PCM1_DO1 (MTK_PIN_NO(34) | 6)
+#define PINMUX_GPIO34__FUNC_DBG_MON_A11 (MTK_PIN_NO(34) | 7)
+
+#define PINMUX_GPIO35__FUNC_GPIO35 (MTK_PIN_NO(35) | 0)
+#define PINMUX_GPIO35__FUNC_MD1_SIM2_SIO (MTK_PIN_NO(35) | 1)
+#define PINMUX_GPIO35__FUNC_CCU_JTAG_TDO (MTK_PIN_NO(35) | 2)
+#define PINMUX_GPIO35__FUNC_MD1_SIM1_SIO (MTK_PIN_NO(35) | 3)
+#define PINMUX_GPIO35__FUNC_SCP_JTAG_TDO (MTK_PIN_NO(35) | 5)
+#define PINMUX_GPIO35__FUNC_CONN_DSP_JMS (MTK_PIN_NO(35) | 6)
+#define PINMUX_GPIO35__FUNC_DBG_MON_A28 (MTK_PIN_NO(35) | 7)
+
+#define PINMUX_GPIO36__FUNC_GPIO36 (MTK_PIN_NO(36) | 0)
+#define PINMUX_GPIO36__FUNC_MD1_SIM2_SRST (MTK_PIN_NO(36) | 1)
+#define PINMUX_GPIO36__FUNC_CCU_JTAG_TMS (MTK_PIN_NO(36) | 2)
+#define PINMUX_GPIO36__FUNC_MD1_SIM1_SRST (MTK_PIN_NO(36) | 3)
+#define PINMUX_GPIO36__FUNC_CONN_MCU_AICE_TMSC (MTK_PIN_NO(36) | 4)
+#define PINMUX_GPIO36__FUNC_SCP_JTAG_TMS (MTK_PIN_NO(36) | 5)
+#define PINMUX_GPIO36__FUNC_CONN_DSP_JINTP (MTK_PIN_NO(36) | 6)
+#define PINMUX_GPIO36__FUNC_DBG_MON_A29 (MTK_PIN_NO(36) | 7)
+
+#define PINMUX_GPIO37__FUNC_GPIO37 (MTK_PIN_NO(37) | 0)
+#define PINMUX_GPIO37__FUNC_MD1_SIM2_SCLK (MTK_PIN_NO(37) | 1)
+#define PINMUX_GPIO37__FUNC_CCU_JTAG_TDI (MTK_PIN_NO(37) | 2)
+#define PINMUX_GPIO37__FUNC_MD1_SIM1_SCLK (MTK_PIN_NO(37) | 3)
+#define PINMUX_GPIO37__FUNC_SCP_JTAG_TDI (MTK_PIN_NO(37) | 5)
+#define PINMUX_GPIO37__FUNC_CONN_DSP_JDO (MTK_PIN_NO(37) | 6)
+#define PINMUX_GPIO37__FUNC_DBG_MON_A30 (MTK_PIN_NO(37) | 7)
+
+#define PINMUX_GPIO38__FUNC_GPIO38 (MTK_PIN_NO(38) | 0)
+#define PINMUX_GPIO38__FUNC_MD1_SIM1_SCLK (MTK_PIN_NO(38) | 1)
+#define PINMUX_GPIO38__FUNC_MD1_SIM2_SCLK (MTK_PIN_NO(38) | 3)
+#define PINMUX_GPIO38__FUNC_CONN_MCU_AICE_TCKC (MTK_PIN_NO(38) | 4)
+#define PINMUX_GPIO38__FUNC_DBG_MON_A20 (MTK_PIN_NO(38) | 7)
+
+#define PINMUX_GPIO39__FUNC_GPIO39 (MTK_PIN_NO(39) | 0)
+#define PINMUX_GPIO39__FUNC_MD1_SIM1_SRST (MTK_PIN_NO(39) | 1)
+#define PINMUX_GPIO39__FUNC_CCU_JTAG_TCK (MTK_PIN_NO(39) | 2)
+#define PINMUX_GPIO39__FUNC_MD1_SIM2_SRST (MTK_PIN_NO(39) | 3)
+#define PINMUX_GPIO39__FUNC_SCP_JTAG_TCK (MTK_PIN_NO(39) | 5)
+#define PINMUX_GPIO39__FUNC_CONN_DSP_JCK (MTK_PIN_NO(39) | 6)
+#define PINMUX_GPIO39__FUNC_DBG_MON_A31 (MTK_PIN_NO(39) | 7)
+
+#define PINMUX_GPIO40__FUNC_GPIO40 (MTK_PIN_NO(40) | 0)
+#define PINMUX_GPIO40__FUNC_MD1_SIM1_SIO (MTK_PIN_NO(40) | 1)
+#define PINMUX_GPIO40__FUNC_CCU_JTAG_TRST (MTK_PIN_NO(40) | 2)
+#define PINMUX_GPIO40__FUNC_MD1_SIM2_SIO (MTK_PIN_NO(40) | 3)
+#define PINMUX_GPIO40__FUNC_SCP_JTAG_TRSTN (MTK_PIN_NO(40) | 5)
+#define PINMUX_GPIO40__FUNC_CONN_DSP_JDI (MTK_PIN_NO(40) | 6)
+#define PINMUX_GPIO40__FUNC_DBG_MON_A32 (MTK_PIN_NO(40) | 7)
+
+#define PINMUX_GPIO41__FUNC_GPIO41 (MTK_PIN_NO(41) | 0)
+#define PINMUX_GPIO41__FUNC_IDDIG (MTK_PIN_NO(41) | 1)
+#define PINMUX_GPIO41__FUNC_URXD1 (MTK_PIN_NO(41) | 2)
+#define PINMUX_GPIO41__FUNC_UCTS0 (MTK_PIN_NO(41) | 3)
+#define PINMUX_GPIO41__FUNC_SSPM_UTXD_AO (MTK_PIN_NO(41) | 4)
+#define PINMUX_GPIO41__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(41) | 5)
+#define PINMUX_GPIO41__FUNC_DMIC_CLK (MTK_PIN_NO(41) | 6)
+
+#define PINMUX_GPIO42__FUNC_GPIO42 (MTK_PIN_NO(42) | 0)
+#define PINMUX_GPIO42__FUNC_USB_DRVVBUS (MTK_PIN_NO(42) | 1)
+#define PINMUX_GPIO42__FUNC_UTXD1 (MTK_PIN_NO(42) | 2)
+#define PINMUX_GPIO42__FUNC_URTS0 (MTK_PIN_NO(42) | 3)
+#define PINMUX_GPIO42__FUNC_SSPM_URXD_AO (MTK_PIN_NO(42) | 4)
+#define PINMUX_GPIO42__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(42) | 5)
+#define PINMUX_GPIO42__FUNC_DMIC_DAT (MTK_PIN_NO(42) | 6)
+
+#define PINMUX_GPIO43__FUNC_GPIO43 (MTK_PIN_NO(43) | 0)
+#define PINMUX_GPIO43__FUNC_DISP_PWM (MTK_PIN_NO(43) | 1)
+
+#define PINMUX_GPIO44__FUNC_GPIO44 (MTK_PIN_NO(44) | 0)
+#define PINMUX_GPIO44__FUNC_DSI_TE (MTK_PIN_NO(44) | 1)
+
+#define PINMUX_GPIO45__FUNC_GPIO45 (MTK_PIN_NO(45) | 0)
+#define PINMUX_GPIO45__FUNC_LCM_RST (MTK_PIN_NO(45) | 1)
+
+#define PINMUX_GPIO46__FUNC_GPIO46 (MTK_PIN_NO(46) | 0)
+#define PINMUX_GPIO46__FUNC_MD_INT2_C2K_UIM1_HOT_PLUG (MTK_PIN_NO(46) | 1)
+#define PINMUX_GPIO46__FUNC_URXD1 (MTK_PIN_NO(46) | 2)
+#define PINMUX_GPIO46__FUNC_UCTS1 (MTK_PIN_NO(46) | 3)
+#define PINMUX_GPIO46__FUNC_CCU_UTXD_AO (MTK_PIN_NO(46) | 4)
+#define PINMUX_GPIO46__FUNC_TP_UCTS1_AO (MTK_PIN_NO(46) | 5)
+#define PINMUX_GPIO46__FUNC_IDDIG (MTK_PIN_NO(46) | 6)
+#define PINMUX_GPIO46__FUNC_I2S5_LRCK (MTK_PIN_NO(46) | 7)
+
+#define PINMUX_GPIO47__FUNC_GPIO47 (MTK_PIN_NO(47) | 0)
+#define PINMUX_GPIO47__FUNC_MD_INT1_C2K_UIM0_HOT_PLUG (MTK_PIN_NO(47) | 1)
+#define PINMUX_GPIO47__FUNC_UTXD1 (MTK_PIN_NO(47) | 2)
+#define PINMUX_GPIO47__FUNC_URTS1 (MTK_PIN_NO(47) | 3)
+#define PINMUX_GPIO47__FUNC_CCU_URXD_AO (MTK_PIN_NO(47) | 4)
+#define PINMUX_GPIO47__FUNC_TP_URTS1_AO (MTK_PIN_NO(47) | 5)
+#define PINMUX_GPIO47__FUNC_USB_DRVVBUS (MTK_PIN_NO(47) | 6)
+#define PINMUX_GPIO47__FUNC_I2S5_DO (MTK_PIN_NO(47) | 7)
+
+#define PINMUX_GPIO48__FUNC_GPIO48 (MTK_PIN_NO(48) | 0)
+#define PINMUX_GPIO48__FUNC_SCL5 (MTK_PIN_NO(48) | 1)
+
+#define PINMUX_GPIO49__FUNC_GPIO49 (MTK_PIN_NO(49) | 0)
+#define PINMUX_GPIO49__FUNC_SDA5 (MTK_PIN_NO(49) | 1)
+
+#define PINMUX_GPIO50__FUNC_GPIO50 (MTK_PIN_NO(50) | 0)
+#define PINMUX_GPIO50__FUNC_SCL3 (MTK_PIN_NO(50) | 1)
+
+#define PINMUX_GPIO51__FUNC_GPIO51 (MTK_PIN_NO(51) | 0)
+#define PINMUX_GPIO51__FUNC_SDA3 (MTK_PIN_NO(51) | 1)
+
+#define PINMUX_GPIO52__FUNC_GPIO52 (MTK_PIN_NO(52) | 0)
+#define PINMUX_GPIO52__FUNC_BPI_ANT2 (MTK_PIN_NO(52) | 1)
+
+#define PINMUX_GPIO53__FUNC_GPIO53 (MTK_PIN_NO(53) | 0)
+#define PINMUX_GPIO53__FUNC_BPI_ANT0 (MTK_PIN_NO(53) | 1)
+
+#define PINMUX_GPIO54__FUNC_GPIO54 (MTK_PIN_NO(54) | 0)
+#define PINMUX_GPIO54__FUNC_BPI_OLAT1 (MTK_PIN_NO(54) | 1)
+
+#define PINMUX_GPIO55__FUNC_GPIO55 (MTK_PIN_NO(55) | 0)
+#define PINMUX_GPIO55__FUNC_BPI_BUS8 (MTK_PIN_NO(55) | 1)
+
+#define PINMUX_GPIO56__FUNC_GPIO56 (MTK_PIN_NO(56) | 0)
+#define PINMUX_GPIO56__FUNC_BPI_BUS9 (MTK_PIN_NO(56) | 1)
+#define PINMUX_GPIO56__FUNC_SCL_6306 (MTK_PIN_NO(56) | 2)
+
+#define PINMUX_GPIO57__FUNC_GPIO57 (MTK_PIN_NO(57) | 0)
+#define PINMUX_GPIO57__FUNC_BPI_BUS10 (MTK_PIN_NO(57) | 1)
+#define PINMUX_GPIO57__FUNC_SDA_6306 (MTK_PIN_NO(57) | 2)
+
+#define PINMUX_GPIO58__FUNC_GPIO58 (MTK_PIN_NO(58) | 0)
+#define PINMUX_GPIO58__FUNC_RFIC0_BSI_D2 (MTK_PIN_NO(58) | 1)
+#define PINMUX_GPIO58__FUNC_SPM_BSI_D2 (MTK_PIN_NO(58) | 2)
+#define PINMUX_GPIO58__FUNC_PWM_B (MTK_PIN_NO(58) | 3)
+
+#define PINMUX_GPIO59__FUNC_GPIO59 (MTK_PIN_NO(59) | 0)
+#define PINMUX_GPIO59__FUNC_RFIC0_BSI_D1 (MTK_PIN_NO(59) | 1)
+#define PINMUX_GPIO59__FUNC_SPM_BSI_D1 (MTK_PIN_NO(59) | 2)
+
+#define PINMUX_GPIO60__FUNC_GPIO60 (MTK_PIN_NO(60) | 0)
+#define PINMUX_GPIO60__FUNC_RFIC0_BSI_D0 (MTK_PIN_NO(60) | 1)
+#define PINMUX_GPIO60__FUNC_SPM_BSI_D0 (MTK_PIN_NO(60) | 2)
+
+#define PINMUX_GPIO61__FUNC_GPIO61 (MTK_PIN_NO(61) | 0)
+#define PINMUX_GPIO61__FUNC_MIPI1_SDATA (MTK_PIN_NO(61) | 1)
+
+#define PINMUX_GPIO62__FUNC_GPIO62 (MTK_PIN_NO(62) | 0)
+#define PINMUX_GPIO62__FUNC_MIPI1_SCLK (MTK_PIN_NO(62) | 1)
+
+#define PINMUX_GPIO63__FUNC_GPIO63 (MTK_PIN_NO(63) | 0)
+#define PINMUX_GPIO63__FUNC_MIPI0_SDATA (MTK_PIN_NO(63) | 1)
+
+#define PINMUX_GPIO64__FUNC_GPIO64 (MTK_PIN_NO(64) | 0)
+#define PINMUX_GPIO64__FUNC_MIPI0_SCLK (MTK_PIN_NO(64) | 1)
+
+#define PINMUX_GPIO65__FUNC_GPIO65 (MTK_PIN_NO(65) | 0)
+#define PINMUX_GPIO65__FUNC_MIPI3_SDATA (MTK_PIN_NO(65) | 1)
+#define PINMUX_GPIO65__FUNC_BPI_OLAT2 (MTK_PIN_NO(65) | 2)
+
+#define PINMUX_GPIO66__FUNC_GPIO66 (MTK_PIN_NO(66) | 0)
+#define PINMUX_GPIO66__FUNC_MIPI3_SCLK (MTK_PIN_NO(66) | 1)
+#define PINMUX_GPIO66__FUNC_BPI_OLAT3 (MTK_PIN_NO(66) | 2)
+
+#define PINMUX_GPIO67__FUNC_GPIO67 (MTK_PIN_NO(67) | 0)
+#define PINMUX_GPIO67__FUNC_MIPI2_SDATA (MTK_PIN_NO(67) | 1)
+
+#define PINMUX_GPIO68__FUNC_GPIO68 (MTK_PIN_NO(68) | 0)
+#define PINMUX_GPIO68__FUNC_MIPI2_SCLK (MTK_PIN_NO(68) | 1)
+
+#define PINMUX_GPIO69__FUNC_GPIO69 (MTK_PIN_NO(69) | 0)
+#define PINMUX_GPIO69__FUNC_BPI_BUS7 (MTK_PIN_NO(69) | 1)
+
+#define PINMUX_GPIO70__FUNC_GPIO70 (MTK_PIN_NO(70) | 0)
+#define PINMUX_GPIO70__FUNC_BPI_BUS6 (MTK_PIN_NO(70) | 1)
+
+#define PINMUX_GPIO71__FUNC_GPIO71 (MTK_PIN_NO(71) | 0)
+#define PINMUX_GPIO71__FUNC_BPI_BUS5 (MTK_PIN_NO(71) | 1)
+
+#define PINMUX_GPIO72__FUNC_GPIO72 (MTK_PIN_NO(72) | 0)
+#define PINMUX_GPIO72__FUNC_BPI_BUS4 (MTK_PIN_NO(72) | 1)
+
+#define PINMUX_GPIO73__FUNC_GPIO73 (MTK_PIN_NO(73) | 0)
+#define PINMUX_GPIO73__FUNC_BPI_BUS3 (MTK_PIN_NO(73) | 1)
+
+#define PINMUX_GPIO74__FUNC_GPIO74 (MTK_PIN_NO(74) | 0)
+#define PINMUX_GPIO74__FUNC_BPI_BUS2 (MTK_PIN_NO(74) | 1)
+
+#define PINMUX_GPIO75__FUNC_GPIO75 (MTK_PIN_NO(75) | 0)
+#define PINMUX_GPIO75__FUNC_BPI_BUS1 (MTK_PIN_NO(75) | 1)
+
+#define PINMUX_GPIO76__FUNC_GPIO76 (MTK_PIN_NO(76) | 0)
+#define PINMUX_GPIO76__FUNC_BPI_BUS0 (MTK_PIN_NO(76) | 1)
+
+#define PINMUX_GPIO77__FUNC_GPIO77 (MTK_PIN_NO(77) | 0)
+#define PINMUX_GPIO77__FUNC_BPI_ANT1 (MTK_PIN_NO(77) | 1)
+
+#define PINMUX_GPIO78__FUNC_GPIO78 (MTK_PIN_NO(78) | 0)
+#define PINMUX_GPIO78__FUNC_BPI_OLAT0 (MTK_PIN_NO(78) | 1)
+
+#define PINMUX_GPIO79__FUNC_GPIO79 (MTK_PIN_NO(79) | 0)
+#define PINMUX_GPIO79__FUNC_BPI_PA_VM1 (MTK_PIN_NO(79) | 1)
+#define PINMUX_GPIO79__FUNC_MIPI4_SDATA (MTK_PIN_NO(79) | 2)
+
+#define PINMUX_GPIO80__FUNC_GPIO80 (MTK_PIN_NO(80) | 0)
+#define PINMUX_GPIO80__FUNC_BPI_PA_VM0 (MTK_PIN_NO(80) | 1)
+#define PINMUX_GPIO80__FUNC_MIPI4_SCLK (MTK_PIN_NO(80) | 2)
+
+#define PINMUX_GPIO81__FUNC_GPIO81 (MTK_PIN_NO(81) | 0)
+#define PINMUX_GPIO81__FUNC_SDA1 (MTK_PIN_NO(81) | 1)
+
+#define PINMUX_GPIO82__FUNC_GPIO82 (MTK_PIN_NO(82) | 0)
+#define PINMUX_GPIO82__FUNC_SDA0 (MTK_PIN_NO(82) | 1)
+
+#define PINMUX_GPIO83__FUNC_GPIO83 (MTK_PIN_NO(83) | 0)
+#define PINMUX_GPIO83__FUNC_SCL0 (MTK_PIN_NO(83) | 1)
+
+#define PINMUX_GPIO84__FUNC_GPIO84 (MTK_PIN_NO(84) | 0)
+#define PINMUX_GPIO84__FUNC_SCL1 (MTK_PIN_NO(84) | 1)
+
+#define PINMUX_GPIO85__FUNC_GPIO85 (MTK_PIN_NO(85) | 0)
+#define PINMUX_GPIO85__FUNC_SPI0_MI (MTK_PIN_NO(85) | 1)
+#define PINMUX_GPIO85__FUNC_SCP_SPI0_MI (MTK_PIN_NO(85) | 2)
+#define PINMUX_GPIO85__FUNC_CLKM3 (MTK_PIN_NO(85) | 3)
+#define PINMUX_GPIO85__FUNC_I2S1_BCK (MTK_PIN_NO(85) | 4)
+#define PINMUX_GPIO85__FUNC_MFG_DFD_JTAG_TDO (MTK_PIN_NO(85) | 5)
+#define PINMUX_GPIO85__FUNC_DFD_TDO (MTK_PIN_NO(85) | 6)
+#define PINMUX_GPIO85__FUNC_JTDO_SEL1 (MTK_PIN_NO(85) | 7)
+
+#define PINMUX_GPIO86__FUNC_GPIO86 (MTK_PIN_NO(86) | 0)
+#define PINMUX_GPIO86__FUNC_SPI0_CSB (MTK_PIN_NO(86) | 1)
+#define PINMUX_GPIO86__FUNC_SCP_SPI0_CS (MTK_PIN_NO(86) | 2)
+#define PINMUX_GPIO86__FUNC_CLKM0 (MTK_PIN_NO(86) | 3)
+#define PINMUX_GPIO86__FUNC_I2S1_LRCK (MTK_PIN_NO(86) | 4)
+#define PINMUX_GPIO86__FUNC_MFG_DFD_JTAG_TMS (MTK_PIN_NO(86) | 5)
+#define PINMUX_GPIO86__FUNC_DFD_TMS (MTK_PIN_NO(86) | 6)
+#define PINMUX_GPIO86__FUNC_JTMS_SEL1 (MTK_PIN_NO(86) | 7)
+
+#define PINMUX_GPIO87__FUNC_GPIO87 (MTK_PIN_NO(87) | 0)
+#define PINMUX_GPIO87__FUNC_SPI0_MO (MTK_PIN_NO(87) | 1)
+#define PINMUX_GPIO87__FUNC_SCP_SPI0_MO (MTK_PIN_NO(87) | 2)
+#define PINMUX_GPIO87__FUNC_SDA1 (MTK_PIN_NO(87) | 3)
+#define PINMUX_GPIO87__FUNC_I2S1_DO (MTK_PIN_NO(87) | 4)
+#define PINMUX_GPIO87__FUNC_MFG_DFD_JTAG_TDI (MTK_PIN_NO(87) | 5)
+#define PINMUX_GPIO87__FUNC_DFD_TDI (MTK_PIN_NO(87) | 6)
+#define PINMUX_GPIO87__FUNC_JTDI_SEL1 (MTK_PIN_NO(87) | 7)
+
+#define PINMUX_GPIO88__FUNC_GPIO88 (MTK_PIN_NO(88) | 0)
+#define PINMUX_GPIO88__FUNC_SPI0_CLK (MTK_PIN_NO(88) | 1)
+#define PINMUX_GPIO88__FUNC_SCP_SPI0_CK (MTK_PIN_NO(88) | 2)
+#define PINMUX_GPIO88__FUNC_SCL1 (MTK_PIN_NO(88) | 3)
+#define PINMUX_GPIO88__FUNC_I2S1_MCK (MTK_PIN_NO(88) | 4)
+#define PINMUX_GPIO88__FUNC_MFG_DFD_JTAG_TCK (MTK_PIN_NO(88) | 5)
+#define PINMUX_GPIO88__FUNC_DFD_TCK_XI (MTK_PIN_NO(88) | 6)
+#define PINMUX_GPIO88__FUNC_JTCK_SEL1 (MTK_PIN_NO(88) | 7)
+
+#define PINMUX_GPIO89__FUNC_GPIO89 (MTK_PIN_NO(89) | 0)
+#define PINMUX_GPIO89__FUNC_SRCLKENAI0 (MTK_PIN_NO(89) | 1)
+#define PINMUX_GPIO89__FUNC_PWM_C (MTK_PIN_NO(89) | 2)
+#define PINMUX_GPIO89__FUNC_I2S5_BCK (MTK_PIN_NO(89) | 3)
+#define PINMUX_GPIO89__FUNC_ANT_SEL6 (MTK_PIN_NO(89) | 4)
+#define PINMUX_GPIO89__FUNC_SDA8 (MTK_PIN_NO(89) | 5)
+#define PINMUX_GPIO89__FUNC_CMVREF0 (MTK_PIN_NO(89) | 6)
+#define PINMUX_GPIO89__FUNC_DBG_MON_A21 (MTK_PIN_NO(89) | 7)
+
+#define PINMUX_GPIO90__FUNC_GPIO90 (MTK_PIN_NO(90) | 0)
+#define PINMUX_GPIO90__FUNC_PWM_A (MTK_PIN_NO(90) | 1)
+#define PINMUX_GPIO90__FUNC_CMMCLK2 (MTK_PIN_NO(90) | 2)
+#define PINMUX_GPIO90__FUNC_I2S5_LRCK (MTK_PIN_NO(90) | 3)
+#define PINMUX_GPIO90__FUNC_SCP_VREQ_VAO (MTK_PIN_NO(90) | 4)
+#define PINMUX_GPIO90__FUNC_SCL8 (MTK_PIN_NO(90) | 5)
+#define PINMUX_GPIO90__FUNC_PTA_RXD (MTK_PIN_NO(90) | 6)
+#define PINMUX_GPIO90__FUNC_DBG_MON_A22 (MTK_PIN_NO(90) | 7)
+
+#define PINMUX_GPIO91__FUNC_GPIO91 (MTK_PIN_NO(91) | 0)
+#define PINMUX_GPIO91__FUNC_KPROW1 (MTK_PIN_NO(91) | 1)
+#define PINMUX_GPIO91__FUNC_PWM_B (MTK_PIN_NO(91) | 2)
+#define PINMUX_GPIO91__FUNC_I2S5_DO (MTK_PIN_NO(91) | 3)
+#define PINMUX_GPIO91__FUNC_ANT_SEL7 (MTK_PIN_NO(91) | 4)
+#define PINMUX_GPIO91__FUNC_CMMCLK3 (MTK_PIN_NO(91) | 5)
+#define PINMUX_GPIO91__FUNC_PTA_TXD (MTK_PIN_NO(91) | 6)
+
+#define PINMUX_GPIO92__FUNC_GPIO92 (MTK_PIN_NO(92) | 0)
+#define PINMUX_GPIO92__FUNC_KPROW0 (MTK_PIN_NO(92) | 1)
+
+#define PINMUX_GPIO93__FUNC_GPIO93 (MTK_PIN_NO(93) | 0)
+#define PINMUX_GPIO93__FUNC_KPCOL0 (MTK_PIN_NO(93) | 1)
+#define PINMUX_GPIO93__FUNC_DBG_MON_B27 (MTK_PIN_NO(93) | 7)
+
+#define PINMUX_GPIO94__FUNC_GPIO94 (MTK_PIN_NO(94) | 0)
+#define PINMUX_GPIO94__FUNC_KPCOL1 (MTK_PIN_NO(94) | 1)
+#define PINMUX_GPIO94__FUNC_I2S2_DI2 (MTK_PIN_NO(94) | 2)
+#define PINMUX_GPIO94__FUNC_I2S5_MCK (MTK_PIN_NO(94) | 3)
+#define PINMUX_GPIO94__FUNC_CMMCLK2 (MTK_PIN_NO(94) | 4)
+#define PINMUX_GPIO94__FUNC_SCP_SPI2_MI (MTK_PIN_NO(94) | 5)
+#define PINMUX_GPIO94__FUNC_SRCLKENAI1 (MTK_PIN_NO(94) | 6)
+#define PINMUX_GPIO94__FUNC_SPI2_MI (MTK_PIN_NO(94) | 7)
+
+#define PINMUX_GPIO95__FUNC_GPIO95 (MTK_PIN_NO(95) | 0)
+#define PINMUX_GPIO95__FUNC_URXD0 (MTK_PIN_NO(95) | 1)
+#define PINMUX_GPIO95__FUNC_UTXD0 (MTK_PIN_NO(95) | 2)
+#define PINMUX_GPIO95__FUNC_MD_URXD0 (MTK_PIN_NO(95) | 3)
+#define PINMUX_GPIO95__FUNC_MD_URXD1 (MTK_PIN_NO(95) | 4)
+#define PINMUX_GPIO95__FUNC_SSPM_URXD_AO (MTK_PIN_NO(95) | 5)
+#define PINMUX_GPIO95__FUNC_CCU_URXD_AO (MTK_PIN_NO(95) | 6)
+
+#define PINMUX_GPIO96__FUNC_GPIO96 (MTK_PIN_NO(96) | 0)
+#define PINMUX_GPIO96__FUNC_UTXD0 (MTK_PIN_NO(96) | 1)
+#define PINMUX_GPIO96__FUNC_URXD0 (MTK_PIN_NO(96) | 2)
+#define PINMUX_GPIO96__FUNC_MD_UTXD0 (MTK_PIN_NO(96) | 3)
+#define PINMUX_GPIO96__FUNC_MD_UTXD1 (MTK_PIN_NO(96) | 4)
+#define PINMUX_GPIO96__FUNC_SSPM_UTXD_AO (MTK_PIN_NO(96) | 5)
+#define PINMUX_GPIO96__FUNC_CCU_UTXD_AO (MTK_PIN_NO(96) | 6)
+#define PINMUX_GPIO96__FUNC_DBG_MON_B2 (MTK_PIN_NO(96) | 7)
+
+#define PINMUX_GPIO97__FUNC_GPIO97 (MTK_PIN_NO(97) | 0)
+#define PINMUX_GPIO97__FUNC_UCTS0 (MTK_PIN_NO(97) | 1)
+#define PINMUX_GPIO97__FUNC_I2S2_MCK (MTK_PIN_NO(97) | 2)
+#define PINMUX_GPIO97__FUNC_IDDIG (MTK_PIN_NO(97) | 3)
+#define PINMUX_GPIO97__FUNC_CONN_MCU_TDO (MTK_PIN_NO(97) | 4)
+#define PINMUX_GPIO97__FUNC_SSPM_JTAG_TDO (MTK_PIN_NO(97) | 5)
+#define PINMUX_GPIO97__FUNC_IO_JTAG_TDO (MTK_PIN_NO(97) | 6)
+#define PINMUX_GPIO97__FUNC_DBG_MON_B3 (MTK_PIN_NO(97) | 7)
+
+#define PINMUX_GPIO98__FUNC_GPIO98 (MTK_PIN_NO(98) | 0)
+#define PINMUX_GPIO98__FUNC_URTS0 (MTK_PIN_NO(98) | 1)
+#define PINMUX_GPIO98__FUNC_I2S2_BCK (MTK_PIN_NO(98) | 2)
+#define PINMUX_GPIO98__FUNC_USB_DRVVBUS (MTK_PIN_NO(98) | 3)
+#define PINMUX_GPIO98__FUNC_CONN_MCU_TMS (MTK_PIN_NO(98) | 4)
+#define PINMUX_GPIO98__FUNC_SSPM_JTAG_TMS (MTK_PIN_NO(98) | 5)
+#define PINMUX_GPIO98__FUNC_IO_JTAG_TMS (MTK_PIN_NO(98) | 6)
+#define PINMUX_GPIO98__FUNC_DBG_MON_B4 (MTK_PIN_NO(98) | 7)
+
+#define PINMUX_GPIO99__FUNC_GPIO99 (MTK_PIN_NO(99) | 0)
+#define PINMUX_GPIO99__FUNC_CMMCLK0 (MTK_PIN_NO(99) | 1)
+#define PINMUX_GPIO99__FUNC_CONN_MCU_AICE_TMSC (MTK_PIN_NO(99) | 4)
+#define PINMUX_GPIO99__FUNC_DBG_MON_B28 (MTK_PIN_NO(99) | 7)
+
+#define PINMUX_GPIO100__FUNC_GPIO100 (MTK_PIN_NO(100) | 0)
+#define PINMUX_GPIO100__FUNC_CMMCLK1 (MTK_PIN_NO(100) | 1)
+#define PINMUX_GPIO100__FUNC_PWM_C (MTK_PIN_NO(100) | 2)
+#define PINMUX_GPIO100__FUNC_MD_INT1_C2K_UIM0_HOT_PLUG (MTK_PIN_NO(100) | 3)
+#define PINMUX_GPIO100__FUNC_CONN_MCU_AICE_TCKC (MTK_PIN_NO(100) | 4)
+#define PINMUX_GPIO100__FUNC_DBG_MON_B29 (MTK_PIN_NO(100) | 7)
+
+#define PINMUX_GPIO101__FUNC_GPIO101 (MTK_PIN_NO(101) | 0)
+#define PINMUX_GPIO101__FUNC_CLKM2 (MTK_PIN_NO(101) | 1)
+#define PINMUX_GPIO101__FUNC_I2S2_LRCK (MTK_PIN_NO(101) | 2)
+#define PINMUX_GPIO101__FUNC_CMVREF1 (MTK_PIN_NO(101) | 3)
+#define PINMUX_GPIO101__FUNC_CONN_MCU_TCK (MTK_PIN_NO(101) | 4)
+#define PINMUX_GPIO101__FUNC_SSPM_JTAG_TCK (MTK_PIN_NO(101) | 5)
+#define PINMUX_GPIO101__FUNC_IO_JTAG_TCK (MTK_PIN_NO(101) | 6)
+
+#define PINMUX_GPIO102__FUNC_GPIO102 (MTK_PIN_NO(102) | 0)
+#define PINMUX_GPIO102__FUNC_CLKM1 (MTK_PIN_NO(102) | 1)
+#define PINMUX_GPIO102__FUNC_I2S2_DI (MTK_PIN_NO(102) | 2)
+#define PINMUX_GPIO102__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(102) | 3)
+#define PINMUX_GPIO102__FUNC_CONN_MCU_TDI (MTK_PIN_NO(102) | 4)
+#define PINMUX_GPIO102__FUNC_SSPM_JTAG_TDI (MTK_PIN_NO(102) | 5)
+#define PINMUX_GPIO102__FUNC_IO_JTAG_TDI (MTK_PIN_NO(102) | 6)
+#define PINMUX_GPIO102__FUNC_DBG_MON_B8 (MTK_PIN_NO(102) | 7)
+
+#define PINMUX_GPIO103__FUNC_GPIO103 (MTK_PIN_NO(103) | 0)
+#define PINMUX_GPIO103__FUNC_SCL2 (MTK_PIN_NO(103) | 1)
+
+#define PINMUX_GPIO104__FUNC_GPIO104 (MTK_PIN_NO(104) | 0)
+#define PINMUX_GPIO104__FUNC_SDA2 (MTK_PIN_NO(104) | 1)
+
+#define PINMUX_GPIO105__FUNC_GPIO105 (MTK_PIN_NO(105) | 0)
+#define PINMUX_GPIO105__FUNC_SCL4 (MTK_PIN_NO(105) | 1)
+
+#define PINMUX_GPIO106__FUNC_GPIO106 (MTK_PIN_NO(106) | 0)
+#define PINMUX_GPIO106__FUNC_SDA4 (MTK_PIN_NO(106) | 1)
+
+#define PINMUX_GPIO107__FUNC_GPIO107 (MTK_PIN_NO(107) | 0)
+#define PINMUX_GPIO107__FUNC_DMIC_CLK (MTK_PIN_NO(107) | 1)
+#define PINMUX_GPIO107__FUNC_ANT_SEL0 (MTK_PIN_NO(107) | 2)
+#define PINMUX_GPIO107__FUNC_CLKM0 (MTK_PIN_NO(107) | 3)
+#define PINMUX_GPIO107__FUNC_SDA7 (MTK_PIN_NO(107) | 4)
+#define PINMUX_GPIO107__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(107) | 5)
+#define PINMUX_GPIO107__FUNC_PWM_A (MTK_PIN_NO(107) | 6)
+#define PINMUX_GPIO107__FUNC_DBG_MON_B12 (MTK_PIN_NO(107) | 7)
+
+#define PINMUX_GPIO108__FUNC_GPIO108 (MTK_PIN_NO(108) | 0)
+#define PINMUX_GPIO108__FUNC_CMMCLK2 (MTK_PIN_NO(108) | 1)
+#define PINMUX_GPIO108__FUNC_ANT_SEL1 (MTK_PIN_NO(108) | 2)
+#define PINMUX_GPIO108__FUNC_CLKM1 (MTK_PIN_NO(108) | 3)
+#define PINMUX_GPIO108__FUNC_SCL8 (MTK_PIN_NO(108) | 4)
+#define PINMUX_GPIO108__FUNC_DAP_MD32_SWD (MTK_PIN_NO(108) | 5)
+#define PINMUX_GPIO108__FUNC_PWM_B (MTK_PIN_NO(108) | 6)
+#define PINMUX_GPIO108__FUNC_DBG_MON_B13 (MTK_PIN_NO(108) | 7)
+
+#define PINMUX_GPIO109__FUNC_GPIO109 (MTK_PIN_NO(109) | 0)
+#define PINMUX_GPIO109__FUNC_DMIC_DAT (MTK_PIN_NO(109) | 1)
+#define PINMUX_GPIO109__FUNC_ANT_SEL2 (MTK_PIN_NO(109) | 2)
+#define PINMUX_GPIO109__FUNC_CLKM2 (MTK_PIN_NO(109) | 3)
+#define PINMUX_GPIO109__FUNC_SDA8 (MTK_PIN_NO(109) | 4)
+#define PINMUX_GPIO109__FUNC_DAP_MD32_SWCK (MTK_PIN_NO(109) | 5)
+#define PINMUX_GPIO109__FUNC_PWM_C (MTK_PIN_NO(109) | 6)
+#define PINMUX_GPIO109__FUNC_DBG_MON_B14 (MTK_PIN_NO(109) | 7)
+
+#define PINMUX_GPIO110__FUNC_GPIO110 (MTK_PIN_NO(110) | 0)
+#define PINMUX_GPIO110__FUNC_SCL7 (MTK_PIN_NO(110) | 1)
+#define PINMUX_GPIO110__FUNC_ANT_SEL0 (MTK_PIN_NO(110) | 2)
+#define PINMUX_GPIO110__FUNC_TP_URXD1_AO (MTK_PIN_NO(110) | 3)
+#define PINMUX_GPIO110__FUNC_USB_DRVVBUS (MTK_PIN_NO(110) | 4)
+#define PINMUX_GPIO110__FUNC_SRCLKENAI1 (MTK_PIN_NO(110) | 5)
+#define PINMUX_GPIO110__FUNC_KPCOL2 (MTK_PIN_NO(110) | 6)
+#define PINMUX_GPIO110__FUNC_URXD1 (MTK_PIN_NO(110) | 7)
+
+#define PINMUX_GPIO111__FUNC_GPIO111 (MTK_PIN_NO(111) | 0)
+#define PINMUX_GPIO111__FUNC_CMMCLK3 (MTK_PIN_NO(111) | 1)
+#define PINMUX_GPIO111__FUNC_ANT_SEL1 (MTK_PIN_NO(111) | 2)
+#define PINMUX_GPIO111__FUNC_SRCLKENAI0 (MTK_PIN_NO(111) | 3)
+#define PINMUX_GPIO111__FUNC_SCP_VREQ_VAO (MTK_PIN_NO(111) | 4)
+#define PINMUX_GPIO111__FUNC_MD_INT2_C2K_UIM1_HOT_PLUG (MTK_PIN_NO(111) | 5)
+#define PINMUX_GPIO111__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(111) | 7)
+
+#define PINMUX_GPIO112__FUNC_GPIO112 (MTK_PIN_NO(112) | 0)
+#define PINMUX_GPIO112__FUNC_SDA7 (MTK_PIN_NO(112) | 1)
+#define PINMUX_GPIO112__FUNC_ANT_SEL2 (MTK_PIN_NO(112) | 2)
+#define PINMUX_GPIO112__FUNC_TP_UTXD1_AO (MTK_PIN_NO(112) | 3)
+#define PINMUX_GPIO112__FUNC_IDDIG (MTK_PIN_NO(112) | 4)
+#define PINMUX_GPIO112__FUNC_AGPS_SYNC (MTK_PIN_NO(112) | 5)
+#define PINMUX_GPIO112__FUNC_KPROW2 (MTK_PIN_NO(112) | 6)
+#define PINMUX_GPIO112__FUNC_UTXD1 (MTK_PIN_NO(112) | 7)
+
+#define PINMUX_GPIO113__FUNC_GPIO113 (MTK_PIN_NO(113) | 0)
+#define PINMUX_GPIO113__FUNC_CONN_TOP_CLK (MTK_PIN_NO(113) | 1)
+#define PINMUX_GPIO113__FUNC_SCL6 (MTK_PIN_NO(113) | 3)
+#define PINMUX_GPIO113__FUNC_AUXIF_CLK0 (MTK_PIN_NO(113) | 4)
+#define PINMUX_GPIO113__FUNC_TP_UCTS1_AO (MTK_PIN_NO(113) | 6)
+
+#define PINMUX_GPIO114__FUNC_GPIO114 (MTK_PIN_NO(114) | 0)
+#define PINMUX_GPIO114__FUNC_CONN_TOP_DATA (MTK_PIN_NO(114) | 1)
+#define PINMUX_GPIO114__FUNC_SDA6 (MTK_PIN_NO(114) | 3)
+#define PINMUX_GPIO114__FUNC_AUXIF_ST0 (MTK_PIN_NO(114) | 4)
+#define PINMUX_GPIO114__FUNC_TP_URTS1_AO (MTK_PIN_NO(114) | 6)
+
+#define PINMUX_GPIO115__FUNC_GPIO115 (MTK_PIN_NO(115) | 0)
+#define PINMUX_GPIO115__FUNC_CONN_BT_CLK (MTK_PIN_NO(115) | 1)
+#define PINMUX_GPIO115__FUNC_UTXD1 (MTK_PIN_NO(115) | 2)
+#define PINMUX_GPIO115__FUNC_PTA_TXD (MTK_PIN_NO(115) | 3)
+#define PINMUX_GPIO115__FUNC_AUXIF_CLK1 (MTK_PIN_NO(115) | 4)
+#define PINMUX_GPIO115__FUNC_DAP_MD32_SWD (MTK_PIN_NO(115) | 5)
+#define PINMUX_GPIO115__FUNC_TP_UTXD1_AO (MTK_PIN_NO(115) | 6)
+
+#define PINMUX_GPIO116__FUNC_GPIO116 (MTK_PIN_NO(116) | 0)
+#define PINMUX_GPIO116__FUNC_CONN_BT_DATA (MTK_PIN_NO(116) | 1)
+#define PINMUX_GPIO116__FUNC_IPU_JTAG_TRST (MTK_PIN_NO(116) | 2)
+#define PINMUX_GPIO116__FUNC_AUXIF_ST1 (MTK_PIN_NO(116) | 4)
+#define PINMUX_GPIO116__FUNC_DAP_MD32_SWCK (MTK_PIN_NO(116) | 5)
+#define PINMUX_GPIO116__FUNC_TP_URXD2_AO (MTK_PIN_NO(116) | 6)
+#define PINMUX_GPIO116__FUNC_DBG_MON_A0 (MTK_PIN_NO(116) | 7)
+
+#define PINMUX_GPIO117__FUNC_GPIO117 (MTK_PIN_NO(117) | 0)
+#define PINMUX_GPIO117__FUNC_CONN_WF_HB0 (MTK_PIN_NO(117) | 1)
+#define PINMUX_GPIO117__FUNC_IPU_JTAG_TDO (MTK_PIN_NO(117) | 2)
+#define PINMUX_GPIO117__FUNC_TP_UTXD2_AO (MTK_PIN_NO(117) | 6)
+#define PINMUX_GPIO117__FUNC_DBG_MON_A4 (MTK_PIN_NO(117) | 7)
+
+#define PINMUX_GPIO118__FUNC_GPIO118 (MTK_PIN_NO(118) | 0)
+#define PINMUX_GPIO118__FUNC_CONN_WF_HB1 (MTK_PIN_NO(118) | 1)
+#define PINMUX_GPIO118__FUNC_IPU_JTAG_TDI (MTK_PIN_NO(118) | 2)
+#define PINMUX_GPIO118__FUNC_SSPM_URXD_AO (MTK_PIN_NO(118) | 5)
+#define PINMUX_GPIO118__FUNC_TP_UCTS2_AO (MTK_PIN_NO(118) | 6)
+#define PINMUX_GPIO118__FUNC_DBG_MON_A5 (MTK_PIN_NO(118) | 7)
+
+#define PINMUX_GPIO119__FUNC_GPIO119 (MTK_PIN_NO(119) | 0)
+#define PINMUX_GPIO119__FUNC_CONN_WF_HB2 (MTK_PIN_NO(119) | 1)
+#define PINMUX_GPIO119__FUNC_IPU_JTAG_TCK (MTK_PIN_NO(119) | 2)
+#define PINMUX_GPIO119__FUNC_SSPM_UTXD_AO (MTK_PIN_NO(119) | 5)
+#define PINMUX_GPIO119__FUNC_TP_URTS2_AO (MTK_PIN_NO(119) | 6)
+
+#define PINMUX_GPIO120__FUNC_GPIO120 (MTK_PIN_NO(120) | 0)
+#define PINMUX_GPIO120__FUNC_CONN_WB_PTA (MTK_PIN_NO(120) | 1)
+#define PINMUX_GPIO120__FUNC_IPU_JTAG_TMS (MTK_PIN_NO(120) | 2)
+#define PINMUX_GPIO120__FUNC_CCU_URXD_AO (MTK_PIN_NO(120) | 5)
+
+#define PINMUX_GPIO121__FUNC_GPIO121 (MTK_PIN_NO(121) | 0)
+#define PINMUX_GPIO121__FUNC_CONN_HRST_B (MTK_PIN_NO(121) | 1)
+#define PINMUX_GPIO121__FUNC_URXD1 (MTK_PIN_NO(121) | 2)
+#define PINMUX_GPIO121__FUNC_PTA_RXD (MTK_PIN_NO(121) | 3)
+#define PINMUX_GPIO121__FUNC_CCU_UTXD_AO (MTK_PIN_NO(121) | 5)
+#define PINMUX_GPIO121__FUNC_TP_URXD1_AO (MTK_PIN_NO(121) | 6)
+
+#define PINMUX_GPIO122__FUNC_GPIO122 (MTK_PIN_NO(122) | 0)
+#define PINMUX_GPIO122__FUNC_MSDC0_CMD (MTK_PIN_NO(122) | 1)
+#define PINMUX_GPIO122__FUNC_SSPM_URXD2_AO (MTK_PIN_NO(122) | 2)
+#define PINMUX_GPIO122__FUNC_ANT_SEL1 (MTK_PIN_NO(122) | 3)
+#define PINMUX_GPIO122__FUNC_DBG_MON_A12 (MTK_PIN_NO(122) | 7)
+
+#define PINMUX_GPIO123__FUNC_GPIO123 (MTK_PIN_NO(123) | 0)
+#define PINMUX_GPIO123__FUNC_MSDC0_DAT0 (MTK_PIN_NO(123) | 1)
+#define PINMUX_GPIO123__FUNC_ANT_SEL0 (MTK_PIN_NO(123) | 3)
+#define PINMUX_GPIO123__FUNC_DBG_MON_A13 (MTK_PIN_NO(123) | 7)
+
+#define PINMUX_GPIO124__FUNC_GPIO124 (MTK_PIN_NO(124) | 0)
+#define PINMUX_GPIO124__FUNC_MSDC0_CLK (MTK_PIN_NO(124) | 1)
+#define PINMUX_GPIO124__FUNC_DBG_MON_A14 (MTK_PIN_NO(124) | 7)
+
+#define PINMUX_GPIO125__FUNC_GPIO125 (MTK_PIN_NO(125) | 0)
+#define PINMUX_GPIO125__FUNC_MSDC0_DAT2 (MTK_PIN_NO(125) | 1)
+#define PINMUX_GPIO125__FUNC_MRG_CLK (MTK_PIN_NO(125) | 3)
+#define PINMUX_GPIO125__FUNC_DBG_MON_A15 (MTK_PIN_NO(125) | 7)
+
+#define PINMUX_GPIO126__FUNC_GPIO126 (MTK_PIN_NO(126) | 0)
+#define PINMUX_GPIO126__FUNC_MSDC0_DAT4 (MTK_PIN_NO(126) | 1)
+#define PINMUX_GPIO126__FUNC_ANT_SEL5 (MTK_PIN_NO(126) | 3)
+#define PINMUX_GPIO126__FUNC_UFS_MPHY_SCL (MTK_PIN_NO(126) | 6)
+#define PINMUX_GPIO126__FUNC_DBG_MON_A16 (MTK_PIN_NO(126) | 7)
+
+#define PINMUX_GPIO127__FUNC_GPIO127 (MTK_PIN_NO(127) | 0)
+#define PINMUX_GPIO127__FUNC_MSDC0_DAT6 (MTK_PIN_NO(127) | 1)
+#define PINMUX_GPIO127__FUNC_ANT_SEL4 (MTK_PIN_NO(127) | 3)
+#define PINMUX_GPIO127__FUNC_UFS_MPHY_SDA (MTK_PIN_NO(127) | 6)
+#define PINMUX_GPIO127__FUNC_DBG_MON_A17 (MTK_PIN_NO(127) | 7)
+
+#define PINMUX_GPIO128__FUNC_GPIO128 (MTK_PIN_NO(128) | 0)
+#define PINMUX_GPIO128__FUNC_MSDC0_DAT1 (MTK_PIN_NO(128) | 1)
+#define PINMUX_GPIO128__FUNC_ANT_SEL2 (MTK_PIN_NO(128) | 3)
+#define PINMUX_GPIO128__FUNC_UFS_UNIPRO_SDA (MTK_PIN_NO(128) | 6)
+#define PINMUX_GPIO128__FUNC_DBG_MON_A18 (MTK_PIN_NO(128) | 7)
+
+#define PINMUX_GPIO129__FUNC_GPIO129 (MTK_PIN_NO(129) | 0)
+#define PINMUX_GPIO129__FUNC_MSDC0_DAT5 (MTK_PIN_NO(129) | 1)
+#define PINMUX_GPIO129__FUNC_ANT_SEL3 (MTK_PIN_NO(129) | 3)
+#define PINMUX_GPIO129__FUNC_UFS_UNIPRO_SCL (MTK_PIN_NO(129) | 6)
+#define PINMUX_GPIO129__FUNC_DBG_MON_A23 (MTK_PIN_NO(129) | 7)
+
+#define PINMUX_GPIO130__FUNC_GPIO130 (MTK_PIN_NO(130) | 0)
+#define PINMUX_GPIO130__FUNC_MSDC0_DAT7 (MTK_PIN_NO(130) | 1)
+#define PINMUX_GPIO130__FUNC_MRG_DO (MTK_PIN_NO(130) | 3)
+#define PINMUX_GPIO130__FUNC_DBG_MON_A24 (MTK_PIN_NO(130) | 7)
+
+#define PINMUX_GPIO131__FUNC_GPIO131 (MTK_PIN_NO(131) | 0)
+#define PINMUX_GPIO131__FUNC_MSDC0_DSL (MTK_PIN_NO(131) | 1)
+#define PINMUX_GPIO131__FUNC_MRG_SYNC (MTK_PIN_NO(131) | 3)
+#define PINMUX_GPIO131__FUNC_DBG_MON_A25 (MTK_PIN_NO(131) | 7)
+
+#define PINMUX_GPIO132__FUNC_GPIO132 (MTK_PIN_NO(132) | 0)
+#define PINMUX_GPIO132__FUNC_MSDC0_DAT3 (MTK_PIN_NO(132) | 1)
+#define PINMUX_GPIO132__FUNC_MRG_DI (MTK_PIN_NO(132) | 3)
+#define PINMUX_GPIO132__FUNC_DBG_MON_A26 (MTK_PIN_NO(132) | 7)
+
+#define PINMUX_GPIO133__FUNC_GPIO133 (MTK_PIN_NO(133) | 0)
+#define PINMUX_GPIO133__FUNC_MSDC0_RSTB (MTK_PIN_NO(133) | 1)
+#define PINMUX_GPIO133__FUNC_AGPS_SYNC (MTK_PIN_NO(133) | 3)
+#define PINMUX_GPIO133__FUNC_DBG_MON_A27 (MTK_PIN_NO(133) | 7)
+
+#define PINMUX_GPIO134__FUNC_GPIO134 (MTK_PIN_NO(134) | 0)
+#define PINMUX_GPIO134__FUNC_RTC32K_CK (MTK_PIN_NO(134) | 1)
+
+#define PINMUX_GPIO135__FUNC_GPIO135 (MTK_PIN_NO(135) | 0)
+#define PINMUX_GPIO135__FUNC_WATCHDOG (MTK_PIN_NO(135) | 1)
+
+#define PINMUX_GPIO136__FUNC_GPIO136 (MTK_PIN_NO(136) | 0)
+#define PINMUX_GPIO136__FUNC_AUD_CLK_MOSI (MTK_PIN_NO(136) | 1)
+#define PINMUX_GPIO136__FUNC_AUD_CLK_MISO (MTK_PIN_NO(136) | 2)
+#define PINMUX_GPIO136__FUNC_I2S1_MCK (MTK_PIN_NO(136) | 3)
+#define PINMUX_GPIO136__FUNC_UFS_UNIPRO_SCL (MTK_PIN_NO(136) | 6)
+
+#define PINMUX_GPIO137__FUNC_GPIO137 (MTK_PIN_NO(137) | 0)
+#define PINMUX_GPIO137__FUNC_AUD_SYNC_MOSI (MTK_PIN_NO(137) | 1)
+#define PINMUX_GPIO137__FUNC_AUD_SYNC_MISO (MTK_PIN_NO(137) | 2)
+#define PINMUX_GPIO137__FUNC_I2S1_BCK (MTK_PIN_NO(137) | 3)
+
+#define PINMUX_GPIO138__FUNC_GPIO138 (MTK_PIN_NO(138) | 0)
+#define PINMUX_GPIO138__FUNC_AUD_DAT_MOSI0 (MTK_PIN_NO(138) | 1)
+#define PINMUX_GPIO138__FUNC_AUD_DAT_MISO0 (MTK_PIN_NO(138) | 2)
+#define PINMUX_GPIO138__FUNC_I2S1_LRCK (MTK_PIN_NO(138) | 3)
+#define PINMUX_GPIO138__FUNC_DBG_MON_B24 (MTK_PIN_NO(138) | 7)
+
+#define PINMUX_GPIO139__FUNC_GPIO139 (MTK_PIN_NO(139) | 0)
+#define PINMUX_GPIO139__FUNC_AUD_DAT_MOSI1 (MTK_PIN_NO(139) | 1)
+#define PINMUX_GPIO139__FUNC_AUD_DAT_MISO1 (MTK_PIN_NO(139) | 2)
+#define PINMUX_GPIO139__FUNC_I2S1_DO (MTK_PIN_NO(139) | 3)
+#define PINMUX_GPIO139__FUNC_UFS_MPHY_SDA (MTK_PIN_NO(139) | 6)
+
+#define PINMUX_GPIO140__FUNC_GPIO140 (MTK_PIN_NO(140) | 0)
+#define PINMUX_GPIO140__FUNC_AUD_CLK_MISO (MTK_PIN_NO(140) | 1)
+#define PINMUX_GPIO140__FUNC_AUD_CLK_MOSI (MTK_PIN_NO(140) | 2)
+#define PINMUX_GPIO140__FUNC_I2S0_MCK (MTK_PIN_NO(140) | 3)
+#define PINMUX_GPIO140__FUNC_UFS_UNIPRO_SDA (MTK_PIN_NO(140) | 6)
+
+#define PINMUX_GPIO141__FUNC_GPIO141 (MTK_PIN_NO(141) | 0)
+#define PINMUX_GPIO141__FUNC_AUD_SYNC_MISO (MTK_PIN_NO(141) | 1)
+#define PINMUX_GPIO141__FUNC_AUD_SYNC_MOSI (MTK_PIN_NO(141) | 2)
+#define PINMUX_GPIO141__FUNC_I2S0_BCK (MTK_PIN_NO(141) | 3)
+
+#define PINMUX_GPIO142__FUNC_GPIO142 (MTK_PIN_NO(142) | 0)
+#define PINMUX_GPIO142__FUNC_AUD_DAT_MISO0 (MTK_PIN_NO(142) | 1)
+#define PINMUX_GPIO142__FUNC_AUD_DAT_MOSI0 (MTK_PIN_NO(142) | 2)
+#define PINMUX_GPIO142__FUNC_I2S0_LRCK (MTK_PIN_NO(142) | 3)
+#define PINMUX_GPIO142__FUNC_VOW_DAT_MISO (MTK_PIN_NO(142) | 4)
+#define PINMUX_GPIO142__FUNC_DBG_MON_B25 (MTK_PIN_NO(142) | 7)
+
+#define PINMUX_GPIO143__FUNC_GPIO143 (MTK_PIN_NO(143) | 0)
+#define PINMUX_GPIO143__FUNC_AUD_DAT_MISO1 (MTK_PIN_NO(143) | 1)
+#define PINMUX_GPIO143__FUNC_AUD_DAT_MOSI1 (MTK_PIN_NO(143) | 2)
+#define PINMUX_GPIO143__FUNC_I2S0_DI (MTK_PIN_NO(143) | 3)
+#define PINMUX_GPIO143__FUNC_VOW_CLK_MISO (MTK_PIN_NO(143) | 4)
+#define PINMUX_GPIO143__FUNC_UFS_MPHY_SCL (MTK_PIN_NO(143) | 6)
+#define PINMUX_GPIO143__FUNC_DBG_MON_B26 (MTK_PIN_NO(143) | 7)
+
+#define PINMUX_GPIO144__FUNC_GPIO144 (MTK_PIN_NO(144) | 0)
+#define PINMUX_GPIO144__FUNC_PWRAP_SPI0_MI (MTK_PIN_NO(144) | 1)
+#define PINMUX_GPIO144__FUNC_PWRAP_SPI0_MO (MTK_PIN_NO(144) | 2)
+
+#define PINMUX_GPIO145__FUNC_GPIO145 (MTK_PIN_NO(145) | 0)
+#define PINMUX_GPIO145__FUNC_PWRAP_SPI0_CSN (MTK_PIN_NO(145) | 1)
+
+#define PINMUX_GPIO146__FUNC_GPIO146 (MTK_PIN_NO(146) | 0)
+#define PINMUX_GPIO146__FUNC_PWRAP_SPI0_MO (MTK_PIN_NO(146) | 1)
+#define PINMUX_GPIO146__FUNC_PWRAP_SPI0_MI (MTK_PIN_NO(146) | 2)
+
+#define PINMUX_GPIO147__FUNC_GPIO147 (MTK_PIN_NO(147) | 0)
+#define PINMUX_GPIO147__FUNC_PWRAP_SPI0_CK (MTK_PIN_NO(147) | 1)
+
+#define PINMUX_GPIO148__FUNC_GPIO148 (MTK_PIN_NO(148) | 0)
+#define PINMUX_GPIO148__FUNC_SRCLKENA0 (MTK_PIN_NO(148) | 1)
+
+#define PINMUX_GPIO149__FUNC_GPIO149 (MTK_PIN_NO(149) | 0)
+#define PINMUX_GPIO149__FUNC_SRCLKENA1 (MTK_PIN_NO(149) | 1)
+
+#define PINMUX_GPIO150__FUNC_GPIO150 (MTK_PIN_NO(150) | 0)
+#define PINMUX_GPIO150__FUNC_PWM_A (MTK_PIN_NO(150) | 1)
+#define PINMUX_GPIO150__FUNC_CMFLASH (MTK_PIN_NO(150) | 2)
+#define PINMUX_GPIO150__FUNC_CLKM0 (MTK_PIN_NO(150) | 3)
+#define PINMUX_GPIO150__FUNC_DBG_MON_B30 (MTK_PIN_NO(150) | 7)
+
+#define PINMUX_GPIO151__FUNC_GPIO151 (MTK_PIN_NO(151) | 0)
+#define PINMUX_GPIO151__FUNC_PWM_B (MTK_PIN_NO(151) | 1)
+#define PINMUX_GPIO151__FUNC_CMVREF0 (MTK_PIN_NO(151) | 2)
+#define PINMUX_GPIO151__FUNC_CLKM1 (MTK_PIN_NO(151) | 3)
+#define PINMUX_GPIO151__FUNC_DBG_MON_B20 (MTK_PIN_NO(151) | 7)
+
+#define PINMUX_GPIO152__FUNC_GPIO152 (MTK_PIN_NO(152) | 0)
+#define PINMUX_GPIO152__FUNC_PWM_C (MTK_PIN_NO(152) | 1)
+#define PINMUX_GPIO152__FUNC_CMFLASH (MTK_PIN_NO(152) | 2)
+#define PINMUX_GPIO152__FUNC_CLKM2 (MTK_PIN_NO(152) | 3)
+#define PINMUX_GPIO152__FUNC_DBG_MON_B21 (MTK_PIN_NO(152) | 7)
+
+#define PINMUX_GPIO153__FUNC_GPIO153 (MTK_PIN_NO(153) | 0)
+#define PINMUX_GPIO153__FUNC_PWM_A (MTK_PIN_NO(153) | 1)
+#define PINMUX_GPIO153__FUNC_CMVREF0 (MTK_PIN_NO(153) | 2)
+#define PINMUX_GPIO153__FUNC_CLKM3 (MTK_PIN_NO(153) | 3)
+#define PINMUX_GPIO153__FUNC_DBG_MON_B22 (MTK_PIN_NO(153) | 7)
+
+#define PINMUX_GPIO154__FUNC_GPIO154 (MTK_PIN_NO(154) | 0)
+#define PINMUX_GPIO154__FUNC_SCP_VREQ_VAO (MTK_PIN_NO(154) | 1)
+#define PINMUX_GPIO154__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(154) | 2)
+#define PINMUX_GPIO154__FUNC_DBG_MON_B18 (MTK_PIN_NO(154) | 7)
+
+#define PINMUX_GPIO155__FUNC_GPIO155 (MTK_PIN_NO(155) | 0)
+#define PINMUX_GPIO155__FUNC_ANT_SEL0 (MTK_PIN_NO(155) | 1)
+#define PINMUX_GPIO155__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(155) | 2)
+#define PINMUX_GPIO155__FUNC_CMVREF1 (MTK_PIN_NO(155) | 3)
+#define PINMUX_GPIO155__FUNC_SCP_JTAG_TDI (MTK_PIN_NO(155) | 7)
+
+#define PINMUX_GPIO156__FUNC_GPIO156 (MTK_PIN_NO(156) | 0)
+#define PINMUX_GPIO156__FUNC_ANT_SEL1 (MTK_PIN_NO(156) | 1)
+#define PINMUX_GPIO156__FUNC_SRCLKENAI0 (MTK_PIN_NO(156) | 2)
+#define PINMUX_GPIO156__FUNC_SCL6 (MTK_PIN_NO(156) | 3)
+#define PINMUX_GPIO156__FUNC_KPCOL2 (MTK_PIN_NO(156) | 4)
+#define PINMUX_GPIO156__FUNC_IDDIG (MTK_PIN_NO(156) | 5)
+#define PINMUX_GPIO156__FUNC_SCP_JTAG_TCK (MTK_PIN_NO(156) | 7)
+
+#define PINMUX_GPIO157__FUNC_GPIO157 (MTK_PIN_NO(157) | 0)
+#define PINMUX_GPIO157__FUNC_ANT_SEL2 (MTK_PIN_NO(157) | 1)
+#define PINMUX_GPIO157__FUNC_SRCLKENAI1 (MTK_PIN_NO(157) | 2)
+#define PINMUX_GPIO157__FUNC_SDA6 (MTK_PIN_NO(157) | 3)
+#define PINMUX_GPIO157__FUNC_KPROW2 (MTK_PIN_NO(157) | 4)
+#define PINMUX_GPIO157__FUNC_USB_DRVVBUS (MTK_PIN_NO(157) | 5)
+#define PINMUX_GPIO157__FUNC_SCP_JTAG_TRSTN (MTK_PIN_NO(157) | 7)
+
+#define PINMUX_GPIO158__FUNC_GPIO158 (MTK_PIN_NO(158) | 0)
+#define PINMUX_GPIO158__FUNC_ANT_SEL3 (MTK_PIN_NO(158) | 1)
+
+#define PINMUX_GPIO159__FUNC_GPIO159 (MTK_PIN_NO(159) | 0)
+#define PINMUX_GPIO159__FUNC_ANT_SEL4 (MTK_PIN_NO(159) | 1)
+
+#define PINMUX_GPIO160__FUNC_GPIO160 (MTK_PIN_NO(160) | 0)
+#define PINMUX_GPIO160__FUNC_ANT_SEL5 (MTK_PIN_NO(160) | 1)
+
+#define PINMUX_GPIO161__FUNC_GPIO161 (MTK_PIN_NO(161) | 0)
+#define PINMUX_GPIO161__FUNC_SPI1_A_MI (MTK_PIN_NO(161) | 1)
+#define PINMUX_GPIO161__FUNC_SCP_SPI1_MI (MTK_PIN_NO(161) | 2)
+#define PINMUX_GPIO161__FUNC_IDDIG (MTK_PIN_NO(161) | 3)
+#define PINMUX_GPIO161__FUNC_ANT_SEL6 (MTK_PIN_NO(161) | 4)
+#define PINMUX_GPIO161__FUNC_KPCOL2 (MTK_PIN_NO(161) | 5)
+#define PINMUX_GPIO161__FUNC_PTA_RXD (MTK_PIN_NO(161) | 6)
+#define PINMUX_GPIO161__FUNC_DBG_MON_B19 (MTK_PIN_NO(161) | 7)
+
+#define PINMUX_GPIO162__FUNC_GPIO162 (MTK_PIN_NO(162) | 0)
+#define PINMUX_GPIO162__FUNC_SPI1_A_CSB (MTK_PIN_NO(162) | 1)
+#define PINMUX_GPIO162__FUNC_SCP_SPI1_CS (MTK_PIN_NO(162) | 2)
+#define PINMUX_GPIO162__FUNC_USB_DRVVBUS (MTK_PIN_NO(162) | 3)
+#define PINMUX_GPIO162__FUNC_ANT_SEL5 (MTK_PIN_NO(162) | 4)
+#define PINMUX_GPIO162__FUNC_KPROW2 (MTK_PIN_NO(162) | 5)
+#define PINMUX_GPIO162__FUNC_PTA_TXD (MTK_PIN_NO(162) | 6)
+
+#define PINMUX_GPIO163__FUNC_GPIO163 (MTK_PIN_NO(163) | 0)
+#define PINMUX_GPIO163__FUNC_SPI1_A_MO (MTK_PIN_NO(163) | 1)
+#define PINMUX_GPIO163__FUNC_SCP_SPI1_MO (MTK_PIN_NO(163) | 2)
+#define PINMUX_GPIO163__FUNC_SDA1 (MTK_PIN_NO(163) | 3)
+#define PINMUX_GPIO163__FUNC_ANT_SEL4 (MTK_PIN_NO(163) | 4)
+#define PINMUX_GPIO163__FUNC_CMMCLK2 (MTK_PIN_NO(163) | 5)
+#define PINMUX_GPIO163__FUNC_DMIC_CLK (MTK_PIN_NO(163) | 6)
+
+#define PINMUX_GPIO164__FUNC_GPIO164 (MTK_PIN_NO(164) | 0)
+#define PINMUX_GPIO164__FUNC_SPI1_A_CLK (MTK_PIN_NO(164) | 1)
+#define PINMUX_GPIO164__FUNC_SCP_SPI1_CK (MTK_PIN_NO(164) | 2)
+#define PINMUX_GPIO164__FUNC_SCL1 (MTK_PIN_NO(164) | 3)
+#define PINMUX_GPIO164__FUNC_ANT_SEL3 (MTK_PIN_NO(164) | 4)
+#define PINMUX_GPIO164__FUNC_CMMCLK3 (MTK_PIN_NO(164) | 5)
+#define PINMUX_GPIO164__FUNC_DMIC_DAT (MTK_PIN_NO(164) | 6)
+
+#define PINMUX_GPIO165__FUNC_GPIO165 (MTK_PIN_NO(165) | 0)
+#define PINMUX_GPIO165__FUNC_PWM_B (MTK_PIN_NO(165) | 1)
+#define PINMUX_GPIO165__FUNC_CMMCLK2 (MTK_PIN_NO(165) | 2)
+#define PINMUX_GPIO165__FUNC_SCP_VREQ_VAO (MTK_PIN_NO(165) | 3)
+#define PINMUX_GPIO165__FUNC_TDM_MCK_2ND (MTK_PIN_NO(165) | 6)
+#define PINMUX_GPIO165__FUNC_SCP_JTAG_TDO (MTK_PIN_NO(165) | 7)
+
+#define PINMUX_GPIO166__FUNC_GPIO166 (MTK_PIN_NO(166) | 0)
+#define PINMUX_GPIO166__FUNC_ANT_SEL6 (MTK_PIN_NO(166) | 1)
+
+#define PINMUX_GPIO167__FUNC_GPIO167 (MTK_PIN_NO(167) | 0)
+#define PINMUX_GPIO167__FUNC_RFIC0_BSI_EN (MTK_PIN_NO(167) | 1)
+#define PINMUX_GPIO167__FUNC_SPM_BSI_EN (MTK_PIN_NO(167) | 2)
+
+#define PINMUX_GPIO168__FUNC_GPIO168 (MTK_PIN_NO(168) | 0)
+#define PINMUX_GPIO168__FUNC_RFIC0_BSI_CK (MTK_PIN_NO(168) | 1)
+#define PINMUX_GPIO168__FUNC_SPM_BSI_CK (MTK_PIN_NO(168) | 2)
+
+#define PINMUX_GPIO169__FUNC_GPIO169 (MTK_PIN_NO(169) | 0)
+#define PINMUX_GPIO169__FUNC_PWM_C (MTK_PIN_NO(169) | 1)
+#define PINMUX_GPIO169__FUNC_CMMCLK3 (MTK_PIN_NO(169) | 2)
+#define PINMUX_GPIO169__FUNC_CMVREF1 (MTK_PIN_NO(169) | 3)
+#define PINMUX_GPIO169__FUNC_ANT_SEL7 (MTK_PIN_NO(169) | 4)
+#define PINMUX_GPIO169__FUNC_AGPS_SYNC (MTK_PIN_NO(169) | 5)
+#define PINMUX_GPIO169__FUNC_TDM_BCK_2ND (MTK_PIN_NO(169) | 6)
+#define PINMUX_GPIO169__FUNC_SCP_JTAG_TMS (MTK_PIN_NO(169) | 7)
+
+#define PINMUX_GPIO170__FUNC_GPIO170 (MTK_PIN_NO(170) | 0)
+#define PINMUX_GPIO170__FUNC_I2S1_BCK (MTK_PIN_NO(170) | 1)
+#define PINMUX_GPIO170__FUNC_I2S3_BCK (MTK_PIN_NO(170) | 2)
+#define PINMUX_GPIO170__FUNC_SCL7 (MTK_PIN_NO(170) | 3)
+#define PINMUX_GPIO170__FUNC_I2S5_BCK (MTK_PIN_NO(170) | 4)
+#define PINMUX_GPIO170__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(170) | 5)
+#define PINMUX_GPIO170__FUNC_TDM_LRCK_2ND (MTK_PIN_NO(170) | 6)
+#define PINMUX_GPIO170__FUNC_ANT_SEL3 (MTK_PIN_NO(170) | 7)
+
+#define PINMUX_GPIO171__FUNC_GPIO171 (MTK_PIN_NO(171) | 0)
+#define PINMUX_GPIO171__FUNC_I2S1_LRCK (MTK_PIN_NO(171) | 1)
+#define PINMUX_GPIO171__FUNC_I2S3_LRCK (MTK_PIN_NO(171) | 2)
+#define PINMUX_GPIO171__FUNC_SDA7 (MTK_PIN_NO(171) | 3)
+#define PINMUX_GPIO171__FUNC_I2S5_LRCK (MTK_PIN_NO(171) | 4)
+#define PINMUX_GPIO171__FUNC_URXD1 (MTK_PIN_NO(171) | 5)
+#define PINMUX_GPIO171__FUNC_TDM_DATA0_2ND (MTK_PIN_NO(171) | 6)
+#define PINMUX_GPIO171__FUNC_ANT_SEL4 (MTK_PIN_NO(171) | 7)
+
+#define PINMUX_GPIO172__FUNC_GPIO172 (MTK_PIN_NO(172) | 0)
+#define PINMUX_GPIO172__FUNC_I2S1_DO (MTK_PIN_NO(172) | 1)
+#define PINMUX_GPIO172__FUNC_I2S3_DO (MTK_PIN_NO(172) | 2)
+#define PINMUX_GPIO172__FUNC_SCL8 (MTK_PIN_NO(172) | 3)
+#define PINMUX_GPIO172__FUNC_I2S5_DO (MTK_PIN_NO(172) | 4)
+#define PINMUX_GPIO172__FUNC_UTXD1 (MTK_PIN_NO(172) | 5)
+#define PINMUX_GPIO172__FUNC_TDM_DATA1_2ND (MTK_PIN_NO(172) | 6)
+#define PINMUX_GPIO172__FUNC_ANT_SEL5 (MTK_PIN_NO(172) | 7)
+
+#define PINMUX_GPIO173__FUNC_GPIO173 (MTK_PIN_NO(173) | 0)
+#define PINMUX_GPIO173__FUNC_I2S1_MCK (MTK_PIN_NO(173) | 1)
+#define PINMUX_GPIO173__FUNC_I2S3_MCK (MTK_PIN_NO(173) | 2)
+#define PINMUX_GPIO173__FUNC_SDA8 (MTK_PIN_NO(173) | 3)
+#define PINMUX_GPIO173__FUNC_I2S5_MCK (MTK_PIN_NO(173) | 4)
+#define PINMUX_GPIO173__FUNC_UCTS0 (MTK_PIN_NO(173) | 5)
+#define PINMUX_GPIO173__FUNC_TDM_DATA2_2ND (MTK_PIN_NO(173) | 6)
+#define PINMUX_GPIO173__FUNC_ANT_SEL6 (MTK_PIN_NO(173) | 7)
+
+#define PINMUX_GPIO174__FUNC_GPIO174 (MTK_PIN_NO(174) | 0)
+#define PINMUX_GPIO174__FUNC_I2S2_DI (MTK_PIN_NO(174) | 1)
+#define PINMUX_GPIO174__FUNC_I2S0_DI (MTK_PIN_NO(174) | 2)
+#define PINMUX_GPIO174__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(174) | 3)
+#define PINMUX_GPIO174__FUNC_I2S2_DI2 (MTK_PIN_NO(174) | 4)
+#define PINMUX_GPIO174__FUNC_URTS0 (MTK_PIN_NO(174) | 5)
+#define PINMUX_GPIO174__FUNC_TDM_DATA3_2ND (MTK_PIN_NO(174) | 6)
+#define PINMUX_GPIO174__FUNC_ANT_SEL7 (MTK_PIN_NO(174) | 7)
+
+#define PINMUX_GPIO175__FUNC_GPIO175 (MTK_PIN_NO(175) | 0)
+#define PINMUX_GPIO175__FUNC_ANT_SEL7 (MTK_PIN_NO(175) | 1)
+
+#define PINMUX_GPIO176__FUNC_GPIO176 (MTK_PIN_NO(176) | 0)
+
+#define PINMUX_GPIO177__FUNC_GPIO177 (MTK_PIN_NO(177) | 0)
+
+#define PINMUX_GPIO178__FUNC_GPIO178 (MTK_PIN_NO(178) | 0)
+
+#define PINMUX_GPIO179__FUNC_GPIO179 (MTK_PIN_NO(179) | 0)
+
+#endif /* __MT8183-PINFUNC_H */

diff --git a/arch/arm64/boot/dts/nvidia/Makefile b/arch/arm64/boot/dts/nvidia/Makefile
index 6b8ab55..bcd018c 100644 (file)
--- a/arch/arm64/boot/dts/nvidia/Makefile
+++ b/arch/arm64/boot/dts/nvidia/Makefile
@@ -3,6 +3,7 @@ dtb-$(CONFIG_ARCH_TEGRA_132_SOC) += tegra132-norrin.dtb
 dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-p2371-0000.dtb
 dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-p2371-2180.dtb
 dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-p2571.dtb
+dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-p3450-0000.dtb
 dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-smaug.dtb
 dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-p2894-0050-a08.dtb
 dtb-$(CONFIG_ARCH_TEGRA_186_SOC) += tegra186-p2771-0000.dtb

diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts b/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts
index 31457f3..75ee6cf 100644 (file)
--- a/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts
+++ b/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts
@@ -58,6 +58,93 @@
                status = "okay";
        };
 
+       padctl@3520000 {
+               status = "okay";
+
+               avdd-pll-erefeut-supply = <&vdd_1v8_pll>;
+               avdd-usb-supply = <&vdd_3v3_sys>;
+               dvdd-pex-supply = <&vdd_pex>;
+               dvdd-pex-pll-supply = <&vdd_pex>;
+               hvdd-pex-supply = <&vdd_1v8>;
+               hvdd-pex-pll-supply = <&vdd_1v8>;
+               vclamp-usb-supply = <&vdd_1v8>;
+               vddio-hsic-supply = <&gnd>;
+
+               pads {
+                       usb2 {
+                               status = "okay";
+
+                               lanes {
+                                       usb2-0 {
+                                               nvidia,function = "xusb";
+                                               status = "okay";
+                                       };
+
+                                       usb2-1 {
+                                               nvidia,function = "xusb";
+                                               status = "okay";
+                                       };
+
+                                       usb2-2 {
+                                               nvidia,function = "xusb";
+                                               status = "okay";
+                                       };
+                               };
+                       };
+
+                       usb3 {
+                               status = "okay";
+
+                               lanes {
+                                       usb3-0 {
+                                               nvidia,function = "xusb";
+                                               status = "okay";
+                                       };
+
+                                       usb3-1 {
+                                               nvidia,function = "xusb";
+                                               status = "okay";
+                                       };
+
+                                       usb3-2 {
+                                               nvidia,function = "xusb";
+                                               status = "okay";
+                                       };
+                               };
+                       };
+               };
+
+               ports {
+                       usb2-0 {
+                               status = "okay";
+                               mode = "otg";
+
+                               vbus-supply = <&vdd_usb0>;
+                       };
+
+                       usb2-1 {
+                               status = "okay";
+                               mode = "host";
+
+                               vbus-supply = <&vdd_usb1>;
+                       };
+
+                       usb3-0 {
+                               nvidia,usb2-companion = <1>;
+                               status = "okay";
+                       };
+               };
+       };
+
+       usb@3530000 {
+               status = "okay";
+
+               phys = <&{/padctl@3520000/pads/usb2/lanes/usb2-0}>,
+                      <&{/padctl@3520000/pads/usb2/lanes/usb2-1}>,
+                      <&{/padctl@3520000/pads/usb3/lanes/usb3-0}>;
+               phy-names = "usb2-0", "usb2-1", "usb3-0";
+       };
+
        pcie@10003000 {
                status = "okay";
 
@@ -182,5 +269,33 @@
 
                        vin-supply = <&vdd_5v0_sys>;
                };
+
+               vdd_usb0: regulator@102 {
+                       compatible = "regulator-fixed";
+                       reg = <102>;
+
+                       regulator-name = "VDD_USB0";
+                       regulator-min-microvolt = <5000000>;
+                       regulator-max-microvolt = <5000000>;
+
+                       gpio = <&gpio TEGRA_MAIN_GPIO(L, 4) GPIO_ACTIVE_HIGH>;
+                       enable-active-high;
+
+                       vin-supply = <&vdd_5v0_sys>;
+               };
+
+               vdd_usb1: regulator@103 {
+                       compatible = "regulator-fixed";
+                       reg = <103>;
+
+                       regulator-name = "VDD_USB1";
+                       regulator-min-microvolt = <5000000>;
+                       regulator-max-microvolt = <5000000>;
+
+                       gpio = <&gpio TEGRA_MAIN_GPIO(L, 5) GPIO_ACTIVE_HIGH>;
+                       enable-active-high;
+
+                       vin-supply = <&vdd_5v0_sys>;
+               };
        };
 };

diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi
index 89a2da4..64686b0 100644 (file)
--- a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi
@@ -268,43 +268,30 @@
                                                regulator-name = "AVDD_DSI_CSI_1V2";
                                                regulator-min-microvolt = <1200000>;
                                                regulator-max-microvolt = <1200000>;
-                                               /* XXX */
-                                               regulator-always-on;
-                                               regulator-boot-on;
                                        };
 
                                        vdd_1v8: sd2 {
                                                regulator-name = "VDD_1V8";
                                                regulator-min-microvolt = <1800000>;
                                                regulator-max-microvolt = <1800000>;
-                                               /* XXX */
-                                               regulator-always-on;
-                                               regulator-boot-on;
                                        };
 
                                        vdd_3v3_sys: sd3 {
                                                regulator-name = "VDD_3V3_SYS";
                                                regulator-min-microvolt = <3300000>;
                                                regulator-max-microvolt = <3300000>;
-                                               /* XXX */
-                                               regulator-always-on;
-                                               regulator-boot-on;
                                        };
 
-                                       ldo0 {
+                                       vdd_1v8_pll: ldo0 {
                                                regulator-name = "VDD_1V8_AP_PLL";
                                                regulator-min-microvolt = <1800000>;
                                                regulator-max-microvolt = <1800000>;
-                                               /* XXX */
-                                               regulator-always-on;
-                                               regulator-boot-on;
                                        };
 
                                        ldo2 {
                                                regulator-name = "VDDIO_3V3_AOHV";
                                                regulator-min-microvolt = <3300000>;
                                                regulator-max-microvolt = <3300000>;
-                                               /* XXX */
                                                regulator-always-on;
                                                regulator-boot-on;
                                        };
@@ -331,18 +318,12 @@
                                                regulator-name = "VDD_HDMI_1V05";
                                                regulator-min-microvolt = <1050000>;
                                                regulator-max-microvolt = <1050000>;
-                                               /* XXX */
-                                               regulator-always-on;
-                                               regulator-boot-on;
                                        };
 
                                        vdd_pex: ldo8 {
                                                regulator-name = "VDD_PEX_1V05";
                                                regulator-min-microvolt = <1050000>;
                                                regulator-max-microvolt = <1050000>;
-                                               /* XXX */
-                                               regulator-always-on;
-                                               regulator-boot-on;
                                        };
                                };
                        };
@@ -360,10 +341,21 @@
                #address-cells = <1>;
                #size-cells = <0>;
 
-               vdd_5v0_sys: regulator@0 {
+               gnd: regulator@0 {
                        compatible = "regulator-fixed";
                        reg = <0>;
 
+                       regulator-name = "GND";
+                       regulator-min-microvolt = <0>;
+                       regulator-max-microvolt = <0>;
+                       regulator-always-on;
+                       regulator-boot-on;
+               };
+
+               vdd_5v0_sys: regulator@1 {
+                       compatible = "regulator-fixed";
+                       reg = <1>;
+
                        regulator-name = "VDD_5V0_SYS";
                        regulator-min-microvolt = <5000000>;
                        regulator-max-microvolt = <5000000>;
@@ -371,18 +363,14 @@
                        regulator-boot-on;
                };
 
-               vdd_1v8_ap: regulator@1 {
+               vdd_1v8_ap: regulator@2 {
                        compatible = "regulator-fixed";
-                       reg = <1>;
+                       reg = <2>;
 
                        regulator-name = "VDD_1V8_AP";
                        regulator-min-microvolt = <1800000>;
                        regulator-max-microvolt = <1800000>;
 
-                       /* XXX */
-                       regulator-always-on;
-                       regulator-boot-on;
-
                        gpio = <&pmic 1 GPIO_ACTIVE_HIGH>;
                        enable-active-high;
 

diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
index 97aeb94..f0bb6ce 100644 (file)
--- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
@@ -317,10 +317,11 @@
                nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x0a>;
                nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>;
                nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x0a>;
-               nvidia,default-tap = <0x5>;
-               nvidia,default-trim = <0x9>;
+               nvidia,default-tap = <0x9>;
+               nvidia,default-trim = <0x5>;
                nvidia,dqs-trim = <63>;
                mmc-hs400-1_8v;
+               supports-cqe;
                status = "disabled";
        };
 
@@ -340,6 +341,141 @@
                status = "disabled";
        };
 
+       padctl: padctl@3520000 {
+               compatible = "nvidia,tegra186-xusb-padctl";
+               reg = <0x0 0x03520000 0x0 0x1000>,
+                     <0x0 0x03540000 0x0 0x1000>;
+               reg-names = "padctl", "ao";
+
+               resets = <&bpmp TEGRA186_RESET_XUSB_PADCTL>;
+               reset-names = "padctl";
+
+               status = "disabled";
+
+               pads {
+                       usb2 {
+                               clocks = <&bpmp TEGRA186_CLK_USB2_TRK>;
+                               clock-names = "trk";
+                               status = "disabled";
+
+                               lanes {
+                                       usb2-0 {
+                                               status = "disabled";
+                                               #phy-cells = <0>;
+                                       };
+
+                                       usb2-1 {
+                                               status = "disabled";
+                                               #phy-cells = <0>;
+                                       };
+
+                                       usb2-2 {
+                                               status = "disabled";
+                                               #phy-cells = <0>;
+                                       };
+                               };
+                       };
+
+                       hsic {
+                               clocks = <&bpmp TEGRA186_CLK_HSIC_TRK>;
+                               clock-names = "trk";
+                               status = "disabled";
+
+                               lanes {
+                                       hsic-0 {
+                                               status = "disabled";
+                                               #phy-cells = <0>;
+                                       };
+                               };
+                       };
+
+                       usb3 {
+                               status = "disabled";
+
+                               lanes {
+                                       usb3-0 {
+                                               status = "disabled";
+                                               #phy-cells = <0>;
+                                       };
+
+                                       usb3-1 {
+                                               status = "disabled";
+                                               #phy-cells = <0>;
+                                       };
+
+                                       usb3-2 {
+                                               status = "disabled";
+                                               #phy-cells = <0>;
+                                       };
+                               };
+                       };
+               };
+
+               ports {
+                       usb2-0 {
+                               status = "disabled";
+                       };
+
+                       usb2-1 {
+                               status = "disabled";
+                       };
+
+                       usb2-2 {
+                               status = "disabled";
+                       };
+
+                       hsic-0 {
+                               status = "disabled";
+                       };
+
+                       usb3-0 {
+                               status = "disabled";
+                       };
+
+                       usb3-1 {
+                               status = "disabled";
+                       };
+
+                       usb3-2 {
+                               status = "disabled";
+                       };
+               };
+       };
+
+       usb@3530000 {
+               compatible = "nvidia,tegra186-xusb";
+               reg = <0x0 0x03530000 0x0 0x8000>,
+                     <0x0 0x03538000 0x0 0x1000>;
+               reg-names = "hcd", "fpci";
+
+               interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
+
+               clocks = <&bpmp TEGRA186_CLK_XUSB_HOST>,
+                        <&bpmp TEGRA186_CLK_XUSB_FALCON>,
+                        <&bpmp TEGRA186_CLK_XUSB_SS>,
+                        <&bpmp TEGRA186_CLK_XUSB_CORE_SS>,
+                        <&bpmp TEGRA186_CLK_CLK_M>,
+                        <&bpmp TEGRA186_CLK_XUSB_FS>,
+                        <&bpmp TEGRA186_CLK_PLLU>,
+                        <&bpmp TEGRA186_CLK_CLK_M>,
+                        <&bpmp TEGRA186_CLK_PLLE>;
+               clock-names = "xusb_host", "xusb_falcon_src", "xusb_ss",
+                             "xusb_ss_src", "xusb_hs_src", "xusb_fs_src",
+                             "pll_u_480m", "clk_m", "pll_e";
+
+               power-domains = <&bpmp TEGRA186_POWER_DOMAIN_XUSBC>,
+                               <&bpmp TEGRA186_POWER_DOMAIN_XUSBA>;
+               power-domain-names = "xusb_host", "xusb_ss";
+               nvidia,xusb-padctl = <&padctl>;
+
+               status = "disabled";
+
+               #address-cells = <1>;
+               #size-cells = <0>;
+       };
+
        fuse@3820000 {
                compatible = "nvidia,tegra186-efuse";
                reg = <0x0 0x03820000 0x0 0x10000>;

diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi b/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi
index 246c1eb..0fd5bd2 100644 (file)
--- a/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi
@@ -256,6 +256,7 @@
                                interrupt-parent = <&gpio>;
                                interrupts = <TEGRA194_MAIN_GPIO(H, 2)
                                              IRQ_TYPE_LEVEL_LOW>;
+                               vcc-supply = <&vdd_1v8ls>;
 
                                #thermal-sensor-cells = <1>;
                        };

diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts b/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts
index b62e969..73801b4 100644 (file)
--- a/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts
+++ b/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts
@@ -57,8 +57,6 @@
                pwms = <&pwm4 0 45334>;
 
                cooling-levels = <0 64 128 255>;
-               cooling-min-state = <0>;
-               cooling-max-state = <3>;
                #cooling-cells = <2>;
        };
 

diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi
index 053458a..4dcd0d3 100644 (file)
--- a/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi
@@ -305,6 +305,12 @@
                cpu@3 {
                        enable-method = "psci";
                };
+
+               idle-states {
+                       cpu-sleep {
+                               status = "okay";
+                       };
+               };
        };
 
        psci {

diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts b/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts
index 9fad0d2..5a57396 100644 (file)
--- a/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts
+++ b/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts
@@ -99,4 +99,16 @@
                pinctrl-0 = <&dvfs_pwm_active_state>;
                pinctrl-1 = <&dvfs_pwm_inactive_state>;
        };
+
+       aconnect@702c0000 {
+               status = "okay";
+
+               dma@702e2000 {
+                       status = "okay";
+               };
+
+               agic@702f9000 {
+                       status = "okay";
+               };
+       };
 };

diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi
index 95e890d..a7dc319 100644 (file)
--- a/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi
@@ -1352,6 +1352,11 @@
        padctl@7009f000 {
                status = "okay";
 
+               avdd-pll-utmip-supply = <&vdd_1v8>;
+               avdd-pll-uerefe-supply = <&avdd_1v05_pll>;
+               dvdd-pex-pll-supply = <&vdd_pex_1v05>;
+               hvdd-pex-pll-e-supply = <&vdd_1v8>;
+
                pads {
                        usb2 {
                                status = "okay";

diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2894.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2894.dtsi
index 3ddf173..88a4b93 100644 (file)
--- a/arch/arm64/boot/dts/nvidia/tegra210-p2894.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra210-p2894.dtsi
@@ -1629,6 +1629,12 @@
                cpu@3 {
                        enable-method = "psci";
                };
+
+               idle-states {
+                       cpu-sleep {
+                               status = "okay";
+                       };
+               };
        };
 
        psci {

diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts
new file mode 100644 (file)
index 0000000..5d01819
--- /dev/null
+++ b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts
@@ -0,0 +1,650 @@
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+
+#include <dt-bindings/input/gpio-keys.h>
+#include <dt-bindings/input/linux-event-codes.h>
+#include <dt-bindings/mfd/max77620.h>
+
+#include "tegra210.dtsi"
+
+/ {
+       model = "NVIDIA Jetson Nano Developer Kit";
+       compatible = "nvidia,p3450-0000", "nvidia,tegra210";
+
+       aliases {
+               ethernet = "/pcie@1003000/pci@2,0/ethernet@0,0";
+               rtc0 = "/i2c@7000d000/pmic@3c";
+               rtc1 = "/rtc@7000e000";
+               serial0 = &uarta;
+       };
+
+       chosen {
+               stdout-path = "serial0:115200n8";
+       };
+
+       memory {
+               device_type = "memory";
+               reg = <0x0 0x80000000 0x1 0x0>;
+       };
+
+       pcie@1003000 {
+               status = "okay";
+
+               avdd-pll-uerefe-supply = <&vdd_pex_1v05>;
+               hvddio-pex-supply = <&vdd_1v8>;
+               dvddio-pex-supply = <&vdd_pex_1v05>;
+               dvdd-pex-pll-supply = <&vdd_pex_1v05>;
+               hvdd-pex-pll-e-supply = <&vdd_1v8>;
+               vddio-pex-ctl-supply = <&vdd_1v8>;
+
+               pci@1,0 {
+                       phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-1}>,
+                              <&{/padctl@7009f000/pads/pcie/lanes/pcie-2}>,
+                              <&{/padctl@7009f000/pads/pcie/lanes/pcie-3}>,
+                              <&{/padctl@7009f000/pads/pcie/lanes/pcie-4}>;
+                       phy-names = "pcie-0", "pcie-1", "pcie-2", "pcie-3";
+                       nvidia,num-lanes = <4>;
+                       status = "okay";
+               };
+
+               pci@2,0 {
+                       phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-0}>;
+                       phy-names = "pcie-0";
+                       status = "okay";
+
+                       ethernet@0,0 {
+                               reg = <0x000000 0 0 0 0>;
+                               local-mac-address = [ 00 00 00 00 00 00 ];
+                       };
+               };
+       };
+
+       host1x@50000000 {
+               dpaux@54040000 {
+                       status = "okay";
+               };
+
+               sor@54580000 {
+                       status = "okay";
+
+                       avdd-io-supply = <&avdd_1v05>;
+                       vdd-pll-supply = <&vdd_1v8>;
+                       hdmi-supply = <&vdd_hdmi>;
+
+                       nvidia,ddc-i2c-bus = <&hdmi_ddc>;
+                       nvidia,hpd-gpio = <&gpio TEGRA_GPIO(CC, 1)
+                                          GPIO_ACTIVE_LOW>;
+                       nvidia,xbar-cfg = <0 1 2 3 4>;
+               };
+       };
+
+       gpu@57000000 {
+               vdd-supply = <&vdd_gpu>;
+               status = "okay";
+       };
+
+       /* debug port */
+       serial@70006000 {
+               status = "okay";
+       };
+
+       hdmi_ddc: i2c@7000c700 {
+               status = "okay";
+               clock-frequency = <100000>;
+       };
+
+       i2c@7000d000 {
+               status = "okay";
+               clock-frequency = <400000>;
+
+               pmic: pmic@3c {
+                       compatible = "maxim,max77620";
+                       reg = <0x3c>;
+                       interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+
+                       #interrupt-cells = <2>;
+                       interrupt-controller;
+
+                       #gpio-cells = <2>;
+                       gpio-controller;
+
+                       pinctrl-names = "default";
+                       pinctrl-0 = <&max77620_default>;
+
+                       max77620_default: pinmux {
+                               gpio0 {
+                                       pins = "gpio0";
+                                       function = "gpio";
+                               };
+
+                               gpio1 {
+                                       pins = "gpio1";
+                                       function = "fps-out";
+                                       drive-push-pull = <1>;
+                                       maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
+                                       maxim,active-fps-power-up-slot = <0>;
+                                       maxim,active-fps-power-down-slot = <7>;
+                               };
+
+                               gpio2 {
+                                       pins = "gpio2";
+                                       function = "fps-out";
+                                       drive-open-drain = <1>;
+                                       maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
+                                       maxim,active-fps-power-up-slot = <0>;
+                                       maxim,active-fps-power-down-slot = <7>;
+                               };
+
+                               gpio3 {
+                                       pins = "gpio3";
+                                       function = "fps-out";
+                                       drive-open-drain = <1>;
+                                       maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
+                                       maxim,active-fps-power-up-slot = <4>;
+                                       maxim,active-fps-power-down-slot = <3>;
+                               };
+
+                               gpio4 {
+                                       pins = "gpio4";
+                                       function = "32k-out1";
+                               };
+
+                               gpio5_6_7 {
+                                       pins = "gpio5", "gpio6", "gpio7";
+                                       function = "gpio";
+                                       drive-push-pull = <1>;
+                               };
+                       };
+
+                       fps {
+                               fps0 {
+                                       maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>;
+                                       maxim,suspend-fps-time-period-us = <5120>;
+                               };
+
+                               fps1 {
+                                       maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN1>;
+                                       maxim,suspend-fps-time-period-us = <5120>;
+                               };
+
+                               fps2 {
+                                       maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>;
+                               };
+                       };
+
+                       regulators {
+                               in-ldo0-1-supply = <&vdd_pre>;
+                               in-ldo2-supply = <&vdd_3v3_sys>;
+                               in-ldo3-5-supply = <&vdd_1v8>;
+                               in-ldo4-6-supply = <&vdd_5v0_sys>;
+                               in-ldo7-8-supply = <&vdd_pre>;
+                               in-sd0-supply = <&vdd_5v0_sys>;
+                               in-sd1-supply = <&vdd_5v0_sys>;
+                               in-sd2-supply = <&vdd_5v0_sys>;
+                               in-sd3-supply = <&vdd_5v0_sys>;
+
+                               vdd_soc: sd0 {
+                                       regulator-name = "VDD_SOC";
+                                       regulator-min-microvolt = <1000000>;
+                                       regulator-max-microvolt = <1170000>;
+                                       regulator-enable-ramp-delay = <146>;
+                                       regulator-disable-ramp-delay = <4080>;
+                                       regulator-ramp-delay = <27500>;
+                                       regulator-ramp-delay-scale = <300>;
+                                       regulator-always-on;
+                                       regulator-boot-on;
+
+                                       maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
+                                       maxim,active-fps-power-up-slot = <1>;
+                                       maxim,active-fps-power-down-slot = <6>;
+                               };
+
+                               vdd_ddr: sd1 {
+                                       regulator-name = "VDD_DDR_1V1_PMIC";
+                                       regulator-min-microvolt = <1150000>;
+                                       regulator-max-microvolt = <1150000>;
+                                       regulator-enable-ramp-delay = <176>;
+                                       regulator-disable-ramp-delay = <145800>;
+                                       regulator-ramp-delay = <27500>;
+                                       regulator-ramp-delay-scale = <300>;
+                                       regulator-always-on;
+                                       regulator-boot-on;
+
+                                       maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
+                                       maxim,active-fps-power-up-slot = <5>;
+                                       maxim,active-fps-power-down-slot = <2>;
+                               };
+
+                               vdd_pre: sd2 {
+                                       regulator-name = "VDD_PRE_REG_1V35";
+                                       regulator-min-microvolt = <1350000>;
+                                       regulator-max-microvolt = <1350000>;
+                                       regulator-enable-ramp-delay = <176>;
+                                       regulator-disable-ramp-delay = <32000>;
+                                       regulator-ramp-delay = <27500>;
+                                       regulator-ramp-delay-scale = <350>;
+                                       regulator-always-on;
+                                       regulator-boot-on;
+
+                                       maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
+                                       maxim,active-fps-power-up-slot = <2>;
+                                       maxim,active-fps-power-down-slot = <5>;
+                               };
+
+                               vdd_1v8: sd3 {
+                                       regulator-name = "VDD_1V8";
+                                       regulator-min-microvolt = <1800000>;
+                                       regulator-max-microvolt = <1800000>;
+                                       regulator-enable-ramp-delay = <242>;
+                                       regulator-disable-ramp-delay = <118000>;
+                                       regulator-ramp-delay = <27500>;
+                                       regulator-ramp-delay-scale = <360>;
+                                       regulator-always-on;
+                                       regulator-boot-on;
+
+                                       maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
+                                       maxim,active-fps-power-up-slot = <3>;
+                                       maxim,active-fps-power-down-slot = <4>;
+                               };
+
+                               vdd_sys_1v2: ldo0 {
+                                       regulator-name = "AVDD_SYS_1V2";
+                                       regulator-min-microvolt = <1200000>;
+                                       regulator-max-microvolt = <1200000>;
+                                       regulator-enable-ramp-delay = <26>;
+                                       regulator-disable-ramp-delay = <626>;
+                                       regulator-ramp-delay = <100000>;
+                                       regulator-ramp-delay-scale = <200>;
+                                       regulator-always-on;
+                                       regulator-boot-on;
+
+                                       maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
+                                       maxim,active-fps-power-up-slot = <0>;
+                                       maxim,active-fps-power-down-slot = <7>;
+                               };
+
+                               vdd_pex_1v05: ldo1 {
+                                       regulator-name = "VDD_PEX_1V05";
+                                       regulator-min-microvolt = <1050000>;
+                                       regulator-max-microvolt = <1050000>;
+                                       regulator-enable-ramp-delay = <22>;
+                                       regulator-disable-ramp-delay = <650>;
+                                       regulator-ramp-delay = <100000>;
+                                       regulator-ramp-delay-scale = <200>;
+
+                                       maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
+                                       maxim,active-fps-power-up-slot = <0>;
+                                       maxim,active-fps-power-down-slot = <7>;
+                               };
+
+                               vddio_sdmmc: ldo2 {
+                                       regulator-name = "VDDIO_SDMMC";
+                                       regulator-min-microvolt = <1800000>;
+                                       regulator-max-microvolt = <3300000>;
+                                       regulator-enable-ramp-delay = <62>;
+                                       regulator-disable-ramp-delay = <650>;
+                                       regulator-ramp-delay = <100000>;
+                                       regulator-ramp-delay-scale = <200>;
+
+                                       maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
+                                       maxim,active-fps-power-up-slot = <0>;
+                                       maxim,active-fps-power-down-slot = <7>;
+                               };
+
+                               ldo3 {
+                                       status = "disabled";
+                               };
+
+                               vdd_rtc: ldo4 {
+                                       regulator-name = "VDD_RTC";
+                                       regulator-min-microvolt = <850000>;
+                                       regulator-max-microvolt = <1100000>;
+                                       regulator-enable-ramp-delay = <22>;
+                                       regulator-disable-ramp-delay = <610>;
+                                       regulator-ramp-delay = <100000>;
+                                       regulator-ramp-delay-scale = <200>;
+                                       regulator-disable-active-discharge;
+                                       regulator-always-on;
+                                       regulator-boot-on;
+
+                                       maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
+                                       maxim,active-fps-power-up-slot = <1>;
+                                       maxim,active-fps-power-down-slot = <6>;
+                               };
+
+                               ldo5 {
+                                       status = "disabled";
+                               };
+
+                               ldo6 {
+                                       status = "disabled";
+                               };
+
+                               avdd_1v05_pll: ldo7 {
+                                       regulator-name = "AVDD_1V05_PLL";
+                                       regulator-min-microvolt = <1050000>;
+                                       regulator-max-microvolt = <1050000>;
+                                       regulator-enable-ramp-delay = <24>;
+                                       regulator-disable-ramp-delay = <2768>;
+                                       regulator-ramp-delay = <100000>;
+                                       regulator-ramp-delay-scale = <200>;
+
+                                       maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
+                                       maxim,active-fps-power-up-slot = <3>;
+                                       maxim,active-fps-power-down-slot = <4>;
+                               };
+
+                               avdd_1v05: ldo8 {
+                                       regulator-name = "AVDD_SATA_HDMI_DP_1V05";
+                                       regulator-min-microvolt = <1050000>;
+                                       regulator-max-microvolt = <1050000>;
+                                       regulator-enable-ramp-delay = <22>;
+                                       regulator-disable-ramp-delay = <1160>;
+                                       regulator-ramp-delay = <100000>;
+                                       regulator-ramp-delay-scale = <200>;
+
+                                       maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
+                                       maxim,active-fps-power-up-slot = <6>;
+                                       maxim,active-fps-power-down-slot = <1>;
+                               };
+                       };
+               };
+       };
+
+       pmc@7000e400 {
+               nvidia,invert-interrupt;
+       };
+
+       hda@70030000 {
+               nvidia,model = "jetson-nano-hda";
+
+               status = "okay";
+       };
+
+       usb@70090000 {
+               phys = <&{/padctl@7009f000/pads/usb2/lanes/usb2-0}>,
+                      <&{/padctl@7009f000/pads/usb2/lanes/usb2-1}>,
+                      <&{/padctl@7009f000/pads/usb2/lanes/usb2-2}>,
+                      <&{/padctl@7009f000/pads/pcie/lanes/pcie-6}>;
+               phy-names = "usb2-0", "usb2-1", "usb2-2", "usb3-0";
+
+               avdd-usb-supply = <&vdd_3v3_sys>;
+               dvddio-pex-supply = <&vdd_pex_1v05>;
+               hvddio-pex-supply = <&vdd_1v8>;
+               /* these really belong to the XUSB pad controller */
+               avdd-pll-utmip-supply = <&vdd_1v8>;
+               avdd-pll-uerefe-supply = <&vdd_pex_1v05>;
+               dvdd-usb-ss-pll-supply = <&vdd_pex_1v05>;
+               hvdd-usb-ss-pll-e-supply = <&vdd_1v8>;
+
+               status = "okay";
+       };
+
+       padctl@7009f000 {
+               status = "okay";
+
+               avdd-pll-utmip-supply = <&vdd_1v8>;
+               avdd-pll-uerefe-supply = <&vdd_pex_1v05>;
+               dvdd-pex-pll-supply = <&vdd_pex_1v05>;
+               hvdd-pex-pll-e-supply = <&vdd_1v8>;
+
+               pads {
+                       usb2 {
+                               status = "okay";
+
+                               lanes {
+                                       usb2-0 {
+                                               nvidia,function = "xusb";
+                                               status = "okay";
+                                       };
+
+                                       usb2-1 {
+                                               nvidia,function = "xusb";
+                                               status = "okay";
+                                       };
+
+                                       usb2-2 {
+                                               nvidia,function = "xusb";
+                                               status = "okay";
+                                       };
+                               };
+                       };
+
+                       pcie {
+                               status = "okay";
+
+                               lanes {
+                                       pcie-0 {
+                                               nvidia,function = "pcie-x1";
+                                               status = "okay";
+                                       };
+
+                                       pcie-1 {
+                                               nvidia,function = "pcie-x4";
+                                               status = "okay";
+                                       };
+
+                                       pcie-2 {
+                                               nvidia,function = "pcie-x4";
+                                               status = "okay";
+                                       };
+
+                                       pcie-3 {
+                                               nvidia,function = "pcie-x4";
+                                               status = "okay";
+                                       };
+
+                                       pcie-4 {
+                                               nvidia,function = "pcie-x4";
+                                               status = "okay";
+                                       };
+
+                                       pcie-5 {
+                                               nvidia,function = "usb3-ss";
+                                               status = "okay";
+                                       };
+
+                                       pcie-6 {
+                                               nvidia,function = "usb3-ss";
+                                               status = "okay";
+                                       };
+                               };
+                       };
+               };
+
+               ports {
+                       usb2-0 {
+                               status = "okay";
+                               mode = "otg";
+                       };
+
+                       usb2-1 {
+                               status = "okay";
+                               mode = "host";
+                       };
+
+                       usb2-2 {
+                               status = "okay";
+                               mode = "host";
+                       };
+
+                       usb3-0 {
+                               status = "okay";
+                               nvidia,usb2-companion = <1>;
+                               vbus-supply = <&vdd_hub_3v3>;
+                       };
+               };
+       };
+
+       sdhci@700b0000 {
+               status = "okay";
+               bus-width = <4>;
+
+               cd-gpios = <&gpio TEGRA_GPIO(Z, 1) GPIO_ACTIVE_LOW>;
+
+               vqmmc-supply = <&vddio_sdmmc>;
+               vmmc-supply = <&vdd_3v3_sd>;
+       };
+
+       clocks {
+               compatible = "simple-bus";
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               clk32k_in: clock@0 {
+                       compatible = "fixed-clock";
+                       reg = <0>;
+                       #clock-cells = <0>;
+                       clock-frequency = <32768>;
+               };
+       };
+
+       cpus {
+               cpu@0 {
+                       enable-method = "psci";
+               };
+
+               cpu@1 {
+                       enable-method = "psci";
+               };
+
+               cpu@2 {
+                       enable-method = "psci";
+               };
+
+               cpu@3 {
+                       enable-method = "psci";
+               };
+       };
+
+       gpio-keys {
+               compatible = "gpio-keys";
+
+               power {
+                       label = "Power";
+                       gpios = <&gpio TEGRA_GPIO(X, 5) GPIO_ACTIVE_LOW>;
+                       linux,input-type = <EV_KEY>;
+                       linux,code = <KEY_POWER>;
+                       debounce-interval = <30>;
+                       wakeup-event-action = <EV_ACT_ASSERTED>;
+                       wakeup-source;
+               };
+
+               force-recovery {
+                       label = "Force Recovery";
+                       gpios = <&gpio TEGRA_GPIO(X, 6) GPIO_ACTIVE_LOW>;
+                       linux,input-type = <EV_KEY>;
+                       linux,code = <BTN_1>;
+                       debounce-interval = <30>;
+               };
+       };
+
+       psci {
+               compatible = "arm,psci-1.0";
+               method = "smc";
+       };
+
+       regulators {
+               compatible = "simple-bus";
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               vdd_5v0_sys: regulator@0 {
+                       compatible = "regulator-fixed";
+                       reg = <0>;
+
+                       regulator-name = "VDD_5V0_SYS";
+                       regulator-min-microvolt = <5000000>;
+                       regulator-max-microvolt = <5000000>;
+                       regulator-always-on;
+                       regulator-boot-on;
+               };
+
+               vdd_3v3_sys: regulator@1 {
+                       compatible = "regulator-fixed";
+                       reg = <1>;
+                       regulator-name = "VDD_3V3_SYS";
+                       regulator-min-microvolt = <3300000>;
+                       regulator-max-microvolt = <3300000>;
+                       regulator-enable-ramp-delay = <240>;
+                       regulator-disable-ramp-delay = <11340>;
+                       regulator-always-on;
+                       regulator-boot-on;
+
+                       gpio = <&pmic 3 GPIO_ACTIVE_HIGH>;
+                       enable-active-high;
+
+                       vin-supply = <&vdd_5v0_sys>;
+               };
+
+               vdd_3v3_sd: regulator@2 {
+                       compatible = "regulator-fixed";
+                       reg = <2>;
+
+                       regulator-name = "VDD_3V3_SD";
+                       regulator-min-microvolt = <3300000>;
+                       regulator-max-microvolt = <3300000>;
+
+                       gpio = <&gpio TEGRA_GPIO(Z, 3) GPIO_ACTIVE_HIGH>;
+                       enable-active-high;
+
+                       vin-supply = <&vdd_3v3_sys>;
+               };
+
+               vdd_hdmi: regulator@3 {
+                       compatible = "regulator-fixed";
+                       reg = <3>;
+
+                       regulator-name = "VDD_HDMI_5V0";
+                       regulator-min-microvolt = <5000000>;
+                       regulator-max-microvolt = <5000000>;
+
+                       vin-supply = <&vdd_5v0_sys>;
+               };
+
+               vdd_hub_3v3: regulator@4 {
+                       compatible = "regulator-fixed";
+                       reg = <4>;
+
+                       regulator-name = "VDD_HUB_3V3";
+                       regulator-min-microvolt = <3300000>;
+                       regulator-max-microvolt = <3300000>;
+
+                       gpio = <&gpio TEGRA_GPIO(A, 6) GPIO_ACTIVE_HIGH>;
+                       enable-active-high;
+
+                       vin-supply = <&vdd_5v0_sys>;
+               };
+
+               vdd_cpu: regulator@5 {
+                       compatible = "regulator-fixed";
+                       reg = <5>;
+
+                       regulator-name = "VDD_CPU";
+                       regulator-min-microvolt = <5000000>;
+                       regulator-max-microvolt = <5000000>;
+                       regulator-always-on;
+                       regulator-boot-on;
+
+                       gpio = <&pmic 5 GPIO_ACTIVE_HIGH>;
+                       enable-active-high;
+
+                       vin-supply = <&vdd_5v0_sys>;
+               };
+
+               vdd_gpu: regulator@6 {
+                       compatible = "regulator-fixed";
+                       reg = <6>;
+
+                       regulator-name = "VDD_GPU";
+                       regulator-min-microvolt = <5000000>;
+                       regulator-max-microvolt = <5000000>;
+                       regulator-enable-ramp-delay = <250>;
+
+                       gpio = <&pmic 6 GPIO_ACTIVE_HIGH>;
+                       enable-active-high;
+
+                       vin-supply = <&vdd_5v0_sys>;
+               };
+       };
+};

diff --git a/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts b/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts
index a4b8f66..72c7a04 100644 (file)
--- a/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts
+++ b/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts
@@ -1654,6 +1654,11 @@
        padctl@7009f000 {
                status = "okay";
 
+               avdd-pll-utmip-supply = <&pp1800>;
+               avdd-pll-uerefe-supply = <&pp1050_avdd>;
+               dvdd-pex-pll-supply = <&avddio_1v05>;
+               hvdd-pex-pll-e-supply = <&pp1800>;
+
                pads {
                        usb2 {
                                status = "okay";
@@ -1751,6 +1756,13 @@
                cpu@3 {
                        enable-method = "psci";
                };
+
+               idle-states {
+                       cpu-sleep {
+                               arm,psci-suspend-param = <0x00010007>;
+                               status = "okay";
+                       };
+               };
        };
 
        gpio-keys {

diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
index 6574396..a550c0a 100644 (file)
--- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
@@ -384,14 +384,22 @@
        };
 
        timer@60005000 {
-               compatible = "nvidia,tegra210-timer", "nvidia,tegra20-timer";
+               compatible = "nvidia,tegra210-timer";
                reg = <0x0 0x60005000 0x0 0x400>;
-               interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+               interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
                             <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
                             <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
                             <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
                             <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
-                            <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
+                            <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&tegra_car TEGRA210_CLK_TIMER>;
                clock-names = "timer";
        };
@@ -1363,24 +1371,51 @@
                                 <&dfll>;
                        clock-names = "cpu_g", "pll_x", "pll_p", "dfll";
                        clock-latency = <300000>;
+                       cpu-idle-states = <&CPU_SLEEP>;
+                       next-level-cache = <&L2>;
                };
 
                cpu@1 {
                        device_type = "cpu";
                        compatible = "arm,cortex-a57";
                        reg = <1>;
+                       cpu-idle-states = <&CPU_SLEEP>;
+                       next-level-cache = <&L2>;
                };
 
                cpu@2 {
                        device_type = "cpu";
                        compatible = "arm,cortex-a57";
                        reg = <2>;
+                       cpu-idle-states = <&CPU_SLEEP>;
+                       next-level-cache = <&L2>;
                };
 
                cpu@3 {
                        device_type = "cpu";
                        compatible = "arm,cortex-a57";
                        reg = <3>;
+                       cpu-idle-states = <&CPU_SLEEP>;
+                       next-level-cache = <&L2>;
+               };
+
+               idle-states {
+                       entry-method = "psci";
+
+                       CPU_SLEEP: cpu-sleep {
+                               compatible = "arm,idle-state";
+                               arm,psci-suspend-param = <0x40000007>;
+                               entry-latency-us = <100>;
+                               exit-latency-us = <30>;
+                               min-residency-us = <1000>;
+                               wakeup-latency-us = <130>;
+                               idle-state-name = "cpu-sleep";
+                               status = "disabled";
+                       };
+               };
+
+               L2: l2-cache {
+                       compatible = "cache";
                };
        };
 

diff --git a/arch/arm64/boot/dts/qcom/apq8096-db820c-pins.dtsi b/arch/arm64/boot/dts/qcom/apq8096-db820c-pins.dtsi
index 6a57387..1c0d06f 100644 (file)
--- a/arch/arm64/boot/dts/qcom/apq8096-db820c-pins.dtsi
+++ b/arch/arm64/boot/dts/qcom/apq8096-db820c-pins.dtsi
@@ -62,4 +62,56 @@
                        bias-disable;
                };
        };
+
+       hdmi_hpd_active: hdmi_hpd_active {
+               mux {
+                       pins = "gpio34";
+                       function = "hdmi_hot";
+               };
+
+               config {
+                       pins = "gpio34";
+                       bias-pull-down;
+                       drive-strength = <16>;
+               };
+       };
+
+       hdmi_hpd_suspend: hdmi_hpd_suspend {
+               mux {
+                       pins = "gpio34";
+                       function = "hdmi_hot";
+               };
+
+               config {
+                       pins = "gpio34";
+                       bias-pull-down;
+                       drive-strength = <2>;
+               };
+       };
+
+       hdmi_ddc_active: hdmi_ddc_active {
+               mux {
+                       pins = "gpio32", "gpio33";
+                       function = "hdmi_ddc";
+               };
+
+               config {
+                       pins = "gpio32", "gpio33";
+                       drive-strength = <2>;
+                       bias-pull-up;
+               };
+       };
+
+       hdmi_ddc_suspend: hdmi_ddc_suspend {
+               mux {
+                       pins = "gpio32", "gpio33";
+                       function = "hdmi_ddc";
+               };
+
+               config {
+                       pins = "gpio32", "gpio33";
+                       drive-strength = <2>;
+                       bias-pull-down;
+               };
+       };
 };

diff --git a/arch/arm64/boot/dts/qcom/apq8096-db820c-pmic-pins.dtsi b/arch/arm64/boot/dts/qcom/apq8096-db820c-pmic-pins.dtsi
index a6ad3d7..31a3e33 100644 (file)
--- a/arch/arm64/boot/dts/qcom/apq8096-db820c-pmic-pins.dtsi
+++ b/arch/arm64/boot/dts/qcom/apq8096-db820c-pmic-pins.dtsi
@@ -36,6 +36,14 @@
                };
        };
 
+       audio_mclk: clk_div1 {
+               pinconf {
+                       pins = "gpio15";
+                       function = "func1";
+                       power-source = <PM8994_GPIO_S4>; // 1.8V
+               };
+       };
+
        volume_up_gpio: pm8996_gpio2 {
                pinconf {
                        pins = "gpio2";

diff --git a/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi b/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi
index 6d50449..943f699 100644 (file)
--- a/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi
+++ b/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi
@@ -18,6 +18,8 @@
 #include "apq8096-db820c-pmic-pins.dtsi"
 #include <dt-bindings/input/input.h>
 #include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/sound/qcom,q6afe.h>
+#include <dt-bindings/sound/qcom,q6asm.h>
 
 /*
  * GPIO name legend: proper name = the GPIO line is used as GPIO
@@ -63,6 +65,7 @@
        };
 
        clocks {
+               compatible = "simple-bus";
                divclk4: divclk4 {
                        compatible = "fixed-clock";
                        #clock-cells = <0>;
@@ -72,6 +75,15 @@
                        pinctrl-names = "default";
                        pinctrl-0 = <&divclk4_pin_a>;
                };
+
+               div1_mclk: divclk1 {
+                       compatible = "gpio-gate-clock";
+                       pinctrl-0 = <&audio_mclk>;
+                       pinctrl-names = "default";
+                       clocks = <&rpmcc RPM_SMD_DIV_CLK1>;
+                       #clock-cells = <0>;
+                       enable-gpios = <&pm8994_gpios 15 0>;
+               };
        };
 
        soc {
@@ -452,6 +464,43 @@
                                perst-gpio = <&msmgpio 114 GPIO_ACTIVE_LOW>;
                        };
                };
+
+               slim_msm: slim@91c0000 {
+                       ngd@1 {
+                               wcd9335: codec@1{
+                                       clock-names = "mclk", "slimbus";
+                                       clocks = <&div1_mclk>,
+                                                <&rpmcc RPM_SMD_BB_CLK1>;
+                               };
+                       };
+               };
+
+               mdss@900000 {
+                       status = "okay";
+
+                       mdp@901000 {
+                               status = "okay";
+                       };
+
+                       hdmi-phy@9a0600 {
+                               status = "okay";
+
+                               vddio-supply = <&pm8994_l12>;
+                               vcca-supply = <&pm8994_l28>;
+                               #phy-cells = <0>;
+                       };
+
+                       hdmi-tx@9a0000 {
+                               status = "okay";
+
+                               pinctrl-names = "default", "sleep";
+                               pinctrl-0 = <&hdmi_hpd_active &hdmi_ddc_active>;
+                               pinctrl-1 = <&hdmi_hpd_suspend &hdmi_ddc_suspend>;
+
+                               core-vdda-supply = <&pm8994_l12>;
+                               core-vcc-supply = <&pm8994_s4>;
+                       };
+               };
        };
 
 
@@ -639,3 +688,75 @@
                };
        };
 };
+
+&sound {
+       compatible = "qcom,apq8096-sndcard";
+       model = "DB820c";
+       audio-routing = "RX_BIAS", "MCLK";
+
+       mm1-dai-link {
+               link-name = "MultiMedia1";
+               cpu {
+                       sound-dai = <&q6asmdai  MSM_FRONTEND_DAI_MULTIMEDIA1>;
+               };
+       };
+
+       mm2-dai-link {
+               link-name = "MultiMedia2";
+               cpu {
+                       sound-dai = <&q6asmdai  MSM_FRONTEND_DAI_MULTIMEDIA2>;
+               };
+       };
+
+       mm3-dai-link {
+               link-name = "MultiMedia3";
+               cpu {
+                       sound-dai = <&q6asmdai  MSM_FRONTEND_DAI_MULTIMEDIA3>;
+               };
+       };
+
+       hdmi-dai-link {
+               link-name = "HDMI";
+               cpu {
+                       sound-dai = <&q6afedai HDMI_RX>;
+               };
+
+               platform {
+                       sound-dai = <&q6routing>;
+               };
+
+               codec {
+                       sound-dai = <&hdmi 0>;
+               };
+       };
+
+       slim-dai-link {
+               link-name = "SLIM Playback";
+               cpu {
+                       sound-dai = <&q6afedai SLIMBUS_6_RX>;
+               };
+
+               platform {
+                       sound-dai = <&q6routing>;
+       };
+
+               codec {
+                       sound-dai = <&wcd9335 6>;
+               };
+       };
+
+       slimcap-dai-link {
+               link-name = "SLIM Capture";
+               cpu {
+                       sound-dai = <&q6afedai SLIMBUS_0_TX>;
+               };
+
+               platform {
+                       sound-dai = <&q6routing>;
+               };
+
+               codec {
+                       sound-dai = <&wcd9335 1>;
+               };
+       };
+};

diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi
index 0803ca8..423dda9 100644 (file)
--- a/arch/arm64/boot/dts/qcom/msm8916.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi
@@ -180,19 +180,19 @@
        };
 
        thermal-zones {
-               cpu-thermal0 {
+               cpu0_1-thermal {
                        polling-delay-passive = <250>;
                        polling-delay = <1000>;
 
                        thermal-sensors = <&tsens 4>;
 
                        trips {
-                               cpu_alert0: trip0 {
+                               cpu0_1_alert0: trip-point@0 {
                                        temperature = <75000>;
                                        hysteresis = <2000>;
                                        type = "passive";
                                };
-                               cpu_crit0: trip1 {
+                               cpu0_1_crit: cpu_crit {
                                        temperature = <110000>;
                                        hysteresis = <2000>;
                                        type = "critical";
@@ -201,7 +201,7 @@
 
                        cooling-maps {
                                map0 {
-                                       trip = <&cpu_alert0>;
+                                       trip = <&cpu0_1_alert0>;
                                        cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
                                                         <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
                                                         <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
@@ -210,19 +210,19 @@
                        };
                };
 
-               cpu-thermal1 {
+               cpu2_3-thermal {
                        polling-delay-passive = <250>;
                        polling-delay = <1000>;
 
                        thermal-sensors = <&tsens 3>;
 
                        trips {
-                               cpu_alert1: trip0 {
+                               cpu2_3_alert0: trip-point@0 {
                                        temperature = <75000>;
                                        hysteresis = <2000>;
                                        type = "passive";
                                };
-                               cpu_crit1: trip1 {
+                               cpu2_3_crit: cpu_crit {
                                        temperature = <110000>;
                                        hysteresis = <2000>;
                                        type = "critical";
@@ -231,7 +231,7 @@
 
                        cooling-maps {
                                map0 {
-                                       trip = <&cpu_alert1>;
+                                       trip = <&cpu2_3_alert0>;
                                        cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
                                                         <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
                                                         <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
@@ -247,12 +247,12 @@
                        thermal-sensors = <&tsens 2>;
 
                        trips {
-                               gpu_alert: trip0 {
+                               gpu_alert0: trip-point@0 {
                                        temperature = <75000>;
                                        hysteresis = <2000>;
                                        type = "passive";
                                };
-                               gpu_crit: trip1 {
+                               gpu_crit: gpu_crit {
                                        temperature = <95000>;
                                        hysteresis = <2000>;
                                        type = "critical";
@@ -267,18 +267,27 @@
                        thermal-sensors = <&tsens 1>;
 
                        trips {
-                               cam_alert: trip0 {
+                               cam_alert0: trip-point@0 {
                                        temperature = <75000>;
                                        hysteresis = <2000>;
-                                       type = "passive";
+                                       type = "hot";
                                };
-                               cam_crit: trip1 {
-                                       temperature = <95000>;
+                       };
+               };
+
+               modem-thermal {
+                       polling-delay-passive = <250>;
+                       polling-delay = <1000>;
+
+                       thermal-sensors = <&tsens 0>;
+
+                       trips {
+                               modem_alert0: trip-point@0 {
+                                       temperature = <85000>;
                                        hysteresis = <2000>;
-                                       type = "critical";
+                                       type = "hot";
                                };
                        };
-
                };
 
        };
@@ -1015,8 +1024,9 @@
                                #clock-cells = <1>;
                                #phy-cells = <0>;
 
-                               clocks = <&gcc GCC_MDSS_AHB_CLK>;
-                               clock-names = "iface";
+                               clocks = <&gcc GCC_MDSS_AHB_CLK>,
+                                        <&xo_board>;
+                               clock-names = "iface", "ref";
                        };
                };
 

diff --git a/arch/arm64/boot/dts/qcom/msm8996-pins.dtsi b/arch/arm64/boot/dts/qcom/msm8996-pins.dtsi
index 131878d..fba2229 100644 (file)
--- a/arch/arm64/boot/dts/qcom/msm8996-pins.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8996-pins.dtsi
@@ -13,6 +13,49 @@
 
 &msmgpio {
 
+       wcd9xxx_intr {
+               wcd_intr_default: wcd_intr_default{
+                       mux {
+                               pins = "gpio54";
+                               function = "gpio";
+                       };
+
+                       config {
+                               pins = "gpio54";
+                               drive-strength = <2>; /* 2 mA */
+                               bias-pull-down; /* pull down */
+                               input-enable;
+                       };
+               };
+       };
+
+       cdc_reset_ctrl {
+               cdc_reset_sleep: cdc_reset_sleep {
+                       mux {
+                               pins = "gpio64";
+                               function = "gpio";
+                       };
+                       config {
+                               pins = "gpio64";
+                               drive-strength = <16>;
+                               bias-disable;
+                               output-low;
+                       };
+               };
+               cdc_reset_active:cdc_reset_active {
+                       mux {
+                               pins = "gpio64";
+                               function = "gpio";
+                       };
+                       config {
+                               pins = "gpio64";
+                               drive-strength = <16>;
+                               bias-pull-down;
+                               output-high;
+                       };
+               };
+       };
+
        blsp1_spi0_default: blsp1_spi0_default {
                pinmux {
                        function = "blsp_spi1";

diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi
index c761269..c4e7fde 100644 (file)
--- a/arch/arm64/boot/dts/qcom/msm8996.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi
@@ -14,6 +14,7 @@
 #include <dt-bindings/clock/qcom,gcc-msm8996.h>
 #include <dt-bindings/clock/qcom,mmcc-msm8996.h>
 #include <dt-bindings/clock/qcom,rpmcc.h>
+#include <dt-bindings/soc/qcom,apr.h>
 
 / {
        interrupt-parent = <&intc>;
@@ -84,6 +85,12 @@
                        qcom,client-id = <1>;
                        qcom,vmid = <15>;
                };
+
+               zap_shader_region: gpu@8f200000 {
+                       compatible = "shared-dma-pool";
+                       reg = <0x0 0x90b00000 0x0 0xa00000>;
+                       no-map;
+               };
        };
 
        cpus {
@@ -154,20 +161,20 @@
        };
 
        thermal-zones {
-               cpu-thermal0 {
+               cpu0-thermal {
                        polling-delay-passive = <250>;
                        polling-delay = <1000>;
 
                        thermal-sensors = <&tsens0 3>;
 
                        trips {
-                               cpu_alert0: trip0 {
+                               cpu0_alert0: trip-point@0 {
                                        temperature = <75000>;
                                        hysteresis = <2000>;
                                        type = "passive";
                                };
 
-                               cpu_crit0: trip1 {
+                               cpu0_crit: cpu_crit {
                                        temperature = <110000>;
                                        hysteresis = <2000>;
                                        type = "critical";
@@ -175,20 +182,20 @@
                        };
                };
 
-               cpu-thermal1 {
+               cpu1-thermal {
                        polling-delay-passive = <250>;
                        polling-delay = <1000>;
 
                        thermal-sensors = <&tsens0 5>;
 
                        trips {
-                               cpu_alert1: trip0 {
+                               cpu1_alert0: trip-point@0 {
                                        temperature = <75000>;
                                        hysteresis = <2000>;
                                        type = "passive";
                                };
 
-                               cpu_crit1: trip1 {
+                               cpu1_crit: cpu_crit {
                                        temperature = <110000>;
                                        hysteresis = <2000>;
                                        type = "critical";
@@ -196,20 +203,20 @@
                        };
                };
 
-               cpu-thermal2 {
+               cpu2-thermal {
                        polling-delay-passive = <250>;
                        polling-delay = <1000>;
 
                        thermal-sensors = <&tsens0 8>;
 
                        trips {
-                               cpu_alert2: trip0 {
+                               cpu2_alert0: trip-point@0 {
                                        temperature = <75000>;
                                        hysteresis = <2000>;
                                        type = "passive";
                                };
 
-                               cpu_crit2: trip1 {
+                               cpu2_crit: cpu_crit {
                                        temperature = <110000>;
                                        hysteresis = <2000>;
                                        type = "critical";
@@ -217,26 +224,176 @@
                        };
                };
 
-               cpu-thermal3 {
+               cpu3-thermal {
                        polling-delay-passive = <250>;
                        polling-delay = <1000>;
 
                        thermal-sensors = <&tsens0 10>;
 
                        trips {
-                               cpu_alert3: trip0 {
+                               cpu3_alert0: trip-point@0 {
                                        temperature = <75000>;
                                        hysteresis = <2000>;
                                        type = "passive";
                                };
 
-                               cpu_crit3: trip1 {
+                               cpu3_crit: cpu_crit {
                                        temperature = <110000>;
                                        hysteresis = <2000>;
                                        type = "critical";
                                };
                        };
                };
+
+               gpu-thermal-top {
+                       polling-delay-passive = <250>;
+                       polling-delay = <1000>;
+
+                       thermal-sensors = <&tsens1 6>;
+
+                       trips {
+                               gpu1_alert0: trip-point@0 {
+                                       temperature = <90000>;
+                                       hysteresis = <2000>;
+                                       type = "hot";
+                               };
+                       };
+               };
+
+               gpu-thermal-bottom {
+                       polling-delay-passive = <250>;
+                       polling-delay = <1000>;
+
+                       thermal-sensors = <&tsens1 7>;
+
+                       trips {
+                               gpu2_alert0: trip-point@0 {
+                                       temperature = <90000>;
+                                       hysteresis = <2000>;
+                                       type = "hot";
+                               };
+                       };
+               };
+
+               m4m-thermal {
+                       polling-delay-passive = <250>;
+                       polling-delay = <1000>;
+
+                       thermal-sensors = <&tsens0 1>;
+
+                       trips {
+                               m4m_alert0: trip-point@0 {
+                                       temperature = <90000>;
+                                       hysteresis = <2000>;
+                                       type = "hot";
+                               };
+                       };
+               };
+
+               l3-or-venus-thermal {
+                       polling-delay-passive = <250>;
+                       polling-delay = <1000>;
+
+                       thermal-sensors = <&tsens0 2>;
+
+                       trips {
+                               l3_or_venus_alert0: trip-point@0 {
+                                       temperature = <90000>;
+                                       hysteresis = <2000>;
+                                       type = "hot";
+                               };
+                       };
+               };
+
+               cluster0-l2-thermal {
+                       polling-delay-passive = <250>;
+                       polling-delay = <1000>;
+
+                       thermal-sensors = <&tsens0 7>;
+
+                       trips {
+                               cluster0_l2_alert0: trip-point@0 {
+                                       temperature = <90000>;
+                                       hysteresis = <2000>;
+                                       type = "hot";
+                               };
+                       };
+               };
+
+               cluster1-l2-thermal {
+                       polling-delay-passive = <250>;
+                       polling-delay = <1000>;
+
+                       thermal-sensors = <&tsens0 12>;
+
+                       trips {
+                               cluster1_l2_alert0: trip-point@0 {
+                                       temperature = <90000>;
+                                       hysteresis = <2000>;
+                                       type = "hot";
+                               };
+                       };
+               };
+
+               camera-thermal {
+                       polling-delay-passive = <250>;
+                       polling-delay = <1000>;
+
+                       thermal-sensors = <&tsens1 1>;
+
+                       trips {
+                               camera_alert0: trip-point@0 {
+                                       temperature = <90000>;
+                                       hysteresis = <2000>;
+                                       type = "hot";
+                               };
+                       };
+               };
+
+               q6-dsp-thermal {
+                       polling-delay-passive = <250>;
+                       polling-delay = <1000>;
+
+                       thermal-sensors = <&tsens1 2>;
+
+                       trips {
+                               q6_dsp_alert0: trip-point@0 {
+                                       temperature = <90000>;
+                                       hysteresis = <2000>;
+                                       type = "hot";
+                               };
+                       };
+               };
+
+               mem-thermal {
+                       polling-delay-passive = <250>;
+                       polling-delay = <1000>;
+
+                       thermal-sensors = <&tsens1 3>;
+
+                       trips {
+                               mem_alert0: trip-point@0 {
+                                       temperature = <90000>;
+                                       hysteresis = <2000>;
+                                       type = "hot";
+                               };
+                       };
+               };
+
+               modemtx-thermal {
+                       polling-delay-passive = <250>;
+                       polling-delay = <1000>;
+
+                       thermal-sensors = <&tsens1 4>;
+
+                       trips {
+                               modemtx_alert0: trip-point@0 {
+                                       temperature = <90000>;
+                                       hysteresis = <2000>;
+                                       type = "hot";
+                               };
+                       };
+               };
        };
 
        timer {
@@ -796,6 +953,11 @@
                                reg = <0x24f 0x1>;
                                bits = <1 4>;
                        };
+
+                       gpu_speed_bin: gpu_speed_bin@133 {
+                               reg = <0x133 0x1>;
+                               bits = <5 3>;
+                       };
                };
 
                phy@34000 {
@@ -1138,6 +1300,70 @@
                        };
                };
 
+               adreno_smmu: arm,smmu@b40000 {
+                       compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
+                       reg = <0xb40000 0x10000>;
+
+                       #global-interrupts = <1>;
+                       interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>;
+                       #iommu-cells = <1>;
+
+                       clocks = <&mmcc GPU_AHB_CLK>,
+                                <&gcc GCC_MMSS_BIMC_GFX_CLK>;
+                       clock-names = "iface", "bus";
+
+                       power-domains = <&mmcc GPU_GDSC>;
+
+                       status = "disabled";
+               };
+
+               mdp_smmu: arm,smmu@d00000 {
+                       compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
+                       reg = <0xd00000 0x10000>;
+
+                       #global-interrupts = <1>;
+                       interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>;
+                       #iommu-cells = <1>;
+                       clocks = <&mmcc SMMU_MDP_AHB_CLK>,
+                                <&mmcc SMMU_MDP_AXI_CLK>;
+                       clock-names = "iface", "bus";
+
+                       power-domains = <&mmcc MDSS_GDSC>;
+
+                       status = "disabled";
+               };
+
+               lpass_q6_smmu: arm,smmu-lpass_q6@1600000 {
+                       compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
+                       reg = <0x1600000 0x20000>;
+                       #iommu-cells = <1>;
+                       power-domains = <&gcc HLOS1_VOTE_LPASS_CORE_GDSC>;
+
+                       #global-interrupts = <1>;
+                       interrupts = <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
+                               <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>,
+                               <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>,
+                               <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>,
+                               <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
+                               <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
+                               <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
+                               <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
+                               <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
+                               <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
+                               <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
+                               <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
+                               <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>;
+
+                       clocks = <&gcc GCC_HLOS1_VOTE_LPASS_CORE_SMMU_CLK>,
+                                <&gcc GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CLK>;
+                       clock-names = "iface", "bus";
+                       status = "disabled";
+               };
+
                agnoc@0 {
                        power-domains = <&gcc AGGRE0_NOC_GDSC>;
                        compatible = "simple-pm-bus";
@@ -1303,6 +1529,265 @@
                                                "bus_slave";
                        };
                };
+
+               slimbam:dma@9184000
+               {
+                       compatible = "qcom,bam-v1.7.0";
+                       qcom,controlled-remotely;
+                       reg = <0x9184000 0x32000>;
+                       num-channels  = <31>;
+                       interrupts = <0 164 IRQ_TYPE_LEVEL_HIGH>;
+                       #dma-cells = <1>;
+                       qcom,ee = <1>;
+                       qcom,num-ees = <2>;
+               };
+
+               slim_msm: slim@91c0000 {
+                       compatible = "qcom,slim-ngd-v1.5.0";
+                       reg = <0x91c0000 0x2C000>;
+                       reg-names = "ctrl";
+                       interrupts = <0 163 IRQ_TYPE_LEVEL_HIGH>;
+                       dmas =  <&slimbam 3>, <&slimbam 4>,
+                               <&slimbam 5>, <&slimbam 6>;
+                       dma-names = "rx", "tx", "tx2", "rx2";
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       ngd@1 {
+                               reg = <1>;
+                               #address-cells = <1>;
+                               #size-cells = <1>;
+
+                               tasha_ifd: tas-ifd {
+                                       compatible = "slim217,1a0";
+                                       reg  = <0 0>;
+                               };
+
+                               wcd9335: codec@1{
+                                       pinctrl-0 = <&cdc_reset_active &wcd_intr_default>;
+                                       pinctrl-names = "default";
+
+                                       compatible = "slim217,1a0";
+                                       reg  = <1 0>;
+
+                                       interrupt-parent = <&msmgpio>;
+                                       interrupts = <54 IRQ_TYPE_LEVEL_HIGH>,
+                                                    <53 IRQ_TYPE_LEVEL_HIGH>;
+                                       interrupt-names  = "intr1", "intr2";
+                                       interrupt-controller;
+                                       #interrupt-cells = <1>;
+                                       reset-gpios = <&msmgpio 64 0>;
+
+                                       slim-ifc-dev  = <&tasha_ifd>;
+
+                                       vdd-buck-supply = <&pm8994_s4>;
+                                       vdd-buck-sido-supply = <&pm8994_s4>;
+                                       vdd-tx-supply = <&pm8994_s4>;
+                                       vdd-rx-supply = <&pm8994_s4>;
+                                       vdd-io-supply = <&pm8994_s4>;
+
+                                       #sound-dai-cells = <1>;
+                               };
+                       };
+               };
+
+               gpu@b00000 {
+                       compatible = "qcom,adreno-530.2", "qcom,adreno";
+                       #stream-id-cells = <16>;
+
+                       reg = <0xb00000 0x3f000>;
+                       reg-names = "kgsl_3d0_reg_memory";
+
+                       interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>;
+
+                       clocks = <&mmcc GPU_GX_GFX3D_CLK>,
+                               <&mmcc GPU_AHB_CLK>,
+                               <&mmcc GPU_GX_RBBMTIMER_CLK>,
+                               <&gcc GCC_BIMC_GFX_CLK>,
+                               <&gcc GCC_MMSS_BIMC_GFX_CLK>;
+
+                       clock-names = "core",
+                               "iface",
+                               "rbbmtimer",
+                               "mem",
+                               "mem_iface";
+
+                       power-domains = <&mmcc GPU_GDSC>;
+                       iommus = <&adreno_smmu 0>;
+
+                       nvmem-cells = <&gpu_speed_bin>;
+                       nvmem-cell-names = "speed_bin";
+
+                       qcom,gpu-quirk-two-pass-use-wfi;
+                       qcom,gpu-quirk-fault-detect-mask;
+
+                       operating-points-v2 = <&gpu_opp_table>;
+
+                       gpu_opp_table: opp-table {
+                               compatible  ="operating-points-v2";
+
+                               /*
+                                * 624Mhz and 560Mhz are only available on speed
+                                * bin (1 << 0). All the rest are available on
+                                * all bins of the hardware
+                                */
+                               opp-624000000 {
+                                       opp-hz = /bits/ 64 <624000000>;
+                                       opp-supported-hw = <0x01>;
+                               };
+                               opp-560000000 {
+                                       opp-hz = /bits/ 64 <560000000>;
+                                       opp-supported-hw = <0x01>;
+                               };
+                               opp-510000000 {
+                                       opp-hz = /bits/ 64 <510000000>;
+                                       opp-supported-hw = <0xFF>;
+                               };
+                               opp-401800000 {
+                                       opp-hz = /bits/ 64 <401800000>;
+                                       opp-supported-hw = <0xFF>;
+                               };
+                               opp-315000000 {
+                                       opp-hz = /bits/ 64 <315000000>;
+                                       opp-supported-hw = <0xFF>;
+                               };
+                               opp-214000000 {
+                                       opp-hz = /bits/ 64 <214000000>;
+                                       opp-supported-hw = <0xFF>;
+                               };
+                               opp-133000000 {
+                                       opp-hz = /bits/ 64 <133000000>;
+                                       opp-supported-hw = <0xFF>;
+                               };
+                       };
+
+                       zap-shader {
+                               memory-region = <&zap_shader_region>;
+                       };
+               };
+
+               mdss: mdss@900000 {
+                       compatible = "qcom,mdss";
+
+                       reg = <0x900000 0x1000>,
+                             <0x9b0000 0x1040>,
+                             <0x9b8000 0x1040>;
+                       reg-names = "mdss_phys",
+                                   "vbif_phys",
+                                   "vbif_nrt_phys";
+
+                       power-domains = <&mmcc MDSS_GDSC>;
+                       interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+
+                       interrupt-controller;
+                       #interrupt-cells = <1>;
+
+                       clocks = <&mmcc MDSS_AHB_CLK>;
+                       clock-names = "iface_clk";
+
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       ranges;
+
+                       mdp: mdp@901000 {
+                               compatible = "qcom,mdp5";
+                               reg = <0x901000 0x90000>;
+                               reg-names = "mdp_phys";
+
+                               interrupt-parent = <&mdss>;
+                               interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
+
+                               clocks = <&mmcc MDSS_AHB_CLK>,
+                                        <&mmcc MDSS_AXI_CLK>,
+                                        <&mmcc MDSS_MDP_CLK>,
+                                        <&mmcc SMMU_MDP_AXI_CLK>,
+                                        <&mmcc MDSS_VSYNC_CLK>;
+                               clock-names = "iface_clk",
+                                             "bus_clk",
+                                             "core_clk",
+                                             "iommu_clk",
+                                             "vsync_clk";
+
+                               iommus = <&mdp_smmu 0>;
+
+                               ports {
+                                       #address-cells = <1>;
+                                       #size-cells = <0>;
+
+                                       port@0 {
+                                               reg = <0>;
+                                               mdp5_intf3_out: endpoint {
+                                                       remote-endpoint = <&hdmi_in>;
+                                               };
+                                       };
+                               };
+                       };
+
+                       hdmi: hdmi-tx@9a0000 {
+                               compatible = "qcom,hdmi-tx-8996";
+                               reg =   <0x009a0000 0x50c>,
+                                       <0x00070000 0x6158>,
+                                       <0x009e0000 0xfff>;
+                               reg-names = "core_physical",
+                                           "qfprom_physical",
+                                           "hdcp_physical";
+
+                               interrupt-parent = <&mdss>;
+                               interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
+
+                               clocks = <&mmcc MDSS_MDP_CLK>,
+                                        <&mmcc MDSS_AHB_CLK>,
+                                        <&mmcc MDSS_HDMI_CLK>,
+                                        <&mmcc MDSS_HDMI_AHB_CLK>,
+                                        <&mmcc MDSS_EXTPCLK_CLK>;
+                               clock-names =
+                                       "mdp_core_clk",
+                                       "iface_clk",
+                                       "core_clk",
+                                       "alt_iface_clk",
+                                       "extp_clk";
+
+                               phys = <&hdmi_phy>;
+                               phy-names = "hdmi_phy";
+                               #sound-dai-cells = <1>;
+
+                               ports {
+                                       #address-cells = <1>;
+                                       #size-cells = <0>;
+
+                                       port@0 {
+                                               reg = <0>;
+                                               hdmi_in: endpoint {
+                                                       remote-endpoint = <&mdp5_intf3_out>;
+                                               };
+                                       };
+                               };
+                       };
+
+                       hdmi_phy: hdmi-phy@9a0600 {
+                               #phy-cells = <0>;
+                               compatible = "qcom,hdmi-phy-8996";
+                               reg = <0x9a0600 0x1c4>,
+                                     <0x9a0a00 0x124>,
+                                     <0x9a0c00 0x124>,
+                                     <0x9a0e00 0x124>,
+                                     <0x9a1000 0x124>,
+                                     <0x9a1200 0x0c8>;
+                               reg-names = "hdmi_pll",
+                                           "hdmi_tx_l0",
+                                           "hdmi_tx_l1",
+                                           "hdmi_tx_l2",
+                                           "hdmi_tx_l3",
+                                           "hdmi_phy";
+
+                               clocks = <&mmcc MDSS_AHB_CLK>,
+                                        <&gcc GCC_HDMI_CLKREF_CLK>;
+                               clock-names = "iface_clk",
+                                             "ref_clk";
+                       };
+               };
+       };
+
+       sound: sound {
        };
 
        adsp-pil {
@@ -1331,6 +1816,55 @@
                        mboxes = <&apcs_glb 8>;
                        qcom,smd-edge = <1>;
                        qcom,remote-pid = <2>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       apr {
+                               power-domains = <&gcc HLOS1_VOTE_LPASS_ADSP_GDSC>;
+                               compatible = "qcom,apr-v2";
+                               qcom,smd-channels = "apr_audio_svc";
+                               reg = <APR_DOMAIN_ADSP>;
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+
+                               q6core {
+                                       reg = <APR_SVC_ADSP_CORE>;
+                                       compatible = "qcom,q6core";
+                               };
+
+                               q6afe: q6afe {
+                                       compatible = "qcom,q6afe";
+                                       reg = <APR_SVC_AFE>;
+                                       q6afedai: dais {
+                                               compatible = "qcom,q6afe-dais";
+                                               #address-cells = <1>;
+                                               #size-cells = <0>;
+                                               #sound-dai-cells = <1>;
+                                               hdmi@1 {
+                                                       reg = <1>;
+                                               };
+                                       };
+                               };
+
+                               q6asm: q6asm {
+                                       compatible = "qcom,q6asm";
+                                       reg = <APR_SVC_ASM>;
+                                       q6asmdai: dais {
+                                               compatible = "qcom,q6asm-dais";
+                                               #sound-dai-cells = <1>;
+                                               iommus = <&lpass_q6_smmu 1>;
+                                       };
+                               };
+
+                               q6adm: q6adm {
+                                       compatible = "qcom,q6adm";
+                                       reg = <APR_SVC_ADM>;
+                                       q6routing: routing {
+                                               compatible = "qcom,q6adm-routing";
+                                               #sound-dai-cells = <0>;
+                                       };
+                               };
+                       };
+
                };
        };
 

diff --git a/arch/arm64/boot/dts/qcom/msm8998-mtp.dtsi b/arch/arm64/boot/dts/qcom/msm8998-mtp.dtsi
index f090106..f09f3e0 100644 (file)
--- a/arch/arm64/boot/dts/qcom/msm8998-mtp.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8998-mtp.dtsi
@@ -15,44 +15,6 @@
                stdout-path = "serial0:115200n8";
        };
 
-       thermal-zones {
-               battery-thermal {
-                       polling-delay-passive = <250>;
-                       polling-delay = <1000>;
-
-                       thermal-sensors = <&tsens0 0>;
-
-                       trips {
-                               battery_crit: trip0 {
-                                       temperature = <60000>;
-                                       hysteresis = <2000>;
-                                       type = "critical";
-                               };
-                       };
-               };
-
-               skin-thermal {
-                       polling-delay-passive = <250>;
-                       polling-delay = <1000>;
-
-                       thermal-sensors = <&tsens1 5>;
-
-                       trips {
-                               skin_alert: trip0 {
-                                       temperature = <44000>;
-                                       hysteresis = <2000>;
-                                       type = "passive";
-                               };
-
-                               skip_crit: trip1 {
-                                       temperature = <70000>;
-                                       hysteresis = <2000>;
-                                       type = "critical";
-                               };
-                       };
-               };
-       };
-
        vph_pwr: vph-pwr-regulator {
                compatible = "regulator-fixed";
                regulator-name = "vph_pwr";
@@ -111,6 +73,7 @@
                vreg_s4a_1p8: s4 {
                        regulator-min-microvolt = <1800000>;
                        regulator-max-microvolt = <1800000>;
+                       regulator-allow-set-load;
                };
                vreg_s5a_2p04: s5 {
                        regulator-min-microvolt = <1904000>;
@@ -195,6 +158,7 @@
                vreg_l20a_2p95: l20 {
                        regulator-min-microvolt = <2960000>;
                        regulator-max-microvolt = <2960000>;
+                       regulator-allow-set-load;
                };
                vreg_l21a_2p95: l21 {
                        regulator-min-microvolt = <2960000>;
@@ -221,6 +185,7 @@
                vreg_l26a_1p2: l26 {
                        regulator-min-microvolt = <1200000>;
                        regulator-max-microvolt = <1200000>;
+                       regulator-allow-set-load;
                };
                vreg_l28_3p0: l28 {
                        regulator-min-microvolt = <3008000>;
@@ -267,6 +232,25 @@
        pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>;
 };
 
+&ufshc {
+       vcc-supply = <&vreg_l20a_2p95>;
+       vccq-supply = <&vreg_l26a_1p2>;
+       vccq2-supply = <&vreg_s4a_1p8>;
+       vcc-max-microamp = <750000>;
+       vccq-max-microamp = <560000>;
+       vccq2-max-microamp = <750000>;
+};
+
+&ufsphy {
+       vdda-phy-supply = <&vreg_l1a_0p875>;
+       vdda-pll-supply = <&vreg_l2a_1p2>;
+       vddp-ref-clk-supply = <&vreg_l26a_1p2>;
+       vdda-phy-max-microamp = <51400>;
+       vdda-pll-max-microamp = <14600>;
+       vddp-ref-clk-max-microamp = <100>;
+       vddp-ref-clk-always-on;
+};
+
 &usb3 {
        status = "okay";
 };

diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi
index 3fd0769..574be78 100644 (file)
--- a/arch/arm64/boot/dts/qcom/msm8998.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi
@@ -78,7 +78,6 @@
                        compatible = "arm,armv8";
                        reg = <0x0 0x0>;
                        enable-method = "psci";
-                       efficiency = <1024>;
                        next-level-cache = <&L2_0>;
                        L2_0: l2-cache {
                                compatible = "arm,arch-cache";
@@ -97,7 +96,6 @@
                        compatible = "arm,armv8";
                        reg = <0x0 0x1>;
                        enable-method = "psci";
-                       efficiency = <1024>;
                        next-level-cache = <&L2_0>;
                        L1_I_1: l1-icache {
                                compatible = "arm,arch-cache";
@@ -112,7 +110,6 @@
                        compatible = "arm,armv8";
                        reg = <0x0 0x2>;
                        enable-method = "psci";
-                       efficiency = <1024>;
                        next-level-cache = <&L2_0>;
                        L1_I_2: l1-icache {
                                compatible = "arm,arch-cache";
@@ -127,7 +124,6 @@
                        compatible = "arm,armv8";
                        reg = <0x0 0x3>;
                        enable-method = "psci";
-                       efficiency = <1024>;
                        next-level-cache = <&L2_0>;
                        L1_I_3: l1-icache {
                                compatible = "arm,arch-cache";
@@ -142,7 +138,6 @@
                        compatible = "arm,armv8";
                        reg = <0x0 0x100>;
                        enable-method = "psci";
-                       efficiency = <1536>;
                        next-level-cache = <&L2_1>;
                        L2_1: l2-cache {
                                compatible = "arm,arch-cache";
@@ -161,7 +156,6 @@
                        compatible = "arm,armv8";
                        reg = <0x0 0x101>;
                        enable-method = "psci";
-                       efficiency = <1536>;
                        next-level-cache = <&L2_1>;
                        L1_I_101: l1-icache {
                                compatible = "arm,arch-cache";
@@ -176,7 +170,6 @@
                        compatible = "arm,armv8";
                        reg = <0x0 0x102>;
                        enable-method = "psci";
-                       efficiency = <1536>;
                        next-level-cache = <&L2_1>;
                        L1_I_102: l1-icache {
                                compatible = "arm,arch-cache";
@@ -191,7 +184,6 @@
                        compatible = "arm,armv8";
                        reg = <0x0 0x103>;
                        enable-method = "psci";
-                       efficiency = <1536>;
                        next-level-cache = <&L2_1>;
                        L1_I_103: l1-icache {
                                compatible = "arm,arch-cache";
@@ -346,20 +338,20 @@
        };
 
        thermal-zones {
-               cpu-thermal0 {
+               cpu0-thermal {
                        polling-delay-passive = <250>;
                        polling-delay = <1000>;
 
-                       thermal-sensors = <&tsens0 6>;
+                       thermal-sensors = <&tsens0 1>;
 
                        trips {
-                               cpu_alert0: trip0 {
+                               cpu0_alert0: trip-point@0 {
                                        temperature = <75000>;
                                        hysteresis = <2000>;
                                        type = "passive";
                                };
 
-                               cpu_crit0: trip1 {
+                               cpu0_crit: cpu_crit {
                                        temperature = <110000>;
                                        hysteresis = <2000>;
                                        type = "critical";
@@ -367,20 +359,20 @@
                        };
                };
 
-               cpu-thermal1 {
+               cpu1-thermal {
                        polling-delay-passive = <250>;
                        polling-delay = <1000>;
 
-                       thermal-sensors = <&tsens0 7>;
+                       thermal-sensors = <&tsens0 2>;
 
                        trips {
-                               cpu_alert1: trip0 {
+                               cpu1_alert0: trip-point@0 {
                                        temperature = <75000>;
                                        hysteresis = <2000>;
                                        type = "passive";
                                };
 
-                               cpu_crit1: trip1 {
+                               cpu1_crit: cpu_crit {
                                        temperature = <110000>;
                                        hysteresis = <2000>;
                                        type = "critical";
@@ -388,20 +380,20 @@
                        };
                };
 
-               cpu-thermal2 {
+               cpu2-thermal {
                        polling-delay-passive = <250>;
                        polling-delay = <1000>;
 
-                       thermal-sensors = <&tsens0 8>;
+                       thermal-sensors = <&tsens0 3>;
 
                        trips {
-                               cpu_alert2: trip0 {
+                               cpu2_alert0: trip-point@0 {
                                        temperature = <75000>;
                                        hysteresis = <2000>;
                                        type = "passive";
                                };
 
-                               cpu_crit2: trip1 {
+                               cpu2_crit: cpu_crit {
                                        temperature = <110000>;
                                        hysteresis = <2000>;
                                        type = "critical";
@@ -409,20 +401,20 @@
                        };
                };
 
-               cpu-thermal3 {
+               cpu3-thermal {
                        polling-delay-passive = <250>;
                        polling-delay = <1000>;
 
-                       thermal-sensors = <&tsens0 9>;
+                       thermal-sensors = <&tsens0 4>;
 
                        trips {
-                               cpu_alert3: trip0 {
+                               cpu3_alert0: trip-point@0 {
                                        temperature = <75000>;
                                        hysteresis = <2000>;
                                        type = "passive";
                                };
 
-                               cpu_crit3: trip1 {
+                               cpu3_crit: cpu_crit {
                                        temperature = <110000>;
                                        hysteresis = <2000>;
                                        type = "critical";
@@ -430,20 +422,20 @@
                        };
                };
 
-               cpu-thermal4 {
+               cpu4-thermal {
                        polling-delay-passive = <250>;
                        polling-delay = <1000>;
 
-                       thermal-sensors = <&tsens0 10>;
+                       thermal-sensors = <&tsens0 7>;
 
                        trips {
-                               cpu_alert4: trip0 {
+                               cpu4_alert0: trip-point@0 {
                                        temperature = <75000>;
                                        hysteresis = <2000>;
                                        type = "passive";
                                };
 
-                               cpu_crit4: trip1 {
+                               cpu4_crit: cpu_crit {
                                        temperature = <110000>;
                                        hysteresis = <2000>;
                                        type = "critical";
@@ -451,20 +443,20 @@
                        };
                };
 
-               cpu-thermal5 {
+               cpu5-thermal {
                        polling-delay-passive = <250>;
                        polling-delay = <1000>;
 
-                       thermal-sensors = <&tsens0 11>;
+                       thermal-sensors = <&tsens0 8>;
 
                        trips {
-                               cpu_alert5: trip0 {
+                               cpu5_alert0: trip-point@0 {
                                        temperature = <75000>;
                                        hysteresis = <2000>;
                                        type = "passive";
                                };
 
-                               cpu_crit5: trip1 {
+                               cpu5_crit: cpu_crit {
                                        temperature = <110000>;
                                        hysteresis = <2000>;
                                        type = "critical";
@@ -472,20 +464,20 @@
                        };
                };
 
-               cpu-thermal6 {
+               cpu6-thermal {
                        polling-delay-passive = <250>;
                        polling-delay = <1000>;
 
-                       thermal-sensors = <&tsens1 0>;
+                       thermal-sensors = <&tsens0 9>;
 
                        trips {
-                               cpu_alert6: trip0 {
+                               cpu6_alert0: trip-point@0 {
                                        temperature = <75000>;
                                        hysteresis = <2000>;
                                        type = "passive";
                                };
 
-                               cpu_crit6: trip1 {
+                               cpu6_crit: cpu_crit {
                                        temperature = <110000>;
                                        hysteresis = <2000>;
                                        type = "critical";
@@ -493,20 +485,20 @@
                        };
                };
 
-               cpu-thermal7 {
+               cpu7-thermal {
                        polling-delay-passive = <250>;
                        polling-delay = <1000>;
 
-                       thermal-sensors = <&tsens1 1>;
+                       thermal-sensors = <&tsens0 10>;
 
                        trips {
-                               cpu_alert7: trip0 {
+                               cpu7_alert0: trip-point@0 {
                                        temperature = <75000>;
                                        hysteresis = <2000>;
                                        type = "passive";
                                };
 
-                               cpu_crit7: trip1 {
+                               cpu7_crit: cpu_crit {
                                        temperature = <110000>;
                                        hysteresis = <2000>;
                                        type = "critical";
@@ -514,11 +506,169 @@
                        };
                };
 
-               gpu-thermal {
+               gpu-thermal-bottom {
+                       polling-delay-passive = <250>;
+                       polling-delay = <1000>;
+
+                       thermal-sensors = <&tsens0 12>;
+
+                       trips {
+                               gpu1_alert0: trip-point@0 {
+                                       temperature = <90000>;
+                                       hysteresis = <2000>;
+                                       type = "hot";
+                               };
+                       };
+               };
+
+               gpu-thermal-top {
+                       polling-delay-passive = <250>;
+                       polling-delay = <1000>;
+
+                       thermal-sensors = <&tsens0 13>;
+
+                       trips {
+                               gpu2_alert0: trip-point@0 {
+                                       temperature = <90000>;
+                                       hysteresis = <2000>;
+                                       type = "hot";
+                               };
+                       };
+               };
+
+               clust0-mhm-thermal {
+                       polling-delay-passive = <250>;
+                       polling-delay = <1000>;
+
+                       thermal-sensors = <&tsens0 5>;
+
+                       trips {
+                               cluster0_mhm_alert0: trip-point@0 {
+                                       temperature = <90000>;
+                                       hysteresis = <2000>;
+                                       type = "hot";
+                               };
+                       };
+               };
+
+               clust1-mhm-thermal {
+                       polling-delay-passive = <250>;
+                       polling-delay = <1000>;
+
+                       thermal-sensors = <&tsens0 6>;
+
+                       trips {
+                               cluster1_mhm_alert0: trip-point@0 {
+                                       temperature = <90000>;
+                                       hysteresis = <2000>;
+                                       type = "hot";
+                               };
+                       };
+               };
+
+               cluster1-l2-thermal {
+                       polling-delay-passive = <250>;
+                       polling-delay = <1000>;
+
+                       thermal-sensors = <&tsens0 11>;
+
+                       trips {
+                               cluster1_l2_alert0: trip-point@0 {
+                                       temperature = <90000>;
+                                       hysteresis = <2000>;
+                                       type = "hot";
+                               };
+                       };
+               };
+
+               modem-thermal {
+                       polling-delay-passive = <250>;
+                       polling-delay = <1000>;
+
+                       thermal-sensors = <&tsens1 1>;
+
+                       trips {
+                               modem_alert0: trip-point@0 {
+                                       temperature = <90000>;
+                                       hysteresis = <2000>;
+                                       type = "hot";
+                               };
+                       };
+               };
+
+               mem-thermal {
+                       polling-delay-passive = <250>;
+                       polling-delay = <1000>;
+
+                       thermal-sensors = <&tsens1 2>;
+
+                       trips {
+                               mem_alert0: trip-point@0 {
+                                       temperature = <90000>;
+                                       hysteresis = <2000>;
+                                       type = "hot";
+                               };
+                       };
+               };
+
+               wlan-thermal {
                        polling-delay-passive = <250>;
                        polling-delay = <1000>;
 
                        thermal-sensors = <&tsens1 3>;
+
+                       trips {
+                               wlan_alert0: trip-point@0 {
+                                       temperature = <90000>;
+                                       hysteresis = <2000>;
+                                       type = "hot";
+                               };
+                       };
+               };
+
+               q6-dsp-thermal {
+                       polling-delay-passive = <250>;
+                       polling-delay = <1000>;
+
+                       thermal-sensors = <&tsens1 4>;
+
+                       trips {
+                               q6_dsp_alert0: trip-point@0 {
+                                       temperature = <90000>;
+                                       hysteresis = <2000>;
+                                       type = "hot";
+                               };
+                       };
+               };
+
+               camera-thermal {
+                       polling-delay-passive = <250>;
+                       polling-delay = <1000>;
+
+                       thermal-sensors = <&tsens1 5>;
+
+                       trips {
+                               camera_alert0: trip-point@0 {
+                                       temperature = <90000>;
+                                       hysteresis = <2000>;
+                                       type = "hot";
+                               };
+                       };
+               };
+
+               multimedia-thermal {
+                       polling-delay-passive = <250>;
+                       polling-delay = <1000>;
+
+                       thermal-sensors = <&tsens1 6>;
+
+                       trips {
+                               multimedia_alert0: trip-point@0 {
+                                       temperature = <90000>;
+                                       hysteresis = <2000>;
+                                       type = "hot";
+                               };
+                       };
                };
        };
 
@@ -590,17 +740,19 @@
                        cell-index = <0>;
                };
 
-               tsens0: thermal@10aa000 {
+               tsens0: thermal@10ab000 {
                        compatible = "qcom,msm8998-tsens", "qcom,tsens-v2";
-                       reg = <0x10aa000 0x2000>;
+                       reg = <0x10ab000 0x1000>, /* TM */
+                             <0x10aa000 0x1000>; /* SROT */
 
-                       #qcom,sensors = <12>;
+                       #qcom,sensors = <14>;
                        #thermal-sensor-cells = <1>;
                };
 
-               tsens1: thermal@10ad000 {
+               tsens1: thermal@10ae000 {
                        compatible = "qcom,msm8998-tsens", "qcom,tsens-v2";
-                       reg = <0x10ad000 0x2000>;
+                       reg = <0x10ae000 0x1000>, /* TM */
+                             <0x10ad000 0x1000>; /* SROT */
 
                        #qcom,sensors = <8>;
                        #thermal-sensor-cells = <1>;
@@ -889,7 +1041,7 @@
 
                blsp2_i2c5: i2c@c1ba000 {
                        compatible = "qcom,i2c-qup-v2.2.1";
-                       reg = <0x0c175000 0x600>;
+                       reg = <0x0c1ba000 0x600>;
                        interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
 
                        clocks = <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>,
@@ -983,6 +1135,75 @@
                        redistributor-stride = <0x0 0x20000>;
                        interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
                };
+
+               ufshc: ufshc@1da4000 {
+                       compatible = "qcom,msm8998-ufshc", "qcom,ufshc", "jedec,ufs-2.0";
+                       reg = <0x01da4000 0x2500>;
+                       interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
+                       phys = <&ufsphy_lanes>;
+                       phy-names = "ufsphy";
+                       lanes-per-direction = <2>;
+                       power-domains = <&gcc UFS_GDSC>;
+                       #reset-cells = <1>;
+
+                       clock-names =
+                               "core_clk",
+                               "bus_aggr_clk",
+                               "iface_clk",
+                               "core_clk_unipro",
+                               "ref_clk",
+                               "tx_lane0_sync_clk",
+                               "rx_lane0_sync_clk",
+                               "rx_lane1_sync_clk";
+                       clocks =
+                               <&gcc GCC_UFS_AXI_CLK>,
+                               <&gcc GCC_AGGRE1_UFS_AXI_CLK>,
+                               <&gcc GCC_UFS_AHB_CLK>,
+                               <&gcc GCC_UFS_UNIPRO_CORE_CLK>,
+                               <&rpmcc RPM_SMD_LN_BB_CLK1>,
+                               <&gcc GCC_UFS_TX_SYMBOL_0_CLK>,
+                               <&gcc GCC_UFS_RX_SYMBOL_0_CLK>,
+                               <&gcc GCC_UFS_RX_SYMBOL_1_CLK>;
+                       freq-table-hz =
+                               <50000000 200000000>,
+                               <0 0>,
+                               <0 0>,
+                               <37500000 150000000>,
+                               <0 0>,
+                               <0 0>,
+                               <0 0>,
+                               <0 0>;
+
+                       resets = <&gcc GCC_UFS_BCR>;
+                       reset-names = "rst";
+               };
+
+               ufsphy: phy@1da7000 {
+                       compatible = "qcom,msm8998-qmp-ufs-phy";
+                       reg = <0x01da7000 0x18c>;
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       ranges;
+
+                       clock-names =
+                               "ref",
+                               "ref_aux";
+                       clocks =
+                               <&gcc GCC_UFS_CLKREF_CLK>,
+                               <&gcc GCC_UFS_PHY_AUX_CLK>;
+
+                       reset-names = "ufsphy";
+                       resets = <&ufshc 0>;
+
+                       ufsphy_lanes: lanes@1da7400 {
+                               reg = <0x01da7400 0x128>,
+                                     <0x01da7600 0x1fc>,
+                                     <0x01da7c00 0x1dc>,
+                                     <0x01da7800 0x128>,
+                                     <0x01da7a00 0x1fc>;
+                               #phy-cells = <0>;
+                       };
+               };
        };
 };
 

diff --git a/arch/arm64/boot/dts/qcom/pm8005.dtsi b/arch/arm64/boot/dts/qcom/pm8005.dtsi
index c0ddf12..3f97607 100644 (file)
--- a/arch/arm64/boot/dts/qcom/pm8005.dtsi
+++ b/arch/arm64/boot/dts/qcom/pm8005.dtsi
@@ -15,6 +15,7 @@
                        compatible = "qcom,pm8005-gpio", "qcom,spmi-gpio";
                        reg = <0xc000>;
                        gpio-controller;
+                       gpio-ranges = <&pm8005_gpio 0 0 4>;
                        #gpio-cells = <2>;
                        interrupt-controller;
                        #interrupt-cells = <2>;

diff --git a/arch/arm64/boot/dts/qcom/pm8998.dtsi b/arch/arm64/boot/dts/qcom/pm8998.dtsi
index 43cb5ea..d3ca35a 100644 (file)
--- a/arch/arm64/boot/dts/qcom/pm8998.dtsi
+++ b/arch/arm64/boot/dts/qcom/pm8998.dtsi
@@ -58,6 +58,8 @@
                        compatible = "qcom,spmi-temp-alarm";
                        reg = <0x2400>;
                        interrupts = <0x0 0x24 0x0 IRQ_TYPE_EDGE_RISING>;
+                       io-channels = <&pm8998_adc ADC5_DIE_TEMP>;
+                       io-channel-names = "thermal";
                        #thermal-sensor-cells = <0>;
                };
 
@@ -93,6 +95,7 @@
                        compatible = "qcom,pm8998-gpio", "qcom,spmi-gpio";
                        reg = <0xc000>;
                        gpio-controller;
+                       gpio-ranges = <&pm8998_gpio 0 0 26>;
                        #gpio-cells = <2>;
                        interrupt-controller;
                        #interrupt-cells = <2>;

diff --git a/arch/arm64/boot/dts/qcom/pmi8994.dtsi b/arch/arm64/boot/dts/qcom/pmi8994.dtsi
index 3aee10e..21e0521 100644 (file)
--- a/arch/arm64/boot/dts/qcom/pmi8994.dtsi
+++ b/arch/arm64/boot/dts/qcom/pmi8994.dtsi
@@ -14,6 +14,7 @@
                        compatible = "qcom,pmi8994-gpio", "qcom,spmi-gpio";
                        reg = <0xc000>;
                        gpio-controller;
+                       gpio-ranges = <&pmi8994_gpios 0 0 10>;
                        #gpio-cells = <2>;
                        interrupt-controller;
                        #interrupt-cells = <2>;

diff --git a/arch/arm64/boot/dts/qcom/pmi8998.dtsi b/arch/arm64/boot/dts/qcom/pmi8998.dtsi
index 051f57e..23f9146 100644 (file)
--- a/arch/arm64/boot/dts/qcom/pmi8998.dtsi
+++ b/arch/arm64/boot/dts/qcom/pmi8998.dtsi
@@ -13,6 +13,7 @@
                        compatible = "qcom,pmi8998-gpio", "qcom,spmi-gpio";
                        reg = <0xc000>;
                        gpio-controller;
+                       gpio-ranges = <&pmi8998_gpio 0 0 14>;
                        #gpio-cells = <2>;
                        interrupt-controller;
                        #interrupt-cells = <2>;

diff --git a/arch/arm64/boot/dts/qcom/pms405.dtsi b/arch/arm64/boot/dts/qcom/pms405.dtsi
index 1bb836d..e8e186b 100644 (file)
--- a/arch/arm64/boot/dts/qcom/pms405.dtsi
+++ b/arch/arm64/boot/dts/qcom/pms405.dtsi
@@ -131,4 +131,15 @@
                        interrupts = <0x0 0x61 0x1 IRQ_TYPE_NONE>;
                };
        };
+
+       pms405_1: pms405@1 {
+               compatible = "qcom,spmi-pmic";
+               reg = <0x1 SPMI_USID>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               pms405_spmi_regulators: regulators {
+                       compatible = "qcom,pms405-regulators";
+               };
+       };
 };

diff --git a/arch/arm64/boot/dts/qcom/qcs404-evb-1000.dts b/arch/arm64/boot/dts/qcom/qcs404-evb-1000.dts
index 2c14903..937eb45 100644 (file)
--- a/arch/arm64/boot/dts/qcom/qcs404-evb-1000.dts
+++ b/arch/arm64/boot/dts/qcom/qcs404-evb-1000.dts
@@ -7,5 +7,6 @@
 
 / {
        model = "Qualcomm Technologies, Inc. QCS404 EVB 1000";
-       compatible = "qcom,qcs404-evb";
+       compatible = "qcom,qcs404-evb-1000", "qcom,qcs404-evb",
+                    "qcom,qcs404";
 };

diff --git a/arch/arm64/boot/dts/qcom/qcs404-evb-4000.dts b/arch/arm64/boot/dts/qcom/qcs404-evb-4000.dts
index 11269ad..479ad3a 100644 (file)
--- a/arch/arm64/boot/dts/qcom/qcs404-evb-4000.dts
+++ b/arch/arm64/boot/dts/qcom/qcs404-evb-4000.dts
@@ -3,9 +3,92 @@
 
 /dts-v1/;
 
+#include <dt-bindings/gpio/gpio.h>
 #include "qcs404-evb.dtsi"
 
 / {
        model = "Qualcomm Technologies, Inc. QCS404 EVB 4000";
-       compatible = "qcom,qcs404-evb";
+       compatible = "qcom,qcs404-evb-4000", "qcom,qcs404-evb",
+                    "qcom,qcs404";
+};
+
+&ethernet {
+       status = "ok";
+
+       snps,reset-gpio = <&tlmm 60 GPIO_ACTIVE_LOW>;
+       snps,reset-active-low;
+       snps,reset-delays-us = <0 10000 10000>;
+
+       pinctrl-names = "default";
+       pinctrl-0 = <&ethernet_defaults>;
+
+       phy-handle = <&phy1>;
+       phy-mode = "rgmii";
+       mdio {
+               #address-cells = <0x1>;
+               #size-cells = <0x0>;
+               compatible = "snps,dwmac-mdio";
+               phy1: phy@4 {
+                       compatible = "ethernet-phy-ieee802.3-c22";
+                       device_type = "ethernet-phy";
+                       reg = <0x4>;
+               };
+       };
+};
+
+&tlmm {
+       ethernet_defaults: ethernet-defaults {
+               int {
+                       pins = "gpio61";
+                       function = "rgmii_int";
+                       bias-disable;
+                       drive-strength = <2>;
+               };
+               mdc {
+                       pins = "gpio76";
+                       function = "rgmii_mdc";
+                       bias-pull-up;
+               };
+               mdio {
+                       pins = "gpio75";
+                       function = "rgmii_mdio";
+                       bias-pull-up;
+               };
+               tx {
+                       pins = "gpio67", "gpio66", "gpio65", "gpio64";
+                       function = "rgmii_tx";
+                       bias-pull-up;
+                       drive-strength = <16>;
+               };
+               rx {
+                       pins = "gpio73", "gpio72", "gpio71", "gpio70";
+                       function = "rgmii_rx";
+                       bias-disable;
+                       drive-strength = <2>;
+               };
+               tx-ctl {
+                       pins = "gpio68";
+                       function = "rgmii_ctl";
+                       bias-pull-up;
+                       drive-strength = <16>;
+               };
+               rx-ctl {
+                       pins = "gpio74";
+                       function = "rgmii_ctl";
+                       bias-disable;
+                       drive-strength = <2>;
+               };
+               tx-ck {
+                       pins = "gpio63";
+                       function = "rgmii_ck";
+                       bias-pull-up;
+                       drive-strength = <16>;
+               };
+               rx-ck {
+                       pins = "gpio69";
+                       function = "rgmii_ck";
+                       bias-disable;
+                       drive-strength = <2>;
+               };
+       };
 };

diff --git a/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi b/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi
index 50b3589..2c31271 100644 (file)
--- a/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi
+++ b/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi
@@ -7,6 +7,7 @@
 / {
        aliases {
                serial0 = &blsp1_uart2;
+               serial1 = &blsp1_uart3;
        };
 
        chosen {
@@ -19,6 +20,52 @@
                regulator-always-on;
                regulator-boot-on;
        };
+
+       vdd_ch0_3p3:
+       vdd_esmps3_3p3: vdd-esmps3-3p3-regulator {
+               compatible = "regulator-fixed";
+               regulator-name = "eSMPS3_3P3";
+
+               regulator-min-microvolt = <3300000>;
+               regulator-max-microvolt = <3300000>;
+               regulator-always-on;
+       };
+};
+
+&blsp1_uart3 {
+       status = "okay";
+
+       bluetooth {
+               compatible = "qcom,wcn3990-bt";
+               vddio-supply = <&vreg_l6_1p8>;
+               vddxo-supply = <&vreg_l5_1p8>;
+               vddrf-supply = <&vreg_l1_1p3>;
+               vddch0-supply = <&vdd_ch0_3p3>;
+
+               local-bd-address = [ 02 00 00 00 5a ad ];
+
+               max-speed = <3200000>;
+       };
+};
+
+&blsp1_dma {
+       qcom,controlled-remotely;
+};
+
+&blsp2_dma {
+       qcom,controlled-remotely;
+};
+
+&pms405_spmi_regulators {
+       vdd_s3-supply = <&pms405_s3>;
+
+       pms405_s3: s3 {
+               regulator-always-on;
+               regulator-boot-on;
+               regulator-name = "vdd_apc";
+               regulator-min-microvolt = <1048000>;
+               regulator-max-microvolt = <1352000>;
+       };
 };
 
 &remoteproc_adsp {
@@ -37,18 +84,18 @@
        pms405-regulators {
                compatible = "qcom,rpm-pms405-regulators";
 
-               vdd-s1-supply = <&vph_pwr>;
-               vdd-s2-supply = <&vph_pwr>;
-               vdd-s3-supply = <&vph_pwr>;
-               vdd-s4-supply = <&vph_pwr>;
-               vdd-s5-supply = <&vph_pwr>;
-               vdd-l1-l2-supply = <&vreg_s5_1p35>;
-               vdd-l3-l8-supply = <&vreg_s5_1p35>;
-               vdd-l4-supply = <&vreg_s5_1p35>;
-               vdd-l5-l6-supply = <&vreg_s4_1p8>;
-               vdd-l7-supply = <&vph_pwr>;
-               vdd-l9-supply = <&vreg_s5_1p35>;
-               vdd-l10-l11-l12-l13-supply = <&vph_pwr>;
+               vdd_s1-supply = <&vph_pwr>;
+               vdd_s2-supply = <&vph_pwr>;
+               vdd_s3-supply = <&vph_pwr>;
+               vdd_s4-supply = <&vph_pwr>;
+               vdd_s5-supply = <&vph_pwr>;
+               vdd_l1_l2-supply = <&vreg_s5_1p35>;
+               vdd_l3_l8-supply = <&vreg_s5_1p35>;
+               vdd_l4-supply = <&vreg_s5_1p35>;
+               vdd_l5_l6-supply = <&vreg_s4_1p8>;
+               vdd_l7-supply = <&vph_pwr>;
+               vdd_l9-supply = <&vreg_s5_1p35>;
+               vdd_l10_l11_l12_l13-supply = <&vph_pwr>;
 
                vreg_s4_1p8: s4 {
                        regulator-min-microvolt = <1728000>;
@@ -56,8 +103,8 @@
                };
 
                vreg_s5_1p35: s5 {
-                       regulator-min-microvolt = <>;
-                       regulator-max-microvolt = <>;
+                       regulator-min-microvolt = <1352000>;
+                       regulator-max-microvolt = <1352000>;
                };
 
                vreg_l1_1p3: l1 {
@@ -71,7 +118,7 @@
                };
 
                vreg_l3_1p05: l3 {
-                       regulator-min-microvolt = <976000>;
+                       regulator-min-microvolt = <1050000>;
                        regulator-max-microvolt = <1160000>;
                };
 
@@ -205,3 +252,21 @@
                bias-disable;
        };
 };
+
+&blsp1_uart3_default {
+       cts {
+               pins = "gpio84";
+               bias-disable;
+       };
+
+       rts-tx {
+               pins = "gpio85", "gpio82";
+               drive-strength = <2>;
+               bias-disable;
+       };
+
+       rx {
+               pins = "gpio83";
+               bias-pull-up;
+       };
+};

diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi
index e8fd266..ffedf96 100644 (file)
--- a/arch/arm64/boot/dts/qcom/qcs404.dtsi
+++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi
@@ -435,7 +435,6 @@
                        clocks = <&gcc GCC_BLSP1_AHB_CLK>;
                        clock-names = "bam_clk";
                        #dma-cells = <1>;
-                       qcom,controlled-remotely = <1>;
                        qcom,ee = <0>;
                        status = "okay";
                };
@@ -479,6 +478,27 @@
                        status = "okay";
                };
 
+               ethernet: ethernet@7a80000 {
+                       compatible = "qcom,qcs404-ethqos";
+                       reg = <0x07a80000 0x10000>,
+                               <0x07a96000 0x100>;
+                       reg-names = "stmmaceth", "rgmii";
+                       clock-names = "stmmaceth", "pclk", "ptp_ref", "rgmii";
+                       clocks = <&gcc GCC_ETH_AXI_CLK>,
+                               <&gcc GCC_ETH_SLAVE_AHB_CLK>,
+                               <&gcc GCC_ETH_PTP_CLK>,
+                               <&gcc GCC_ETH_RGMII_CLK>;
+                       interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
+                                       <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-names = "macirq", "eth_lpi";
+
+                       snps,tso;
+                       rx-fifo-depth = <4096>;
+                       tx-fifo-depth = <4096>;
+
+                       status = "disabled";
+               };
+
                wifi: wifi@a000000 {
                        compatible = "qcom,wcn3990-wifi";
                        reg = <0xa000000 0x800000>;
@@ -659,7 +679,6 @@
                        clocks = <&gcc GCC_BLSP2_AHB_CLK>;
                        clock-names = "bam_clk";
                        #dma-cells = <1>;
-                       qcom,controlled-remotely = <1>;
                        qcom,ee = <0>;
                        status = "disabled";
                };

diff --git a/arch/arm64/boot/dts/qcom/sdm845-mtp.dts b/arch/arm64/boot/dts/qcom/sdm845-mtp.dts
index af8c6a2..02b8357 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sdm845-mtp.dts
+++ b/arch/arm64/boot/dts/qcom/sdm845-mtp.dts
@@ -48,6 +48,10 @@
        };
 };
 
+&adsp_pas {
+       status = "okay";
+};
+
 &apps_rsc {
        pm8998-rpmh-regulators {
                compatible = "qcom,pm8998-rpmh-regulators";
@@ -344,6 +348,10 @@
        };
 };
 
+&cdsp_pas {
+       status = "okay";
+};
+
 &gcc {
        protected-clocks = <GCC_QSPI_CORE_CLK>,
                           <GCC_QSPI_CORE_CLK_SRC>,

diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index 5308f16..fcb9330 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
@@ -11,8 +11,10 @@
 #include <dt-bindings/clock/qcom,lpass-sdm845.h>
 #include <dt-bindings/clock/qcom,rpmh.h>
 #include <dt-bindings/clock/qcom,videocc-sdm845.h>
+#include <dt-bindings/interconnect/qcom,sdm845.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/phy/phy-qcom-qusb2.h>
+#include <dt-bindings/power/qcom-rpmpd.h>
 #include <dt-bindings/reset/qcom,sdm845-aoss.h>
 #include <dt-bindings/reset/qcom,sdm845-pdc.h>
 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
@@ -73,29 +75,78 @@
                #size-cells = <2>;
                ranges;
 
-               memory@85fc0000 {
+               hyp_mem: memory@85700000 {
+                       reg = <0 0x85700000 0 0x600000>;
+                       no-map;
+               };
+
+               xbl_mem: memory@85e00000 {
+                       reg = <0 0x85e00000 0 0x100000>;
+                       no-map;
+               };
+
+               aop_mem: memory@85fc0000 {
                        reg = <0 0x85fc0000 0 0x20000>;
                        no-map;
                };
 
-               memory@85fe0000 {
+               aop_cmd_db_mem: memory@85fe0000 {
                        compatible = "qcom,cmd-db";
-                       reg = <0x0 0x85fe0000 0x0 0x20000>;
+                       reg = <0x0 0x85fe0000 0 0x20000>;
                        no-map;
                };
 
                smem_mem: memory@86000000 {
-                       reg = <0x0 0x86000000 0x0 0x200000>;
+                       reg = <0x0 0x86000000 0 0x200000>;
                        no-map;
                };
 
-               memory@86200000 {
+               tz_mem: memory@86200000 {
                        reg = <0 0x86200000 0 0x2d00000>;
                        no-map;
                };
 
-               wlan_msa_mem: memory@96700000 {
-                       reg = <0 0x96700000 0 0x100000>;
+               rmtfs_mem: memory@88f00000 {
+                       compatible = "qcom,rmtfs-mem";
+                       reg = <0 0x88f00000 0 0x200000>;
+                       no-map;
+
+                       qcom,client-id = <1>;
+                       qcom,vmid = <15>;
+               };
+
+               qseecom_mem: memory@8ab00000 {
+                       reg = <0 0x8ab00000 0 0x1400000>;
+                       no-map;
+               };
+
+               camera_mem: memory@8bf00000 {
+                       reg = <0 0x8bf00000 0 0x500000>;
+                       no-map;
+               };
+
+               ipa_fw_mem: memory@8c400000 {
+                       reg = <0 0x8c400000 0 0x10000>;
+                       no-map;
+               };
+
+               ipa_gsi_mem: memory@8c410000 {
+                       reg = <0 0x8c410000 0 0x5000>;
+                       no-map;
+               };
+
+               gpu_mem: memory@8c415000 {
+                       reg = <0 0x8c415000 0 0x2000>;
+                       no-map;
+               };
+
+               adsp_mem: memory@8c500000 {
+                       reg = <0 0x8c500000 0 0x1a00000>;
+                       no-map;
+               };
+
+               wlan_msa_mem: memory@8df00000 {
+                       reg = <0 0x8df00000 0 0x100000>;
                        no-map;
                };
 
@@ -104,10 +155,30 @@
                        no-map;
                };
 
+               venus_mem: memory@95800000 {
+                       reg = <0 0x95800000 0 0x500000>;
+                       no-map;
+               };
+
+               cdsp_mem: memory@95d00000 {
+                       reg = <0 0x95d00000 0 0x800000>;
+                       no-map;
+               };
+
                mba_region: memory@96500000 {
                        reg = <0 0x96500000 0 0x200000>;
                        no-map;
                };
+
+               slpi_mem: memory@96700000 {
+                       reg = <0 0x96700000 0 0x1400000>;
+                       no-map;
+               };
+
+               spss_mem: memory@97b00000 {
+                       reg = <0 0x97b00000 0 0x100000>;
+                       no-map;
+               };
        };
 
        cpus {
@@ -119,6 +190,7 @@
                        compatible = "qcom,kryo385";
                        reg = <0x0 0x0>;
                        enable-method = "psci";
+                       capacity-dmips-mhz = <607>;
                        qcom,freq-domain = <&cpufreq_hw 0>;
                        #cooling-cells = <2>;
                        next-level-cache = <&L2_0>;
@@ -136,6 +208,7 @@
                        compatible = "qcom,kryo385";
                        reg = <0x0 0x100>;
                        enable-method = "psci";
+                       capacity-dmips-mhz = <607>;
                        qcom,freq-domain = <&cpufreq_hw 0>;
                        #cooling-cells = <2>;
                        next-level-cache = <&L2_100>;
@@ -150,6 +223,7 @@
                        compatible = "qcom,kryo385";
                        reg = <0x0 0x200>;
                        enable-method = "psci";
+                       capacity-dmips-mhz = <607>;
                        qcom,freq-domain = <&cpufreq_hw 0>;
                        #cooling-cells = <2>;
                        next-level-cache = <&L2_200>;
@@ -164,6 +238,7 @@
                        compatible = "qcom,kryo385";
                        reg = <0x0 0x300>;
                        enable-method = "psci";
+                       capacity-dmips-mhz = <607>;
                        qcom,freq-domain = <&cpufreq_hw 0>;
                        #cooling-cells = <2>;
                        next-level-cache = <&L2_300>;
@@ -178,6 +253,7 @@
                        compatible = "qcom,kryo385";
                        reg = <0x0 0x400>;
                        enable-method = "psci";
+                       capacity-dmips-mhz = <1024>;
                        qcom,freq-domain = <&cpufreq_hw 1>;
                        #cooling-cells = <2>;
                        next-level-cache = <&L2_400>;
@@ -192,6 +268,7 @@
                        compatible = "qcom,kryo385";
                        reg = <0x0 0x500>;
                        enable-method = "psci";
+                       capacity-dmips-mhz = <1024>;
                        qcom,freq-domain = <&cpufreq_hw 1>;
                        #cooling-cells = <2>;
                        next-level-cache = <&L2_500>;
@@ -206,6 +283,7 @@
                        compatible = "qcom,kryo385";
                        reg = <0x0 0x600>;
                        enable-method = "psci";
+                       capacity-dmips-mhz = <1024>;
                        qcom,freq-domain = <&cpufreq_hw 1>;
                        #cooling-cells = <2>;
                        next-level-cache = <&L2_600>;
@@ -220,6 +298,7 @@
                        compatible = "qcom,kryo385";
                        reg = <0x0 0x700>;
                        enable-method = "psci";
+                       capacity-dmips-mhz = <1024>;
                        qcom,freq-domain = <&cpufreq_hw 1>;
                        #cooling-cells = <2>;
                        next-level-cache = <&L2_700>;
@@ -228,6 +307,44 @@
                                next-level-cache = <&L3_0>;
                        };
                };
+
+               cpu-map {
+                       cluster0 {
+                               core0 {
+                                       cpu = <&CPU0>;
+                               };
+
+                               core1 {
+                                       cpu = <&CPU1>;
+                               };
+
+                               core2 {
+                                       cpu = <&CPU2>;
+                               };
+
+                               core3 {
+                                       cpu = <&CPU3>;
+                               };
+                       };
+
+                       cluster1 {
+                               core0 {
+                                       cpu = <&CPU4>;
+                               };
+
+                               core1 {
+                                       cpu = <&CPU5>;
+                               };
+
+                               core2 {
+                                       cpu = <&CPU6>;
+                               };
+
+                               core3 {
+                                       cpu = <&CPU7>;
+                               };
+                       };
+               };
        };
 
        pmu {
@@ -264,6 +381,64 @@
                };
        };
 
+       adsp_pas: remoteproc-adsp {
+               compatible = "qcom,sdm845-adsp-pas";
+
+               interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
+                                     <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
+                                     <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
+                                     <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
+                                     <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
+               interrupt-names = "wdog", "fatal", "ready",
+                                 "handover", "stop-ack";
+
+               clocks = <&rpmhcc RPMH_CXO_CLK>;
+               clock-names = "xo";
+
+               memory-region = <&adsp_mem>;
+
+               qcom,smem-states = <&adsp_smp2p_out 0>;
+               qcom,smem-state-names = "stop";
+
+               status = "disabled";
+
+               glink-edge {
+                       interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
+                       label = "lpass";
+                       qcom,remote-pid = <2>;
+                       mboxes = <&apss_shared 8>;
+               };
+       };
+
+       cdsp_pas: remoteproc-cdsp {
+               compatible = "qcom,sdm845-cdsp-pas";
+
+               interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
+                                     <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
+                                     <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
+                                     <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
+                                     <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
+               interrupt-names = "wdog", "fatal", "ready",
+                                 "handover", "stop-ack";
+
+               clocks = <&rpmhcc RPMH_CXO_CLK>;
+               clock-names = "xo";
+
+               memory-region = <&cdsp_mem>;
+
+               qcom,smem-states = <&cdsp_smp2p_out 0>;
+               qcom,smem-state-names = "stop";
+
+               status = "disabled";
+
+               glink-edge {
+                       interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>;
+                       label = "turing";
+                       qcom,remote-pid = <5>;
+                       mboxes = <&apss_shared 4>;
+               };
+       };
+
        tcsr_mutex: hwlock {
                compatible = "qcom,tcsr-mutex";
                syscon = <&tcsr_mutex_regs 0 0x1000>;
@@ -1033,6 +1208,7 @@
                        phy-names = "ufsphy";
                        lanes-per-direction = <2>;
                        power-domains = <&gcc UFS_PHY_GDSC>;
+                       #reset-cells = <1>;
 
                        iommus = <&apps_smmu 0x100 0xf>;
 
@@ -1078,6 +1254,8 @@
                        clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>,
                                 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
 
+                       resets = <&ufs_mem_hc 0>;
+                       reset-names = "ufsphy";
                        status = "disabled";
 
                        ufs_mem_phy_lanes: lanes@1d87400 {
@@ -1853,8 +2031,9 @@
                                #clock-cells = <1>;
                                #phy-cells = <0>;
 
-                               clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>;
-                               clock-names = "iface";
+                               clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+                                        <&rpmhcc RPMH_CXO_CLK>;
+                               clock-names = "iface", "ref";
 
                                status = "disabled";
                        };
@@ -1919,8 +2098,9 @@
                                #clock-cells = <1>;
                                #phy-cells = <0>;
 
-                               clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>;
-                               clock-names = "iface";
+                               clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+                                        <&rpmhcc RPMH_CXO_CLK>;
+                               clock-names = "iface", "ref";
 
                                status = "disabled";
                        };
@@ -2098,43 +2278,43 @@
                                        compatible = "operating-points-v2";
 
                                        rpmhpd_opp_ret: opp1 {
-                                               opp-level = <16>;
+                                               opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
                                        };
 
                                        rpmhpd_opp_min_svs: opp2 {
-                                               opp-level = <48>;
+                                               opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
                                        };
 
                                        rpmhpd_opp_low_svs: opp3 {
-                                               opp-level = <64>;
+                                               opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
                                        };
 
                                        rpmhpd_opp_svs: opp4 {
-                                               opp-level = <128>;
+                                               opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
                                        };
 
                                        rpmhpd_opp_svs_l1: opp5 {
-                                               opp-level = <192>;
+                                               opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
                                        };
 
                                        rpmhpd_opp_nom: opp6 {
-                                               opp-level = <256>;
+                                               opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
                                        };
 
                                        rpmhpd_opp_nom_l1: opp7 {
-                                               opp-level = <320>;
+                                               opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
                                        };
 
                                        rpmhpd_opp_nom_l2: opp8 {
-                                               opp-level = <336>;
+                                               opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
                                        };
 
                                        rpmhpd_opp_turbo: opp9 {
-                                               opp-level = <384>;
+                                               opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
                                        };
 
                                        rpmhpd_opp_turbo_l1: opp10 {
-                                               opp-level = <416>;
+                                               opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
                                        };
                                };
                        };
@@ -2611,5 +2791,210 @@
                                };
                        };
                };
+
+               aoss0-thermal {
+                       polling-delay-passive = <250>;
+                       polling-delay = <1000>;
+
+                       thermal-sensors = <&tsens0 0>;
+
+                       trips {
+                               aoss0_alert0: trip-point@0 {
+                                       temperature = <90000>;
+                                       hysteresis = <2000>;
+                                       type = "hot";
+                               };
+                       };
+               };
+
+               cluster0-thermal {
+                       polling-delay-passive = <250>;
+                       polling-delay = <1000>;
+
+                       thermal-sensors = <&tsens0 5>;
+
+                       trips {
+                               cluster0_alert0: trip-point@0 {
+                                       temperature = <90000>;
+                                       hysteresis = <2000>;
+                                       type = "hot";
+                               };
+                               cluster0_crit: cluster0_crit {
+                                       temperature = <110000>;
+                                       hysteresis = <2000>;
+                                       type = "critical";
+                               };
+                       };
+               };
+
+               cluster1-thermal {
+                       polling-delay-passive = <250>;
+                       polling-delay = <1000>;
+
+                       thermal-sensors = <&tsens0 6>;
+
+                       trips {
+                               cluster1_alert0: trip-point@0 {
+                                       temperature = <90000>;
+                                       hysteresis = <2000>;
+                                       type = "hot";
+                               };
+                               cluster1_crit: cluster1_crit {
+                                       temperature = <110000>;
+                                       hysteresis = <2000>;
+                                       type = "critical";
+                               };
+                       };
+               };
+
+               gpu-thermal-top {
+                       polling-delay-passive = <250>;
+                       polling-delay = <1000>;
+
+                       thermal-sensors = <&tsens0 11>;
+
+                       trips {
+                               gpu1_alert0: trip-point@0 {
+                                       temperature = <90000>;
+                                       hysteresis = <2000>;
+                                       type = "hot";
+                               };
+                       };
+               };
+
+               gpu-thermal-bottom {
+                       polling-delay-passive = <250>;
+                       polling-delay = <1000>;
+
+                       thermal-sensors = <&tsens0 12>;
+
+                       trips {
+                               gpu2_alert0: trip-point@0 {
+                                       temperature = <90000>;
+                                       hysteresis = <2000>;
+                                       type = "hot";
+                               };
+                       };
+               };
+
+               aoss1-thermal {
+                       polling-delay-passive = <250>;
+                       polling-delay = <1000>;
+
+                       thermal-sensors = <&tsens1 0>;
+
+                       trips {
+                               aoss1_alert0: trip-point@0 {
+                                       temperature = <90000>;
+                                       hysteresis = <2000>;
+                                       type = "hot";
+                               };
+                       };
+               };
+
+               q6-modem-thermal {
+                       polling-delay-passive = <250>;
+                       polling-delay = <1000>;
+
+                       thermal-sensors = <&tsens1 1>;
+
+                       trips {
+                               q6_modem_alert0: trip-point@0 {
+                                       temperature = <90000>;
+                                       hysteresis = <2000>;
+                                       type = "hot";
+                               };
+                       };
+               };
+
+               mem-thermal {
+                       polling-delay-passive = <250>;
+                       polling-delay = <1000>;
+
+                       thermal-sensors = <&tsens1 2>;
+
+                       trips {
+                               mem_alert0: trip-point@0 {
+                                       temperature = <90000>;
+                                       hysteresis = <2000>;
+                                       type = "hot";
+                               };
+                       };
+               };
+
+               wlan-thermal {
+                       polling-delay-passive = <250>;
+                       polling-delay = <1000>;
+
+                       thermal-sensors = <&tsens1 3>;
+
+                       trips {
+                               wlan_alert0: trip-point@0 {
+                                       temperature = <90000>;
+                                       hysteresis = <2000>;
+                                       type = "hot";
+                               };
+                       };
+               };
+
+               q6-hvx-thermal {
+                       polling-delay-passive = <250>;
+                       polling-delay = <1000>;
+
+                       thermal-sensors = <&tsens1 4>;
+
+                       trips {
+                               q6_hvx_alert0: trip-point@0 {
+                                       temperature = <90000>;
+                                       hysteresis = <2000>;
+                                       type = "hot";
+                               };
+                       };
+               };
+
+               camera-thermal {
+                       polling-delay-passive = <250>;
+                       polling-delay = <1000>;
+
+                       thermal-sensors = <&tsens1 5>;
+
+                       trips {
+                               camera_alert0: trip-point@0 {
+                                       temperature = <90000>;
+                                       hysteresis = <2000>;
+                                       type = "hot";
+                               };
+                       };
+               };
+
+               video-thermal {
+                       polling-delay-passive = <250>;
+                       polling-delay = <1000>;
+
+                       thermal-sensors = <&tsens1 6>;
+
+                       trips {
+                               video_alert0: trip-point@0 {
+                                       temperature = <90000>;
+                                       hysteresis = <2000>;
+                                       type = "hot";
+                               };
+                       };
+               };
+
+               modem-thermal {
+                       polling-delay-passive = <250>;
+                       polling-delay = <1000>;
+
+                       thermal-sensors = <&tsens1 7>;
+
+                       trips {
+                               modem_alert0: trip-point@0 {
+                                       temperature = <90000>;
+                                       hysteresis = <2000>;
+                                       type = "hot";
+                               };
+                       };
+               };
        };
 };

diff --git a/arch/arm64/boot/dts/renesas/cat875.dtsi b/arch/arm64/boot/dts/renesas/cat875.dtsi
index 14db667..aaefc3a 100644 (file)
--- a/arch/arm64/boot/dts/renesas/cat875.dtsi
+++ b/arch/arm64/boot/dts/renesas/cat875.dtsi
@@ -30,6 +30,18 @@
        };
 };
 
+&can0 {
+       pinctrl-0 = <&can0_pins>;
+       pinctrl-names = "default";
+       status = "okay";
+};
+
+&can1 {
+       pinctrl-0 = <&can1_pins>;
+       pinctrl-names = "default";
+       status = "okay";
+};
+
 &pciec0 {
        status = "okay";
 };
@@ -41,4 +53,14 @@
                        function = "avb";
                };
        };
+
+       can0_pins: can0 {
+               groups = "can0_data";
+               function = "can0";
+       };
+
+       can1_pins: can1 {
+               groups = "can1_data";
+               function = "can1";
+       };
 };

diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
index ef3cff2..de282c4 100644 (file)
--- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
@@ -879,8 +879,10 @@
                                     "renesas,rcar-gen3-can";
                        reg = <0 0xe6c30000 0 0x1000>;
                        interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
-                       clocks = <&cpg CPG_MOD 916>, <&can_clk>;
-                       clock-names = "clkp1", "can_clk";
+                       clocks = <&cpg CPG_MOD 916>,
+                                <&cpg CPG_CORE R8A774A1_CLK_CANFD>,
+                                <&can_clk>;
+                       clock-names = "clkp1", "clkp2", "can_clk";
                        power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
                        resets = <&cpg 916>;
                        status = "disabled";
@@ -891,8 +893,10 @@
                                     "renesas,rcar-gen3-can";
                        reg = <0 0xe6c38000 0 0x1000>;
                        interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
-                       clocks = <&cpg CPG_MOD 915>, <&can_clk>;
-                       clock-names = "clkp1", "can_clk";
+                       clocks = <&cpg CPG_MOD 915>,
+                                <&cpg CPG_CORE R8A774A1_CLK_CANFD>,
+                                <&can_clk>;
+                       clock-names = "clkp1", "clkp2", "can_clk";
                        power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
                        resets = <&cpg 915>;
                        status = "disabled";

diff --git a/arch/arm64/boot/dts/renesas/r8a774c0-cat874.dts b/arch/arm64/boot/dts/renesas/r8a774c0-cat874.dts
index 96ee0d2..013a48c 100644 (file)
--- a/arch/arm64/boot/dts/renesas/r8a774c0-cat874.dts
+++ b/arch/arm64/boot/dts/renesas/r8a774c0-cat874.dts
@@ -22,6 +22,30 @@
                stdout-path = "serial0:115200n8";
        };
 
+       leds {
+               compatible = "gpio-leds";
+
+               led0 {
+                       gpios = <&gpio5 19 GPIO_ACTIVE_HIGH>;
+                       label = "LED0";
+               };
+
+               led1 {
+                       gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>;
+                       label = "LED1";
+               };
+
+               led2 {
+                       gpios = <&gpio4 10 GPIO_ACTIVE_HIGH>;
+                       label = "LED2";
+               };
+
+               led3 {
+                       gpios = <&gpio6 4 GPIO_ACTIVE_HIGH>;
+                       label = "LED3";
+               };
+       };
+
        memory@48000000 {
                device_type = "memory";
                /* first 128MB is reserved for secure area. */
@@ -52,10 +76,33 @@
        };
 };
 
+&ehci0 {
+       dr_mode = "host";
+       status = "okay";
+};
+
 &extal_clk {
        clock-frequency = <48000000>;
 };
 
+&i2c1 {
+       pinctrl-0 = <&i2c1_pins>;
+       pinctrl-names = "default";
+
+       status = "okay";
+       clock-frequency = <400000>;
+
+       rtc@32 {
+               compatible = "epson,rx8571";
+               reg = <0x32>;
+       };
+};
+
+&ohci0 {
+       dr_mode = "host";
+       status = "okay";
+};
+
 &pcie_bus_clk {
        clock-frequency = <100000000>;
 };
@@ -66,6 +113,11 @@
 };
 
 &pfc {
+       i2c1_pins: i2c1 {
+               groups = "i2c1_b";
+               function = "i2c1";
+       };
+
        scif2_pins: scif2 {
                groups = "scif2_data_a";
                function = "scif2";
@@ -84,6 +136,11 @@
        };
 };
 
+&rwdt {
+       timeout-sec = <60>;
+       status = "okay";
+};
+
 &scif2 {
        pinctrl-0 = <&scif2_pins>;
        pinctrl-names = "default";
@@ -104,3 +161,8 @@
        sd-uhs-sdr104;
        status = "okay";
 };
+
+&usb2_phy0 {
+       renesas,no-otg-pins;
+       status = "okay";
+};

diff --git a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
index 1ea684a..3f86db1 100644 (file)
--- a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
@@ -76,7 +76,7 @@
                        power-domains = <&sysc R8A774C0_PD_CA53_CPU0>;
                        next-level-cache = <&L2_CA53>;
                        enable-method = "psci";
-                       clocks =<&cpg CPG_CORE R8A774C0_CLK_Z2>;
+                       clocks = <&cpg CPG_CORE R8A774C0_CLK_Z2>;
                        operating-points-v2 = <&cluster1_opp>;
                };
 
@@ -87,7 +87,7 @@
                        power-domains = <&sysc R8A774C0_PD_CA53_CPU1>;
                        next-level-cache = <&L2_CA53>;
                        enable-method = "psci";
-                       clocks =<&cpg CPG_CORE R8A774C0_CLK_Z2>;
+                       clocks = <&cpg CPG_CORE R8A774C0_CLK_Z2>;
                        operating-points-v2 = <&cluster1_opp>;
                };
 
@@ -969,8 +969,10 @@
                                     "renesas,rcar-gen3-can";
                        reg = <0 0xe6c30000 0 0x1000>;
                        interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
-                       clocks = <&cpg CPG_MOD 916>, <&can_clk>;
-                       clock-names = "clkp1", "can_clk";
+                       clocks = <&cpg CPG_MOD 916>,
+                                <&cpg CPG_CORE R8A774C0_CLK_CANFD>,
+                                <&can_clk>;
+                       clock-names = "clkp1", "clkp2", "can_clk";
                        power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
                        resets = <&cpg 916>;
                        status = "disabled";
@@ -981,13 +983,40 @@
                                     "renesas,rcar-gen3-can";
                        reg = <0 0xe6c38000 0 0x1000>;
                        interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
-                       clocks = <&cpg CPG_MOD 915>, <&can_clk>;
-                       clock-names = "clkp1", "can_clk";
+                       clocks = <&cpg CPG_MOD 915>,
+                                <&cpg CPG_CORE R8A774C0_CLK_CANFD>,
+                                <&can_clk>;
+                       clock-names = "clkp1", "clkp2", "can_clk";
                        power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
                        resets = <&cpg 915>;
                        status = "disabled";
                };
 
+               canfd: can@e66c0000 {
+                       compatible = "renesas,r8a774c0-canfd",
+                                    "renesas,rcar-gen3-canfd";
+                       reg = <0 0xe66c0000 0 0x8000>;
+                       interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 914>,
+                                <&cpg CPG_CORE R8A774C0_CLK_CANFD>,
+                                <&can_clk>;
+                       clock-names = "fck", "canfd", "can_clk";
+                       assigned-clocks = <&cpg CPG_CORE R8A774C0_CLK_CANFD>;
+                       assigned-clock-rates = <40000000>;
+                       power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
+                       resets = <&cpg 914>;
+                       status = "disabled";
+
+                       channel0 {
+                               status = "disabled";
+                       };
+
+                       channel1 {
+                               status = "disabled";
+                       };
+               };
+
                pwm0: pwm@e6e30000 {
                        compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar";
                        reg = <0 0xe6e30000 0 0x8>;
@@ -1740,8 +1769,7 @@
                };
 
                csi40: csi2@feaa0000 {
-                       compatible = "renesas,r8a774c0-csi2",
-                                    "renesas,rcar-gen3-csi2";
+                       compatible = "renesas,r8a774c0-csi2";
                        reg = <0 0xfeaa0000 0 0x10000>;
                        interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
                        clocks = <&cpg CPG_MOD 716>;

diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
index abeac30..097538c 100644 (file)
--- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
@@ -462,6 +462,76 @@
                        reg = <0 0xe6060000 0 0x50c>;
                };
 
+               cmt0: timer@e60f0000 {
+                       compatible = "renesas,r8a7795-cmt0",
+                                    "renesas,rcar-gen3-cmt0";
+                       reg = <0 0xe60f0000 0 0x1004>;
+                       interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 303>;
+                       clock-names = "fck";
+                       power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+                       resets = <&cpg 303>;
+                       status = "disabled";
+               };
+
+               cmt1: timer@e6130000 {
+                       compatible = "renesas,r8a7795-cmt1",
+                                    "renesas,rcar-gen3-cmt1";
+                       reg = <0 0xe6130000 0 0x1004>;
+                       interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 302>;
+                       clock-names = "fck";
+                       power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+                       resets = <&cpg 302>;
+                       status = "disabled";
+               };
+
+               cmt2: timer@e6140000 {
+                       compatible = "renesas,r8a7795-cmt1",
+                                    "renesas,rcar-gen3-cmt1";
+                       reg = <0 0xe6140000 0 0x1004>;
+                       interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 301>;
+                       clock-names = "fck";
+                       power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+                       resets = <&cpg 301>;
+                       status = "disabled";
+               };
+
+               cmt3: timer@e6148000 {
+                       compatible = "renesas,r8a7795-cmt1",
+                                    "renesas,rcar-gen3-cmt1";
+                       reg = <0 0xe6148000 0 0x1004>;
+                       interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 300>;
+                       clock-names = "fck";
+                       power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+                       resets = <&cpg 300>;
+                       status = "disabled";
+               };
+
                cpg: clock-controller@e6150000 {
                        compatible = "renesas,r8a7795-cpg-mssr";
                        reg = <0 0xe6150000 0 0x1000>;
@@ -1836,7 +1906,7 @@
                                <0 0xec5a0000 0 0x100>,  /* ADG */
                                <0 0xec540000 0 0x1000>, /* SSIU */
                                <0 0xec541000 0 0x280>,  /* SSI */
-                               <0 0xec740000 0 0x200>;  /* Audio DMAC peri peri*/
+                               <0 0xec760000 0 0x200>;  /* Audio DMAC peri peri*/
                        reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
 
                        clocks = <&cpg CPG_MOD 1005>,

diff --git a/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts b/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts
index b4f9567..2aefa53 100644 (file)
--- a/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts
+++ b/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts
@@ -68,6 +68,7 @@
        ports {
                /* rsnd_port0 is on salvator-common */
                rsnd_port1: port@1 {
+                       reg = <1>;
                        rsnd_endpoint1: endpoint {
                                remote-endpoint = <&dw_hdmi0_snd_in>;
 

diff --git a/arch/arm64/boot/dts/renesas/r8a7796-salvator-xs.dts b/arch/arm64/boot/dts/renesas/r8a7796-salvator-xs.dts
index 31f1205..d58ede1 100644 (file)
--- a/arch/arm64/boot/dts/renesas/r8a7796-salvator-xs.dts
+++ b/arch/arm64/boot/dts/renesas/r8a7796-salvator-xs.dts
@@ -68,6 +68,7 @@
        ports {
                /* rsnd_port0 is on salvator-common */
                rsnd_port1: port@1 {
+                       reg = <1>;
                        rsnd_endpoint1: endpoint {
                                remote-endpoint = <&dw_hdmi0_snd_in>;
 

diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
index cdf7848..d5e2f4a 100644 (file)
--- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
@@ -1775,7 +1775,7 @@
                                <0 0xec5a0000 0 0x100>,  /* ADG */
                                <0 0xec540000 0 0x1000>, /* SSIU */
                                <0 0xec541000 0 0x280>,  /* SSI */
-                               <0 0xec740000 0 0x200>;  /* Audio DMAC peri peri*/
+                               <0 0xec760000 0 0x200>;  /* Audio DMAC peri peri*/
                        reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
 
                        clocks = <&cpg CPG_MOD 1005>,
@@ -2162,17 +2162,6 @@
                                        dma-names = "rx", "tx";
                                };
                        };
-
-                       ports {
-                               #address-cells = <1>;
-                               #size-cells = <0>;
-                               port@0 {
-                                       reg = <0>;
-                               };
-                               port@1 {
-                                       reg = <1>;
-                               };
-                       };
                };
 
                audma0: dma-controller@ec700000 {

diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
index 9763d10..2554b17 100644 (file)
--- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
@@ -317,6 +317,76 @@
                        reg = <0 0xe6060000 0 0x50c>;
                };
 
+               cmt0: timer@e60f0000 {
+                       compatible = "renesas,r8a77965-cmt0",
+                                    "renesas,rcar-gen3-cmt0";
+                       reg = <0 0xe60f0000 0 0x1004>;
+                       interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 303>;
+                       clock-names = "fck";
+                       power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
+                       resets = <&cpg 303>;
+                       status = "disabled";
+               };
+
+               cmt1: timer@e6130000 {
+                       compatible = "renesas,r8a77965-cmt1",
+                                    "renesas,rcar-gen3-cmt1";
+                       reg = <0 0xe6130000 0 0x1004>;
+                       interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 302>;
+                       clock-names = "fck";
+                       power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
+                       resets = <&cpg 302>;
+                       status = "disabled";
+               };
+
+               cmt2: timer@e6140000 {
+                       compatible = "renesas,r8a77965-cmt1",
+                                    "renesas,rcar-gen3-cmt1";
+                       reg = <0 0xe6140000 0 0x1004>;
+                       interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 301>;
+                       clock-names = "fck";
+                       power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
+                       resets = <&cpg 301>;
+                       status = "disabled";
+               };
+
+               cmt3: timer@e6148000 {
+                       compatible = "renesas,r8a77965-cmt1",
+                                    "renesas,rcar-gen3-cmt1";
+                       reg = <0 0xe6148000 0 0x1004>;
+                       interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 300>;
+                       clock-names = "fck";
+                       power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
+                       resets = <&cpg 300>;
+                       status = "disabled";
+               };
+
                cpg: clock-controller@e6150000 {
                        compatible = "renesas,r8a77965-cpg-mssr";
                        reg = <0 0xe6150000 0 0x1000>;
@@ -1461,7 +1531,7 @@
                                <0 0xec5a0000 0 0x100>,  /* ADG */
                                <0 0xec540000 0 0x1000>, /* SSIU */
                                <0 0xec541000 0 0x280>,  /* SSI */
-                               <0 0xec740000 0 0x200>;  /* Audio DMAC peri peri*/
+                               <0 0xec760000 0 0x200>;  /* Audio DMAC peri peri*/
                        reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
 
                        clocks = <&cpg CPG_MOD 1005>,
@@ -1585,56 +1655,267 @@
                                };
                        };
 
+                       rcar_sound,ssiu {
+                               ssiu00: ssiu-0 {
+                                       dmas = <&audma0 0x15>, <&audma1 0x16>;
+                                       dma-names = "rx", "tx";
+                               };
+                               ssiu01: ssiu-1 {
+                                       dmas = <&audma0 0x35>, <&audma1 0x36>;
+                                       dma-names = "rx", "tx";
+                               };
+                               ssiu02: ssiu-2 {
+                                       dmas = <&audma0 0x37>, <&audma1 0x38>;
+                                       dma-names = "rx", "tx";
+                               };
+                               ssiu03: ssiu-3 {
+                                       dmas = <&audma0 0x47>, <&audma1 0x48>;
+                                       dma-names = "rx", "tx";
+                               };
+                               ssiu04: ssiu-4 {
+                                       dmas = <&audma0 0x3F>, <&audma1 0x40>;
+                                       dma-names = "rx", "tx";
+                               };
+                               ssiu05: ssiu-5 {
+                                       dmas = <&audma0 0x43>, <&audma1 0x44>;
+                                       dma-names = "rx", "tx";
+                               };
+                               ssiu06: ssiu-6 {
+                                       dmas = <&audma0 0x4F>, <&audma1 0x50>;
+                                       dma-names = "rx", "tx";
+                               };
+                               ssiu07: ssiu-7 {
+                                       dmas = <&audma0 0x53>, <&audma1 0x54>;
+                                       dma-names = "rx", "tx";
+                               };
+                               ssiu10: ssiu-8 {
+                                       dmas = <&audma0 0x49>, <&audma1 0x4a>;
+                                       dma-names = "rx", "tx";
+                               };
+                               ssiu11: ssiu-9 {
+                                       dmas = <&audma0 0x4B>, <&audma1 0x4C>;
+                                       dma-names = "rx", "tx";
+                               };
+                               ssiu12: ssiu-10 {
+                                       dmas = <&audma0 0x57>, <&audma1 0x58>;
+                                       dma-names = "rx", "tx";
+                               };
+                               ssiu13: ssiu-11 {
+                                       dmas = <&audma0 0x59>, <&audma1 0x5A>;
+                                       dma-names = "rx", "tx";
+                               };
+                               ssiu14: ssiu-12 {
+                                       dmas = <&audma0 0x5F>, <&audma1 0x60>;
+                                       dma-names = "rx", "tx";
+                               };
+                               ssiu15: ssiu-13 {
+                                       dmas = <&audma0 0xC3>, <&audma1 0xC4>;
+                                       dma-names = "rx", "tx";
+                               };
+                               ssiu16: ssiu-14 {
+                                       dmas = <&audma0 0xC7>, <&audma1 0xC8>;
+                                       dma-names = "rx", "tx";
+                               };
+                               ssiu17: ssiu-15 {
+                                       dmas = <&audma0 0xCB>, <&audma1 0xCC>;
+                                       dma-names = "rx", "tx";
+                               };
+                               ssiu20: ssiu-16 {
+                                       dmas = <&audma0 0x63>, <&audma1 0x64>;
+                                       dma-names = "rx", "tx";
+                               };
+                               ssiu21: ssiu-17 {
+                                       dmas = <&audma0 0x67>, <&audma1 0x68>;
+                                       dma-names = "rx", "tx";
+                               };
+                               ssiu22: ssiu-18 {
+                                       dmas = <&audma0 0x6B>, <&audma1 0x6C>;
+                                       dma-names = "rx", "tx";
+                               };
+                               ssiu23: ssiu-19 {
+                                       dmas = <&audma0 0x6D>, <&audma1 0x6E>;
+                                       dma-names = "rx", "tx";
+                               };
+                               ssiu24: ssiu-20 {
+                                       dmas = <&audma0 0xCF>, <&audma1 0xCE>;
+                                       dma-names = "rx", "tx";
+                               };
+                               ssiu25: ssiu-21 {
+                                       dmas = <&audma0 0xEB>, <&audma1 0xEC>;
+                                       dma-names = "rx", "tx";
+                               };
+                               ssiu26: ssiu-22 {
+                                       dmas = <&audma0 0xED>, <&audma1 0xEE>;
+                                       dma-names = "rx", "tx";
+                               };
+                               ssiu27: ssiu-23 {
+                                       dmas = <&audma0 0xEF>, <&audma1 0xF0>;
+                                       dma-names = "rx", "tx";
+                               };
+                               ssiu30: ssiu-24 {
+                                       dmas = <&audma0 0x6f>, <&audma1 0x70>;
+                                       dma-names = "rx", "tx";
+                               };
+                               ssiu31: ssiu-25 {
+                                       dmas = <&audma0 0x21>, <&audma1 0x22>;
+                                       dma-names = "rx", "tx";
+                               };
+                               ssiu32: ssiu-26 {
+                                       dmas = <&audma0 0x23>, <&audma1 0x24>;
+                                       dma-names = "rx", "tx";
+                               };
+                               ssiu33: ssiu-27 {
+                                       dmas = <&audma0 0x25>, <&audma1 0x26>;
+                                       dma-names = "rx", "tx";
+                               };
+                               ssiu34: ssiu-28 {
+                                       dmas = <&audma0 0x27>, <&audma1 0x28>;
+                                       dma-names = "rx", "tx";
+                               };
+                               ssiu35: ssiu-29 {
+                                       dmas = <&audma0 0x29>, <&audma1 0x2A>;
+                                       dma-names = "rx", "tx";
+                               };
+                               ssiu36: ssiu-30 {
+                                       dmas = <&audma0 0x2B>, <&audma1 0x2C>;
+                                       dma-names = "rx", "tx";
+                               };
+                               ssiu37: ssiu-31 {
+                                       dmas = <&audma0 0x2D>, <&audma1 0x2E>;
+                                       dma-names = "rx", "tx";
+                               };
+                               ssiu40: ssiu-32 {
+                                       dmas =  <&audma0 0x71>, <&audma1 0x72>;
+                                       dma-names = "rx", "tx";
+                               };
+                               ssiu41: ssiu-33 {
+                                       dmas = <&audma0 0x17>, <&audma1 0x18>;
+                                       dma-names = "rx", "tx";
+                               };
+                               ssiu42: ssiu-34 {
+                                       dmas = <&audma0 0x19>, <&audma1 0x1A>;
+                                       dma-names = "rx", "tx";
+                               };
+                               ssiu43: ssiu-35 {
+                                       dmas = <&audma0 0x1B>, <&audma1 0x1C>;
+                                       dma-names = "rx", "tx";
+                               };
+                               ssiu44: ssiu-36 {
+                                       dmas = <&audma0 0x1D>, <&audma1 0x1E>;
+                                       dma-names = "rx", "tx";
+                               };
+                               ssiu45: ssiu-37 {
+                                       dmas = <&audma0 0x1F>, <&audma1 0x20>;
+                                       dma-names = "rx", "tx";
+                               };
+                               ssiu46: ssiu-38 {
+                                       dmas = <&audma0 0x31>, <&audma1 0x32>;
+                                       dma-names = "rx", "tx";
+                               };
+                               ssiu47: ssiu-39 {
+                                       dmas = <&audma0 0x33>, <&audma1 0x34>;
+                                       dma-names = "rx", "tx";
+                               };
+                               ssiu50: ssiu-40 {
+                                       dmas = <&audma0 0x73>, <&audma1 0x74>;
+                                       dma-names = "rx", "tx";
+                               };
+                               ssiu60: ssiu-41 {
+                                       dmas = <&audma0 0x75>, <&audma1 0x76>;
+                                       dma-names = "rx", "tx";
+                               };
+                               ssiu70: ssiu-42 {
+                                       dmas = <&audma0 0x79>, <&audma1 0x7a>;
+                                       dma-names = "rx", "tx";
+                               };
+                               ssiu80: ssiu-43 {
+                                       dmas = <&audma0 0x7b>, <&audma1 0x7c>;
+                                       dma-names = "rx", "tx";
+                               };
+                               ssiu90: ssiu-44 {
+                                       dmas = <&audma0 0x7d>, <&audma1 0x7e>;
+                                       dma-names = "rx", "tx";
+                               };
+                               ssiu91: ssiu-45 {
+                                       dmas = <&audma0 0x7F>, <&audma1 0x80>;
+                                       dma-names = "rx", "tx";
+                               };
+                               ssiu92: ssiu-46 {
+                                       dmas = <&audma0 0x81>, <&audma1 0x82>;
+                                       dma-names = "rx", "tx";
+                               };
+                               ssiu93: ssiu-47 {
+                                       dmas = <&audma0 0x83>, <&audma1 0x84>;
+                                       dma-names = "rx", "tx";
+                               };
+                               ssiu94: ssiu-48 {
+                                       dmas = <&audma0 0xA3>, <&audma1 0xA4>;
+                                       dma-names = "rx", "tx";
+                               };
+                               ssiu95: ssiu-49 {
+                                       dmas = <&audma0 0xA5>, <&audma1 0xA6>;
+                                       dma-names = "rx", "tx";
+                               };
+                               ssiu96: ssiu-50 {
+                                       dmas = <&audma0 0xA7>, <&audma1 0xA8>;
+                                       dma-names = "rx", "tx";
+                               };
+                               ssiu97: ssiu-51 {
+                                       dmas = <&audma0 0xA9>, <&audma1 0xAA>;
+                                       dma-names = "rx", "tx";
+                               };
+                       };
+
                        rcar_sound,ssi {
                                ssi0: ssi-0 {
                                        interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
-                                       dmas = <&audma0 0x01>, <&audma1 0x02>, <&audma0 0x15>, <&audma1 0x16>;
-                                       dma-names = "rx", "tx", "rxu", "txu";
+                                       dmas = <&audma0 0x01>, <&audma1 0x02>;
+                                       dma-names = "rx", "tx";
                                };
                                ssi1: ssi-1 {
                                        interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
-                                       dmas = <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>;
-                                       dma-names = "rx", "tx", "rxu", "txu";
+                                       dmas = <&audma0 0x03>, <&audma1 0x04>;
+                                       dma-names = "rx", "tx";
                                };
                                ssi2: ssi-2 {
                                        interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
-                                       dmas = <&audma0 0x05>, <&audma1 0x06>, <&audma0 0x63>, <&audma1 0x64>;
-                                       dma-names = "rx", "tx", "rxu", "txu";
+                                       dmas = <&audma0 0x05>, <&audma1 0x06>;
+                                       dma-names = "rx", "tx";
                                };
                                ssi3: ssi-3 {
                                        interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
-                                       dmas = <&audma0 0x07>, <&audma1 0x08>, <&audma0 0x6f>, <&audma1 0x70>;
-                                       dma-names = "rx", "tx", "rxu", "txu";
+                                       dmas = <&audma0 0x07>, <&audma1 0x08>;
+                                       dma-names = "rx", "tx";
                                };
                                ssi4: ssi-4 {
                                        interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
-                                       dmas = <&audma0 0x09>, <&audma1 0x0a>, <&audma0 0x71>, <&audma1 0x72>;
-                                       dma-names = "rx", "tx", "rxu", "txu";
+                                       dmas = <&audma0 0x09>, <&audma1 0x0a>;
+                                       dma-names = "rx", "tx";
                                };
                                ssi5: ssi-5 {
                                        interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
-                                       dmas = <&audma0 0x0b>, <&audma1 0x0c>, <&audma0 0x73>, <&audma1 0x74>;
-                                       dma-names = "rx", "tx", "rxu", "txu";
+                                       dmas = <&audma0 0x0b>, <&audma1 0x0c>;
+                                       dma-names = "rx", "tx";
                                };
                                ssi6: ssi-6 {
                                        interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
-                                       dmas = <&audma0 0x0d>, <&audma1 0x0e>, <&audma0 0x75>, <&audma1 0x76>;
-                                       dma-names = "rx", "tx", "rxu", "txu";
+                                       dmas = <&audma0 0x0d>, <&audma1 0x0e>;
+                                       dma-names = "rx", "tx";
                                };
                                ssi7: ssi-7 {
                                        interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
-                                       dmas = <&audma0 0x0f>, <&audma1 0x10>, <&audma0 0x79>, <&audma1 0x7a>;
-                                       dma-names = "rx", "tx", "rxu", "txu";
+                                       dmas = <&audma0 0x0f>, <&audma1 0x10>;
+                                       dma-names = "rx", "tx";
                                };
                                ssi8: ssi-8 {
                                        interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
-                                       dmas = <&audma0 0x11>, <&audma1 0x12>, <&audma0 0x7b>, <&audma1 0x7c>;
-                                       dma-names = "rx", "tx", "rxu", "txu";
+                                       dmas = <&audma0 0x11>, <&audma1 0x12>;
+                                       dma-names = "rx", "tx";
                                };
                                ssi9: ssi-9 {
                                        interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
-                                       dmas = <&audma0 0x13>, <&audma1 0x14>, <&audma0 0x7d>, <&audma1 0x7e>;
-                                       dma-names = "rx", "tx", "rxu", "txu";
+                                       dmas = <&audma0 0x13>, <&audma1 0x14>;
+                                       dma-names = "rx", "tx";
                                };
                        };
                };
@@ -2166,7 +2447,6 @@
                du: display@feb00000 {
                        compatible = "renesas,du-r8a77965";
                        reg = <0 0xfeb00000 0 0x80000>;
-                       reg-names = "du";
                        interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
                                     <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
                                     <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>;

diff --git a/arch/arm64/boot/dts/renesas/r8a77980.dtsi b/arch/arm64/boot/dts/renesas/r8a77980.dtsi
index 4081622..a901a34 100644 (file)
--- a/arch/arm64/boot/dts/renesas/r8a77980.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77980.dtsi
@@ -865,6 +865,7 @@
                        clocks = <&cpg CPG_MOD 811>;
                        power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
                        resets = <&cpg 811>;
+                       renesas,id = <0>;
                        status = "disabled";
 
                        ports {
@@ -892,6 +893,7 @@
                        clocks = <&cpg CPG_MOD 810>;
                        power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
                        status = "disabled";
+                       renesas,id = <1>;
                        resets = <&cpg 810>;
 
                        ports {
@@ -919,6 +921,7 @@
                        clocks = <&cpg CPG_MOD 809>;
                        power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
                        resets = <&cpg 809>;
+                       renesas,id = <2>;
                        status = "disabled";
 
                        ports {
@@ -946,6 +949,7 @@
                        clocks = <&cpg CPG_MOD 808>;
                        power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
                        resets = <&cpg 808>;
+                       renesas,id = <3>;
                        status = "disabled";
 
                        ports {
@@ -973,6 +977,7 @@
                        clocks = <&cpg CPG_MOD 807>;
                        power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
                        resets = <&cpg 807>;
+                       renesas,id = <4>;
                        status = "disabled";
 
                        ports {
@@ -1000,6 +1005,7 @@
                        clocks = <&cpg CPG_MOD 806>;
                        power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
                        resets = <&cpg 806>;
+                       renesas,id = <5>;
                        status = "disabled";
 
                        ports {
@@ -1027,6 +1033,7 @@
                        clocks = <&cpg CPG_MOD 805>;
                        power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
                        resets = <&cpg 805>;
+                       renesas,id = <6>;
                        status = "disabled";
 
                        ports {
@@ -1054,6 +1061,7 @@
                        clocks = <&cpg CPG_MOD 804>;
                        power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
                        resets = <&cpg 804>;
+                       renesas,id = <7>;
                        status = "disabled";
 
                        ports {
@@ -1081,6 +1089,7 @@
                        clocks = <&cpg CPG_MOD 628>;
                        power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
                        resets = <&cpg 628>;
+                       renesas,id = <8>;
                        status = "disabled";
                };
 
@@ -1091,6 +1100,7 @@
                        clocks = <&cpg CPG_MOD 627>;
                        power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
                        resets = <&cpg 627>;
+                       renesas,id = <9>;
                        status = "disabled";
                };
 
@@ -1101,6 +1111,7 @@
                        clocks = <&cpg CPG_MOD 625>;
                        power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
                        resets = <&cpg 625>;
+                       renesas,id = <10>;
                        status = "disabled";
                };
 
@@ -1111,6 +1122,7 @@
                        clocks = <&cpg CPG_MOD 618>;
                        power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
                        resets = <&cpg 618>;
+                       renesas,id = <11>;
                        status = "disabled";
                };
 
@@ -1121,6 +1133,7 @@
                        clocks = <&cpg CPG_MOD 612>;
                        power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
                        resets = <&cpg 612>;
+                       renesas,id = <12>;
                        status = "disabled";
                };
 
@@ -1131,6 +1144,7 @@
                        clocks = <&cpg CPG_MOD 608>;
                        power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
                        resets = <&cpg 608>;
+                       renesas,id = <13>;
                        status = "disabled";
                };
 
@@ -1141,6 +1155,7 @@
                        clocks = <&cpg CPG_MOD 605>;
                        power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
                        resets = <&cpg 605>;
+                       renesas,id = <14>;
                        status = "disabled";
                };
 
@@ -1151,6 +1166,7 @@
                        clocks = <&cpg CPG_MOD 604>;
                        power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
                        resets = <&cpg 604>;
+                       renesas,id = <15>;
                        status = "disabled";
                };
 

diff --git a/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts b/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts
index 144c082..c727725 100644 (file)
--- a/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts
+++ b/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts
@@ -1,4 +1,4 @@
-/* SPDX-License-Identifier: GPL-2.0 */
+// SPDX-License-Identifier: GPL-2.0
 /*
  * Device Tree Source for the ebisu board
  *
@@ -19,7 +19,7 @@
        };
 
        chosen {
-               bootargs = "ignore_loglevel";
+               bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
                stdout-path = "serial0:115200n8";
        };
 
@@ -337,6 +337,15 @@
 &i2c0 {
        status = "okay";
 
+       io_expander: gpio@20 {
+               compatible = "onnn,pca9654";
+               reg = <0x20>;
+               gpio-controller;
+               #gpio-cells = <2>;
+               interrupt-parent = <&gpio2>;
+               interrupts = <22 IRQ_TYPE_LEVEL_LOW>;
+       };
+
        hdmi-encoder@39 {
                compatible = "adi,adv7511w";
                reg = <0x39>;
@@ -398,7 +407,7 @@
                };
 
                port@a {
-                       reg = <0xa>;
+                       reg = <10>;
 
                        adv7482_txa: endpoint {
                                clock-lanes = <0>;
@@ -440,6 +449,28 @@
        };
 };
 
+&i2c_dvfs {
+       status = "okay";
+
+       clock-frequency = <400000>;
+
+       pmic: pmic@30 {
+               pinctrl-0 = <&irq0_pins>;
+               pinctrl-names = "default";
+
+               compatible = "rohm,bd9571mwv";
+               reg = <0x30>;
+               interrupt-parent = <&intc_ex>;
+               interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+               interrupt-controller;
+               #interrupt-cells = <2>;
+               gpio-controller;
+               #gpio-cells = <2>;
+               rohm,ddr-backup-power = <0x1>;
+               rohm,rstbmode-level;
+       };
+};
+
 &lvds0 {
        status = "okay";
 
@@ -458,6 +489,13 @@
 };
 
 &lvds1 {
+       /*
+        * Even though the LVDS1 output is not connected, the encoder must be
+        * enabled to supply a pixel clock to the DU for the DPAD output when
+        * LVDS0 is in use.
+        */
+       status = "okay";
+
        clocks = <&cpg CPG_MOD 727>,
                 <&x13_clk>,
                 <&extal_clk>;
@@ -495,6 +533,11 @@
                function = "du";
        };
 
+       irq0_pins: irq0 {
+               groups = "intc_ex_irq0";
+               function = "intc_ex";
+       };
+
        pwm3_pins: pwm3 {
                groups = "pwm3_b";
                function = "pwm3";
@@ -650,6 +693,10 @@
        status = "okay";
 };
 
+&vin5 {
+       status = "okay";
+};
+
 &xhci0 {
        pinctrl-0 = <&usb30_pins>;
        pinctrl-names = "default";

diff --git a/arch/arm64/boot/dts/renesas/r8a77990.dtsi b/arch/arm64/boot/dts/renesas/r8a77990.dtsi
index d2ad665..56cb566 100644 (file)
--- a/arch/arm64/boot/dts/renesas/r8a77990.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi
@@ -1,4 +1,4 @@
-/* SPDX-License-Identifier: GPL-2.0 */
+// SPDX-License-Identifier: GPL-2.0
 /*
  * Device Tree Source for the R-Car E3 (R8A77990) SoC
  *
@@ -284,6 +284,76 @@
                        status = "disabled";
                };
 
+               cmt0: timer@e60f0000 {
+                       compatible = "renesas,r8a77990-cmt0",
+                                    "renesas,rcar-gen3-cmt0";
+                       reg = <0 0xe60f0000 0 0x1004>;
+                       interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 303>;
+                       clock-names = "fck";
+                       power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
+                       resets = <&cpg 303>;
+                       status = "disabled";
+               };
+
+               cmt1: timer@e6130000 {
+                       compatible = "renesas,r8a77990-cmt1",
+                                    "renesas,rcar-gen3-cmt1";
+                       reg = <0 0xe6130000 0 0x1004>;
+                       interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 302>;
+                       clock-names = "fck";
+                       power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
+                       resets = <&cpg 302>;
+                       status = "disabled";
+               };
+
+               cmt2: timer@e6140000 {
+                       compatible = "renesas,r8a77990-cmt1",
+                                    "renesas,rcar-gen3-cmt1";
+                       reg = <0 0xe6140000 0 0x1004>;
+                       interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 301>;
+                       clock-names = "fck";
+                       power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
+                       resets = <&cpg 301>;
+                       status = "disabled";
+               };
+
+               cmt3: timer@e6148000 {
+                       compatible = "renesas,r8a77990-cmt1",
+                                    "renesas,rcar-gen3-cmt1";
+                       reg = <0 0xe6148000 0 0x1004>;
+                       interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 300>;
+                       clock-names = "fck";
+                       power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
+                       resets = <&cpg 300>;
+                       status = "disabled";
+               };
+
                cpg: clock-controller@e6150000 {
                        compatible = "renesas,r8a77990-cpg-mssr";
                        reg = <0 0xe6150000 0 0x1000>;
@@ -1656,7 +1726,7 @@
                };
 
                csi40: csi2@feaa0000 {
-                       compatible = "renesas,r8a77990-csi2", "renesas,rcar-gen3-csi2";
+                       compatible = "renesas,r8a77990-csi2";
                        reg = <0 0xfeaa0000 0 0x10000>;
                        interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
                        clocks = <&cpg CPG_MOD 716>;

diff --git a/arch/arm64/boot/dts/renesas/r8a77995-draak.dts b/arch/arm64/boot/dts/renesas/r8a77995-draak.dts
index db2bed1..a7dc11e 100644 (file)
--- a/arch/arm64/boot/dts/renesas/r8a77995-draak.dts
+++ b/arch/arm64/boot/dts/renesas/r8a77995-draak.dts
@@ -20,7 +20,7 @@
        };
 
        chosen {
-               bootargs = "ignore_loglevel";
+               bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
                stdout-path = "serial0:115200n8";
        };
 
@@ -168,7 +168,6 @@
        pinctrl-names = "default";
        renesas,no-ether-link;
        phy-handle = <&phy0>;
-       phy-mode = "rgmii-txid";
        status = "okay";
 
        phy0: ethernet-phy@0 {
@@ -179,6 +178,18 @@
        };
 };
 
+&can0 {
+       pinctrl-0 = <&can0_pins>;
+       pinctrl-names = "default";
+       status = "okay";
+};
+
+&can1 {
+       pinctrl-0 = <&can1_pins>;
+       pinctrl-names = "default";
+       status = "okay";
+};
+
 &du {
        pinctrl-0 = <&du_pins>;
        pinctrl-names = "default";
@@ -356,6 +367,13 @@
 };
 
 &lvds1 {
+       /*
+        * Even though the LVDS1 output is not connected, the encoder must be
+        * enabled to supply a pixel clock to the DU for the DPAD output when
+        * LVDS0 is in use.
+        */
+       status = "okay";
+
        clocks = <&cpg CPG_MOD 727>,
                 <&x12_clk>,
                 <&extal_clk>;
@@ -375,6 +393,16 @@
                };
        };
 
+       can0_pins: can0 {
+               groups = "can0_data_a";
+               function = "can0";
+       };
+
+       can1_pins: can1 {
+               groups = "can1_data_a";
+               function = "can1";
+       };
+
        du_pins: du {
                groups = "du_rgb888", "du_sync", "du_disp", "du_clk_out_0";
                function = "du";

diff --git a/arch/arm64/boot/dts/renesas/salvator-common.dtsi b/arch/arm64/boot/dts/renesas/salvator-common.dtsi
index a225c24..2dba132 100644 (file)
--- a/arch/arm64/boot/dts/renesas/salvator-common.dtsi
+++ b/arch/arm64/boot/dts/renesas/salvator-common.dtsi
@@ -29,6 +29,7 @@
  */
 
 #include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
 
 / {
        aliases {
@@ -86,6 +87,63 @@
                };
        };
 
+       keys {
+               compatible = "gpio-keys";
+
+               pinctrl-0 = <&keys_pins>;
+               pinctrl-names = "default";
+
+               key-1 {
+                       gpios = <&gpio5 17 GPIO_ACTIVE_LOW>;
+                       linux,code = <KEY_1>;
+                       label = "SW4-1";
+                       wakeup-source;
+                       debounce-interval = <20>;
+               };
+               key-2 {
+                       gpios = <&gpio5 20 GPIO_ACTIVE_LOW>;
+                       linux,code = <KEY_2>;
+                       label = "SW4-2";
+                       wakeup-source;
+                       debounce-interval = <20>;
+               };
+               key-3 {
+                       gpios = <&gpio5 22 GPIO_ACTIVE_LOW>;
+                       linux,code = <KEY_3>;
+                       label = "SW4-3";
+                       wakeup-source;
+                       debounce-interval = <20>;
+               };
+               key-4 {
+                       gpios = <&gpio5 23 GPIO_ACTIVE_LOW>;
+                       linux,code = <KEY_4>;
+                       label = "SW4-4";
+                       wakeup-source;
+                       debounce-interval = <20>;
+               };
+               key-a {
+                       gpios = <&gpio6 11 GPIO_ACTIVE_LOW>;
+                       linux,code = <KEY_A>;
+                       label = "TSW0";
+                       wakeup-source;
+                       debounce-interval = <20>;
+               };
+               key-b {
+                       gpios = <&gpio6 12 GPIO_ACTIVE_LOW>;
+                       linux,code = <KEY_B>;
+                       label = "TSW1";
+                       wakeup-source;
+                       debounce-interval = <20>;
+               };
+               key-c {
+                       gpios = <&gpio6 13 GPIO_ACTIVE_LOW>;
+                       linux,code = <KEY_C>;
+                       label = "TSW2";
+                       wakeup-source;
+                       debounce-interval = <20>;
+               };
+       };
+
        reg_1p8v: regulator0 {
                compatible = "regulator-fixed";
                regulator-name = "fixed-1.8V";
@@ -572,6 +630,11 @@
                function = "intc_ex";
        };
 
+       keys_pins: keys {
+               pins = "GP_5_17", "GP_5_20", "GP_5_22";
+               bias-pull-up;
+       };
+
        pwm1_pins: pwm1 {
                groups = "pwm1_a";
                function = "pwm1";
@@ -719,6 +782,11 @@
        };
 };
 
+&rwdt {
+       timeout-sec = <60>;
+       status = "okay";
+};
+
 &scif1 {
        pinctrl-0 = <&scif1_pins>;
        pinctrl-names = "default";
@@ -857,11 +925,6 @@
        status = "okay";
 };
 
-&rwdt {
-       timeout-sec = <60>;
-       status = "okay";
-};
-
 &xhci0 {
        pinctrl-0 = <&usb30_pins>;
        pinctrl-names = "default";

diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile
index 1b28fa7..5f2687a 100644 (file)
--- a/arch/arm64/boot/dts/rockchip/Makefile
+++ b/arch/arm64/boot/dts/rockchip/Makefile
@@ -18,6 +18,8 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-gru-scarlet-inx.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-gru-scarlet-kd.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-nanopc-t4.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-nanopi-m4.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-nanopi-neo4.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-orangepi.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-puma-haikou.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-roc-pc.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rock-pi-4.dtb

diff --git a/arch/arm64/boot/dts/rockchip/px30-evb.dts b/arch/arm64/boot/dts/rockchip/px30-evb.dts
index 263d7f3..6eb7407 100644 (file)
--- a/arch/arm64/boot/dts/rockchip/px30-evb.dts
+++ b/arch/arm64/boot/dts/rockchip/px30-evb.dts
@@ -145,12 +145,12 @@
 
                soc_slppin_slp: soc_slppin_slp {
                        rockchip,pins =
-                               <0 RK_PA4 RK_FUNC_1 &pcfg_pull_none>;
+                               <0 RK_PA4 1 &pcfg_pull_none>;
                };
 
                soc_slppin_rst: soc_slppin_rst {
                        rockchip,pins =
-                               <0 RK_PA4 RK_FUNC_2 &pcfg_pull_none>;
+                               <0 RK_PA4 2 &pcfg_pull_none>;
                };
        };
 

diff --git a/arch/arm64/boot/dts/rockchip/rk3328-evb.dts b/arch/arm64/boot/dts/rockchip/rk3328-evb.dts
index 8302d86..49c4b96 100644 (file)
--- a/arch/arm64/boot/dts/rockchip/rk3328-evb.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3328-evb.dts
@@ -208,7 +208,7 @@
        sdio-pwrseq {
                wifi_enable_h: wifi-enable-h {
                rockchip,pins =
-                       <1 18 RK_FUNC_GPIO &pcfg_pull_none>;
+                       <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
                };
        };
 };

diff --git a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts
index 0e34354..5d499c9 100644 (file)
--- a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts
@@ -81,18 +81,55 @@
                regulator-always-on;
                regulator-boot-on;
        };
+
+       leds {
+               compatible = "gpio-leds";
+
+               power {
+                       label = "firefly:blue:power";
+                       linux,default-trigger = "heartbeat";
+                       gpios = <&rk805 1 GPIO_ACTIVE_LOW>;
+                       default-state = "on";
+                       mode = <0x23>;
+               };
+
+               user {
+                       label = "firefly:yellow:user";
+                       linux,default-trigger = "mmc1";
+                       gpios = <&rk805 0 GPIO_ACTIVE_LOW>;
+                       default-state = "off";
+                       mode = <0x05>;
+               };
+       };
 };
 
 &cpu0 {
        cpu-supply = <&vdd_arm>;
 };
 
+&cpu1 {
+       cpu-supply = <&vdd_arm>;
+};
+
+&cpu2 {
+       cpu-supply = <&vdd_arm>;
+};
+
+&cpu3 {
+       cpu-supply = <&vdd_arm>;
+};
+
 &emmc {
        bus-width = <8>;
        cap-mmc-highspeed;
+       max-frequency = <150000000>;
+       mmc-ddr-1_8v;
+       mmc-hs200-1_8v;
        non-removable;
        pinctrl-names = "default";
        pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
+       vmmc-supply = <&vcc_io>;
+       vqmmc-supply = <&vcc18_emmc>;
        status = "okay";
 };
 
@@ -113,6 +150,14 @@
        status = "okay";
 };
 
+&hdmi {
+       status = "okay";
+};
+
+&hdmiphy {
+       status = "okay";
+};
+
 &i2c1 {
        status = "okay";
 
@@ -296,3 +341,11 @@
 &usb_host0_ohci {
        status = "okay";
 };
+
+&vop {
+       status = "okay";
+};
+
+&vop_mmu {
+       status = "okay";
+};

diff --git a/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts b/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts
index 79b4d1d..7cfd5ca 100644 (file)
--- a/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts
@@ -64,6 +64,27 @@
                regulator-max-microvolt = <5000000>;
        };
 
+       ir-receiver {
+               compatible = "gpio-ir-receiver";
+               gpios = <&gpio2 RK_PA2 GPIO_ACTIVE_LOW>;
+               pinctrl-0 = <&ir_int>;
+               pinctrl-names = "default";
+       };
+
+       leds {
+               compatible = "gpio-leds";
+
+               power {
+                       gpios = <&rk805 1 GPIO_ACTIVE_LOW>;
+                       linux,default-trigger = "mmc0";
+               };
+
+               standby {
+                       gpios = <&rk805 0 GPIO_ACTIVE_LOW>;
+                       linux,default-trigger = "heartbeat";
+               };
+       };
+
        sound {
                compatible = "audio-graph-card";
                label = "rockchip,rk3328";
@@ -156,6 +177,8 @@
                interrupts = <6 IRQ_TYPE_LEVEL_LOW>;
                #clock-cells = <1>;
                clock-output-names = "xin32k", "rk805-clkout2";
+               gpio-controller;
+               #gpio-cells = <2>;
                pinctrl-names = "default";
                pinctrl-0 = <&pmic_int_l>;
                rockchip,system-power-controller;
@@ -217,7 +240,7 @@
                        };
 
                        vcc_18: LDO_REG1 {
-                               regulator-name = "vdd_18";
+                               regulator-name = "vcc_18";
                                regulator-min-microvolt = <1800000>;
                                regulator-max-microvolt = <1800000>;
                                regulator-always-on;
@@ -229,7 +252,7 @@
                        };
 
                        vcc18_emmc: LDO_REG2 {
-                               regulator-name = "vcc_18emmc";
+                               regulator-name = "vcc18_emmc";
                                regulator-min-microvolt = <1800000>;
                                regulator-max-microvolt = <1800000>;
                                regulator-always-on;
@@ -280,6 +303,12 @@
 };
 
 &pinctrl {
+       ir {
+               ir_int: ir-int {
+                       rockchip,pins = <2 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
+               };
+       };
+
        pmic {
                pmic_int_l: pmic-int-l {
                        rockchip,pins = <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>;

diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
index dabef1a..9944686 100644 (file)
--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
@@ -657,14 +657,17 @@
                interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
                             <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&cru PCLK_HDMI>,
-                        <&cru SCLK_HDMI_SFC>;
+                        <&cru SCLK_HDMI_SFC>,
+                        <&cru SCLK_RTC32K>;
                clock-names = "iahb",
-                             "isfr";
+                             "isfr",
+                             "cec";
                phys = <&hdmiphy>;
                phy-names = "hdmi";
                pinctrl-names = "default";
                pinctrl-0 = <&hdmi_cec &hdmii2c_xfer &hdmi_hpd>;
                rockchip,grf = <&grf>;
+               #sound-dai-cells = <0>;
                status = "disabled";
 
                ports {

diff --git a/arch/arm64/boot/dts/rockchip/rk3368-evb.dtsi b/arch/arm64/boot/dts/rockchip/rk3368-evb.dtsi
index e96eb62..1c52f47 100644 (file)
--- a/arch/arm64/boot/dts/rockchip/rk3368-evb.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3368-evb.dtsi
@@ -154,60 +154,60 @@
 
        backlight {
                bl_en: bl-en {
-                       rockchip,pins = <0 20 RK_FUNC_GPIO &pcfg_pull_none>;
+                       rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>;
                };
        };
 
        emmc {
                emmc_bus8: emmc-bus8 {
-                       rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,
-                                       <1 19 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,
-                                       <1 20 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,
-                                       <1 21 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,
-                                       <1 22 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,
-                                       <1 23 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,
-                                       <1 24 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,
-                                       <1 25 RK_FUNC_2 &pcfg_pull_up_drv_8ma>;
+                       rockchip,pins = <1 RK_PC2 2 &pcfg_pull_up_drv_8ma>,
+                                       <1 RK_PC3 2 &pcfg_pull_up_drv_8ma>,
+                                       <1 RK_PC4 2 &pcfg_pull_up_drv_8ma>,
+                                       <1 RK_PC5 2 &pcfg_pull_up_drv_8ma>,
+                                       <1 RK_PC6 2 &pcfg_pull_up_drv_8ma>,
+                                       <1 RK_PC7 2 &pcfg_pull_up_drv_8ma>,
+                                       <1 RK_PD0 2 &pcfg_pull_up_drv_8ma>,
+                                       <1 RK_PD1 2 &pcfg_pull_up_drv_8ma>;
                };
 
                emmc-clk {
-                       rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none_drv_8ma>;
+                       rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none_drv_8ma>;
                };
 
                emmc-cmd {
-                       rockchip,pins = <1 26 RK_FUNC_2 &pcfg_pull_up_drv_8ma>;
+                       rockchip,pins = <1 RK_PD2 2 &pcfg_pull_up_drv_8ma>;
                };
 
                emmc_reset: emmc-reset {
-                       rockchip,pins = <2 3 RK_FUNC_GPIO &pcfg_pull_none>;
+                       rockchip,pins = <2 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
                };
        };
 
        keys {
                pwr_key: pwr-key {
-                       rockchip,pins = <0 2 RK_FUNC_GPIO &pcfg_pull_up>;
+                       rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>;
                };
        };
 
        pmic {
                pmic_int: pmic-int {
-                       rockchip,pins = <0 1 RK_FUNC_GPIO &pcfg_pull_up>;
+                       rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>;
                };
        };
 
        sdio {
                wifi_reg_on: wifi-reg-on {
-                       rockchip,pins = <3 4 RK_FUNC_GPIO &pcfg_pull_none>;
+                       rockchip,pins = <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
                };
 
                bt_rst: bt-rst {
-                       rockchip,pins = <3 5 RK_FUNC_GPIO &pcfg_pull_none>;
+                       rockchip,pins = <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
                };
        };
 
        usb {
                host_vbus_drv: host-vbus-drv {
-                       rockchip,pins = <0 4 RK_FUNC_GPIO &pcfg_pull_none>;
+                       rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
                };
        };
 };

diff --git a/arch/arm64/boot/dts/rockchip/rk3368-geekbox.dts b/arch/arm64/boot/dts/rockchip/rk3368-geekbox.dts
index 8fa550c..1d0778f 100644 (file)
--- a/arch/arm64/boot/dts/rockchip/rk3368-geekbox.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3368-geekbox.dts
@@ -233,23 +233,23 @@
 &pinctrl {
        ir {
                ir_int: ir-int {
-                       rockchip,pins = <3 30 RK_FUNC_GPIO &pcfg_pull_none>;
+                       rockchip,pins = <3 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
                };
        };
 
        keys {
                pwr_key: pwr-key {
-                       rockchip,pins = <0 2 RK_FUNC_GPIO &pcfg_pull_none>;
+                       rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
                };
        };
 
        pmic {
                pmic_sleep: pmic-sleep {
-                       rockchip,pins = <0 0 RK_FUNC_2 &pcfg_pull_none>;
+                       rockchip,pins = <0 RK_PA0 2 &pcfg_pull_none>;
                };
 
                pmic_int: pmic-int {
-                       rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_up>;
+                       rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;
                };
        };
 };

diff --git a/arch/arm64/boot/dts/rockchip/rk3368-lion-haikou.dts b/arch/arm64/boot/dts/rockchip/rk3368-lion-haikou.dts
index fca8e87..8251f3c 100644 (file)
--- a/arch/arm64/boot/dts/rockchip/rk3368-lion-haikou.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3368-lion-haikou.dts
@@ -113,34 +113,34 @@
                haikou_pin_hog: haikou-pin-hog {
                        rockchip,pins =
                                /* LID_BTN */
-                               <RK_GPIO3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>,
+                               <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>,
                                /* BATLOW# */
-                               <RK_GPIO0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up>,
+                               <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up>,
                                /* SLP_BTN# */
-                               <RK_GPIO3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>,
+                               <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>,
                                /* BIOS_DISABLE# */
-                               <RK_GPIO3 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>;
+                               <3 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>;
                };
        };
 
        leds {
                led_sd_haikou: led-sd-gpio {
                        rockchip,pins =
-                               <RK_GPIO0 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
+                               <0 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
                };
        };
 
        sdmmc {
                sdmmc_cd_gpio: sdmmc-cd-gpio {
                        rockchip,pins =
-                               <RK_GPIO2 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
+                               <2 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
                };
        };
 
        usb_otg {
                otg_vbus_drv: otg-vbus-drv {
                        rockchip,pins =
-                               <RK_GPIO0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
+                               <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
                };
        };
 };

diff --git a/arch/arm64/boot/dts/rockchip/rk3368-lion.dtsi b/arch/arm64/boot/dts/rockchip/rk3368-lion.dtsi
index 1b35d61..e17311e 100644 (file)
--- a/arch/arm64/boot/dts/rockchip/rk3368-lion.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3368-lion.dtsi
@@ -56,8 +56,6 @@
                        fan: fan@18 {
                                compatible = "ti,amc6821";
                                reg = <0x18>;
-                               cooling-min-state = <0>;
-                               cooling-max-state = <9>;
                                #cooling-cells = <2>;
                        };
 
@@ -274,17 +272,17 @@
        leds {
                led_pins_module: led-module-gpio {
                        rockchip,pins =
-                               <RK_GPIO2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>,
-                               <RK_GPIO3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
+                               <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>,
+                               <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
                };
        };
        pmic {
                pmic_int_l: pmic-int-l {
-                       rockchip,pins = <RK_GPIO0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;
+                       rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;
                };
 
                pmic_sleep: pmic-sleep {
-                       rockchip,pins = <RK_GPIO0 RK_PA0 RK_FUNC_2 &pcfg_pull_none>;
+                       rockchip,pins = <0 RK_PA0 2 &pcfg_pull_none>;
                };
        };
 };

diff --git a/arch/arm64/boot/dts/rockchip/rk3368-orion-r68-meta.dts b/arch/arm64/boot/dts/rockchip/rk3368-orion-r68-meta.dts
index f5aa3ca..6cc3102 100644 (file)
--- a/arch/arm64/boot/dts/rockchip/rk3368-orion-r68-meta.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3368-orion-r68-meta.dts
@@ -226,73 +226,73 @@
 
        emmc {
                emmc_bus8: emmc-bus8 {
-                       rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,
-                                       <1 19 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,
-                                       <1 20 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,
-                                       <1 21 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,
-                                       <1 22 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,
-                                       <1 23 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,
-                                       <1 24 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,
-                                       <1 25 RK_FUNC_2 &pcfg_pull_up_drv_8ma>;
+                       rockchip,pins = <1 RK_PC2 2 &pcfg_pull_up_drv_8ma>,
+                                       <1 RK_PC3 2 &pcfg_pull_up_drv_8ma>,
+                                       <1 RK_PC4 2 &pcfg_pull_up_drv_8ma>,
+                                       <1 RK_PC5 2 &pcfg_pull_up_drv_8ma>,
+                                       <1 RK_PC6 2 &pcfg_pull_up_drv_8ma>,
+                                       <1 RK_PC7 2 &pcfg_pull_up_drv_8ma>,
+                                       <1 RK_PD0 2 &pcfg_pull_up_drv_8ma>,
+                                       <1 RK_PD1 2 &pcfg_pull_up_drv_8ma>;
                };
 
                emmc-clk {
-                       rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none_drv_8ma>;
+                       rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none_drv_8ma>;
                };
 
                emmc-cmd {
-                       rockchip,pins = <1 26 RK_FUNC_2 &pcfg_pull_up_drv_8ma>;
+                       rockchip,pins = <1 RK_PD2 2 &pcfg_pull_up_drv_8ma>;
                };
 
                emmc_reset: emmc-reset {
-                       rockchip,pins = <2 3 RK_FUNC_GPIO &pcfg_pull_none>;
+                       rockchip,pins = <2 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
                };
        };
 
        keys {
                pwr_key: pwr-key {
-                       rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_down>;
+                       rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_down>;
                };
        };
 
        leds {
                stby_pwren: stby-pwren {
-                       rockchip,pins = <0 12 RK_FUNC_GPIO &pcfg_pull_none>;
+                       rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>;
                };
 
                led_ctl: led-ctl {
-                       rockchip,pins = <3 29 RK_FUNC_GPIO &pcfg_pull_none>;
+                       rockchip,pins = <3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
                };
        };
 
        sdmmc {
                sdmmc_clk: sdmmc-clk {
-                       rockchip,pins = <2 9 RK_FUNC_1 &pcfg_pull_none_drv_8ma>;
+                       rockchip,pins = <2 RK_PB1 1 &pcfg_pull_none_drv_8ma>;
                };
 
                sdmmc_cmd: sdmmc-cmd {
-                       rockchip,pins = <2 10 RK_FUNC_1 &pcfg_pull_up_drv_8ma>;
+                       rockchip,pins = <2 RK_PB2 1 &pcfg_pull_up_drv_8ma>;
                };
 
                sdmmc_cd: sdmmc-cd {
-                       rockchip,pins = <2 11 RK_FUNC_1 &pcfg_pull_up_drv_8ma>;
+                       rockchip,pins = <2 RK_PB3 1 &pcfg_pull_up_drv_8ma>;
                };
 
                sdmmc_bus1: sdmmc-bus1 {
-                       rockchip,pins = <2 5 RK_FUNC_1 &pcfg_pull_up_drv_8ma>;
+                       rockchip,pins = <2 RK_PA5 1 &pcfg_pull_up_drv_8ma>;
                };
 
                sdmmc_bus4: sdmmc-bus4 {
-                       rockchip,pins = <2 5 RK_FUNC_1 &pcfg_pull_up_drv_8ma>,
-                                       <2 6 RK_FUNC_1 &pcfg_pull_up_drv_8ma>,
-                                       <2 7 RK_FUNC_1 &pcfg_pull_up_drv_8ma>,
-                                       <2 8 RK_FUNC_1 &pcfg_pull_up_drv_8ma>;
+                       rockchip,pins = <2 RK_PA5 1 &pcfg_pull_up_drv_8ma>,
+                                       <2 RK_PA6 1 &pcfg_pull_up_drv_8ma>,
+                                       <2 RK_PA7 1 &pcfg_pull_up_drv_8ma>,
+                                       <2 RK_PB0 1 &pcfg_pull_up_drv_8ma>;
                };
        };
 
        usb {
                host_vbus_drv: host-vbus-drv {
-                       rockchip,pins = <0 4 RK_FUNC_GPIO &pcfg_pull_none>;
+                       rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
                };
        };
 };

diff --git a/arch/arm64/boot/dts/rockchip/rk3368-px5-evb.dts b/arch/arm64/boot/dts/rockchip/rk3368-px5-evb.dts
index 41edcfd..231db03 100644 (file)
--- a/arch/arm64/boot/dts/rockchip/rk3368-px5-evb.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3368-px5-evb.dts
@@ -218,17 +218,17 @@
 &pinctrl {
        keys {
                pwr_key: pwr-key {
-                       rockchip,pins = <0 2 RK_FUNC_GPIO &pcfg_pull_none>;
+                       rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
                };
        };
 
        pmic {
                pmic_sleep: pmic-sleep {
-                       rockchip,pins = <0 0 RK_FUNC_2 &pcfg_pull_none>;
+                       rockchip,pins = <0 RK_PA0 2 &pcfg_pull_none>;
                };
 
                pmic_int: pmic-int {
-                       rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_up>;
+                       rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;
                };
        };
 };

diff --git a/arch/arm64/boot/dts/rockchip/rk3368-r88.dts b/arch/arm64/boot/dts/rockchip/rk3368-r88.dts
index d34064c..006a1fb 100644 (file)
--- a/arch/arm64/boot/dts/rockchip/rk3368-r88.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3368-r88.dts
@@ -235,64 +235,64 @@
 
        emmc {
                emmc_bus8: emmc-bus8 {
-                       rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,
-                                       <1 19 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,
-                                       <1 20 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,
-                                       <1 21 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,
-                                       <1 22 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,
-                                       <1 23 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,
-                                       <1 24 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,
-                                       <1 25 RK_FUNC_2 &pcfg_pull_up_drv_8ma>;
+                       rockchip,pins = <1 RK_PC2 2 &pcfg_pull_up_drv_8ma>,
+                                       <1 RK_PC3 2 &pcfg_pull_up_drv_8ma>,
+                                       <1 RK_PC4 2 &pcfg_pull_up_drv_8ma>,
+                                       <1 RK_PC5 2 &pcfg_pull_up_drv_8ma>,
+                                       <1 RK_PC6 2 &pcfg_pull_up_drv_8ma>,
+                                       <1 RK_PC7 2 &pcfg_pull_up_drv_8ma>,
+                                       <1 RK_PD0 2 &pcfg_pull_up_drv_8ma>,
+                                       <1 RK_PD1 2 &pcfg_pull_up_drv_8ma>;
                };
 
                emmc-clk {
-                       rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none_drv_8ma>;
+                       rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none_drv_8ma>;
                };
 
                emmc-cmd {
-                       rockchip,pins = <1 26 RK_FUNC_2 &pcfg_pull_up_drv_8ma>;
+                       rockchip,pins = <1 RK_PD2 2 &pcfg_pull_up_drv_8ma>;
                };
 
                emmc_reset: emmc-reset {
-                       rockchip,pins = <2 3 RK_FUNC_GPIO &pcfg_pull_none>;
+                       rockchip,pins = <2 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
                };
        };
 
        ir {
                ir_int: ir-int {
-                       rockchip,pins = <3 30 RK_FUNC_GPIO &pcfg_pull_up>;
+                       rockchip,pins = <3 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up>;
                };
        };
 
        keys {
                pwr_key: pwr-key {
-                       rockchip,pins = <0 2 RK_FUNC_GPIO &pcfg_pull_up>;
+                       rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>;
                };
        };
 
        leds {
                stby_pwren: stby-pwren {
-                       rockchip,pins = <0 12 RK_FUNC_GPIO &pcfg_pull_none>;
+                       rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>;
                };
 
                led_ctl: led-ctl {
-                       rockchip,pins = <3 29 RK_FUNC_GPIO &pcfg_pull_none>;
+                       rockchip,pins = <3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
                };
        };
 
        sdio {
                wifi_reg_on: wifi-reg-on {
-                       rockchip,pins = <3 4 RK_FUNC_GPIO &pcfg_pull_none>;
+                       rockchip,pins = <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
                };
 
                bt_rst: bt-rst {
-                       rockchip,pins = <3 5 RK_FUNC_GPIO &pcfg_pull_none>;
+                       rockchip,pins = <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
                };
        };
 
        usb {
                host_vbus_drv: host-vbus-drv {
-                       rockchip,pins = <0 4 RK_FUNC_GPIO &pcfg_pull_none>;
+                       rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
                };
        };
 };

diff --git a/arch/arm64/boot/dts/rockchip/rk3368.dtsi b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
index 06e7c31..fd86188 100644 (file)
--- a/arch/arm64/boot/dts/rockchip/rk3368.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
@@ -881,345 +881,345 @@
 
                emmc {
                        emmc_clk: emmc-clk {
-                               rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>;
+                               rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>;
                        };
 
                        emmc_cmd: emmc-cmd {
-                               rockchip,pins = <1 26 RK_FUNC_2 &pcfg_pull_up>;
+                               rockchip,pins = <1 RK_PD2 2 &pcfg_pull_up>;
                        };
 
                        emmc_pwr: emmc-pwr {
-                               rockchip,pins = <1 27 RK_FUNC_2 &pcfg_pull_up>;
+                               rockchip,pins = <1 RK_PD3 2 &pcfg_pull_up>;
                        };
 
                        emmc_bus1: emmc-bus1 {
-                               rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>;
+                               rockchip,pins = <1 RK_PC2 2 &pcfg_pull_up>;
                        };
 
                        emmc_bus4: emmc-bus4 {
-                               rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>,
-                                               <1 19 RK_FUNC_2 &pcfg_pull_up>,
-                                               <1 20 RK_FUNC_2 &pcfg_pull_up>,
-                                               <1 21 RK_FUNC_2 &pcfg_pull_up>;
+                               rockchip,pins = <1 RK_PC2 2 &pcfg_pull_up>,
+                                               <1 RK_PC3 2 &pcfg_pull_up>,
+                                               <1 RK_PC4 2 &pcfg_pull_up>,
+                                               <1 RK_PC5 2 &pcfg_pull_up>;
                        };
 
                        emmc_bus8: emmc-bus8 {
-                               rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>,
-                                               <1 19 RK_FUNC_2 &pcfg_pull_up>,
-                                               <1 20 RK_FUNC_2 &pcfg_pull_up>,
-                                               <1 21 RK_FUNC_2 &pcfg_pull_up>,
-                                               <1 22 RK_FUNC_2 &pcfg_pull_up>,
-                                               <1 23 RK_FUNC_2 &pcfg_pull_up>,
-                                               <1 24 RK_FUNC_2 &pcfg_pull_up>,
-                                               <1 25 RK_FUNC_2 &pcfg_pull_up>;
+                               rockchip,pins = <1 RK_PC2 2 &pcfg_pull_up>,
+                                               <1 RK_PC3 2 &pcfg_pull_up>,
+                                               <1 RK_PC4 2 &pcfg_pull_up>,
+                                               <1 RK_PC5 2 &pcfg_pull_up>,
+                                               <1 RK_PC6 2 &pcfg_pull_up>,
+                                               <1 RK_PC7 2 &pcfg_pull_up>,
+                                               <1 RK_PD0 2 &pcfg_pull_up>,
+                                               <1 RK_PD1 2 &pcfg_pull_up>;
                        };
                };
 
                gmac {
                        rgmii_pins: rgmii-pins {
-                               rockchip,pins = <3 22 RK_FUNC_1 &pcfg_pull_none>,
-                                               <3 24 RK_FUNC_1 &pcfg_pull_none>,
-                                               <3 19 RK_FUNC_1 &pcfg_pull_none>,
-                                               <3 8 RK_FUNC_1 &pcfg_pull_none_12ma>,
-                                               <3 9 RK_FUNC_1 &pcfg_pull_none_12ma>,
-                                               <3 10 RK_FUNC_1 &pcfg_pull_none_12ma>,
-                                               <3 14 RK_FUNC_1 &pcfg_pull_none_12ma>,
-                                               <3 28 RK_FUNC_1 &pcfg_pull_none_12ma>,
-                                               <3 13 RK_FUNC_1 &pcfg_pull_none_12ma>,
-                                               <3 15 RK_FUNC_1 &pcfg_pull_none>,
-                                               <3 16 RK_FUNC_1 &pcfg_pull_none>,
-                                               <3 17 RK_FUNC_1 &pcfg_pull_none>,
-                                               <3 18 RK_FUNC_1 &pcfg_pull_none>,
-                                               <3 25 RK_FUNC_1 &pcfg_pull_none>,
-                                               <3 20 RK_FUNC_1 &pcfg_pull_none>;
+                               rockchip,pins = <3 RK_PC6 1 &pcfg_pull_none>,
+                                               <3 RK_PD0 1 &pcfg_pull_none>,
+                                               <3 RK_PC3 1 &pcfg_pull_none>,
+                                               <3 RK_PB0 1 &pcfg_pull_none_12ma>,
+                                               <3 RK_PB1 1 &pcfg_pull_none_12ma>,
+                                               <3 RK_PB2 1 &pcfg_pull_none_12ma>,
+                                               <3 RK_PB6 1 &pcfg_pull_none_12ma>,
+                                               <3 RK_PD4 1 &pcfg_pull_none_12ma>,
+                                               <3 RK_PB5 1 &pcfg_pull_none_12ma>,
+                                               <3 RK_PB7 1 &pcfg_pull_none>,
+                                               <3 RK_PC0 1 &pcfg_pull_none>,
+                                               <3 RK_PC1 1 &pcfg_pull_none>,
+                                               <3 RK_PC2 1 &pcfg_pull_none>,
+                                               <3 RK_PD1 1 &pcfg_pull_none>,
+                                               <3 RK_PC4 1 &pcfg_pull_none>;
                        };
 
                        rmii_pins: rmii-pins {
-                               rockchip,pins = <3 22 RK_FUNC_1 &pcfg_pull_none>,
-                                               <3 24 RK_FUNC_1 &pcfg_pull_none>,
-                                               <3 19 RK_FUNC_1 &pcfg_pull_none>,
-                                               <3 8 RK_FUNC_1 &pcfg_pull_none_12ma>,
-                                               <3 9 RK_FUNC_1 &pcfg_pull_none_12ma>,
-                                               <3 13 RK_FUNC_1 &pcfg_pull_none_12ma>,
-                                               <3 15 RK_FUNC_1 &pcfg_pull_none>,
-                                               <3 16 RK_FUNC_1 &pcfg_pull_none>,
-                                               <3 20 RK_FUNC_1 &pcfg_pull_none>,
-                                               <3 21 RK_FUNC_1 &pcfg_pull_none>;
+                               rockchip,pins = <3 RK_PC6 1 &pcfg_pull_none>,
+                                               <3 RK_PD0 1 &pcfg_pull_none>,
+                                               <3 RK_PC3 1 &pcfg_pull_none>,
+                                               <3 RK_PB0 1 &pcfg_pull_none_12ma>,
+                                               <3 RK_PB1 1 &pcfg_pull_none_12ma>,
+                                               <3 RK_PB5 1 &pcfg_pull_none_12ma>,
+                                               <3 RK_PB7 1 &pcfg_pull_none>,
+                                               <3 RK_PC0 1 &pcfg_pull_none>,
+                                               <3 RK_PC4 1 &pcfg_pull_none>,
+                                               <3 RK_PC5 1 &pcfg_pull_none>;
                        };
                };
 
                i2c0 {
                        i2c0_xfer: i2c0-xfer {
-                               rockchip,pins = <0 6 RK_FUNC_1 &pcfg_pull_none>,
-                                               <0 7 RK_FUNC_1 &pcfg_pull_none>;
+                               rockchip,pins = <0 RK_PA6 1 &pcfg_pull_none>,
+                                               <0 RK_PA7 1 &pcfg_pull_none>;
                        };
                };
 
                i2c1 {
                        i2c1_xfer: i2c1-xfer {
-                               rockchip,pins = <2 21 RK_FUNC_1 &pcfg_pull_none>,
-                                               <2 22 RK_FUNC_1 &pcfg_pull_none>;
+                               rockchip,pins = <2 RK_PC5 1 &pcfg_pull_none>,
+                                               <2 RK_PC6 1 &pcfg_pull_none>;
                        };
                };
 
                i2c2 {
                        i2c2_xfer: i2c2-xfer {
-                               rockchip,pins = <0 9 RK_FUNC_2 &pcfg_pull_none>,
-                                               <3 31 RK_FUNC_2 &pcfg_pull_none>;
+                               rockchip,pins = <0 RK_PB1 2 &pcfg_pull_none>,
+                                               <3 RK_PD7 2 &pcfg_pull_none>;
                        };
                };
 
                i2c3 {
                        i2c3_xfer: i2c3-xfer {
-                               rockchip,pins = <1 16 RK_FUNC_1 &pcfg_pull_none>,
-                                               <1 17 RK_FUNC_1 &pcfg_pull_none>;
+                               rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none>,
+                                               <1 RK_PC1 1 &pcfg_pull_none>;
                        };
                };
 
                i2c4 {
                        i2c4_xfer: i2c4-xfer {
-                               rockchip,pins = <3 24 RK_FUNC_2 &pcfg_pull_none>,
-                                               <3 25 RK_FUNC_2 &pcfg_pull_none>;
+                               rockchip,pins = <3 RK_PD0 2 &pcfg_pull_none>,
+                                               <3 RK_PD1 2 &pcfg_pull_none>;
                        };
                };
 
                i2c5 {
                        i2c5_xfer: i2c5-xfer {
-                               rockchip,pins = <3 26 RK_FUNC_2 &pcfg_pull_none>,
-                                               <3 27 RK_FUNC_2 &pcfg_pull_none>;
+                               rockchip,pins = <3 RK_PD2 2 &pcfg_pull_none>,
+                                               <3 RK_PD3 2 &pcfg_pull_none>;
                        };
                };
 
                i2s {
                        i2s_8ch_bus: i2s-8ch-bus {
-                               rockchip,pins = <2 12 RK_FUNC_1 &pcfg_pull_none>,
-                                               <2 13 RK_FUNC_1 &pcfg_pull_none>,
-                                               <2 14 RK_FUNC_1 &pcfg_pull_none>,
-                                               <2 15 RK_FUNC_1 &pcfg_pull_none>,
-                                               <2 16 RK_FUNC_1 &pcfg_pull_none>,
-                                               <2 17 RK_FUNC_1 &pcfg_pull_none>,
-                                               <2 18 RK_FUNC_1 &pcfg_pull_none>,
-                                               <2 19 RK_FUNC_1 &pcfg_pull_none>,
-                                               <2 20 RK_FUNC_1 &pcfg_pull_none>;
+                               rockchip,pins = <2 RK_PB4 1 &pcfg_pull_none>,
+                                               <2 RK_PB5 1 &pcfg_pull_none>,
+                                               <2 RK_PB6 1 &pcfg_pull_none>,
+                                               <2 RK_PB7 1 &pcfg_pull_none>,
+                                               <2 RK_PC0 1 &pcfg_pull_none>,
+                                               <2 RK_PC1 1 &pcfg_pull_none>,
+                                               <2 RK_PC2 1 &pcfg_pull_none>,
+                                               <2 RK_PC3 1 &pcfg_pull_none>,
+                                               <2 RK_PC4 1 &pcfg_pull_none>;
                        };
                };
 
                pwm0 {
                        pwm0_pin: pwm0-pin {
-                               rockchip,pins = <3 8 RK_FUNC_2 &pcfg_pull_none>;
+                               rockchip,pins = <3 RK_PB0 2 &pcfg_pull_none>;
                        };
                };
 
                pwm1 {
                        pwm1_pin: pwm1-pin {
-                               rockchip,pins = <0 8 RK_FUNC_2 &pcfg_pull_none>;
+                               rockchip,pins = <0 RK_PB0 2 &pcfg_pull_none>;
                        };
                };
 
                pwm3 {
                        pwm3_pin: pwm3-pin {
-                               rockchip,pins = <3 29 RK_FUNC_3 &pcfg_pull_none>;
+                               rockchip,pins = <3 RK_PD5 3 &pcfg_pull_none>;
                        };
                };
 
                sdio0 {
                        sdio0_bus1: sdio0-bus1 {
-                               rockchip,pins = <2 28 RK_FUNC_1 &pcfg_pull_up>;
+                               rockchip,pins = <2 RK_PD4 1 &pcfg_pull_up>;
                        };
 
                        sdio0_bus4: sdio0-bus4 {
-                               rockchip,pins = <2 28 RK_FUNC_1 &pcfg_pull_up>,
-                                               <2 29 RK_FUNC_1 &pcfg_pull_up>,
-                                               <2 30 RK_FUNC_1 &pcfg_pull_up>,
-                                               <2 31 RK_FUNC_1 &pcfg_pull_up>;
+                               rockchip,pins = <2 RK_PD4 1 &pcfg_pull_up>,
+                                               <2 RK_PD5 1 &pcfg_pull_up>,
+                                               <2 RK_PD6 1 &pcfg_pull_up>,
+                                               <2 RK_PD7 1 &pcfg_pull_up>;
                        };
 
                        sdio0_cmd: sdio0-cmd {
-                               rockchip,pins = <3 0 RK_FUNC_1 &pcfg_pull_up>;
+                               rockchip,pins = <3 RK_PA0 1 &pcfg_pull_up>;
                        };
 
                        sdio0_clk: sdio0-clk {
-                               rockchip,pins = <3 1 RK_FUNC_1 &pcfg_pull_none>;
+                               rockchip,pins = <3 RK_PA1 1 &pcfg_pull_none>;
                        };
 
                        sdio0_cd: sdio0-cd {
-                               rockchip,pins = <3 2 RK_FUNC_1 &pcfg_pull_up>;
+                               rockchip,pins = <3 RK_PA2 1 &pcfg_pull_up>;
                        };
 
                        sdio0_wp: sdio0-wp {
-                               rockchip,pins = <3 3 RK_FUNC_1 &pcfg_pull_up>;
+                               rockchip,pins = <3 RK_PA3 1 &pcfg_pull_up>;
                        };
 
                        sdio0_pwr: sdio0-pwr {
-                               rockchip,pins = <3 4 RK_FUNC_1 &pcfg_pull_up>;
+                               rockchip,pins = <3 RK_PA4 1 &pcfg_pull_up>;
                        };
 
                        sdio0_bkpwr: sdio0-bkpwr {
-                               rockchip,pins = <3 5 RK_FUNC_1 &pcfg_pull_up>;
+                               rockchip,pins = <3 RK_PA5 1 &pcfg_pull_up>;
                        };
 
                        sdio0_int: sdio0-int {
-                               rockchip,pins = <3 6 RK_FUNC_1 &pcfg_pull_up>;
+                               rockchip,pins = <3 RK_PA6 1 &pcfg_pull_up>;
                        };
                };
 
                sdmmc {
                        sdmmc_clk: sdmmc-clk {
-                               rockchip,pins = <2 9 RK_FUNC_1 &pcfg_pull_none>;
+                               rockchip,pins = <2 RK_PB1 1 &pcfg_pull_none>;
                        };
 
                        sdmmc_cmd: sdmmc-cmd {
-                               rockchip,pins = <2 10 RK_FUNC_1 &pcfg_pull_up>;
+                               rockchip,pins = <2 RK_PB2 1 &pcfg_pull_up>;
                        };
 
                        sdmmc_cd: sdmmc-cd {
-                               rockchip,pins = <2 11 RK_FUNC_1 &pcfg_pull_up>;
+                               rockchip,pins = <2 RK_PB3 1 &pcfg_pull_up>;
                        };
 
                        sdmmc_bus1: sdmmc-bus1 {
-                               rockchip,pins = <2 5 RK_FUNC_1 &pcfg_pull_up>;
+                               rockchip,pins = <2 RK_PA5 1 &pcfg_pull_up>;
                        };
 
                        sdmmc_bus4: sdmmc-bus4 {
-                               rockchip,pins = <2 5 RK_FUNC_1 &pcfg_pull_up>,
-                                               <2 6 RK_FUNC_1 &pcfg_pull_up>,
-                                               <2 7 RK_FUNC_1 &pcfg_pull_up>,
-                                               <2 8 RK_FUNC_1 &pcfg_pull_up>;
+                               rockchip,pins = <2 RK_PA5 1 &pcfg_pull_up>,
+                                               <2 RK_PA6 1 &pcfg_pull_up>,
+                                               <2 RK_PA7 1 &pcfg_pull_up>,
+                                               <2 RK_PB0 1 &pcfg_pull_up>;
                        };
                };
 
                spdif {
                        spdif_tx: spdif-tx {
-                               rockchip,pins = <2 RK_PC7 RK_FUNC_1 &pcfg_pull_none>;
+                               rockchip,pins = <2 RK_PC7 1 &pcfg_pull_none>;
                        };
                };
 
                spi0 {
                        spi0_clk: spi0-clk {
-                               rockchip,pins = <1 29 RK_FUNC_2 &pcfg_pull_up>;
+                               rockchip,pins = <1 RK_PD5 2 &pcfg_pull_up>;
                        };
                        spi0_cs0: spi0-cs0 {
-                               rockchip,pins = <1 24 RK_FUNC_3 &pcfg_pull_up>;
+                               rockchip,pins = <1 RK_PD0 3 &pcfg_pull_up>;
                        };
                        spi0_cs1: spi0-cs1 {
-                               rockchip,pins = <1 25 RK_FUNC_3 &pcfg_pull_up>;
+                               rockchip,pins = <1 RK_PD1 3 &pcfg_pull_up>;
                        };
                        spi0_tx: spi0-tx {
-                               rockchip,pins = <1 23 RK_FUNC_3 &pcfg_pull_up>;
+                               rockchip,pins = <1 RK_PC7 3 &pcfg_pull_up>;
                        };
                        spi0_rx: spi0-rx {
-                               rockchip,pins = <1 22 RK_FUNC_3 &pcfg_pull_up>;
+                               rockchip,pins = <1 RK_PC6 3 &pcfg_pull_up>;
                        };
                };
 
                spi1 {
                        spi1_clk: spi1-clk {
-                               rockchip,pins = <1 14 RK_FUNC_2 &pcfg_pull_up>;
+                               rockchip,pins = <1 RK_PB6 2 &pcfg_pull_up>;
                        };
                        spi1_cs0: spi1-cs0 {
-                               rockchip,pins = <1 15 RK_FUNC_2 &pcfg_pull_up>;
+                               rockchip,pins = <1 RK_PB7 2 &pcfg_pull_up>;
                        };
                        spi1_cs1: spi1-cs1 {
-                               rockchip,pins = <3 28 RK_FUNC_2 &pcfg_pull_up>;
+                               rockchip,pins = <3 RK_PD4 2 &pcfg_pull_up>;
                        };
                        spi1_rx: spi1-rx {
-                               rockchip,pins = <1 16 RK_FUNC_2 &pcfg_pull_up>;
+                               rockchip,pins = <1 RK_PC0 2 &pcfg_pull_up>;
                        };
                        spi1_tx: spi1-tx {
-                               rockchip,pins = <1 17 RK_FUNC_2 &pcfg_pull_up>;
+                               rockchip,pins = <1 RK_PC1 2 &pcfg_pull_up>;
                        };
                };
 
                spi2 {
                        spi2_clk: spi2-clk {
-                               rockchip,pins = <0 12 RK_FUNC_2 &pcfg_pull_up>;
+                               rockchip,pins = <0 RK_PB4 2 &pcfg_pull_up>;
                        };
                        spi2_cs0: spi2-cs0 {
-                               rockchip,pins = <0 13 RK_FUNC_2 &pcfg_pull_up>;
+                               rockchip,pins = <0 RK_PB5 2 &pcfg_pull_up>;
                        };
                        spi2_rx: spi2-rx {
-                               rockchip,pins = <0 10 RK_FUNC_2 &pcfg_pull_up>;
+                               rockchip,pins = <0 RK_PB2 2 &pcfg_pull_up>;
                        };
                        spi2_tx: spi2-tx {
-                               rockchip,pins = <0 11 RK_FUNC_2 &pcfg_pull_up>;
+                               rockchip,pins = <0 RK_PB3 2 &pcfg_pull_up>;
                        };
                };
 
                tsadc {
                        otp_gpio: otp-gpio {
-                               rockchip,pins = <0 3 RK_FUNC_GPIO &pcfg_pull_none>;
+                               rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
                        };
 
                        otp_out: otp-out {
-                               rockchip,pins = <0 3 RK_FUNC_1 &pcfg_pull_none>;
+                               rockchip,pins = <0 RK_PA3 1 &pcfg_pull_none>;
                        };
                };
 
                uart0 {
                        uart0_xfer: uart0-xfer {
-                               rockchip,pins = <2 24 RK_FUNC_1 &pcfg_pull_up>,
-                                               <2 25 RK_FUNC_1 &pcfg_pull_none>;
+                               rockchip,pins = <2 RK_PD0 1 &pcfg_pull_up>,
+                                               <2 RK_PD1 1 &pcfg_pull_none>;
                        };
 
                        uart0_cts: uart0-cts {
-                               rockchip,pins = <2 26 RK_FUNC_1 &pcfg_pull_none>;
+                               rockchip,pins = <2 RK_PD2 1 &pcfg_pull_none>;
                        };
 
                        uart0_rts: uart0-rts {
-                               rockchip,pins = <2 27 RK_FUNC_1 &pcfg_pull_none>;
+                               rockchip,pins = <2 RK_PD3 1 &pcfg_pull_none>;
                        };
                };
 
                uart1 {
                        uart1_xfer: uart1-xfer {
-                               rockchip,pins = <0 20 RK_FUNC_3 &pcfg_pull_up>,
-                                               <0 21 RK_FUNC_3 &pcfg_pull_none>;
+                               rockchip,pins = <0 RK_PC4 3 &pcfg_pull_up>,
+                                               <0 RK_PC5 3 &pcfg_pull_none>;
                        };
 
                        uart1_cts: uart1-cts {
-                               rockchip,pins = <0 22 RK_FUNC_3 &pcfg_pull_none>;
+                               rockchip,pins = <0 RK_PC6 3 &pcfg_pull_none>;
                        };
 
                        uart1_rts: uart1-rts {
-                               rockchip,pins = <0 23 RK_FUNC_3 &pcfg_pull_none>;
+                               rockchip,pins = <0 RK_PC7 3 &pcfg_pull_none>;
                        };
                };
 
                uart2 {
                        uart2_xfer: uart2-xfer {
-                               rockchip,pins = <2 6 RK_FUNC_2 &pcfg_pull_up>,
-                                               <2 5 RK_FUNC_2 &pcfg_pull_none>;
+                               rockchip,pins = <2 RK_PA6 2 &pcfg_pull_up>,
+                                               <2 RK_PA5 2 &pcfg_pull_none>;
                        };
                        /* no rts / cts for uart2 */
                };
 
                uart3 {
                        uart3_xfer: uart3-xfer {
-                               rockchip,pins = <3 29 RK_FUNC_2 &pcfg_pull_up>,
-                                               <3 30 RK_FUNC_3 &pcfg_pull_none>;
+                               rockchip,pins = <3 RK_PD5 2 &pcfg_pull_up>,
+                                               <3 RK_PD6 3 &pcfg_pull_none>;
                        };
 
                        uart3_cts: uart3-cts {
-                               rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_none>;
+                               rockchip,pins = <3 RK_PC0 2 &pcfg_pull_none>;
                        };
 
                        uart3_rts: uart3-rts {
-                               rockchip,pins = <3 17 RK_FUNC_2 &pcfg_pull_none>;
+                               rockchip,pins = <3 RK_PC1 2 &pcfg_pull_none>;
                        };
                };
 
                uart4 {
                        uart4_xfer: uart4-xfer {
-                               rockchip,pins = <0 27 RK_FUNC_3 &pcfg_pull_up>,
-                                               <0 26 RK_FUNC_3 &pcfg_pull_none>;
+                               rockchip,pins = <0 RK_PD3 3 &pcfg_pull_up>,
+                                               <0 RK_PD2 3 &pcfg_pull_none>;
                        };
 
                        uart4_cts: uart4-cts {
-                               rockchip,pins = <0 24 RK_FUNC_3 &pcfg_pull_none>;
+                               rockchip,pins = <0 RK_PD0 3 &pcfg_pull_none>;
                        };
 
                        uart4_rts: uart4-rts {
-                               rockchip,pins = <0 25 RK_FUNC_3 &pcfg_pull_none>;
+                               rockchip,pins = <0 RK_PD1 3 &pcfg_pull_none>;
                        };
                };
        };

diff --git a/arch/arm64/boot/dts/rockchip/rk3399-evb.dts b/arch/arm64/boot/dts/rockchip/rk3399-evb.dts
index 959ddc3..77008dc 100644 (file)
--- a/arch/arm64/boot/dts/rockchip/rk3399-evb.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3399-evb.dts
@@ -208,19 +208,19 @@
        pmic {
                pmic_int_l: pmic-int-l {
                        rockchip,pins =
-                               <1 21 RK_FUNC_GPIO &pcfg_pull_up>;
+                               <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
                };
 
                pmic_dvs2: pmic-dvs2 {
                        rockchip,pins =
-                               <1 18 RK_FUNC_GPIO &pcfg_pull_down>;
+                               <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>;
                };
        };
 
        usb2 {
                vcc5v0_host_en: vcc5v0-host-en {
                        rockchip,pins =
-                               <4 25 RK_FUNC_GPIO &pcfg_pull_none>;
+                               <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>;
                };
        };
 };

diff --git a/arch/arm64/boot/dts/rockchip/rk3399-ficus.dts b/arch/arm64/boot/dts/rockchip/rk3399-ficus.dts
index 027d428..6b059bd 100644 (file)
--- a/arch/arm64/boot/dts/rockchip/rk3399-ficus.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3399-ficus.dts
@@ -95,53 +95,53 @@
        gmac {
                rgmii_sleep_pins: rgmii-sleep-pins {
                        rockchip,pins =
-                               <3 15 RK_FUNC_GPIO &pcfg_output_low>;
+                               <3 RK_PB7 RK_FUNC_GPIO &pcfg_output_low>;
                };
        };
 
        pcie {
                pcie_drv: pcie-drv {
                        rockchip,pins =
-                               <1 24 RK_FUNC_GPIO &pcfg_pull_none>;
+                               <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
                        };
        };
 
        usb2 {
                host_vbus_drv: host-vbus-drv {
                        rockchip,pins =
-                               <4 27 RK_FUNC_GPIO &pcfg_pull_none>;
+                               <4 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
                };
        };
 
        leds {
                user_led1: user_led1 {
                        rockchip,pins =
-                               <4 25 RK_FUNC_GPIO &pcfg_pull_none>;
+                               <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>;
                };
 
                user_led2: user_led2 {
                        rockchip,pins =
-                               <4 26 RK_FUNC_GPIO &pcfg_pull_none>;
+                               <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
                };
 
                user_led3: user_led3 {
                        rockchip,pins =
-                               <4 30 RK_FUNC_GPIO &pcfg_pull_none>;
+                               <4 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
                };
 
                user_led4: user_led4 {
                        rockchip,pins =
-                               <1 0 RK_FUNC_GPIO &pcfg_pull_none>;
+                               <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
                };
 
                wlan_led: wlan_led {
                        rockchip,pins =
-                               <1 1 RK_FUNC_GPIO &pcfg_pull_none>;
+                               <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>;
                };
 
                bt_led: bt_led {
                        rockchip,pins =
-                               <1 4 RK_FUNC_GPIO &pcfg_pull_none>;
+                               <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
                };
        };
 };

diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru-bob.dts b/arch/arm64/boot/dts/rockchip/rk3399-gru-bob.dts
index d1cf404..a9f4d6d 100644 (file)
--- a/arch/arm64/boot/dts/rockchip/rk3399-gru-bob.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3399-gru-bob.dts
@@ -73,7 +73,7 @@
 &pinctrl {
        tpm {
                h1_int_od_l: h1-int-od-l {
-                       rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_up>;
+                       rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;
                };
        };
 };

diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru-chromebook.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-gru-chromebook.dtsi
index 931640e..7cd6d47 100644 (file)
--- a/arch/arm64/boot/dts/rockchip/rk3399-gru-chromebook.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399-gru-chromebook.dtsi
@@ -365,27 +365,27 @@ ap_i2c_tp: &i2c5 {
 &pinctrl {
        discrete-regulators {
                pp1500_en: pp1500-en {
-                       rockchip,pins = <RK_GPIO0 10 RK_FUNC_GPIO
+                       rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO
                                         &pcfg_pull_none>;
                };
 
                pp1800_audio_en: pp1800-audio-en {
-                       rockchip,pins = <RK_GPIO0 2 RK_FUNC_GPIO
+                       rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO
                                         &pcfg_pull_down>;
                };
 
                pp3000_en: pp3000-en {
-                       rockchip,pins = <RK_GPIO0 12 RK_FUNC_GPIO
+                       rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO
                                         &pcfg_pull_none>;
                };
 
                pp3300_disp_en: pp3300-disp-en {
-                       rockchip,pins = <RK_GPIO4 27 RK_FUNC_GPIO
+                       rockchip,pins = <4 RK_PD3 RK_FUNC_GPIO
                                         &pcfg_pull_none>;
                };
 
                wlan_module_pd_l: wlan-module-pd-l {
-                       rockchip,pins = <RK_GPIO0 4 RK_FUNC_GPIO
+                       rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO
                                         &pcfg_pull_down>;
                };
        };
@@ -393,10 +393,10 @@ ap_i2c_tp: &i2c5 {
 
 &wifi {
        wifi_perst_l: wifi-perst-l {
-               rockchip,pins = <2 27 RK_FUNC_GPIO &pcfg_pull_none>;
+               rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
        };
 
        wlan_host_wake_l: wlan-host-wake-l {
-               rockchip,pins = <0 8 RK_FUNC_GPIO &pcfg_pull_none>;
+               rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
        };
 };

diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru-kevin.dts b/arch/arm64/boot/dts/rockchip/rk3399-gru-kevin.dts
index 15e254a..3e2272b 100644 (file)
--- a/arch/arm64/boot/dts/rockchip/rk3399-gru-kevin.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3399-gru-kevin.dts
@@ -290,24 +290,24 @@ ap_i2c_dig: &i2c2 {
        digitizer {
                /* Has external pullup */
                cpu1_dig_irq_l: cpu1-dig-irq-l {
-                       rockchip,pins = <2 4 RK_FUNC_GPIO &pcfg_pull_none>;
+                       rockchip,pins = <2 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
                };
 
                /* Has external pullup */
                cpu1_dig_pdct_l: cpu1-dig-pdct-l {
-                       rockchip,pins = <2 5 RK_FUNC_GPIO &pcfg_pull_none>;
+                       rockchip,pins = <2 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
                };
        };
 
        discrete-regulators {
                cpu3_pen_pwr_en: cpu3-pen-pwr-en {
-                       rockchip,pins = <4 30 RK_FUNC_GPIO &pcfg_pull_none>;
+                       rockchip,pins = <4 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
                };
        };
 
        pen {
                cpu1_pen_eject: cpu1-pen-eject {
-                       rockchip,pins = <0 13 RK_FUNC_GPIO &pcfg_pull_up>;
+                       rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>;
                };
        };
 };

diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet.dtsi
index 62ea7d6..50dfab5 100644 (file)
--- a/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet.dtsi
@@ -455,58 +455,58 @@ camera: &i2c7 {
 
 /* PINCTRL OVERRIDES */
 &ec_ap_int_l {
-       rockchip,pins = <1 18 RK_FUNC_GPIO &pcfg_pull_up>;
+       rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up>;
 };
 
 &ap_fw_wp {
-       rockchip,pins = <0 13 RK_FUNC_GPIO &pcfg_pull_none>;
+       rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
 };
 
 &bl_en {
-       rockchip,pins = <4 21 RK_FUNC_GPIO &pcfg_pull_none>;
+       rockchip,pins = <4 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
 };
 
 &bt_host_wake_l {
-       rockchip,pins = <1 2 RK_FUNC_GPIO &pcfg_pull_none>;
+       rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
 };
 
 &ec_ap_int_l {
-       rockchip,pins = <1 18 RK_FUNC_GPIO &pcfg_pull_up>;
+       rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up>;
 };
 
 &headset_int_l {
-       rockchip,pins = <1 23 RK_FUNC_GPIO &pcfg_pull_up>;
+       rockchip,pins = <1 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>;
 };
 
 &i2s0_8ch_bus {
        rockchip,pins =
-               <3 24 RK_FUNC_1 &pcfg_pull_none_6ma>,
-               <3 25 RK_FUNC_1 &pcfg_pull_none_6ma>,
-               <3 26 RK_FUNC_1 &pcfg_pull_none_6ma>,
-               <3 27 RK_FUNC_1 &pcfg_pull_none_6ma>,
-               <3 31 RK_FUNC_1 &pcfg_pull_none_6ma>,
-               <4 0 RK_FUNC_1 &pcfg_pull_none_6ma>;
+               <3 RK_PD0 1 &pcfg_pull_none_6ma>,
+               <3 RK_PD1 1 &pcfg_pull_none_6ma>,
+               <3 RK_PD2 1 &pcfg_pull_none_6ma>,
+               <3 RK_PD3 1 &pcfg_pull_none_6ma>,
+               <3 RK_PD7 1 &pcfg_pull_none_6ma>,
+               <4 RK_PA0 1 &pcfg_pull_none_6ma>;
 };
 
 /* there is no external pull up, so need to set this pin pull up */
 &sdmmc_cd_gpio {
-       rockchip,pins = <1 11 RK_FUNC_GPIO &pcfg_pull_up>;
+       rockchip,pins = <1 RK_PB3 RK_FUNC_GPIO &pcfg_pull_up>;
 };
 
 &sd_pwr_1800_sel {
-       rockchip,pins = <2 28 RK_FUNC_GPIO &pcfg_pull_up>;
+       rockchip,pins = <2 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>;
 };
 
 &sdmode_en {
-       rockchip,pins = <0 2 RK_FUNC_GPIO &pcfg_pull_down>;
+       rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_down>;
 };
 
 &touch_reset_l {
-       rockchip,pins = <0 10 RK_FUNC_GPIO &pcfg_pull_down>;
+       rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_down>;
 };
 
 &touch_int_l {
-       rockchip,pins = <1 4 RK_FUNC_GPIO &pcfg_pull_down>;
+       rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_down>;
 };
 
 &pinctrl {
@@ -523,84 +523,84 @@ camera: &i2c7 {
 
        camera {
                pp1250_cam_en: pp1250-dvdd {
-                       rockchip,pins = <2 4 RK_FUNC_GPIO &pcfg_pull_none>;
+                       rockchip,pins = <2 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
                };
 
                pp2800_cam_en: pp2800-avdd {
-                       rockchip,pins = <2 24 RK_FUNC_GPIO &pcfg_pull_none>;
+                       rockchip,pins = <2 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
                };
 
                ucam_rst: ucam_rst {
-                       rockchip,pins = <2 3 RK_FUNC_GPIO &pcfg_pull_none>;
+                       rockchip,pins = <2 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
                };
 
                wcam_rst: wcam_rst {
-                       rockchip,pins = <2 5 RK_FUNC_GPIO &pcfg_pull_none>;
+                       rockchip,pins = <2 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
                };
        };
 
        digitizer {
                pen_int_odl: pen-int-odl {
-                       rockchip,pins = <1 0 RK_FUNC_GPIO &pcfg_pull_up>;
+                       rockchip,pins = <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>;
                };
 
                pen_reset_l: pen-reset-l {
-                       rockchip,pins = <0 12 RK_FUNC_GPIO &pcfg_pull_none>;
+                       rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>;
                };
        };
 
        discrete-regulators {
                display_rst_l: display-rst-l {
-                       rockchip,pins = <4 25 RK_FUNC_GPIO &pcfg_pull_down>;
+                       rockchip,pins = <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_down>;
                };
 
                ppvarp_lcd_en: ppvarp-lcd-en {
-                       rockchip,pins = <4 27 RK_FUNC_GPIO &pcfg_pull_none>;
+                       rockchip,pins = <4 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
                };
 
                ppvarn_lcd_en: ppvarn-lcd-en {
-                       rockchip,pins = <4 28 RK_FUNC_GPIO &pcfg_pull_none>;
+                       rockchip,pins = <4 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
                };
        };
 
        dmic {
                dmic_en: dmic-en {
-                       rockchip,pins = <4 3 RK_FUNC_GPIO &pcfg_pull_none>;
+                       rockchip,pins = <4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
                };
        };
 
        pen {
                pen_eject_odl: pen-eject-odl {
-                       rockchip,pins = <1 1 RK_FUNC_GPIO &pcfg_pull_up>;
+                       rockchip,pins = <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>;
                };
        };
 
        tpm {
                h1_int_od_l: h1-int-od-l {
-                       rockchip,pins = <1 17 RK_FUNC_GPIO &pcfg_pull_up>;
+                       rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up>;
                };
        };
 };
 
 &wifi {
        bt_en_1v8_l: bt-en-1v8-l {
-               rockchip,pins = <0 8 RK_FUNC_GPIO &pcfg_pull_none>;
+               rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
        };
 
        wlan_pd_1v8_l: wlan-pd-1v8-l {
-               rockchip,pins = <0 4 RK_FUNC_GPIO &pcfg_pull_none>;
+               rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
        };
 
        /* Default pull-up, but just to be clear */
        wlan_rf_kill_1v8_l: wlan-rf-kill-1v8-l {
-               rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_up>;
+               rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;
        };
 
        wifi_perst_l: wifi-perst-l {
-               rockchip,pins = <0 3 RK_FUNC_GPIO &pcfg_pull_none>;
+               rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
        };
 
        wlan_host_wake_l: wlan-host-wake-l {
-               rockchip,pins = <1 3 RK_FUNC_GPIO &pcfg_pull_up>;
+               rockchip,pins = <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
        };
 };

diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi
index da03fa9..dd56249 100644 (file)
--- a/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi
@@ -676,29 +676,29 @@ ap_i2c_audio: &i2c8 {
 
        backlight-enable {
                bl_en: bl-en {
-                       rockchip,pins = <1 17 RK_FUNC_GPIO &pcfg_pull_none>;
+                       rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
                };
        };
 
        cros-ec {
                ec_ap_int_l: ec-ap-int-l {
-                       rockchip,pins = <RK_GPIO0 1 RK_FUNC_GPIO &pcfg_pull_up>;
+                       rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>;
                };
        };
 
        discrete-regulators {
                sd_io_pwr_en: sd-io-pwr-en {
-                       rockchip,pins = <RK_GPIO2 2 RK_FUNC_GPIO
+                       rockchip,pins = <2 RK_PA2 RK_FUNC_GPIO
                                         &pcfg_pull_none>;
                };
 
                sd_pwr_1800_sel: sd-pwr-1800-sel {
-                       rockchip,pins = <RK_GPIO2 28 RK_FUNC_GPIO
+                       rockchip,pins = <2 RK_PD4 RK_FUNC_GPIO
                                         &pcfg_pull_none>;
                };
 
                sd_slot_pwr_en: sd-slot-pwr-en {
-                       rockchip,pins = <RK_GPIO4 29 RK_FUNC_GPIO
+                       rockchip,pins = <4 RK_PD5 RK_FUNC_GPIO
                                         &pcfg_pull_none>;
                };
        };
@@ -706,17 +706,17 @@ ap_i2c_audio: &i2c8 {
        codec {
                /* Has external pullup */
                headset_int_l: headset-int-l {
-                       rockchip,pins = <1 23 RK_FUNC_GPIO &pcfg_pull_none>;
+                       rockchip,pins = <1 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>;
                };
 
                mic_int: mic-int {
-                       rockchip,pins = <1 13 RK_FUNC_GPIO &pcfg_pull_down>;
+                       rockchip,pins = <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_down>;
                };
        };
 
        max98357a {
                sdmode_en: sdmode-en {
-                       rockchip,pins = <1 2 RK_FUNC_GPIO &pcfg_pull_down>;
+                       rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_down>;
                };
        };
 
@@ -727,7 +727,7 @@ ap_i2c_audio: &i2c8 {
                         * to hack this as gpio, so the EP could be able to
                         * de-assert it along and make ClockPM(CPM) work.
                         */
-                       rockchip,pins = <2 26 RK_FUNC_GPIO &pcfg_pull_none>;
+                       rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
                };
        };
 
@@ -738,20 +738,20 @@ ap_i2c_audio: &i2c8 {
                 */
                sdmmc_bus4: sdmmc-bus4 {
                        rockchip,pins =
-                               <4 8 RK_FUNC_1 &pcfg_pull_none_8ma>,
-                               <4 9 RK_FUNC_1 &pcfg_pull_none_8ma>,
-                               <4 10 RK_FUNC_1 &pcfg_pull_none_8ma>,
-                               <4 11 RK_FUNC_1 &pcfg_pull_none_8ma>;
+                               <4 RK_PB0 1 &pcfg_pull_none_8ma>,
+                               <4 RK_PB1 1 &pcfg_pull_none_8ma>,
+                               <4 RK_PB2 1 &pcfg_pull_none_8ma>,
+                               <4 RK_PB3 1 &pcfg_pull_none_8ma>;
                };
 
                sdmmc_clk: sdmmc-clk {
                        rockchip,pins =
-                               <4 12 RK_FUNC_1 &pcfg_pull_none_8ma>;
+                               <4 RK_PB4 1 &pcfg_pull_none_8ma>;
                };
 
                sdmmc_cmd: sdmmc-cmd {
                        rockchip,pins =
-                               <4 13 RK_FUNC_1 &pcfg_pull_none_8ma>;
+                               <4 RK_PB5 1 &pcfg_pull_none_8ma>;
                };
 
                /*
@@ -765,12 +765,12 @@ ap_i2c_audio: &i2c8 {
                 */
                sdmmc_cd: sdmmc-cd {
                        rockchip,pins =
-                               <0 7 RK_FUNC_1 &pcfg_pull_none>;
+                               <0 RK_PA7 1 &pcfg_pull_none>;
                };
 
                /* This is where we actually hook up CD; has external pull */
                sdmmc_cd_gpio: sdmmc-cd-gpio {
-                       rockchip,pins = <4 24 RK_FUNC_GPIO &pcfg_pull_none>;
+                       rockchip,pins = <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
                };
        };
 
@@ -780,47 +780,47 @@ ap_i2c_audio: &i2c8 {
                         * Pull down SPI1 CLK/CS/RX/TX during suspend, to
                         * prevent leakage.
                         */
-                       rockchip,pins = <1 9 RK_FUNC_GPIO &pcfg_pull_down>,
-                                       <1 10 RK_FUNC_GPIO &pcfg_pull_down>,
-                                       <1 7 RK_FUNC_GPIO &pcfg_pull_down>,
-                                       <1 8 RK_FUNC_GPIO &pcfg_pull_down>;
+                       rockchip,pins = <1 RK_PB1 RK_FUNC_GPIO &pcfg_pull_down>,
+                                       <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_down>,
+                                       <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_down>,
+                                       <1 RK_PB0 RK_FUNC_GPIO &pcfg_pull_down>;
                };
        };
 
        touchscreen {
                touch_int_l: touch-int-l {
-                       rockchip,pins = <3 13 RK_FUNC_GPIO &pcfg_pull_up>;
+                       rockchip,pins = <3 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>;
                };
 
                touch_reset_l: touch-reset-l {
-                       rockchip,pins = <4 26 RK_FUNC_GPIO &pcfg_pull_none>;
+                       rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
                };
        };
 
        trackpad {
                ap_i2c_tp_pu_en: ap-i2c-tp-pu-en {
-                       rockchip,pins = <3 12 RK_FUNC_GPIO &pcfg_output_high>;
+                       rockchip,pins = <3 RK_PB4 RK_FUNC_GPIO &pcfg_output_high>;
                };
 
                trackpad_int_l: trackpad-int-l {
-                       rockchip,pins = <1 4 RK_FUNC_GPIO &pcfg_pull_up>;
+                       rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>;
                };
        };
 
        wifi: wifi {
                wlan_module_reset_l: wlan-module-reset-l {
-                       rockchip,pins = <1 11 RK_FUNC_GPIO &pcfg_pull_none>;
+                       rockchip,pins = <1 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
                };
 
                bt_host_wake_l: bt-host-wake-l {
                        /* Kevin has an external pull up, but Gru does not */
-                       rockchip,pins = <0 3 RK_FUNC_GPIO &pcfg_pull_up>;
+                       rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
                };
        };
 
        write-protect {
                ap_fw_wp: ap-fw-wp {
-                       rockchip,pins = <1 18 RK_FUNC_GPIO &pcfg_pull_up>;
+                       rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up>;
                };
        };
 };

diff --git a/arch/arm64/boot/dts/rockchip/rk3399-nanopc-t4.dts b/arch/arm64/boot/dts/rockchip/rk3399-nanopc-t4.dts
index 84433cf..2a12798 100644 (file)
--- a/arch/arm64/boot/dts/rockchip/rk3399-nanopc-t4.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopc-t4.dts
@@ -52,13 +52,80 @@
                pinctrl-names = "default";
                pinctrl-0 = <&ir_rx>;
        };
+
+       fan: pwm-fan {
+               compatible = "pwm-fan";
+               /*
+                * With 20KHz PWM and an EVERCOOL EC4007H12SA fan, these levels
+                * work out to 0, ~1200, ~3000, and 5000RPM respectively.
+                */
+               cooling-levels = <0 12 18 255>;
+               #cooling-cells = <2>;
+               fan-supply = <&vcc12v0_sys>;
+               pwms = <&pwm1 0 50000 0>;
+       };
+};
+
+&cpu_thermal {
+       trips {
+               cpu_warm: cpu_warm {
+                       temperature = <55000>;
+                       hysteresis = <2000>;
+                       type = "active";
+               };
+
+               cpu_hot: cpu_hot {
+                       temperature = <65000>;
+                       hysteresis = <2000>;
+                       type = "active";
+               };
+       };
+
+       cooling-maps {
+               map2 {
+                       trip = <&cpu_warm>;
+                       cooling-device = <&fan THERMAL_NO_LIMIT 1>;
+               };
+
+               map3 {
+                       trip = <&cpu_hot>;
+                       cooling-device = <&fan 2 THERMAL_NO_LIMIT>;
+               };
+       };
+};
+
+&gpu_thermal {
+       trips {
+               gpu_warm: gpu_warm {
+                       temperature = <55000>;
+                       hysteresis = <2000>;
+                       type = "active";
+               };
+
+               gpu_hot: gpu_hot {
+                       temperature = <65000>;
+                       hysteresis = <2000>;
+                       type = "active";
+               };
+       };
+       cooling-maps {
+               map1 {
+                       trip = <&gpu_warm>;
+                       cooling-device = <&fan THERMAL_NO_LIMIT 1>;
+               };
+
+               map2 {
+                       trip = <&gpu_hot>;
+                       cooling-device = <&fan 2 THERMAL_NO_LIMIT>;
+               };
+       };
 };
 
 &pinctrl {
        ir {
                ir_rx: ir-rx {
                        /* external pullup to VCC3V3_SYS, despite being 1.8V :/ */
-                       rockchip,pins = <0 RK_PA6 RK_FUNC_1 &pcfg_pull_none>;
+                       rockchip,pins = <0 RK_PA6 1 &pcfg_pull_none>;
                };
        };
 };

diff --git a/arch/arm64/boot/dts/rockchip/rk3399-nanopi-neo4.dts b/arch/arm64/boot/dts/rockchip/rk3399-nanopi-neo4.dts
new file mode 100644 (file)
index 0000000..195410b
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi-neo4.dts
@@ -0,0 +1,50 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2019 Amarula Solutions B.V.
+ * Author: Jagan Teki <jagan@amarulasolutions.com>
+ */
+
+/dts-v1/;
+
+#include "rk3399-nanopi4.dtsi"
+
+/ {
+       model = "FriendlyARM NanoPi NEO4";
+       compatible = "friendlyarm,nanopi-neo4", "rockchip,rk3399";
+
+       vdd_5v: vdd-5v {
+               compatible = "regulator-fixed";
+               regulator-name = "vdd_5v";
+               regulator-always-on;
+               regulator-boot-on;
+       };
+
+       vcc5v0_core: vcc5v0-core {
+               compatible = "regulator-fixed";
+               regulator-name = "vcc5v0_core";
+               regulator-always-on;
+               regulator-boot-on;
+               vin-supply = <&vdd_5v>;
+       };
+
+       vcc5v0_usb1: vcc5v0-usb1 {
+               compatible = "regulator-fixed";
+               regulator-name = "vcc5v0_usb1";
+               regulator-always-on;
+               regulator-boot-on;
+               vin-supply = <&vcc5v0_sys>;
+       };
+};
+
+&vcc3v3_sys {
+       vin-supply = <&vcc5v0_core>;
+};
+
+&u2phy0_host {
+       phy-supply = <&vcc5v0_usb1>;
+};
+
+&vbus_typec {
+       regulator-always-on;
+       vin-supply = <&vdd_5v>;
+};

diff --git a/arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi
index d325e11..dd16c80 100644 (file)
--- a/arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi
@@ -148,15 +148,28 @@
        assigned-clocks = <&cru SCLK_RMII_SRC>;
        clock_in_out = "input";
        pinctrl-names = "default";
-       pinctrl-0 = <&rgmii_pins>;
+       pinctrl-0 = <&rgmii_pins>, <&phy_intb>, <&phy_rstb>;
+       phy-handle = <&rtl8211e>;
        phy-mode = "rgmii";
        phy-supply = <&vcc3v3_s3>;
        snps,reset-active-low;
-       snps,reset-delays-us = <0 10000 50000>;
+       snps,reset-delays-us = <0 10000 30000>;
        snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
        tx_delay = <0x28>;
        rx_delay = <0x11>;
        status = "okay";
+
+       mdio {
+               compatible = "snps,dwmac-mdio";
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               rtl8211e: phy@1 {
+                       reg = <1>;
+                       interrupt-parent = <&gpio3>;
+                       interrupts = <RK_PB2 IRQ_TYPE_LEVEL_LOW>;
+               };
+       };
 };
 
 &gpu {
@@ -481,6 +494,16 @@
                };
        };
 
+       phy {
+               phy_intb: phy-intb {
+                       rockchip,pins = <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>;
+               };
+
+               phy_rstb: phy-rstb {
+                       rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
+               };
+       };
+
        pmic {
                cpu_b_sleep: cpu-b-sleep {
                        rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>;

diff --git a/arch/arm64/boot/dts/rockchip/rk3399-orangepi.dts b/arch/arm64/boot/dts/rockchip/rk3399-orangepi.dts
new file mode 100644 (file)
index 0000000..0541dfc
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3399-orangepi.dts
@@ -0,0 +1,790 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd.
+ */
+
+/dts-v1/;
+
+#include "dt-bindings/pwm/pwm.h"
+#include "dt-bindings/input/input.h"
+#include "rk3399.dtsi"
+#include "rk3399-opp.dtsi"
+
+/ {
+       model = "Orange Pi RK3399 Board";
+       compatible = "rockchip,rk3399-orangepi", "rockchip,rk3399";
+
+       chosen {
+               stdout-path = "serial2:1500000n8";
+       };
+
+       clkin_gmac: external-gmac-clock {
+               compatible = "fixed-clock";
+               clock-frequency = <125000000>;
+               clock-output-names = "clkin_gmac";
+               #clock-cells = <0>;
+       };
+
+       adc-keys {
+               compatible = "adc-keys";
+               io-channels = <&saradc 1>;
+               io-channel-names = "buttons";
+               keyup-threshold-microvolt = <1800000>;
+               poll-interval = <100>;
+
+               button-up {
+                       label = "Volume Up";
+                       linux,code = <KEY_VOLUMEUP>;
+                       press-threshold-microvolt = <100000>;
+               };
+
+               button-down {
+                       label = "Volume Down";
+                       linux,code = <KEY_VOLUMEDOWN>;
+                       press-threshold-microvolt = <300000>;
+               };
+
+               back {
+                       label = "Back";
+                       linux,code = <KEY_BACK>;
+                       press-threshold-microvolt = <985000>;
+               };
+
+               menu {
+                       label = "Menu";
+                       linux,code = <KEY_MENU>;
+                       press-threshold-microvolt = <1314000>;
+               };
+       };
+
+       dc_12v: dc-12v {
+               compatible = "regulator-fixed";
+               regulator-name = "dc_12v";
+               regulator-always-on;
+               regulator-boot-on;
+               regulator-min-microvolt = <12000000>;
+               regulator-max-microvolt = <12000000>;
+       };
+
+       keys: gpio-keys {
+               compatible = "gpio-keys";
+               autorepeat;
+
+               power {
+                       debounce-interval = <100>;
+                       gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
+                       label = "GPIO Power";
+                       linux,code = <KEY_POWER>;
+                       linux,input-type = <1>;
+                       pinctrl-names = "default";
+                       pinctrl-0 = <&pwr_btn>;
+                       wakeup-source;
+               };
+       };
+
+       sdio_pwrseq: sdio-pwrseq {
+               compatible = "mmc-pwrseq-simple";
+               clocks = <&rk808 1>;
+               clock-names = "ext_clock";
+               pinctrl-names = "default";
+               pinctrl-0 = <&wifi_reg_on_h>;
+               reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>;
+       };
+
+       /* switched by pmic_sleep */
+       vcc1v8_s3: vcca1v8_s3: vcc1v8-s3 {
+               compatible = "regulator-fixed";
+               regulator-name = "vcc1v8_s3";
+               regulator-always-on;
+               regulator-boot-on;
+               regulator-min-microvolt = <1800000>;
+               regulator-max-microvolt = <1800000>;
+               vin-supply = <&vcc_1v8>;
+       };
+
+       vcc3v0_sd: vcc3v0-sd {
+               compatible = "regulator-fixed";
+               enable-active-high;
+               gpio = <&gpio0 RK_PA1 GPIO_ACTIVE_HIGH>;
+               pinctrl-names = "default";
+               pinctrl-0 = <&sdmmc0_pwr_h>;
+               regulator-boot-on;
+               regulator-max-microvolt = <3000000>;
+               regulator-min-microvolt = <3000000>;
+               regulator-name = "vcc3v0_sd";
+               vin-supply = <&vcc3v3_sys>;
+       };
+
+       vcc3v3_sys: vcc3v3-sys {
+               compatible = "regulator-fixed";
+               regulator-name = "vcc3v3_sys";
+               regulator-always-on;
+               regulator-boot-on;
+               regulator-min-microvolt = <3300000>;
+               regulator-max-microvolt = <3300000>;
+               vin-supply = <&vcc_sys>;
+       };
+
+       vcc5v0_host: vcc5v0-host-regulator {
+               compatible = "regulator-fixed";
+               enable-active-high;
+               gpio = <&gpio4 RK_PD1 GPIO_ACTIVE_HIGH>;
+               pinctrl-names = "default";
+               pinctrl-0 = <&vcc5v0_host_en>;
+               regulator-name = "vcc5v0_host";
+               regulator-always-on;
+               vin-supply = <&vcc_sys>;
+       };
+
+       vbus_typec: vbus-typec-regulator {
+               compatible = "regulator-fixed";
+               enable-active-high;
+               gpio = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>;
+               pinctrl-names = "default";
+               pinctrl-0 = <&vcc5v0_typec_en>;
+               regulator-name = "vbus_typec";
+               vin-supply = <&vcc_sys>;
+       };
+
+       vcc_sys: vcc-sys {
+               compatible = "regulator-fixed";
+               regulator-name = "vcc_sys";
+               regulator-always-on;
+               regulator-boot-on;
+               regulator-min-microvolt = <5000000>;
+               regulator-max-microvolt = <5000000>;
+               vin-supply = <&dc_12v>;
+       };
+
+       vdd_log: vdd-log {
+               compatible = "pwm-regulator";
+               pwms = <&pwm2 0 25000 1>;
+               regulator-name = "vdd_log";
+               regulator-always-on;
+               regulator-boot-on;
+               regulator-min-microvolt = <800000>;
+               regulator-max-microvolt = <1400000>;
+               vin-supply = <&vcc_sys>;
+       };
+};
+
+&cpu_l0 {
+       cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l1 {
+       cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l2 {
+       cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l3 {
+       cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_b0 {
+       cpu-supply = <&vdd_cpu_b>;
+};
+
+&cpu_b1 {
+       cpu-supply = <&vdd_cpu_b>;
+};
+
+&emmc_phy {
+       status = "okay";
+};
+
+&gmac {
+       assigned-clocks = <&cru SCLK_RMII_SRC>;
+       assigned-clock-parents = <&clkin_gmac>;
+       clock_in_out = "input";
+       phy-supply = <&vcc3v3_s3>;
+       phy-mode = "rgmii";
+       pinctrl-names = "default";
+       pinctrl-0 = <&rgmii_pins>;
+       snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
+       snps,reset-active-low;
+       snps,reset-delays-us = <0 10000 50000>;
+       tx_delay = <0x28>;
+       rx_delay = <0x11>;
+       status = "okay";
+};
+
+&gpu {
+       mali-supply = <&vdd_gpu>;
+       status = "okay";
+};
+
+&hdmi {
+       ddc-i2c-bus = <&i2c3>;
+       status = "okay";
+};
+
+&hdmi_sound {
+       status = "okay";
+};
+
+&i2c0 {
+       clock-frequency = <400000>;
+       i2c-scl-rising-time-ns = <168>;
+       i2c-scl-falling-time-ns = <4>;
+       status = "okay";
+
+       rk808: pmic@1b {
+               compatible = "rockchip,rk808";
+               reg = <0x1b>;
+               interrupt-parent = <&gpio1>;
+               interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
+               #clock-cells = <1>;
+               clock-output-names = "rtc_clko_soc", "rtc_clko_wifi";
+               pinctrl-names = "default";
+               pinctrl-0 = <&pmic_int_l>;
+               rockchip,system-power-controller;
+               wakeup-source;
+
+               vcc1-supply = <&vcc3v3_sys>;
+               vcc2-supply = <&vcc3v3_sys>;
+               vcc3-supply = <&vcc3v3_sys>;
+               vcc4-supply = <&vcc3v3_sys>;
+               vcc6-supply = <&vcc3v3_sys>;
+               vcc7-supply = <&vcc3v3_sys>;
+               vcc8-supply = <&vcc3v3_sys>;
+               vcc9-supply = <&vcc3v3_sys>;
+               vcc10-supply = <&vcc3v3_sys>;
+               vcc11-supply = <&vcc3v3_sys>;
+               vcc12-supply = <&vcc3v3_sys>;
+               vddio-supply = <&vcc_3v0>;
+
+               regulators {
+                       vdd_center: DCDC_REG1 {
+                               regulator-name = "vdd_center";
+                               regulator-always-on;
+                               regulator-boot-on;
+                               regulator-min-microvolt = <700000>;
+                               regulator-max-microvolt = <1500000>;
+                               regulator-ramp-delay = <6001>;
+                               regulator-state-mem {
+                                       regulator-off-in-suspend;
+                               };
+                       };
+
+                       vdd_cpu_l: DCDC_REG2 {
+                               regulator-name = "vdd_cpu_l";
+                               regulator-always-on;
+                               regulator-boot-on;
+                               regulator-min-microvolt = <700000>;
+                               regulator-max-microvolt = <1500000>;
+                               regulator-ramp-delay = <6001>;
+                               regulator-state-mem {
+                                       regulator-off-in-suspend;
+                               };
+                       };
+
+                       vcc_ddr: DCDC_REG3 {
+                               regulator-name = "vcc_ddr";
+                               regulator-always-on;
+                               regulator-boot-on;
+                               regulator-state-mem {
+                                       regulator-on-in-suspend;
+                               };
+                       };
+
+                       vcc_1v8: DCDC_REG4 {
+                               regulator-name = "vcc_1v8";
+                               regulator-always-on;
+                               regulator-boot-on;
+                               regulator-min-microvolt = <1800000>;
+                               regulator-max-microvolt = <3300000>;
+                               regulator-state-mem {
+                                       regulator-on-in-suspend;
+                                       regulator-suspend-microvolt = <1800000>;
+                               };
+                       };
+
+                       vcc1v8_dvp: LDO_REG1 {
+                               regulator-name = "vcc1v8_dvp";
+                               regulator-always-on;
+                               regulator-boot-on;
+                               regulator-min-microvolt = <1800000>;
+                               regulator-max-microvolt = <3400000>;
+                               regulator-state-mem {
+                                       regulator-off-in-suspend;
+                               };
+                       };
+
+                       vcc3v0_tp: LDO_REG2 {
+                               regulator-name = "vcc3v0_tp";
+                               regulator-always-on;
+                               regulator-boot-on;
+                               regulator-min-microvolt = <1800000>;
+                               regulator-max-microvolt = <3400000>;
+                               regulator-state-mem {
+                                       regulator-off-in-suspend;
+                               };
+                       };
+
+                       vcc1v8_pmupll: LDO_REG3 {
+                               regulator-name = "vcc1v8_pmupll";
+                               regulator-always-on;
+                               regulator-boot-on;
+                               regulator-min-microvolt = <800000>;
+                               regulator-max-microvolt = <2500000>;
+                               regulator-state-mem {
+                                       regulator-on-in-suspend;
+                                       regulator-suspend-microvolt = <1800000>;
+                               };
+                       };
+
+                       vcc_sdio: LDO_REG4 {
+                               regulator-name = "vcc_sdio";
+                               regulator-always-on;
+                               regulator-boot-on;
+                               regulator-min-microvolt = <1800000>;
+                               regulator-max-microvolt = <3400000>;
+                               regulator-state-mem {
+                                       regulator-on-in-suspend;
+                                       regulator-suspend-microvolt = <3000000>;
+                               };
+                       };
+
+                       vcca3v0_codec: LDO_REG5 {
+                               regulator-name = "vcca3v0_codec";
+                               regulator-always-on;
+                               regulator-boot-on;
+                               regulator-min-microvolt = <1800000>;
+                               regulator-max-microvolt = <3400000>;
+                               regulator-state-mem {
+                                       regulator-off-in-suspend;
+                               };
+                       };
+
+                       vcc_1v5: LDO_REG6 {
+                               regulator-name = "vcc_1v5";
+                               regulator-always-on;
+                               regulator-boot-on;
+                               regulator-min-microvolt = <800000>;
+                               regulator-max-microvolt = <2500000>;
+                               regulator-state-mem {
+                                       regulator-on-in-suspend;
+                                       regulator-suspend-microvolt = <1500000>;
+                               };
+                       };
+
+                       vcca1v8_codec: LDO_REG7 {
+                               regulator-name = "vcca1v8_codec";
+                               regulator-always-on;
+                               regulator-boot-on;
+                               regulator-min-microvolt = <800000>;
+                               regulator-max-microvolt = <2500000>;
+                               regulator-state-mem {
+                                       regulator-off-in-suspend;
+                               };
+                       };
+
+                       vcc_3v0: LDO_REG8 {
+                               regulator-name = "vcc_3v0";
+                               regulator-always-on;
+                               regulator-boot-on;
+                               regulator-min-microvolt = <1800000>;
+                               regulator-max-microvolt = <3400000>;
+                               regulator-state-mem {
+                                       regulator-on-in-suspend;
+                                       regulator-suspend-microvolt = <3000000>;
+                               };
+                       };
+
+                       vcc3v3_s3: SWITCH_REG1 {
+                               regulator-name = "vcc3v3_s3";
+                               regulator-always-on;
+                               regulator-boot-on;
+                               regulator-state-mem {
+                                       regulator-off-in-suspend;
+                               };
+                       };
+
+                       vcc3v3_s0: SWITCH_REG2 {
+                               regulator-name = "vcc3v3_s0";
+                               regulator-always-on;
+                               regulator-boot-on;
+                               regulator-state-mem {
+                                       regulator-off-in-suspend;
+                               };
+                       };
+               };
+       };
+
+       vdd_cpu_b: regulator@40 {
+               compatible = "silergy,syr827";
+               reg = <0x40>;
+               fcs,suspend-voltage-selector = <1>;
+               regulator-name = "vdd_cpu_b";
+               regulator-min-microvolt = <712500>;
+               regulator-max-microvolt = <1500000>;
+               regulator-ramp-delay = <1000>;
+               regulator-always-on;
+               regulator-boot-on;
+               vin-supply = <&vcc3v3_sys>;
+
+               regulator-state-mem {
+                       regulator-off-in-suspend;
+               };
+       };
+
+       vdd_gpu: regulator@41 {
+               compatible = "silergy,syr828";
+               reg = <0x41>;
+               fcs,suspend-voltage-selector = <1>;
+               regulator-name = "vdd_gpu";
+               regulator-min-microvolt = <712500>;
+               regulator-max-microvolt = <1500000>;
+               regulator-ramp-delay = <1000>;
+               regulator-always-on;
+               regulator-boot-on;
+               vin-supply = <&vcc3v3_sys>;
+
+               regulator-state-mem {
+                       regulator-off-in-suspend;
+               };
+       };
+};
+
+&i2c1 {
+       i2c-scl-rising-time-ns = <450>;
+       i2c-scl-falling-time-ns = <15>;
+       status = "okay";
+};
+
+&i2c3 {
+       i2c-scl-rising-time-ns = <450>;
+       i2c-scl-falling-time-ns = <15>;
+       status = "okay";
+};
+
+&i2c4 {
+       clock-frequency = <400000>;
+       i2c-scl-rising-time-ns = <450>;
+       i2c-scl-falling-time-ns = <15>;
+       status = "okay";
+
+       ak09911@c {
+               compatible = "asahi-kasei,ak09911";
+               reg = <0x0c>;
+               vdd-supply = <&vcc3v3_s3>;
+               vid-supply = <&vcc3v3_s3>;
+       };
+
+       mpu6500@68 {
+               compatible = "invensense,mpu6500";
+               reg = <0x68>;
+               interrupt-parent = <&gpio1>;
+               interrupts = <RK_PC6 IRQ_TYPE_EDGE_RISING>;
+               pinctrl-names = "default";
+               pinctrl-0 = <&gsensor_int_l>;
+               vddio-supply = <&vcc3v3_s3>;
+       };
+
+       lsm6ds3@6a {
+               compatible = "st,lsm6ds3";
+               reg = <0x6a>;
+               interrupt-parent = <&gpio1>;
+               interrupts = <RK_PD0 IRQ_TYPE_EDGE_RISING>;
+               pinctrl-names = "default";
+               pinctrl-0 = <&gyr_int_l>;
+               vdd-supply = <&vcc3v3_s3>;
+               vddio-supply = <&vcc3v3_s3>;
+       };
+
+       cm32181@10 {
+               compatible = "capella,cm32181";
+               reg = <0x10>;
+               interrupt-parent = <&gpio4>;
+               interrupts = <RK_PD0 IRQ_TYPE_EDGE_RISING>;
+               pinctrl-names = "default";
+               pinctrl-0 = <&light_int_l>;
+               vdd-supply = <&vcc3v3_s3>;
+       };
+
+       fusb302@22 {
+               compatible = "fcs,fusb302";
+               reg = <0x22>;
+               interrupt-parent = <&gpio1>;
+               interrupts = <RK_PA2 IRQ_TYPE_LEVEL_LOW>;
+               pinctrl-names = "default";
+               pinctrl-0 = <&chg_cc_int_l>;
+               vbus-supply = <&vbus_typec>;
+       };
+};
+
+&io_domains {
+       status = "okay";
+       bt656-supply = <&vcc_3v0>;
+       audio-supply = <&vcca1v8_codec>;
+       sdmmc-supply = <&vcc_sdio>;
+       gpio1830-supply = <&vcc_3v0>;
+};
+
+&pmu_io_domains {
+       status = "okay";
+       pmu1830-supply = <&vcc_3v0>;
+};
+
+&pinctrl {
+       buttons {
+               pwr_btn: pwr-btn {
+                       rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;
+               };
+       };
+
+       pmic {
+               pmic_int_l: pmic-int-l {
+                       rockchip,pins =
+                               <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
+               };
+       };
+
+       sd {
+               sdmmc0_pwr_h: sdmmc0-pwr-h {
+                       rockchip,pins =
+                               <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>;
+               };
+       };
+
+       usb2 {
+               vcc5v0_host_en: vcc5v0-host-en {
+                       rockchip,pins =
+                               <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>;
+               };
+
+               vcc5v0_typec_en: vcc5v0-typec-en {
+                       rockchip,pins =
+                               <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
+               };
+       };
+
+       sdio-pwrseq {
+               wifi_reg_on_h: wifi-reg-on-h {
+                       rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
+               };
+       };
+
+       wifi {
+               wifi_host_wake_l: wifi-host-wake-l {
+                       rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
+               };
+       };
+
+       bluetooth {
+               bt_reg_on_h: bt-enable-h {
+                       rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
+               };
+
+               bt_host_wake_l: bt-host-wake-l {
+                       rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
+               };
+
+               bt_wake_l: bt-wake-l {
+                       rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
+               };
+       };
+
+       mpu6500 {
+               gsensor_int_l: gsensor-int-l {
+                       rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
+               };
+       };
+
+       lsm6ds3 {
+               gyr_int_l: gyr-int-l {
+                       rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
+               };
+       };
+
+       cm32181 {
+               light_int_l: light-int-l {
+                       rockchip,pins = <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
+               };
+       };
+
+       fusb302 {
+               chg_cc_int_l: chg-cc-int-l {
+                       rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>;
+               };
+       };
+};
+
+&pwm0 {
+       status = "okay";
+};
+
+&pwm2 {
+       status = "okay";
+};
+
+&saradc {
+       vref-supply = <&vcca1v8_s3>;
+       status = "okay";
+};
+
+&sdhci {
+       bus-width = <8>;
+       mmc-hs400-1_8v;
+       mmc-hs400-enhanced-strobe;
+       non-removable;
+       status = "okay";
+};
+
+&sdio0 {
+       bus-width = <4>;
+       cap-sd-highspeed;
+       cap-sdio-irq;
+       clock-frequency = <50000000>;
+       disable-wp;
+       keep-power-in-suspend;
+       max-frequency = <50000000>;
+       mmc-pwrseq = <&sdio_pwrseq>;
+       non-removable;
+       pinctrl-names = "default";
+       pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
+       sd-uhs-sdr104;
+       status = "okay";
+
+       brcmf: wifi@1 {
+               compatible = "brcm,bcm4329-fmac";
+               interrupt-parent = <&gpio0>;
+               interrupts = <RK_PA3 GPIO_ACTIVE_HIGH>;
+               interrupt-names = "host-wake";
+               pinctrl-names = "default";
+               pinctrl-0 = <&wifi_host_wake_l>;
+       };
+};
+
+&sdmmc {
+       bus-width = <4>;
+       cap-mmc-highspeed;
+       cap-sd-highspeed;
+       cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>;
+       clock-frequency = <150000000>;
+       disable-wp;
+       max-frequency = <150000000>;
+       pinctrl-names = "default";
+       pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
+       vmmc-supply = <&vcc3v0_sd>;
+       vqmmc-supply = <&vcc_sdio>;
+       status = "okay";
+};
+
+&tcphy0 {
+       status = "okay";
+};
+
+&tcphy1 {
+       status = "okay";
+};
+
+&tsadc {
+       rockchip,hw-tshut-mode = <1>;
+       rockchip,hw-tshut-polarity = <1>;
+       status = "okay";
+};
+
+&u2phy0 {
+       status = "okay";
+
+       u2phy0_otg: otg-port {
+               phy-supply = <&vbus_typec>;
+               status = "okay";
+       };
+
+       u2phy0_host: host-port {
+               phy-supply = <&vcc5v0_host>;
+               status = "okay";
+       };
+};
+
+&u2phy1 {
+       status = "okay";
+
+       u2phy1_otg: otg-port {
+               status = "okay";
+       };
+
+       u2phy1_host: host-port {
+               phy-supply = <&vcc5v0_host>;
+               status = "okay";
+       };
+};
+
+&uart0 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
+       status = "okay";
+
+       bluetooth {
+               compatible = "brcm,bcm43438-bt";
+               clocks = <&rk808 1>;
+               clock-names = "lpo";
+               device-wakeup-gpios = <&gpio2 RK_PD2 GPIO_ACTIVE_HIGH>;
+               host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>;
+               shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>;
+               pinctrl-names = "default";
+               pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_reg_on_h>;
+               vbat-supply = <&vcc3v3_sys>;
+               vddio-supply = <&vcc_1v8>;
+       };
+};
+
+&uart2 {
+       status = "okay";
+};
+
+&usb_host0_ehci {
+       status = "okay";
+};
+
+&usb_host0_ohci {
+       status = "okay";
+};
+
+&usb_host1_ehci {
+       status = "okay";
+};
+
+&usb_host1_ohci {
+       status = "okay";
+};
+
+&usbdrd3_0 {
+       status = "okay";
+};
+
+&usbdrd_dwc3_0 {
+       status = "okay";
+       dr_mode = "otg";
+};
+
+&usbdrd3_1 {
+       status = "okay";
+};
+
+&usbdrd_dwc3_1 {
+       status = "okay";
+       dr_mode = "host";
+};
+
+&vopb {
+       status = "okay";
+};
+
+&vopb_mmu {
+       status = "okay";
+};
+
+&vopl {
+       status = "okay";
+};
+
+&vopl_mmu {
+       status = "okay";
+};

diff --git a/arch/arm64/boot/dts/rockchip/rk3399-puma-haikou.dts b/arch/arm64/boot/dts/rockchip/rk3399-puma-haikou.dts
index 1e6a710..d80d6b7 100644 (file)
--- a/arch/arm64/boot/dts/rockchip/rk3399-puma-haikou.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3399-puma-haikou.dts
@@ -168,27 +168,27 @@
                haikou_pin_hog: haikou-pin-hog {
                        rockchip,pins =
                          /* LID_BTN */
-                         <RK_GPIO0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>,
+                         <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>,
                          /* BATLOW# */
-                         <RK_GPIO0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>,
+                         <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>,
                          /* SLP_BTN# */
-                         <RK_GPIO0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_up>,
+                         <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_up>,
                          /* BIOS_DISABLE# */
-                         <RK_GPIO0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>;
+                         <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>;
                };
        };
 
        leds {
                led_sd_haikou: led-sd-gpio {
                        rockchip,pins =
-                         <RK_GPIO1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
+                         <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
                };
        };
 
        usb2 {
                otg_vbus_drv: otg-vbus-drv {
                        rockchip,pins =
-                         <RK_GPIO0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
+                         <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
                };
        };
 };

diff --git a/arch/arm64/boot/dts/rockchip/rk3399-puma.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-puma.dtsi
index 0130b9f..62ea288 100644 (file)
--- a/arch/arm64/boot/dts/rockchip/rk3399-puma.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399-puma.dtsi
@@ -146,6 +146,7 @@
 
 &emmc_phy {
        status = "okay";
+       drive-impedance-ohm = <33>;
 };
 
 &gmac {
@@ -369,8 +370,6 @@
        fan: fan@18 {
                compatible = "ti,amc6821";
                reg = <0x18>;
-               cooling-min-state = <0>;
-               cooling-max-state = <9>;
                #cooling-cells = <2>;
        };
 
@@ -413,10 +412,10 @@
  */
 &i2s0_2ch_bus {
        rockchip,pins =
-               <RK_GPIO3 RK_PD0 RK_FUNC_1 &pcfg_pull_none>,
-               <RK_GPIO3 RK_PD2 RK_FUNC_1 &pcfg_pull_none>,
-               <RK_GPIO3 RK_PD3 RK_FUNC_1 &pcfg_pull_none>,
-               <RK_GPIO3 RK_PD7 RK_FUNC_1 &pcfg_pull_none>;
+               <3 RK_PD0 1 &pcfg_pull_none>,
+               <3 RK_PD2 1 &pcfg_pull_none>,
+               <3 RK_PD3 1 &pcfg_pull_none>,
+               <3 RK_PD7 1 &pcfg_pull_none>;
 };
 
 &io_domains {
@@ -440,29 +439,29 @@
        i2c8 {
                i2c8_xfer_a: i2c8-xfer {
                        rockchip,pins =
-                         <RK_GPIO1 RK_PC4 RK_FUNC_1 &pcfg_pull_up>,
-                         <RK_GPIO1 RK_PC5 RK_FUNC_1 &pcfg_pull_up>;
+                         <1 RK_PC4 1 &pcfg_pull_up>,
+                         <1 RK_PC5 1 &pcfg_pull_up>;
                };
        };
 
        leds {
                led_pin_module: led-module-gpio {
                        rockchip,pins =
-                         <RK_GPIO2 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>;
+                         <2 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>;
                };
        };
 
        pmic {
                pmic_int_l: pmic-int-l {
                        rockchip,pins =
-                         <RK_GPIO1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>;
+                         <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>;
                };
        };
 
        usb2 {
                vcc5v0_host_en: vcc5v0-host-en {
                        rockchip,pins =
-                         <RK_GPIO4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
+                         <4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
                };
        };
 };

diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dts b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dts
index 844eac9..e030627 100644 (file)
--- a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dts
@@ -157,6 +157,11 @@
        status = "okay";
 };
 
+&gpu {
+       mali-supply = <&vdd_gpu>;
+       status = "okay";
+};
+
 &hdmi {
        ddc-i2c-bus = <&i2c3>;
        pinctrl-names = "default";

diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock960.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-rock960.dtsi
index 2927db4..c7d48d4 100644 (file)
--- a/arch/arm64/boot/dts/rockchip/rk3399-rock960.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399-rock960.dtsi
@@ -18,6 +18,15 @@
                reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>;
        };
 
+       vcc12v_dcin: vcc12v-dcin {
+               compatible = "regulator-fixed";
+               regulator-name = "vcc12v_dcin";
+               regulator-min-microvolt = <12000000>;
+               regulator-max-microvolt = <12000000>;
+               regulator-always-on;
+               regulator-boot-on;
+       };
+
        vcc1v8_s0: vcc1v8-s0 {
                compatible = "regulator-fixed";
                regulator-name = "vcc1v8_s0";
@@ -26,12 +35,13 @@
                regulator-always-on;
        };
 
-       vcc_sys: vcc-sys {
+       vcc5v0_sys: vcc5v0-sys {
                compatible = "regulator-fixed";
-               regulator-name = "vcc_sys";
+               regulator-name = "vcc5v0_sys";
                regulator-min-microvolt = <5000000>;
                regulator-max-microvolt = <5000000>;
                regulator-always-on;
+               vin-supply = <&vcc12v_dcin>;
        };
 
        vcc3v3_sys: vcc3v3-sys {
@@ -40,7 +50,7 @@
                regulator-min-microvolt = <3300000>;
                regulator-max-microvolt = <3300000>;
                regulator-always-on;
-               vin-supply = <&vcc_sys>;
+               vin-supply = <&vcc5v0_sys>;
        };
 
        vcc3v3_pcie: vcc3v3-pcie-regulator {
@@ -64,7 +74,7 @@
                regulator-min-microvolt = <5000000>;
                regulator-max-microvolt = <5000000>;
                regulator-always-on;
-               vin-supply = <&vcc_sys>;
+               vin-supply = <&vcc5v0_sys>;
        };
 };
 
@@ -96,6 +106,11 @@
        status = "okay";
 };
 
+&gpu {
+       mali-supply = <&vdd_gpu>;
+       status = "okay";
+};
+
 &hdmi {
        ddc-i2c-bus = <&i2c3>;
        pinctrl-names = "default";
@@ -123,7 +138,7 @@
                regulator-ramp-delay = <1000>;
                regulator-always-on;
                regulator-boot-on;
-               vin-supply = <&vcc_sys>;
+               vin-supply = <&vcc5v0_sys>;
                status = "okay";
 
                regulator-state-mem {
@@ -141,7 +156,7 @@
                regulator-ramp-delay = <1000>;
                regulator-always-on;
                regulator-boot-on;
-               vin-supply = <&vcc_sys>;
+               vin-supply = <&vcc5v0_sys>;
                regulator-state-mem {
                        regulator-off-in-suspend;
                };
@@ -159,16 +174,16 @@
                #clock-cells = <1>;
                clock-output-names = "xin32k", "rk808-clkout2";
 
-               vcc1-supply = <&vcc_sys>;
-               vcc2-supply = <&vcc_sys>;
-               vcc3-supply = <&vcc_sys>;
-               vcc4-supply = <&vcc_sys>;
-               vcc6-supply = <&vcc_sys>;
-               vcc7-supply = <&vcc_sys>;
+               vcc1-supply = <&vcc5v0_sys>;
+               vcc2-supply = <&vcc5v0_sys>;
+               vcc3-supply = <&vcc5v0_sys>;
+               vcc4-supply = <&vcc5v0_sys>;
+               vcc6-supply = <&vcc5v0_sys>;
+               vcc7-supply = <&vcc5v0_sys>;
                vcc8-supply = <&vcc3v3_sys>;
-               vcc9-supply = <&vcc_sys>;
-               vcc10-supply = <&vcc_sys>;
-               vcc11-supply = <&vcc_sys>;
+               vcc9-supply = <&vcc5v0_sys>;
+               vcc10-supply = <&vcc5v0_sys>;
+               vcc11-supply = <&vcc5v0_sys>;
                vcc12-supply = <&vcc3v3_sys>;
                vddio-supply = <&vcc_1v8>;
 
@@ -396,62 +411,62 @@
        sdmmc {
                sdmmc_bus1: sdmmc-bus1 {
                        rockchip,pins =
-                               <4 8 RK_FUNC_1 &pcfg_pull_up_8ma>;
+                               <4 RK_PB0 1 &pcfg_pull_up_8ma>;
                };
 
                sdmmc_bus4: sdmmc-bus4 {
                        rockchip,pins =
-                               <4 8 RK_FUNC_1 &pcfg_pull_up_8ma>,
-                               <4 9 RK_FUNC_1 &pcfg_pull_up_8ma>,
-                               <4 10 RK_FUNC_1 &pcfg_pull_up_8ma>,
-                               <4 11 RK_FUNC_1 &pcfg_pull_up_8ma>;
+                               <4 RK_PB0 1 &pcfg_pull_up_8ma>,
+                               <4 RK_PB1 1 &pcfg_pull_up_8ma>,
+                               <4 RK_PB2 1 &pcfg_pull_up_8ma>,
+                               <4 RK_PB3 1 &pcfg_pull_up_8ma>;
                };
 
                sdmmc_clk: sdmmc-clk {
                        rockchip,pins =
-                               <4 12 RK_FUNC_1 &pcfg_pull_none_18ma>;
+                               <4 RK_PB4 1 &pcfg_pull_none_18ma>;
                };
 
                sdmmc_cmd: sdmmc-cmd {
                        rockchip,pins =
-                               <4 13 RK_FUNC_1 &pcfg_pull_up_8ma>;
+                               <4 RK_PB5 1 &pcfg_pull_up_8ma>;
                };
        };
 
        sdio0 {
                sdio0_bus4: sdio0-bus4 {
                        rockchip,pins =
-                               <2 20 RK_FUNC_1 &pcfg_pull_up_20ma>,
-                               <2 21 RK_FUNC_1 &pcfg_pull_up_20ma>,
-                               <2 22 RK_FUNC_1 &pcfg_pull_up_20ma>,
-                               <2 23 RK_FUNC_1 &pcfg_pull_up_20ma>;
+                               <2 RK_PC4 1 &pcfg_pull_up_20ma>,
+                               <2 RK_PC5 1 &pcfg_pull_up_20ma>,
+                               <2 RK_PC6 1 &pcfg_pull_up_20ma>,
+                               <2 RK_PC7 1 &pcfg_pull_up_20ma>;
                };
 
                sdio0_cmd: sdio0-cmd {
                        rockchip,pins =
-                               <2 24 RK_FUNC_1 &pcfg_pull_up_20ma>;
+                               <2 RK_PD0 1 &pcfg_pull_up_20ma>;
                };
 
                sdio0_clk: sdio0-clk {
                        rockchip,pins =
-                               <2 25 RK_FUNC_1 &pcfg_pull_none_20ma>;
+                               <2 RK_PD1 1 &pcfg_pull_none_20ma>;
                };
        };
 
        pmic {
                pmic_int_l: pmic-int-l {
                        rockchip,pins =
-                               <1 21 RK_FUNC_GPIO &pcfg_pull_up>;
+                               <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
                };
 
                vsel1_gpio: vsel1-gpio {
                        rockchip,pins =
-                               <1 17 RK_FUNC_GPIO &pcfg_pull_down>;
+                               <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>;
                };
 
                vsel2_gpio: vsel2-gpio {
                        rockchip,pins =
-                               <1 14 RK_FUNC_GPIO &pcfg_pull_down>;
+                               <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>;
                };
        };
 

diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dts b/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dts
index 1f2394e..20ec7d1 100644 (file)
--- a/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dts
@@ -222,6 +222,10 @@
        status = "okay";
 };
 
+&hdmi_sound {
+       status = "okay";
+};
+
 &gpu {
        mali-supply = <&vdd_gpu>;
        status = "okay";
@@ -504,7 +508,7 @@
        status = "okay";
 
        bt656-supply = <&vcc1v8_dvp>;
-       audio-supply = <&vcca1v8_codec>;
+       audio-supply = <&vcc_3v0>;
        sdmmc-supply = <&vcc_sdio>;
        gpio1830-supply = <&vcc_3v0>;
 };

diff --git a/arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi
index 946d358..04623e5 100644 (file)
--- a/arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi
@@ -471,7 +471,7 @@
        fan {
                motor_pwr: motor-pwr {
                        rockchip,pins =
-                               <RK_GPIO1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
+                               <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
                };
        };
 
@@ -493,7 +493,7 @@
        sd {
                sdmmc0_pwr_h: sdmmc0-pwr-h {
                        rockchip,pins =
-                               <RK_GPIO0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>;
+                               <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>;
                };
        };
 

diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index db9d948..196ac9b 100644 (file)
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -71,6 +71,7 @@
                        compatible = "arm,cortex-a53";
                        reg = <0x0 0x0>;
                        enable-method = "psci";
+                       capacity-dmips-mhz = <485>;
                        clocks = <&cru ARMCLKL>;
                        #cooling-cells = <2>; /* min followed by max */
                        dynamic-power-coefficient = <100>;
@@ -82,6 +83,7 @@
                        compatible = "arm,cortex-a53";
                        reg = <0x0 0x1>;
                        enable-method = "psci";
+                       capacity-dmips-mhz = <485>;
                        clocks = <&cru ARMCLKL>;
                        #cooling-cells = <2>; /* min followed by max */
                        dynamic-power-coefficient = <100>;
@@ -93,6 +95,7 @@
                        compatible = "arm,cortex-a53";
                        reg = <0x0 0x2>;
                        enable-method = "psci";
+                       capacity-dmips-mhz = <485>;
                        clocks = <&cru ARMCLKL>;
                        #cooling-cells = <2>; /* min followed by max */
                        dynamic-power-coefficient = <100>;
@@ -104,6 +107,7 @@
                        compatible = "arm,cortex-a53";
                        reg = <0x0 0x3>;
                        enable-method = "psci";
+                       capacity-dmips-mhz = <485>;
                        clocks = <&cru ARMCLKL>;
                        #cooling-cells = <2>; /* min followed by max */
                        dynamic-power-coefficient = <100>;
@@ -115,6 +119,7 @@
                        compatible = "arm,cortex-a72";
                        reg = <0x0 0x100>;
                        enable-method = "psci";
+                       capacity-dmips-mhz = <1024>;
                        clocks = <&cru ARMCLKB>;
                        #cooling-cells = <2>; /* min followed by max */
                        dynamic-power-coefficient = <436>;
@@ -126,6 +131,7 @@
                        compatible = "arm,cortex-a72";
                        reg = <0x0 0x101>;
                        enable-method = "psci";
+                       capacity-dmips-mhz = <1024>;
                        clocks = <&cru ARMCLKB>;
                        #cooling-cells = <2>; /* min followed by max */
                        dynamic-power-coefficient = <436>;
@@ -333,6 +339,7 @@
                phys = <&emmc_phy>;
                phy-names = "phy_arasan";
                power-domains = <&power RK3399_PD_EMMC>;
+               disable-cqe-dcmd;
                status = "disabled";
        };
 
@@ -1450,6 +1457,7 @@
                        clock-names = "refclk";
                        #phy-cells = <1>;
                        resets = <&cru SRST_PCIEPHY>;
+                       drive-impedance-ohm = <50>;
                        reset-names = "phy";
                        status = "disabled";
                };
@@ -2045,14 +2053,14 @@
 
                clock {
                        clk_32k: clk-32k {
-                               rockchip,pins = <0 0 RK_FUNC_2 &pcfg_pull_none>;
+                               rockchip,pins = <0 RK_PA0 2 &pcfg_pull_none>;
                        };
                };
 
                edp {
                        edp_hpd: edp-hpd {
                                rockchip,pins =
-                                       <4 23 RK_FUNC_2 &pcfg_pull_none>;
+                                       <4 RK_PC7 2 &pcfg_pull_none>;
                        };
                };
 
@@ -2060,576 +2068,576 @@
                        rgmii_pins: rgmii-pins {
                                rockchip,pins =
                                        /* mac_txclk */
-                                       <3 17 RK_FUNC_1 &pcfg_pull_none_13ma>,
+                                       <3 RK_PC1 1 &pcfg_pull_none_13ma>,
                                        /* mac_rxclk */
-                                       <3 14 RK_FUNC_1 &pcfg_pull_none>,
+                                       <3 RK_PB6 1 &pcfg_pull_none>,
                                        /* mac_mdio */
-                                       <3 13 RK_FUNC_1 &pcfg_pull_none>,
+                                       <3 RK_PB5 1 &pcfg_pull_none>,
                                        /* mac_txen */
-                                       <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
+                                       <3 RK_PB4 1 &pcfg_pull_none_13ma>,
                                        /* mac_clk */
-                                       <3 11 RK_FUNC_1 &pcfg_pull_none>,
+                                       <3 RK_PB3 1 &pcfg_pull_none>,
                                        /* mac_rxdv */
-                                       <3 9 RK_FUNC_1 &pcfg_pull_none>,
+                                       <3 RK_PB1 1 &pcfg_pull_none>,
                                        /* mac_mdc */
-                                       <3 8 RK_FUNC_1 &pcfg_pull_none>,
+                                       <3 RK_PB0 1 &pcfg_pull_none>,
                                        /* mac_rxd1 */
-                                       <3 7 RK_FUNC_1 &pcfg_pull_none>,
+                                       <3 RK_PA7 1 &pcfg_pull_none>,
                                        /* mac_rxd0 */
-                                       <3 6 RK_FUNC_1 &pcfg_pull_none>,
+                                       <3 RK_PA6 1 &pcfg_pull_none>,
                                        /* mac_txd1 */
-                                       <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
+                                       <3 RK_PA5 1 &pcfg_pull_none_13ma>,
                                        /* mac_txd0 */
-                                       <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>,
+                                       <3 RK_PA4 1 &pcfg_pull_none_13ma>,
                                        /* mac_rxd3 */
-                                       <3 3 RK_FUNC_1 &pcfg_pull_none>,
+                                       <3 RK_PA3 1 &pcfg_pull_none>,
                                        /* mac_rxd2 */
-                                       <3 2 RK_FUNC_1 &pcfg_pull_none>,
+                                       <3 RK_PA2 1 &pcfg_pull_none>,
                                        /* mac_txd3 */
-                                       <3 1 RK_FUNC_1 &pcfg_pull_none_13ma>,
+                                       <3 RK_PA1 1 &pcfg_pull_none_13ma>,
                                        /* mac_txd2 */
-                                       <3 0 RK_FUNC_1 &pcfg_pull_none_13ma>;
+                                       <3 RK_PA0 1 &pcfg_pull_none_13ma>;
                        };
 
                        rmii_pins: rmii-pins {
                                rockchip,pins =
                                        /* mac_mdio */
-                                       <3 13 RK_FUNC_1 &pcfg_pull_none>,
+                                       <3 RK_PB5 1 &pcfg_pull_none>,
                                        /* mac_txen */
-                                       <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
+                                       <3 RK_PB4 1 &pcfg_pull_none_13ma>,
                                        /* mac_clk */
-                                       <3 11 RK_FUNC_1 &pcfg_pull_none>,
+                                       <3 RK_PB3 1 &pcfg_pull_none>,
                                        /* mac_rxer */
-                                       <3 10 RK_FUNC_1 &pcfg_pull_none>,
+                                       <3 RK_PB2 1 &pcfg_pull_none>,
                                        /* mac_rxdv */
-                                       <3 9 RK_FUNC_1 &pcfg_pull_none>,
+                                       <3 RK_PB1 1 &pcfg_pull_none>,
                                        /* mac_mdc */
-                                       <3 8 RK_FUNC_1 &pcfg_pull_none>,
+                                       <3 RK_PB0 1 &pcfg_pull_none>,
                                        /* mac_rxd1 */
-                                       <3 7 RK_FUNC_1 &pcfg_pull_none>,
+                                       <3 RK_PA7 1 &pcfg_pull_none>,
                                        /* mac_rxd0 */
-                                       <3 6 RK_FUNC_1 &pcfg_pull_none>,
+                                       <3 RK_PA6 1 &pcfg_pull_none>,
                                        /* mac_txd1 */
-                                       <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
+                                       <3 RK_PA5 1 &pcfg_pull_none_13ma>,
                                        /* mac_txd0 */
-                                       <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>;
+                                       <3 RK_PA4 1 &pcfg_pull_none_13ma>;
                        };
                };
 
                i2c0 {
                        i2c0_xfer: i2c0-xfer {
                                rockchip,pins =
-                                       <1 15 RK_FUNC_2 &pcfg_pull_none>,
-                                       <1 16 RK_FUNC_2 &pcfg_pull_none>;
+                                       <1 RK_PB7 2 &pcfg_pull_none>,
+                                       <1 RK_PC0 2 &pcfg_pull_none>;
                        };
                };
 
                i2c1 {
                        i2c1_xfer: i2c1-xfer {
                                rockchip,pins =
-                                       <4 2 RK_FUNC_1 &pcfg_pull_none>,
-                                       <4 1 RK_FUNC_1 &pcfg_pull_none>;
+                                       <4 RK_PA2 1 &pcfg_pull_none>,
+                                       <4 RK_PA1 1 &pcfg_pull_none>;
                        };
                };
 
                i2c2 {
                        i2c2_xfer: i2c2-xfer {
                                rockchip,pins =
-                                       <2 1 RK_FUNC_2 &pcfg_pull_none_12ma>,
-                                       <2 0 RK_FUNC_2 &pcfg_pull_none_12ma>;
+                                       <2 RK_PA1 2 &pcfg_pull_none_12ma>,
+                                       <2 RK_PA0 2 &pcfg_pull_none_12ma>;
                        };
                };
 
                i2c3 {
                        i2c3_xfer: i2c3-xfer {
                                rockchip,pins =
-                                       <4 17 RK_FUNC_1 &pcfg_pull_none>,
-                                       <4 16 RK_FUNC_1 &pcfg_pull_none>;
+                                       <4 RK_PC1 1 &pcfg_pull_none>,
+                                       <4 RK_PC0 1 &pcfg_pull_none>;
                        };
                };
 
                i2c4 {
                        i2c4_xfer: i2c4-xfer {
                                rockchip,pins =
-                                       <1 12 RK_FUNC_1 &pcfg_pull_none>,
-                                       <1 11 RK_FUNC_1 &pcfg_pull_none>;
+                                       <1 RK_PB4 1 &pcfg_pull_none>,
+                                       <1 RK_PB3 1 &pcfg_pull_none>;
                        };
                };
 
                i2c5 {
                        i2c5_xfer: i2c5-xfer {
                                rockchip,pins =
-                                       <3 11 RK_FUNC_2 &pcfg_pull_none>,
-                                       <3 10 RK_FUNC_2 &pcfg_pull_none>;
+                                       <3 RK_PB3 2 &pcfg_pull_none>,
+                                       <3 RK_PB2 2 &pcfg_pull_none>;
                        };
                };
 
                i2c6 {
                        i2c6_xfer: i2c6-xfer {
                                rockchip,pins =
-                                       <2 10 RK_FUNC_2 &pcfg_pull_none>,
-                                       <2 9 RK_FUNC_2 &pcfg_pull_none>;
+                                       <2 RK_PB2 2 &pcfg_pull_none>,
+                                       <2 RK_PB1 2 &pcfg_pull_none>;
                        };
                };
 
                i2c7 {
                        i2c7_xfer: i2c7-xfer {
                                rockchip,pins =
-                                       <2 8 RK_FUNC_2 &pcfg_pull_none>,
-                                       <2 7 RK_FUNC_2 &pcfg_pull_none>;
+                                       <2 RK_PB0 2 &pcfg_pull_none>,
+                                       <2 RK_PA7 2 &pcfg_pull_none>;
                        };
                };
 
                i2c8 {
                        i2c8_xfer: i2c8-xfer {
                                rockchip,pins =
-                                       <1 21 RK_FUNC_1 &pcfg_pull_none>,
-                                       <1 20 RK_FUNC_1 &pcfg_pull_none>;
+                                       <1 RK_PC5 1 &pcfg_pull_none>,
+                                       <1 RK_PC4 1 &pcfg_pull_none>;
                        };
                };
 
                i2s0 {
                        i2s0_2ch_bus: i2s0-2ch-bus {
                                rockchip,pins =
-                                       <3 24 RK_FUNC_1 &pcfg_pull_none>,
-                                       <3 25 RK_FUNC_1 &pcfg_pull_none>,
-                                       <3 26 RK_FUNC_1 &pcfg_pull_none>,
-                                       <3 27 RK_FUNC_1 &pcfg_pull_none>,
-                                       <3 31 RK_FUNC_1 &pcfg_pull_none>,
-                                       <4 0 RK_FUNC_1 &pcfg_pull_none>;
+                                       <3 RK_PD0 1 &pcfg_pull_none>,
+                                       <3 RK_PD1 1 &pcfg_pull_none>,
+                                       <3 RK_PD2 1 &pcfg_pull_none>,
+                                       <3 RK_PD3 1 &pcfg_pull_none>,
+                                       <3 RK_PD7 1 &pcfg_pull_none>,
+                                       <4 RK_PA0 1 &pcfg_pull_none>;
                        };
 
                        i2s0_8ch_bus: i2s0-8ch-bus {
                                rockchip,pins =
-                                       <3 24 RK_FUNC_1 &pcfg_pull_none>,
-                                       <3 25 RK_FUNC_1 &pcfg_pull_none>,
-                                       <3 26 RK_FUNC_1 &pcfg_pull_none>,
-                                       <3 27 RK_FUNC_1 &pcfg_pull_none>,
-                                       <3 28 RK_FUNC_1 &pcfg_pull_none>,
-                                       <3 29 RK_FUNC_1 &pcfg_pull_none>,
-                                       <3 30 RK_FUNC_1 &pcfg_pull_none>,
-                                       <3 31 RK_FUNC_1 &pcfg_pull_none>,
-                                       <4 0 RK_FUNC_1 &pcfg_pull_none>;
+                                       <3 RK_PD0 1 &pcfg_pull_none>,
+                                       <3 RK_PD1 1 &pcfg_pull_none>,
+                                       <3 RK_PD2 1 &pcfg_pull_none>,
+                                       <3 RK_PD3 1 &pcfg_pull_none>,
+                                       <3 RK_PD4 1 &pcfg_pull_none>,
+                                       <3 RK_PD5 1 &pcfg_pull_none>,
+                                       <3 RK_PD6 1 &pcfg_pull_none>,
+                                       <3 RK_PD7 1 &pcfg_pull_none>,
+                                       <4 RK_PA0 1 &pcfg_pull_none>;
                        };
                };
 
                i2s1 {
                        i2s1_2ch_bus: i2s1-2ch-bus {
                                rockchip,pins =
-                                       <4 3 RK_FUNC_1 &pcfg_pull_none>,
-                                       <4 4 RK_FUNC_1 &pcfg_pull_none>,
-                                       <4 5 RK_FUNC_1 &pcfg_pull_none>,
-                                       <4 6 RK_FUNC_1 &pcfg_pull_none>,
-                                       <4 7 RK_FUNC_1 &pcfg_pull_none>;
+                                       <4 RK_PA3 1 &pcfg_pull_none>,
+                                       <4 RK_PA4 1 &pcfg_pull_none>,
+                                       <4 RK_PA5 1 &pcfg_pull_none>,
+                                       <4 RK_PA6 1 &pcfg_pull_none>,
+                                       <4 RK_PA7 1 &pcfg_pull_none>;
                        };
                };
 
                sdio0 {
                        sdio0_bus1: sdio0-bus1 {
                                rockchip,pins =
-                                       <2 RK_PC4 RK_FUNC_1 &pcfg_pull_up>;
+                                       <2 RK_PC4 1 &pcfg_pull_up>;
                        };
 
                        sdio0_bus4: sdio0-bus4 {
                                rockchip,pins =
-                                       <2 RK_PC4 RK_FUNC_1 &pcfg_pull_up>,
-                                       <2 RK_PC5 RK_FUNC_1 &pcfg_pull_up>,
-                                       <2 RK_PC6 RK_FUNC_1 &pcfg_pull_up>,
-                                       <2 RK_PC7 RK_FUNC_1 &pcfg_pull_up>;
+                                       <2 RK_PC4 1 &pcfg_pull_up>,
+                                       <2 RK_PC5 1 &pcfg_pull_up>,
+                                       <2 RK_PC6 1 &pcfg_pull_up>,
+                                       <2 RK_PC7 1 &pcfg_pull_up>;
                        };
 
                        sdio0_cmd: sdio0-cmd {
                                rockchip,pins =
-                                       <2 RK_PD0 RK_FUNC_1 &pcfg_pull_up>;
+                                       <2 RK_PD0 1 &pcfg_pull_up>;
                        };
 
                        sdio0_clk: sdio0-clk {
                                rockchip,pins =
-                                       <2 RK_PD1 RK_FUNC_1 &pcfg_pull_none>;
+                                       <2 RK_PD1 1 &pcfg_pull_none>;
                        };
 
                        sdio0_cd: sdio0-cd {
                                rockchip,pins =
-                                       <2 RK_PD2 RK_FUNC_1 &pcfg_pull_up>;
+                                       <2 RK_PD2 1 &pcfg_pull_up>;
                        };
 
                        sdio0_pwr: sdio0-pwr {
                                rockchip,pins =
-                                       <2 RK_PD3 RK_FUNC_1 &pcfg_pull_up>;
+                                       <2 RK_PD3 1 &pcfg_pull_up>;
                        };
 
                        sdio0_bkpwr: sdio0-bkpwr {
                                rockchip,pins =
-                                       <2 RK_PD4 RK_FUNC_1 &pcfg_pull_up>;
+                                       <2 RK_PD4 1 &pcfg_pull_up>;
                        };
 
                        sdio0_wp: sdio0-wp {
                                rockchip,pins =
-                                       <0 RK_PA3 RK_FUNC_1 &pcfg_pull_up>;
+                                       <0 RK_PA3 1 &pcfg_pull_up>;
                        };
 
                        sdio0_int: sdio0-int {
                                rockchip,pins =
-                                       <0 RK_PA4 RK_FUNC_1 &pcfg_pull_up>;
+                                       <0 RK_PA4 1 &pcfg_pull_up>;
                        };
                };
 
                sdmmc {
                        sdmmc_bus1: sdmmc-bus1 {
                                rockchip,pins =
-                                       <4 RK_PB0 RK_FUNC_1 &pcfg_pull_up>;
+                                       <4 RK_PB0 1 &pcfg_pull_up>;
                        };
 
                        sdmmc_bus4: sdmmc-bus4 {
                                rockchip,pins =
-                                       <4 RK_PB0 RK_FUNC_1 &pcfg_pull_up>,
-                                       <4 RK_PB1 RK_FUNC_1 &pcfg_pull_up>,
-                                       <4 RK_PB2 RK_FUNC_1 &pcfg_pull_up>,
-                                       <4 RK_PB3 RK_FUNC_1 &pcfg_pull_up>;
+                                       <4 RK_PB0 1 &pcfg_pull_up>,
+                                       <4 RK_PB1 1 &pcfg_pull_up>,
+                                       <4 RK_PB2 1 &pcfg_pull_up>,
+                                       <4 RK_PB3 1 &pcfg_pull_up>;
                        };
 
                        sdmmc_clk: sdmmc-clk {
                                rockchip,pins =
-                                       <4 RK_PB4 RK_FUNC_1 &pcfg_pull_none>;
+                                       <4 RK_PB4 1 &pcfg_pull_none>;
                        };
 
                        sdmmc_cmd: sdmmc-cmd {
                                rockchip,pins =
-                                       <4 RK_PB5 RK_FUNC_1 &pcfg_pull_up>;
+                                       <4 RK_PB5 1 &pcfg_pull_up>;
                        };
 
                        sdmmc_cd: sdmmc-cd {
                                rockchip,pins =
-                                       <0 RK_PA7 RK_FUNC_1 &pcfg_pull_up>;
+                                       <0 RK_PA7 1 &pcfg_pull_up>;
                        };
 
                        sdmmc_wp: sdmmc-wp {
                                rockchip,pins =
-                                       <0 RK_PB0 RK_FUNC_1 &pcfg_pull_up>;
+                                       <0 RK_PB0 1 &pcfg_pull_up>;
                        };
                };
 
                sleep {
                        ap_pwroff: ap-pwroff {
-                               rockchip,pins = <1 5 RK_FUNC_1 &pcfg_pull_none>;
+                               rockchip,pins = <1 RK_PA5 1 &pcfg_pull_none>;
                        };
 
                        ddrio_pwroff: ddrio-pwroff {
-                               rockchip,pins = <0 1 RK_FUNC_1 &pcfg_pull_none>;
+                               rockchip,pins = <0 RK_PA1 1 &pcfg_pull_none>;
                        };
                };
 
                spdif {
                        spdif_bus: spdif-bus {
                                rockchip,pins =
-                                       <4 21 RK_FUNC_1 &pcfg_pull_none>;
+                                       <4 RK_PC5 1 &pcfg_pull_none>;
                        };
 
                        spdif_bus_1: spdif-bus-1 {
                                rockchip,pins =
-                                       <3 RK_PC0 RK_FUNC_3 &pcfg_pull_none>;
+                                       <3 RK_PC0 3 &pcfg_pull_none>;
                        };
                };
 
                spi0 {
                        spi0_clk: spi0-clk {
                                rockchip,pins =
-                                       <3 6 RK_FUNC_2 &pcfg_pull_up>;
+                                       <3 RK_PA6 2 &pcfg_pull_up>;
                        };
                        spi0_cs0: spi0-cs0 {
                                rockchip,pins =
-                                       <3 7 RK_FUNC_2 &pcfg_pull_up>;
+                                       <3 RK_PA7 2 &pcfg_pull_up>;
                        };
                        spi0_cs1: spi0-cs1 {
                                rockchip,pins =
-                                       <3 8 RK_FUNC_2 &pcfg_pull_up>;
+                                       <3 RK_PB0 2 &pcfg_pull_up>;
                        };
                        spi0_tx: spi0-tx {
                                rockchip,pins =
-                                       <3 5 RK_FUNC_2 &pcfg_pull_up>;
+                                       <3 RK_PA5 2 &pcfg_pull_up>;
                        };
                        spi0_rx: spi0-rx {
                                rockchip,pins =
-                                       <3 4 RK_FUNC_2 &pcfg_pull_up>;
+                                       <3 RK_PA4 2 &pcfg_pull_up>;
                        };
                };
 
                spi1 {
                        spi1_clk: spi1-clk {
                                rockchip,pins =
-                                       <1 9 RK_FUNC_2 &pcfg_pull_up>;
+                                       <1 RK_PB1 2 &pcfg_pull_up>;
                        };
                        spi1_cs0: spi1-cs0 {
                                rockchip,pins =
-                                       <1 10 RK_FUNC_2 &pcfg_pull_up>;
+                                       <1 RK_PB2 2 &pcfg_pull_up>;
                        };
                        spi1_rx: spi1-rx {
                                rockchip,pins =
-                                       <1 7 RK_FUNC_2 &pcfg_pull_up>;
+                                       <1 RK_PA7 2 &pcfg_pull_up>;
                        };
                        spi1_tx: spi1-tx {
                                rockchip,pins =
-                                       <1 8 RK_FUNC_2 &pcfg_pull_up>;
+                                       <1 RK_PB0 2 &pcfg_pull_up>;
                        };
                };
 
                spi2 {
                        spi2_clk: spi2-clk {
                                rockchip,pins =
-                                       <2 11 RK_FUNC_1 &pcfg_pull_up>;
+                                       <2 RK_PB3 1 &pcfg_pull_up>;
                        };
                        spi2_cs0: spi2-cs0 {
                                rockchip,pins =
-                                       <2 12 RK_FUNC_1 &pcfg_pull_up>;
+                                       <2 RK_PB4 1 &pcfg_pull_up>;
                        };
                        spi2_rx: spi2-rx {
                                rockchip,pins =
-                                       <2 9 RK_FUNC_1 &pcfg_pull_up>;
+                                       <2 RK_PB1 1 &pcfg_pull_up>;
                        };
                        spi2_tx: spi2-tx {
                                rockchip,pins =
-                                       <2 10 RK_FUNC_1 &pcfg_pull_up>;
+                                       <2 RK_PB2 1 &pcfg_pull_up>;
                        };
                };
 
                spi3 {
                        spi3_clk: spi3-clk {
                                rockchip,pins =
-                                       <1 17 RK_FUNC_1 &pcfg_pull_up>;
+                                       <1 RK_PC1 1 &pcfg_pull_up>;
                        };
                        spi3_cs0: spi3-cs0 {
                                rockchip,pins =
-                                       <1 18 RK_FUNC_1 &pcfg_pull_up>;
+                                       <1 RK_PC2 1 &pcfg_pull_up>;
                        };
                        spi3_rx: spi3-rx {
                                rockchip,pins =
-                                       <1 15 RK_FUNC_1 &pcfg_pull_up>;
+                                       <1 RK_PB7 1 &pcfg_pull_up>;
                        };
                        spi3_tx: spi3-tx {
                                rockchip,pins =
-                                       <1 16 RK_FUNC_1 &pcfg_pull_up>;
+                                       <1 RK_PC0 1 &pcfg_pull_up>;
                        };
                };
 
                spi4 {
                        spi4_clk: spi4-clk {
                                rockchip,pins =
-                                       <3 2 RK_FUNC_2 &pcfg_pull_up>;
+                                       <3 RK_PA2 2 &pcfg_pull_up>;
                        };
                        spi4_cs0: spi4-cs0 {
                                rockchip,pins =
-                                       <3 3 RK_FUNC_2 &pcfg_pull_up>;
+                                       <3 RK_PA3 2 &pcfg_pull_up>;
                        };
                        spi4_rx: spi4-rx {
                                rockchip,pins =
-                                       <3 0 RK_FUNC_2 &pcfg_pull_up>;
+                                       <3 RK_PA0 2 &pcfg_pull_up>;
                        };
                        spi4_tx: spi4-tx {
                                rockchip,pins =
-                                       <3 1 RK_FUNC_2 &pcfg_pull_up>;
+                                       <3 RK_PA1 2 &pcfg_pull_up>;
                        };
                };
 
                spi5 {
                        spi5_clk: spi5-clk {
                                rockchip,pins =
-                                       <2 22 RK_FUNC_2 &pcfg_pull_up>;
+                                       <2 RK_PC6 2 &pcfg_pull_up>;
                        };
                        spi5_cs0: spi5-cs0 {
                                rockchip,pins =
-                                       <2 23 RK_FUNC_2 &pcfg_pull_up>;
+                                       <2 RK_PC7 2 &pcfg_pull_up>;
                        };
                        spi5_rx: spi5-rx {
                                rockchip,pins =
-                                       <2 20 RK_FUNC_2 &pcfg_pull_up>;
+                                       <2 RK_PC4 2 &pcfg_pull_up>;
                        };
                        spi5_tx: spi5-tx {
                                rockchip,pins =
-                                       <2 21 RK_FUNC_2 &pcfg_pull_up>;
+                                       <2 RK_PC5 2 &pcfg_pull_up>;
                        };
                };
 
                testclk {
                        test_clkout0: test-clkout0 {
                                rockchip,pins =
-                                       <0 0 RK_FUNC_1 &pcfg_pull_none>;
+                                       <0 RK_PA0 1 &pcfg_pull_none>;
                        };
 
                        test_clkout1: test-clkout1 {
                                rockchip,pins =
-                                       <2 25 RK_FUNC_2 &pcfg_pull_none>;
+                                       <2 RK_PD1 2 &pcfg_pull_none>;
                        };
 
                        test_clkout2: test-clkout2 {
                                rockchip,pins =
-                                       <0 8 RK_FUNC_3 &pcfg_pull_none>;
+                                       <0 RK_PB0 3 &pcfg_pull_none>;
                        };
                };
 
                tsadc {
                        otp_gpio: otp-gpio {
-                               rockchip,pins = <1 6 RK_FUNC_GPIO &pcfg_pull_none>;
+                               rockchip,pins = <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
                        };
 
                        otp_out: otp-out {
-                               rockchip,pins = <1 6 RK_FUNC_1 &pcfg_pull_none>;
+                               rockchip,pins = <1 RK_PA6 1 &pcfg_pull_none>;
                        };
                };
 
                uart0 {
                        uart0_xfer: uart0-xfer {
                                rockchip,pins =
-                                       <2 16 RK_FUNC_1 &pcfg_pull_up>,
-                                       <2 17 RK_FUNC_1 &pcfg_pull_none>;
+                                       <2 RK_PC0 1 &pcfg_pull_up>,
+                                       <2 RK_PC1 1 &pcfg_pull_none>;
                        };
 
                        uart0_cts: uart0-cts {
                                rockchip,pins =
-                                       <2 18 RK_FUNC_1 &pcfg_pull_none>;
+                                       <2 RK_PC2 1 &pcfg_pull_none>;
                        };
 
                        uart0_rts: uart0-rts {
                                rockchip,pins =
-                                       <2 19 RK_FUNC_1 &pcfg_pull_none>;
+                                       <2 RK_PC3 1 &pcfg_pull_none>;
                        };
                };
 
                uart1 {
                        uart1_xfer: uart1-xfer {
                                rockchip,pins =
-                                       <3 12 RK_FUNC_2 &pcfg_pull_up>,
-                                       <3 13 RK_FUNC_2 &pcfg_pull_none>;
+                                       <3 RK_PB4 2 &pcfg_pull_up>,
+                                       <3 RK_PB5 2 &pcfg_pull_none>;
                        };
                };
 
                uart2a {
                        uart2a_xfer: uart2a-xfer {
                                rockchip,pins =
-                                       <4 8 RK_FUNC_2 &pcfg_pull_up>,
-                                       <4 9 RK_FUNC_2 &pcfg_pull_none>;
+                                       <4 RK_PB0 2 &pcfg_pull_up>,
+                                       <4 RK_PB1 2 &pcfg_pull_none>;
                        };
                };
 
                uart2b {
                        uart2b_xfer: uart2b-xfer {
                                rockchip,pins =
-                                       <4 16 RK_FUNC_2 &pcfg_pull_up>,
-                                       <4 17 RK_FUNC_2 &pcfg_pull_none>;
+                                       <4 RK_PC0 2 &pcfg_pull_up>,
+                                       <4 RK_PC1 2 &pcfg_pull_none>;
                        };
                };
 
                uart2c {
                        uart2c_xfer: uart2c-xfer {
                                rockchip,pins =
-                                       <4 19 RK_FUNC_1 &pcfg_pull_up>,
-                                       <4 20 RK_FUNC_1 &pcfg_pull_none>;
+                                       <4 RK_PC3 1 &pcfg_pull_up>,
+                                       <4 RK_PC4 1 &pcfg_pull_none>;
                        };
                };
 
                uart3 {
                        uart3_xfer: uart3-xfer {
                                rockchip,pins =
-                                       <3 14 RK_FUNC_2 &pcfg_pull_up>,
-                                       <3 15 RK_FUNC_2 &pcfg_pull_none>;
+                                       <3 RK_PB6 2 &pcfg_pull_up>,
+                                       <3 RK_PB7 2 &pcfg_pull_none>;
                        };
 
                        uart3_cts: uart3-cts {
                                rockchip,pins =
-                                       <3 18 RK_FUNC_2 &pcfg_pull_none>;
+                                       <3 RK_PC0 2 &pcfg_pull_none>;
                        };
 
                        uart3_rts: uart3-rts {
                                rockchip,pins =
-                                       <3 19 RK_FUNC_2 &pcfg_pull_none>;
+                                       <3 RK_PC1 2 &pcfg_pull_none>;
                        };
                };
 
                uart4 {
                        uart4_xfer: uart4-xfer {
                                rockchip,pins =
-                                       <1 7 RK_FUNC_1 &pcfg_pull_up>,
-                                       <1 8 RK_FUNC_1 &pcfg_pull_none>;
+                                       <1 RK_PA7 1 &pcfg_pull_up>,
+                                       <1 RK_PB0 1 &pcfg_pull_none>;
                        };
                };
 
                uarthdcp {
                        uarthdcp_xfer: uarthdcp-xfer {
                                rockchip,pins =
-                                       <4 21 RK_FUNC_2 &pcfg_pull_up>,
-                                       <4 22 RK_FUNC_2 &pcfg_pull_none>;
+                                       <4 RK_PC5 2 &pcfg_pull_up>,
+                                       <4 RK_PC6 2 &pcfg_pull_none>;
                        };
                };
 
                pwm0 {
                        pwm0_pin: pwm0-pin {
                                rockchip,pins =
-                                       <4 RK_PC2 RK_FUNC_1 &pcfg_pull_none>;
+                                       <4 RK_PC2 1 &pcfg_pull_none>;
                        };
 
                        pwm0_pin_pull_down: pwm0-pin-pull-down {
                                rockchip,pins =
-                                       <4 RK_PC2 RK_FUNC_1 &pcfg_pull_down>;
+                                       <4 RK_PC2 1 &pcfg_pull_down>;
                        };
 
                        vop0_pwm_pin: vop0-pwm-pin {
                                rockchip,pins =
-                                       <4 RK_PC2 RK_FUNC_2 &pcfg_pull_none>;
+                                       <4 RK_PC2 2 &pcfg_pull_none>;
                        };
 
                        vop1_pwm_pin: vop1-pwm-pin {
                                rockchip,pins =
-                                       <4 RK_PC2 RK_FUNC_3 &pcfg_pull_none>;
+                                       <4 RK_PC2 3 &pcfg_pull_none>;
                        };
                };
 
                pwm1 {
                        pwm1_pin: pwm1-pin {
                                rockchip,pins =
-                                       <4 RK_PC6 RK_FUNC_1 &pcfg_pull_none>;
+                                       <4 RK_PC6 1 &pcfg_pull_none>;
                        };
 
                        pwm1_pin_pull_down: pwm1-pin-pull-down {
                                rockchip,pins =
-                                       <4 RK_PC6 RK_FUNC_1 &pcfg_pull_down>;
+                                       <4 RK_PC6 1 &pcfg_pull_down>;
                        };
                };
 
                pwm2 {
                        pwm2_pin: pwm2-pin {
                                rockchip,pins =
-                                       <1 RK_PC3 RK_FUNC_1 &pcfg_pull_none>;
+                                       <1 RK_PC3 1 &pcfg_pull_none>;
                        };
 
                        pwm2_pin_pull_down: pwm2-pin-pull-down {
                                rockchip,pins =
-                                       <1 RK_PC3 RK_FUNC_1 &pcfg_pull_down>;
+                                       <1 RK_PC3 1 &pcfg_pull_down>;
                        };
                };
 
                pwm3a {
                        pwm3a_pin: pwm3a-pin {
                                rockchip,pins =
-                                       <0 RK_PA6 RK_FUNC_1 &pcfg_pull_none>;
+                                       <0 RK_PA6 1 &pcfg_pull_none>;
                        };
                };
 
                pwm3b {
                        pwm3b_pin: pwm3b-pin {
                                rockchip,pins =
-                                       <1 RK_PB6 RK_FUNC_1 &pcfg_pull_none>;
+                                       <1 RK_PB6 1 &pcfg_pull_none>;
                        };
                };
 
                hdmi {
                        hdmi_i2c_xfer: hdmi-i2c-xfer {
                                rockchip,pins =
-                                       <4 RK_PC1 RK_FUNC_3 &pcfg_pull_none>,
-                                       <4 RK_PC0 RK_FUNC_3 &pcfg_pull_none>;
+                                       <4 RK_PC1 3 &pcfg_pull_none>,
+                                       <4 RK_PC0 3 &pcfg_pull_none>;
                        };
 
                        hdmi_cec: hdmi-cec {
                                rockchip,pins =
-                                       <4 RK_PC7 RK_FUNC_1 &pcfg_pull_none>;
+                                       <4 RK_PC7 1 &pcfg_pull_none>;
                        };
                };
 

diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts
index 11cc671..2421ec7 100644 (file)
--- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts
@@ -89,6 +89,7 @@
                ti,rx-internal-delay = <0x8>;
                ti,tx-internal-delay = <0xa>;
                ti,fifo-depth = <0x1>;
+               ti,dp83867-rxctrl-strap-quirk;
        };
 };
 

diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts
index cef8167..2a3b665 100644 (file)
--- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts
@@ -110,6 +110,7 @@
                ti,rx-internal-delay = <0x8>;
                ti,tx-internal-delay = <0xa>;
                ti,fifo-depth = <0x1>;
+               ti,dp83867-rxctrl-strap-quirk;
        };
 };
 

diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revB.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revB.dts
index af4d868..1780ed2 100644 (file)
--- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revB.dts
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revB.dts
@@ -21,6 +21,7 @@
                ti,rx-internal-delay = <0x8>;
                ti,tx-internal-delay = <0xa>;
                ti,fifo-depth = <0x1>;
+               ti,dp83867-rxctrl-strap-quirk;
        };
        /* Cleanup from RevA */
        /delete-node/ phy@21;

diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts
index d4ad19a..8f45614 100644 (file)
--- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts
@@ -55,6 +55,7 @@
                ti,rx-internal-delay = <0x8>;
                ti,tx-internal-delay = <0xa>;
                ti,fifo-depth = <0x1>;
+               ti,dp83867-rxctrl-strap-quirk;
        };
 };
 

diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts
index 94cf509..93ce7eb 100644 (file)
--- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts
@@ -111,6 +111,7 @@
                ti,rx-internal-delay = <0x8>;
                ti,tx-internal-delay = <0xa>;
                ti,fifo-depth = <0x1>;
+               ti,dp83867-rxctrl-strap-quirk;
        };
 };
 

diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts
index 460adc3..8bb0001 100644 (file)
--- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts
@@ -106,6 +106,7 @@
                ti,rx-internal-delay = <0x8>;
                ti,tx-internal-delay = <0xa>;
                ti,fifo-depth = <0x1>;
+               ti,dp83867-rxctrl-strap-quirk;
        };
 };
 

diff --git a/include/dt-bindings/clock/xlnx,zynqmp-clk.h b/include/dt-bindings/clock/xlnx,zynqmp-clk.h
deleted file mode 100644 (file)
index 4aebe6e..0000000
--- a/include/dt-bindings/clock/xlnx,zynqmp-clk.h
+++ /dev/null
@@ -1,116 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Xilinx Zynq MPSoC Firmware layer
- *
- *  Copyright (C) 2014-2018 Xilinx, Inc.
- *
- */
-
-#ifndef _DT_BINDINGS_CLK_ZYNQMP_H
-#define _DT_BINDINGS_CLK_ZYNQMP_H
-
-#define IOPLL                  0
-#define RPLL                   1
-#define APLL                   2
-#define DPLL                   3
-#define VPLL                   4
-#define IOPLL_TO_FPD           5
-#define RPLL_TO_FPD            6
-#define APLL_TO_LPD            7
-#define DPLL_TO_LPD            8
-#define VPLL_TO_LPD            9
-#define ACPU                   10
-#define ACPU_HALF              11
-#define DBF_FPD                        12
-#define DBF_LPD                        13
-#define DBG_TRACE              14
-#define DBG_TSTMP              15
-#define DP_VIDEO_REF           16
-#define DP_AUDIO_REF           17
-#define DP_STC_REF             18
-#define GDMA_REF               19
-#define DPDMA_REF              20
-#define DDR_REF                        21
-#define SATA_REF               22
-#define PCIE_REF               23
-#define GPU_REF                        24
-#define GPU_PP0_REF            25
-#define GPU_PP1_REF            26
-#define TOPSW_MAIN             27
-#define TOPSW_LSBUS            28
-#define GTGREF0_REF            29
-#define LPD_SWITCH             30
-#define LPD_LSBUS              31
-#define USB0_BUS_REF           32
-#define USB1_BUS_REF           33
-#define USB3_DUAL_REF          34
-#define USB0                   35
-#define USB1                   36
-#define CPU_R5                 37
-#define CPU_R5_CORE            38
-#define CSU_SPB                        39
-#define CSU_PLL                        40
-#define PCAP                   41
-#define IOU_SWITCH             42
-#define GEM_TSU_REF            43
-#define GEM_TSU                        44
-#define GEM0_REF               45
-#define GEM1_REF               46
-#define GEM2_REF               47
-#define GEM3_REF               48
-#define GEM0_TX                        49
-#define GEM1_TX                        50
-#define GEM2_TX                        51
-#define GEM3_TX                        52
-#define QSPI_REF               53
-#define SDIO0_REF              54
-#define SDIO1_REF              55
-#define UART0_REF              56
-#define UART1_REF              57
-#define SPI0_REF               58
-#define SPI1_REF               59
-#define NAND_REF               60
-#define I2C0_REF               61
-#define I2C1_REF               62
-#define CAN0_REF               63
-#define CAN1_REF               64
-#define CAN0                   65
-#define CAN1                   66
-#define DLL_REF                        67
-#define ADMA_REF               68
-#define TIMESTAMP_REF          69
-#define AMS_REF                        70
-#define PL0_REF                        71
-#define PL1_REF                        72
-#define PL2_REF                        73
-#define PL3_REF                        74
-#define WDT                    75
-#define IOPLL_INT              76
-#define IOPLL_PRE_SRC          77
-#define IOPLL_HALF             78
-#define IOPLL_INT_MUX          79
-#define IOPLL_POST_SRC         80
-#define RPLL_INT               81
-#define RPLL_PRE_SRC           82
-#define RPLL_HALF              83
-#define RPLL_INT_MUX           84
-#define RPLL_POST_SRC          85
-#define APLL_INT               86
-#define APLL_PRE_SRC           87
-#define APLL_HALF              88
-#define APLL_INT_MUX           89
-#define APLL_POST_SRC          90
-#define DPLL_INT               91
-#define DPLL_PRE_SRC           92
-#define DPLL_HALF              93
-#define DPLL_INT_MUX           94
-#define DPLL_POST_SRC          95
-#define VPLL_INT               96
-#define VPLL_PRE_SRC           97
-#define VPLL_HALF              98
-#define VPLL_INT_MUX           99
-#define VPLL_POST_SRC          100
-#define CAN0_MIO               101
-#define CAN1_MIO               102
-
-#endif

diff --git a/include/dt-bindings/clock/xlnx-zynqmp-clk.h b/include/dt-bindings/clock/xlnx-zynqmp-clk.h
new file mode 100644 (file)
index 0000000..cdc4c0b
--- /dev/null
+++ b/include/dt-bindings/clock/xlnx-zynqmp-clk.h
@@ -0,0 +1,126 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Xilinx Zynq MPSoC Firmware layer
+ *
+ *  Copyright (C) 2014-2018 Xilinx, Inc.
+ *
+ */
+
+#ifndef _DT_BINDINGS_CLK_ZYNQMP_H
+#define _DT_BINDINGS_CLK_ZYNQMP_H
+
+#define IOPLL                  0
+#define RPLL                   1
+#define APLL                   2
+#define DPLL                   3
+#define VPLL                   4
+#define IOPLL_TO_FPD           5
+#define RPLL_TO_FPD            6
+#define APLL_TO_LPD            7
+#define DPLL_TO_LPD            8
+#define VPLL_TO_LPD            9
+#define ACPU                   10
+#define ACPU_HALF              11
+#define DBF_FPD                        12
+#define DBF_LPD                        13
+#define DBG_TRACE              14
+#define DBG_TSTMP              15
+#define DP_VIDEO_REF           16
+#define DP_AUDIO_REF           17
+#define DP_STC_REF             18
+#define GDMA_REF               19
+#define DPDMA_REF              20
+#define DDR_REF                        21
+#define SATA_REF               22
+#define PCIE_REF               23
+#define GPU_REF                        24
+#define GPU_PP0_REF            25
+#define GPU_PP1_REF            26
+#define TOPSW_MAIN             27
+#define TOPSW_LSBUS            28
+#define GTGREF0_REF            29
+#define LPD_SWITCH             30
+#define LPD_LSBUS              31
+#define USB0_BUS_REF           32
+#define USB1_BUS_REF           33
+#define USB3_DUAL_REF          34
+#define USB0                   35
+#define USB1                   36
+#define CPU_R5                 37
+#define CPU_R5_CORE            38
+#define CSU_SPB                        39
+#define CSU_PLL                        40
+#define PCAP                   41
+#define IOU_SWITCH             42
+#define GEM_TSU_REF            43
+#define GEM_TSU                        44
+#define GEM0_TX                        45
+#define GEM1_TX                        46
+#define GEM2_TX                        47
+#define GEM3_TX                        48
+#define GEM0_RX                        49
+#define GEM1_RX                        50
+#define GEM2_RX                        51
+#define GEM3_RX                        52
+#define QSPI_REF               53
+#define SDIO0_REF              54
+#define SDIO1_REF              55
+#define UART0_REF              56
+#define UART1_REF              57
+#define SPI0_REF               58
+#define SPI1_REF               59
+#define NAND_REF               60
+#define I2C0_REF               61
+#define I2C1_REF               62
+#define CAN0_REF               63
+#define CAN1_REF               64
+#define CAN0                   65
+#define CAN1                   66
+#define DLL_REF                        67
+#define ADMA_REF               68
+#define TIMESTAMP_REF          69
+#define AMS_REF                        70
+#define PL0_REF                        71
+#define PL1_REF                        72
+#define PL2_REF                        73
+#define PL3_REF                        74
+#define WDT                    75
+#define IOPLL_INT              76
+#define IOPLL_PRE_SRC          77
+#define IOPLL_HALF             78
+#define IOPLL_INT_MUX          79
+#define IOPLL_POST_SRC         80
+#define RPLL_INT               81
+#define RPLL_PRE_SRC           82
+#define RPLL_HALF              83
+#define RPLL_INT_MUX           84
+#define RPLL_POST_SRC          85
+#define APLL_INT               86
+#define APLL_PRE_SRC           87
+#define APLL_HALF              88
+#define APLL_INT_MUX           89
+#define APLL_POST_SRC          90
+#define DPLL_INT               91
+#define DPLL_PRE_SRC           92
+#define DPLL_HALF              93
+#define DPLL_INT_MUX           94
+#define DPLL_POST_SRC          95
+#define VPLL_INT               96
+#define VPLL_PRE_SRC           97
+#define VPLL_HALF              98
+#define VPLL_INT_MUX           99
+#define VPLL_POST_SRC          100
+#define CAN0_MIO               101
+#define CAN1_MIO               102
+#define ACPU_FULL              103
+#define GEM0_REF               104
+#define GEM1_REF               105
+#define GEM2_REF               106
+#define GEM3_REF               107
+#define GEM0_REF_UNG           108
+#define GEM1_REF_UNG           109
+#define GEM2_REF_UNG           110
+#define GEM3_REF_UNG           111
+#define LPD_WDT                        112
+
+#endif

diff --git a/include/dt-bindings/firmware/imx/rsrc.h b/include/dt-bindings/firmware/imx/rsrc.h
index 4481f2d..4e61f64 100644 (file)
--- a/include/dt-bindings/firmware/imx/rsrc.h
+++ b/include/dt-bindings/firmware/imx/rsrc.h
@@ -36,15 +36,11 @@
 #define IMX_SC_R_DC_0_BLIT1            20
 #define IMX_SC_R_DC_0_BLIT2            21
 #define IMX_SC_R_DC_0_BLIT_OUT         22
-#define IMX_SC_R_DC_0_CAPTURE0         23
-#define IMX_SC_R_DC_0_CAPTURE1         24
+#define IMX_SC_R_PERF                  23
 #define IMX_SC_R_DC_0_WARP             25
-#define IMX_SC_R_DC_0_INTEGRAL0                26
-#define IMX_SC_R_DC_0_INTEGRAL1                27
 #define IMX_SC_R_DC_0_VIDEO0           28
 #define IMX_SC_R_DC_0_VIDEO1           29
 #define IMX_SC_R_DC_0_FRAC0            30
-#define IMX_SC_R_DC_0_FRAC1            31
 #define IMX_SC_R_DC_0                  32
 #define IMX_SC_R_GPU_2_PID0            33
 #define IMX_SC_R_DC_0_PLL_0            34
@@ -53,17 +49,11 @@
 #define IMX_SC_R_DC_1_BLIT1            37
 #define IMX_SC_R_DC_1_BLIT2            38
 #define IMX_SC_R_DC_1_BLIT_OUT         39
-#define IMX_SC_R_DC_1_CAPTURE0         40
-#define IMX_SC_R_DC_1_CAPTURE1         41
 #define IMX_SC_R_DC_1_WARP             42
-#define IMX_SC_R_DC_1_INTEGRAL0                43
-#define IMX_SC_R_DC_1_INTEGRAL1                44
 #define IMX_SC_R_DC_1_VIDEO0           45
 #define IMX_SC_R_DC_1_VIDEO1           46
 #define IMX_SC_R_DC_1_FRAC0            47
-#define IMX_SC_R_DC_1_FRAC1            48
 #define IMX_SC_R_DC_1                  49
-#define IMX_SC_R_GPU_3_PID0            50
 #define IMX_SC_R_DC_1_PLL_0            51
 #define IMX_SC_R_DC_1_PLL_1            52
 #define IMX_SC_R_SPI_0                 53
@@ -303,8 +293,6 @@
 #define IMX_SC_R_M4_0_UART             287
 #define IMX_SC_R_M4_0_I2C              288
 #define IMX_SC_R_M4_0_INTMUX           289
-#define IMX_SC_R_M4_0_SIM              290
-#define IMX_SC_R_M4_0_WDOG             291
 #define IMX_SC_R_M4_0_MU_0B            292
 #define IMX_SC_R_M4_0_MU_0A0           293
 #define IMX_SC_R_M4_0_MU_0A1           294
@@ -323,8 +311,6 @@
 #define IMX_SC_R_M4_1_UART             307
 #define IMX_SC_R_M4_1_I2C              308
 #define IMX_SC_R_M4_1_INTMUX           309
-#define IMX_SC_R_M4_1_SIM              310
-#define IMX_SC_R_M4_1_WDOG             311
 #define IMX_SC_R_M4_1_MU_0B            312
 #define IMX_SC_R_M4_1_MU_0A0           313
 #define IMX_SC_R_M4_1_MU_0A1           314
@@ -337,7 +323,7 @@
 #define IMX_SC_R_IRQSTR_SCU2           321
 #define IMX_SC_R_IRQSTR_DSP            322
 #define IMX_SC_R_ELCDIF_PLL            323
-#define IMX_SC_R_UNUSED6               324
+#define IMX_SC_R_OCRAM                 324
 #define IMX_SC_R_AUDIO_PLL_0           325
 #define IMX_SC_R_PI_0                  326
 #define IMX_SC_R_PI_0_PWM_0            327
@@ -554,6 +540,11 @@
 #define IMX_SC_R_VPU_MU_3              538
 #define IMX_SC_R_VPU_ENC_1             539
 #define IMX_SC_R_VPU                   540
-#define IMX_SC_R_LAST                  541
+#define IMX_SC_R_DMA_5_CH0             541
+#define IMX_SC_R_DMA_5_CH1             542
+#define IMX_SC_R_DMA_5_CH2             543
+#define IMX_SC_R_DMA_5_CH3             544
+#define IMX_SC_R_ATTESTATION           545
+#define IMX_SC_R_LAST                  546
 
 #endif /* __DT_BINDINGS_RSCRC_IMX_H */

diff --git a/include/dt-bindings/pinctrl/am33xx.h b/include/dt-bindings/pinctrl/am33xx.h
index 7d947a5..17877e8 100644 (file)
--- a/include/dt-bindings/pinctrl/am33xx.h
+++ b/include/dt-bindings/pinctrl/am33xx.h
@@ -40,5 +40,133 @@
 #undef PIN_OFF_INPUT_PULLDOWN
 #undef PIN_OFF_WAKEUPENABLE
 
-#endif
+#define AM335X_PIN_OFFSET_MIN                  0x0800U
+
+#define AM335X_PIN_GPMC_AD0                    0x800
+#define AM335X_PIN_GPMC_AD1                    0x804
+#define AM335X_PIN_GPMC_AD2                    0x808
+#define AM335X_PIN_GPMC_AD3                    0x80c
+#define AM335X_PIN_GPMC_AD4                    0x810
+#define AM335X_PIN_GPMC_AD5                    0x814
+#define AM335X_PIN_GPMC_AD6                    0x818
+#define AM335X_PIN_GPMC_AD7                    0x81c
+#define AM335X_PIN_GPMC_AD8                    0x820
+#define AM335X_PIN_GPMC_AD9                    0x824
+#define AM335X_PIN_GPMC_AD10                   0x828
+#define AM335X_PIN_GPMC_AD11                   0x82c
+#define AM335X_PIN_GPMC_AD12                   0x830
+#define AM335X_PIN_GPMC_AD13                   0x834
+#define AM335X_PIN_GPMC_AD14                   0x838
+#define AM335X_PIN_GPMC_AD15                   0x83c
+#define AM335X_PIN_GPMC_A0                     0x840
+#define AM335X_PIN_GPMC_A1                     0x844
+#define AM335X_PIN_GPMC_A2                     0x848
+#define AM335X_PIN_GPMC_A3                     0x84c
+#define AM335X_PIN_GPMC_A4                     0x850
+#define AM335X_PIN_GPMC_A5                     0x854
+#define AM335X_PIN_GPMC_A6                     0x858
+#define AM335X_PIN_GPMC_A7                     0x85c
+#define AM335X_PIN_GPMC_A8                     0x860
+#define AM335X_PIN_GPMC_A9                     0x864
+#define AM335X_PIN_GPMC_A10                    0x868
+#define AM335X_PIN_GPMC_A11                    0x86c
+#define AM335X_PIN_GPMC_WAIT0                  0x870
+#define AM335X_PIN_GPMC_WPN                    0x874
+#define AM335X_PIN_GPMC_BEN1                   0x878
+#define AM335X_PIN_GPMC_CSN0                   0x87c
+#define AM335X_PIN_GPMC_CSN1                   0x880
+#define AM335X_PIN_GPMC_CSN2                   0x884
+#define AM335X_PIN_GPMC_CSN3                   0x888
+#define AM335X_PIN_GPMC_CLK                    0x88c
+#define AM335X_PIN_GPMC_ADVN_ALE               0x890
+#define AM335X_PIN_GPMC_OEN_REN                        0x894
+#define AM335X_PIN_GPMC_WEN                    0x898
+#define AM335X_PIN_GPMC_BEN0_CLE               0x89c
+#define AM335X_PIN_LCD_DATA0                   0x8a0
+#define AM335X_PIN_LCD_DATA1                   0x8a4
+#define AM335X_PIN_LCD_DATA2                   0x8a8
+#define AM335X_PIN_LCD_DATA3                   0x8ac
+#define AM335X_PIN_LCD_DATA4                   0x8b0
+#define AM335X_PIN_LCD_DATA5                   0x8b4
+#define AM335X_PIN_LCD_DATA6                   0x8b8
+#define AM335X_PIN_LCD_DATA7                   0x8bc
+#define AM335X_PIN_LCD_DATA8                   0x8c0
+#define AM335X_PIN_LCD_DATA9                   0x8c4
+#define AM335X_PIN_LCD_DATA10                  0x8c8
+#define AM335X_PIN_LCD_DATA11                  0x8cc
+#define AM335X_PIN_LCD_DATA12                  0x8d0
+#define AM335X_PIN_LCD_DATA13                  0x8d4
+#define AM335X_PIN_LCD_DATA14                  0x8d8
+#define AM335X_PIN_LCD_DATA15                  0x8dc
+#define AM335X_PIN_LCD_VSYNC                   0x8e0
+#define AM335X_PIN_LCD_HSYNC                   0x8e4
+#define AM335X_PIN_LCD_PCLK                    0x8e8
+#define AM335X_PIN_LCD_AC_BIAS_EN              0x8ec
+#define AM335X_PIN_MMC0_DAT3                   0x8f0
+#define AM335X_PIN_MMC0_DAT2                   0x8f4
+#define AM335X_PIN_MMC0_DAT1                   0x8f8
+#define AM335X_PIN_MMC0_DAT0                   0x8fc
+#define AM335X_PIN_MMC0_CLK                    0x900
+#define AM335X_PIN_MMC0_CMD                    0x904
+#define AM335X_PIN_MII1_COL                    0x908
+#define AM335X_PIN_MII1_CRS                    0x90c
+#define AM335X_PIN_MII1_RX_ER                  0x910
+#define AM335X_PIN_MII1_TX_EN                  0x914
+#define AM335X_PIN_MII1_RX_DV                  0x918
+#define AM335X_PIN_MII1_TXD3                   0x91c
+#define AM335X_PIN_MII1_TXD2                   0x920
+#define AM335X_PIN_MII1_TXD1                   0x924
+#define AM335X_PIN_MII1_TXD0                   0x928
+#define AM335X_PIN_MII1_TX_CLK                 0x92c
+#define AM335X_PIN_MII1_RX_CLK                 0x930
+#define AM335X_PIN_MII1_RXD3                   0x934
+#define AM335X_PIN_MII1_RXD2                   0x938
+#define AM335X_PIN_MII1_RXD1                   0x93c
+#define AM335X_PIN_MII1_RXD0                   0x940
+#define AM335X_PIN_RMII1_REF_CLK               0x944
+#define AM335X_PIN_MDIO                                0x948
+#define AM335X_PIN_MDC                         0x94c
+#define AM335X_PIN_SPI0_SCLK                   0x950
+#define AM335X_PIN_SPI0_D0                     0x954
+#define AM335X_PIN_SPI0_D1                     0x958
+#define AM335X_PIN_SPI0_CS0                    0x95c
+#define AM335X_PIN_SPI0_CS1                    0x960
+#define AM335X_PIN_ECAP0_IN_PWM0_OUT           0x964
+#define AM335X_PIN_UART0_CTSN                  0x968
+#define AM335X_PIN_UART0_RTSN                  0x96c
+#define AM335X_PIN_UART0_RXD                   0x970
+#define AM335X_PIN_UART0_TXD                   0x974
+#define AM335X_PIN_UART1_CTSN                  0x978
+#define AM335X_PIN_UART1_RTSN                  0x97c
+#define AM335X_PIN_UART1_RXD                   0x980
+#define AM335X_PIN_UART1_TXD                   0x984
+#define AM335X_PIN_I2C0_SDA                    0x988
+#define AM335X_PIN_I2C0_SCL                    0x98c
+#define AM335X_PIN_MCASP0_ACLKX                        0x990
+#define AM335X_PIN_MCASP0_FSX                  0x994
+#define AM335X_PIN_MCASP0_AXR0                 0x998
+#define AM335X_PIN_MCASP0_AHCLKR               0x99c
+#define AM335X_PIN_MCASP0_ACLKR                        0x9a0
+#define AM335X_PIN_MCASP0_FSR                  0x9a4
+#define AM335X_PIN_MCASP0_AXR1                 0x9a8
+#define AM335X_PIN_MCASP0_AHCLKX               0x9ac
+#define AM335X_PIN_XDMA_EVENT_INTR0            0x9b0
+#define AM335X_PIN_XDMA_EVENT_INTR1            0x9b4
+#define AM335X_PIN_WARMRSTN                    0x9b8
+#define AM335X_PIN_NNMI                                0x9c0
+#define AM335X_PIN_TMS                         0x9d0
+#define AM335X_PIN_TDI                         0x9d4
+#define AM335X_PIN_TDO                         0x9d8
+#define AM335X_PIN_TCK                         0x9dc
+#define AM335X_PIN_TRSTN                       0x9e0
+#define AM335X_PIN_EMU0                                0x9e4
+#define AM335X_PIN_EMU1                                0x9e8
+#define AM335X_PIN_RTC_PWRONRSTN               0x9f8
+#define AM335X_PIN_PMIC_POWER_EN               0x9fc
+#define AM335X_PIN_EXT_WAKEUP                  0xa00
+#define AM335X_PIN_USB0_DRVVBUS                        0xa1c
+#define AM335X_PIN_USB1_DRVVBUS                        0xa34
 
+#define AM335X_PIN_OFFSET_MAX                  0x0a34U
+
+#endif

diff --git a/include/dt-bindings/pinctrl/omap.h b/include/dt-bindings/pinctrl/omap.h
index 49b5dea..6257180 100644 (file)
--- a/include/dt-bindings/pinctrl/omap.h
+++ b/include/dt-bindings/pinctrl/omap.h
@@ -65,6 +65,7 @@
 #define DM814X_IOPAD(pa, val)          OMAP_IOPAD_OFFSET((pa), 0x0800) (val)
 #define DM816X_IOPAD(pa, val)          OMAP_IOPAD_OFFSET((pa), 0x0800) (val)
 #define AM33XX_IOPAD(pa, val)          OMAP_IOPAD_OFFSET((pa), 0x0800) (val)
+#define AM33XX_PADCONF(pa, dir, mux)   OMAP_IOPAD_OFFSET((pa), 0x0800) ((dir) | (mux))
 
 /*
  * Macros to allow using the offset from the padconf physical address

diff --git a/include/dt-bindings/power/r8a77965-sysc.h b/include/dt-bindings/power/r8a77965-sysc.h
index 05a4b59..de82d8a 100644 (file)
--- a/include/dt-bindings/power/r8a77965-sysc.h
+++ b/include/dt-bindings/power/r8a77965-sysc.h
@@ -21,7 +21,6 @@
 #define R8A77965_PD_A3VC               14
 #define R8A77965_PD_3DG_A              17
 #define R8A77965_PD_3DG_B              18
-#define R8A77965_PD_A3IR               24
 #define R8A77965_PD_A2VC1              26
 
 /* Always-on power area */