drm/amd/powerplay: maximum code sharing around watermarks setting

Maximum code sharing.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 02e335a..5023df3 100644 (file)
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -1486,23 +1486,12 @@ static int amdgpu_dm_smu_write_watermarks_table(struct amdgpu_device *adev)
                return 0;
        }
 
-       mutex_lock(&smu->mutex);
-
-       /* pass data to smu controller */
-       if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
-                       !(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
-               ret = smu_write_watermarks_table(smu);
-
-               if (ret) {
-                       mutex_unlock(&smu->mutex);
-                       DRM_ERROR("Failed to update WMTABLE!\n");
-                       return ret;
-               }
-               smu->watermarks_bitmap |= WATERMARKS_LOADED;
+       ret = smu_write_watermarks_table(smu);
+       if (ret) {
+               DRM_ERROR("Failed to update WMTABLE!\n");
+               return ret;
        }
 
-       mutex_unlock(&smu->mutex);
-
        return 0;
 }
 

diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index 6006f7a..b9ff398 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -1706,35 +1706,34 @@ int smu_allow_xgmi_power_down(struct smu_context *smu, bool en)
 
 int smu_write_watermarks_table(struct smu_context *smu)
 {
-       void *watermarks_table = smu->smu_table.watermarks_table;
+       int ret = 0;
 
-       if (!watermarks_table)
-               return -EINVAL;
+       if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
+               return -EOPNOTSUPP;
 
-       return smu_update_table(smu,
-                               SMU_TABLE_WATERMARKS,
-                               0,
-                               watermarks_table,
-                               true);
+       mutex_lock(&smu->mutex);
+
+       ret = smu_set_watermarks_table(smu, NULL);
+
+       mutex_unlock(&smu->mutex);
+
+       return ret;
 }
 
 int smu_set_watermarks_for_clock_ranges(struct smu_context *smu,
                struct dm_pp_wm_sets_with_clock_ranges_soc15 *clock_ranges)
 {
-       void *table = smu->smu_table.watermarks_table;
+       int ret = 0;
 
        if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
                return -EOPNOTSUPP;
 
-       if (!table)
-               return -EINVAL;
-
        mutex_lock(&smu->mutex);
 
        if (!smu->disable_watermark &&
                        smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&
                        smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
-               smu_set_watermarks_table(smu, table, clock_ranges);
+               ret = smu_set_watermarks_table(smu, clock_ranges);
 
                if (!(smu->watermarks_bitmap & WATERMARKS_EXIST)) {
                        smu->watermarks_bitmap |= WATERMARKS_EXIST;
@@ -1744,7 +1743,7 @@ int smu_set_watermarks_for_clock_ranges(struct smu_context *smu,
 
        mutex_unlock(&smu->mutex);
 
-       return 0;
+       return ret;
 }
 
 int smu_set_ac_dc(struct smu_context *smu)

diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index 4f57104..a8f98f3 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -493,7 +493,7 @@ struct pptable_funcs {
        int (*tables_init)(struct smu_context *smu, struct smu_table *tables);
        int (*get_fan_speed_percent)(struct smu_context *smu, uint32_t *speed);
        int (*get_fan_speed_rpm)(struct smu_context *smu, uint32_t *speed);
-       int (*set_watermarks_table)(struct smu_context *smu, void *watermarks,
+       int (*set_watermarks_table)(struct smu_context *smu,
                                    struct dm_pp_wm_sets_with_clock_ranges_soc15 *clock_ranges);
        int (*get_thermal_temperature_range)(struct smu_context *smu, struct smu_temperature_range *range);
        int (*get_uclk_dpm_states)(struct smu_context *smu, uint32_t *clocks_in_khz, uint32_t *num_states);

diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
index 25ca6c4..4ea2cd5 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
@@ -1577,67 +1577,65 @@ static int navi10_notify_smc_display_config(struct smu_context *smu)
 }
 
 static int navi10_set_watermarks_table(struct smu_context *smu,
-                                      void *watermarks, struct
-                                      dm_pp_wm_sets_with_clock_ranges_soc15
-                                      *clock_ranges)
+                                      struct dm_pp_wm_sets_with_clock_ranges_soc15 *clock_ranges)
 {
-       int i;
+       Watermarks_t *table = smu->smu_table.watermarks_table;
        int ret = 0;
-       Watermarks_t *table = watermarks;
+       int i;
 
-       if (!table || !clock_ranges)
-               return -EINVAL;
+       if (clock_ranges) {
+               if (clock_ranges->num_wm_dmif_sets > 4 ||
+                   clock_ranges->num_wm_mcif_sets > 4)
+                       return -EINVAL;
 
-       if (clock_ranges->num_wm_dmif_sets > 4 ||
-           clock_ranges->num_wm_mcif_sets > 4)
-               return -EINVAL;
+               for (i = 0; i < clock_ranges->num_wm_dmif_sets; i++) {
+                       table->WatermarkRow[1][i].MinClock =
+                               cpu_to_le16((uint16_t)
+                               (clock_ranges->wm_dmif_clocks_ranges[i].wm_min_dcfclk_clk_in_khz /
+                               1000));
+                       table->WatermarkRow[1][i].MaxClock =
+                               cpu_to_le16((uint16_t)
+                               (clock_ranges->wm_dmif_clocks_ranges[i].wm_max_dcfclk_clk_in_khz /
+                               1000));
+                       table->WatermarkRow[1][i].MinUclk =
+                               cpu_to_le16((uint16_t)
+                               (clock_ranges->wm_dmif_clocks_ranges[i].wm_min_mem_clk_in_khz /
+                               1000));
+                       table->WatermarkRow[1][i].MaxUclk =
+                               cpu_to_le16((uint16_t)
+                               (clock_ranges->wm_dmif_clocks_ranges[i].wm_max_mem_clk_in_khz /
+                               1000));
+                       table->WatermarkRow[1][i].WmSetting = (uint8_t)
+                                       clock_ranges->wm_dmif_clocks_ranges[i].wm_set_id;
+               }
 
-       for (i = 0; i < clock_ranges->num_wm_dmif_sets; i++) {
-               table->WatermarkRow[1][i].MinClock =
-                       cpu_to_le16((uint16_t)
-                       (clock_ranges->wm_dmif_clocks_ranges[i].wm_min_dcfclk_clk_in_khz /
-                       1000));
-               table->WatermarkRow[1][i].MaxClock =
-                       cpu_to_le16((uint16_t)
-                       (clock_ranges->wm_dmif_clocks_ranges[i].wm_max_dcfclk_clk_in_khz /
-                       1000));
-               table->WatermarkRow[1][i].MinUclk =
-                       cpu_to_le16((uint16_t)
-                       (clock_ranges->wm_dmif_clocks_ranges[i].wm_min_mem_clk_in_khz /
-                       1000));
-               table->WatermarkRow[1][i].MaxUclk =
-                       cpu_to_le16((uint16_t)
-                       (clock_ranges->wm_dmif_clocks_ranges[i].wm_max_mem_clk_in_khz /
-                       1000));
-               table->WatermarkRow[1][i].WmSetting = (uint8_t)
-                               clock_ranges->wm_dmif_clocks_ranges[i].wm_set_id;
-       }
+               for (i = 0; i < clock_ranges->num_wm_mcif_sets; i++) {
+                       table->WatermarkRow[0][i].MinClock =
+                               cpu_to_le16((uint16_t)
+                               (clock_ranges->wm_mcif_clocks_ranges[i].wm_min_socclk_clk_in_khz /
+                               1000));
+                       table->WatermarkRow[0][i].MaxClock =
+                               cpu_to_le16((uint16_t)
+                               (clock_ranges->wm_mcif_clocks_ranges[i].wm_max_socclk_clk_in_khz /
+                               1000));
+                       table->WatermarkRow[0][i].MinUclk =
+                               cpu_to_le16((uint16_t)
+                               (clock_ranges->wm_mcif_clocks_ranges[i].wm_min_mem_clk_in_khz /
+                               1000));
+                       table->WatermarkRow[0][i].MaxUclk =
+                               cpu_to_le16((uint16_t)
+                               (clock_ranges->wm_mcif_clocks_ranges[i].wm_max_mem_clk_in_khz /
+                               1000));
+                       table->WatermarkRow[0][i].WmSetting = (uint8_t)
+                                       clock_ranges->wm_mcif_clocks_ranges[i].wm_set_id;
+               }
 
-       for (i = 0; i < clock_ranges->num_wm_mcif_sets; i++) {
-               table->WatermarkRow[0][i].MinClock =
-                       cpu_to_le16((uint16_t)
-                       (clock_ranges->wm_mcif_clocks_ranges[i].wm_min_socclk_clk_in_khz /
-                       1000));
-               table->WatermarkRow[0][i].MaxClock =
-                       cpu_to_le16((uint16_t)
-                       (clock_ranges->wm_mcif_clocks_ranges[i].wm_max_socclk_clk_in_khz /
-                       1000));
-               table->WatermarkRow[0][i].MinUclk =
-                       cpu_to_le16((uint16_t)
-                       (clock_ranges->wm_mcif_clocks_ranges[i].wm_min_mem_clk_in_khz /
-                       1000));
-               table->WatermarkRow[0][i].MaxUclk =
-                       cpu_to_le16((uint16_t)
-                       (clock_ranges->wm_mcif_clocks_ranges[i].wm_max_mem_clk_in_khz /
-                       1000));
-               table->WatermarkRow[0][i].WmSetting = (uint8_t)
-                               clock_ranges->wm_mcif_clocks_ranges[i].wm_set_id;
+               smu->watermarks_bitmap |= WATERMARKS_EXIST;
        }
 
-       smu->watermarks_bitmap |= WATERMARKS_EXIST;
-
        /* pass data to smu controller */
-       if (!(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
+       if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
+            !(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
                ret = smu_write_watermarks_table(smu);
                if (ret) {
                        dev_err(smu->adev->dev, "Failed to update WMTABLE!");

diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
index 2e0a540..8763073 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
@@ -841,59 +841,58 @@ static int renoir_set_performance_level(struct smu_context *smu,
  */
 static int renoir_set_watermarks_table(
                struct smu_context *smu,
-               void *watermarks,
                struct dm_pp_wm_sets_with_clock_ranges_soc15 *clock_ranges)
 {
-       int i;
+       Watermarks_t *table = smu->smu_table.watermarks_table;
        int ret = 0;
-       Watermarks_t *table = watermarks;
+       int i;
 
-       if (!table || !clock_ranges)
-               return -EINVAL;
+       if (clock_ranges) {
+               if (clock_ranges->num_wm_dmif_sets > 4 ||
+                               clock_ranges->num_wm_mcif_sets > 4)
+                       return -EINVAL;
 
-       if (clock_ranges->num_wm_dmif_sets > 4 ||
-                       clock_ranges->num_wm_mcif_sets > 4)
-               return -EINVAL;
+               /* save into smu->smu_table.tables[SMU_TABLE_WATERMARKS]->cpu_addr*/
+               for (i = 0; i < clock_ranges->num_wm_dmif_sets; i++) {
+                       table->WatermarkRow[WM_DCFCLK][i].MinClock =
+                               cpu_to_le16((uint16_t)
+                               (clock_ranges->wm_dmif_clocks_ranges[i].wm_min_dcfclk_clk_in_khz));
+                       table->WatermarkRow[WM_DCFCLK][i].MaxClock =
+                               cpu_to_le16((uint16_t)
+                               (clock_ranges->wm_dmif_clocks_ranges[i].wm_max_dcfclk_clk_in_khz));
+                       table->WatermarkRow[WM_DCFCLK][i].MinMclk =
+                               cpu_to_le16((uint16_t)
+                               (clock_ranges->wm_dmif_clocks_ranges[i].wm_min_mem_clk_in_khz));
+                       table->WatermarkRow[WM_DCFCLK][i].MaxMclk =
+                               cpu_to_le16((uint16_t)
+                               (clock_ranges->wm_dmif_clocks_ranges[i].wm_max_mem_clk_in_khz));
+                       table->WatermarkRow[WM_DCFCLK][i].WmSetting = (uint8_t)
+                                       clock_ranges->wm_dmif_clocks_ranges[i].wm_set_id;
+               }
 
-       /* save into smu->smu_table.tables[SMU_TABLE_WATERMARKS]->cpu_addr*/
-       for (i = 0; i < clock_ranges->num_wm_dmif_sets; i++) {
-               table->WatermarkRow[WM_DCFCLK][i].MinClock =
-                       cpu_to_le16((uint16_t)
-                       (clock_ranges->wm_dmif_clocks_ranges[i].wm_min_dcfclk_clk_in_khz));
-               table->WatermarkRow[WM_DCFCLK][i].MaxClock =
-                       cpu_to_le16((uint16_t)
-                       (clock_ranges->wm_dmif_clocks_ranges[i].wm_max_dcfclk_clk_in_khz));
-               table->WatermarkRow[WM_DCFCLK][i].MinMclk =
-                       cpu_to_le16((uint16_t)
-                       (clock_ranges->wm_dmif_clocks_ranges[i].wm_min_mem_clk_in_khz));
-               table->WatermarkRow[WM_DCFCLK][i].MaxMclk =
-                       cpu_to_le16((uint16_t)
-                       (clock_ranges->wm_dmif_clocks_ranges[i].wm_max_mem_clk_in_khz));
-               table->WatermarkRow[WM_DCFCLK][i].WmSetting = (uint8_t)
-                               clock_ranges->wm_dmif_clocks_ranges[i].wm_set_id;
-       }
+               for (i = 0; i < clock_ranges->num_wm_mcif_sets; i++) {
+                       table->WatermarkRow[WM_SOCCLK][i].MinClock =
+                               cpu_to_le16((uint16_t)
+                               (clock_ranges->wm_mcif_clocks_ranges[i].wm_min_socclk_clk_in_khz));
+                       table->WatermarkRow[WM_SOCCLK][i].MaxClock =
+                               cpu_to_le16((uint16_t)
+                               (clock_ranges->wm_mcif_clocks_ranges[i].wm_max_socclk_clk_in_khz));
+                       table->WatermarkRow[WM_SOCCLK][i].MinMclk =
+                               cpu_to_le16((uint16_t)
+                               (clock_ranges->wm_mcif_clocks_ranges[i].wm_min_mem_clk_in_khz));
+                       table->WatermarkRow[WM_SOCCLK][i].MaxMclk =
+                               cpu_to_le16((uint16_t)
+                               (clock_ranges->wm_mcif_clocks_ranges[i].wm_max_mem_clk_in_khz));
+                       table->WatermarkRow[WM_SOCCLK][i].WmSetting = (uint8_t)
+                                       clock_ranges->wm_mcif_clocks_ranges[i].wm_set_id;
+               }
 
-       for (i = 0; i < clock_ranges->num_wm_mcif_sets; i++) {
-               table->WatermarkRow[WM_SOCCLK][i].MinClock =
-                       cpu_to_le16((uint16_t)
-                       (clock_ranges->wm_mcif_clocks_ranges[i].wm_min_socclk_clk_in_khz));
-               table->WatermarkRow[WM_SOCCLK][i].MaxClock =
-                       cpu_to_le16((uint16_t)
-                       (clock_ranges->wm_mcif_clocks_ranges[i].wm_max_socclk_clk_in_khz));
-               table->WatermarkRow[WM_SOCCLK][i].MinMclk =
-                       cpu_to_le16((uint16_t)
-                       (clock_ranges->wm_mcif_clocks_ranges[i].wm_min_mem_clk_in_khz));
-               table->WatermarkRow[WM_SOCCLK][i].MaxMclk =
-                       cpu_to_le16((uint16_t)
-                       (clock_ranges->wm_mcif_clocks_ranges[i].wm_max_mem_clk_in_khz));
-               table->WatermarkRow[WM_SOCCLK][i].WmSetting = (uint8_t)
-                               clock_ranges->wm_mcif_clocks_ranges[i].wm_set_id;
+               smu->watermarks_bitmap |= WATERMARKS_EXIST;
        }
 
-       smu->watermarks_bitmap |= WATERMARKS_EXIST;
-
        /* pass data to smu controller */
-       if (!(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
+       if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
+            !(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
                ret = smu_write_watermarks_table(smu);
                if (ret) {
                        dev_err(smu->adev->dev, "Failed to update WMTABLE!");

diff --git a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
index 2d49d30..830d93a 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
@@ -1380,66 +1380,65 @@ static int sienna_cichlid_notify_smc_display_config(struct smu_context *smu)
 }
 
 static int sienna_cichlid_set_watermarks_table(struct smu_context *smu,
-                                      void *watermarks, struct
-                                      dm_pp_wm_sets_with_clock_ranges_soc15
-                                      *clock_ranges)
+                                              struct dm_pp_wm_sets_with_clock_ranges_soc15
+                                              *clock_ranges)
 {
-       int i;
+       Watermarks_t *table = smu->smu_table.watermarks_table;
        int ret = 0;
-       Watermarks_t *table = watermarks;
+       int i;
 
-       if (!table || !clock_ranges)
-               return -EINVAL;
+       if (clock_ranges) {
+               if (clock_ranges->num_wm_dmif_sets > 4 ||
+                   clock_ranges->num_wm_mcif_sets > 4)
+                       return -EINVAL;
+
+               for (i = 0; i < clock_ranges->num_wm_dmif_sets; i++) {
+                       table->WatermarkRow[1][i].MinClock =
+                               cpu_to_le16((uint16_t)
+                               (clock_ranges->wm_dmif_clocks_ranges[i].wm_min_dcfclk_clk_in_khz /
+                               1000));
+                       table->WatermarkRow[1][i].MaxClock =
+                               cpu_to_le16((uint16_t)
+                               (clock_ranges->wm_dmif_clocks_ranges[i].wm_max_dcfclk_clk_in_khz /
+                               1000));
+                       table->WatermarkRow[1][i].MinUclk =
+                               cpu_to_le16((uint16_t)
+                               (clock_ranges->wm_dmif_clocks_ranges[i].wm_min_mem_clk_in_khz /
+                               1000));
+                       table->WatermarkRow[1][i].MaxUclk =
+                               cpu_to_le16((uint16_t)
+                               (clock_ranges->wm_dmif_clocks_ranges[i].wm_max_mem_clk_in_khz /
+                               1000));
+                       table->WatermarkRow[1][i].WmSetting = (uint8_t)
+                                       clock_ranges->wm_dmif_clocks_ranges[i].wm_set_id;
+               }
 
-       if (clock_ranges->num_wm_dmif_sets > 4 ||
-           clock_ranges->num_wm_mcif_sets > 4)
-                return -EINVAL;
-
-        for (i = 0; i < clock_ranges->num_wm_dmif_sets; i++) {
-               table->WatermarkRow[1][i].MinClock =
-                       cpu_to_le16((uint16_t)
-                       (clock_ranges->wm_dmif_clocks_ranges[i].wm_min_dcfclk_clk_in_khz /
-                       1000));
-               table->WatermarkRow[1][i].MaxClock =
-                       cpu_to_le16((uint16_t)
-                       (clock_ranges->wm_dmif_clocks_ranges[i].wm_max_dcfclk_clk_in_khz /
-                       1000));
-               table->WatermarkRow[1][i].MinUclk =
-                       cpu_to_le16((uint16_t)
-                       (clock_ranges->wm_dmif_clocks_ranges[i].wm_min_mem_clk_in_khz /
-                       1000));
-               table->WatermarkRow[1][i].MaxUclk =
-                       cpu_to_le16((uint16_t)
-                       (clock_ranges->wm_dmif_clocks_ranges[i].wm_max_mem_clk_in_khz /
-                       1000));
-               table->WatermarkRow[1][i].WmSetting = (uint8_t)
-                               clock_ranges->wm_dmif_clocks_ranges[i].wm_set_id;
-        }
-
-       for (i = 0; i < clock_ranges->num_wm_mcif_sets; i++) {
-               table->WatermarkRow[0][i].MinClock =
-                       cpu_to_le16((uint16_t)
-                       (clock_ranges->wm_mcif_clocks_ranges[i].wm_min_socclk_clk_in_khz /
-                       1000));
-               table->WatermarkRow[0][i].MaxClock =
-                       cpu_to_le16((uint16_t)
-                       (clock_ranges->wm_mcif_clocks_ranges[i].wm_max_socclk_clk_in_khz /
-                       1000));
-               table->WatermarkRow[0][i].MinUclk =
-                       cpu_to_le16((uint16_t)
-                       (clock_ranges->wm_mcif_clocks_ranges[i].wm_min_mem_clk_in_khz /
-                       1000));
-               table->WatermarkRow[0][i].MaxUclk =
-                       cpu_to_le16((uint16_t)
-                       (clock_ranges->wm_mcif_clocks_ranges[i].wm_max_mem_clk_in_khz /
-                       1000));
-               table->WatermarkRow[0][i].WmSetting = (uint8_t)
-                               clock_ranges->wm_mcif_clocks_ranges[i].wm_set_id;
-        }
-
-       smu->watermarks_bitmap |= WATERMARKS_EXIST;
-
-       if (!(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
+               for (i = 0; i < clock_ranges->num_wm_mcif_sets; i++) {
+                       table->WatermarkRow[0][i].MinClock =
+                               cpu_to_le16((uint16_t)
+                               (clock_ranges->wm_mcif_clocks_ranges[i].wm_min_socclk_clk_in_khz /
+                               1000));
+                       table->WatermarkRow[0][i].MaxClock =
+                               cpu_to_le16((uint16_t)
+                               (clock_ranges->wm_mcif_clocks_ranges[i].wm_max_socclk_clk_in_khz /
+                               1000));
+                       table->WatermarkRow[0][i].MinUclk =
+                               cpu_to_le16((uint16_t)
+                               (clock_ranges->wm_mcif_clocks_ranges[i].wm_min_mem_clk_in_khz /
+                               1000));
+                       table->WatermarkRow[0][i].MaxUclk =
+                               cpu_to_le16((uint16_t)
+                               (clock_ranges->wm_mcif_clocks_ranges[i].wm_max_mem_clk_in_khz /
+                               1000));
+                       table->WatermarkRow[0][i].WmSetting = (uint8_t)
+                                       clock_ranges->wm_mcif_clocks_ranges[i].wm_set_id;
+               }
+
+               smu->watermarks_bitmap |= WATERMARKS_EXIST;
+       }
+
+       if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
+            !(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
                ret = smu_write_watermarks_table(smu);
                if (ret) {
                        dev_err(smu->adev->dev, "Failed to update WMTABLE!");

diff --git a/drivers/gpu/drm/amd/powerplay/smu_internal.h b/drivers/gpu/drm/amd/powerplay/smu_internal.h
index a27e05a..7847272 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/smu_internal.h
+++ b/drivers/gpu/drm/amd/powerplay/smu_internal.h
@@ -79,7 +79,7 @@
 #define smu_get_current_shallow_sleep_clocks(smu, clocks)              smu_ppt_funcs(get_current_shallow_sleep_clocks, 0, smu, clocks)
 #define smu_dpm_set_vcn_enable(smu, enable)                            smu_ppt_funcs(dpm_set_vcn_enable, 0, smu, enable)
 #define smu_dpm_set_jpeg_enable(smu, enable)                           smu_ppt_funcs(dpm_set_jpeg_enable, 0, smu, enable)
-#define smu_set_watermarks_table(smu, tab, clock_ranges)               smu_ppt_funcs(set_watermarks_table, 0, smu, tab, clock_ranges)
+#define smu_set_watermarks_table(smu, clock_ranges)                    smu_ppt_funcs(set_watermarks_table, 0, smu, clock_ranges)
 #define smu_thermal_temperature_range_update(smu, range, rw)           smu_ppt_funcs(thermal_temperature_range_update, 0, smu, range, rw)
 #define smu_register_irq_handler(smu)                                  smu_ppt_funcs(register_irq_handler, 0, smu)
 #define smu_get_dpm_ultimate_freq(smu, param, min, max)                        smu_ppt_funcs(get_dpm_ultimate_freq, 0, smu, param, min, max)