arm64: dts: uniphier: Add missing clock-names and reset-names to pcie-phy

This adds missing clock-names and reset-names to pcie-phy node according to
Documentation/devicetree/bindings/phy/socionext,uniphier-pcie.yaml.

Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi
index f4a56b2..a87b8a6 100644 (file)
--- a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi
+++ b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi
@@ -936,7 +936,9 @@
                        compatible = "socionext,uniphier-ld20-pcie-phy";
                        reg = <0x66038000 0x4000>;
                        #phy-cells = <0>;
+                       clock-names = "link";
                        clocks = <&sys_clk 24>;
+                       reset-names = "link";
                        resets = <&sys_rst 24>;
                        socionext,syscon = <&soc_glue>;
                };

diff --git a/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi b/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi
index 72f1688..0e52dad 100644 (file)
--- a/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi
+++ b/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi
@@ -833,7 +833,9 @@
                        compatible = "socionext,uniphier-pxs3-pcie-phy";
                        reg = <0x66038000 0x4000>;
                        #phy-cells = <0>;
+                       clock-names = "link";
                        clocks = <&sys_clk 24>;
+                       reset-names = "link";
                        resets = <&sys_rst 24>;
                        socionext,syscon = <&soc_glue>;
                };