Merge branch 'v4.21-shared/clkids' into v4.21-clk/next

diff --git a/drivers/clk/rockchip/clk-rk3188.c b/drivers/clk/rockchip/clk-rk3188.c
index fa25e35..7ea2034 100644 (file)
--- a/drivers/clk/rockchip/clk-rk3188.c
+++ b/drivers/clk/rockchip/clk-rk3188.c
@@ -362,8 +362,8 @@ static struct rockchip_clk_branch common_clk_branches[] __initdata = {
                        RK2928_CLKGATE_CON(2), 5, GFLAGS),
        MUX(SCLK_MAC, "sclk_macref", mux_sclk_macref_p, CLK_SET_RATE_PARENT,
                        RK2928_CLKSEL_CON(21), 4, 1, MFLAGS),
-       GATE(0, "sclk_mac_lbtest", "sclk_macref",
-                       RK2928_CLKGATE_CON(2), 12, 0, GFLAGS),
+       GATE(0, "sclk_mac_lbtest", "sclk_macref", 0,
+                       RK2928_CLKGATE_CON(2), 12, GFLAGS),
 
        COMPOSITE(0, "hsadc_src", mux_pll_src_gpll_cpll_p, 0,
                        RK2928_CLKSEL_CON(22), 0, 1, MFLAGS, 8, 8, DFLAGS,
@@ -382,7 +382,7 @@ static struct rockchip_clk_branch common_clk_branches[] __initdata = {
        COMPOSITE_NOMUX(0, "spdif_pre", "i2s_src", 0,
                        RK2928_CLKSEL_CON(5), 0, 7, DFLAGS,
                        RK2928_CLKGATE_CON(0), 13, GFLAGS),
-       COMPOSITE_FRACMUX(0, "spdif_frac", "spdif_pll", CLK_SET_RATE_PARENT,
+       COMPOSITE_FRACMUX(0, "spdif_frac", "spdif_pre", CLK_SET_RATE_PARENT,
                        RK2928_CLKSEL_CON(9), 0,
                        RK2928_CLKGATE_CON(0), 14, GFLAGS,
                        &common_spdif_fracmux),
@@ -391,8 +391,8 @@ static struct rockchip_clk_branch common_clk_branches[] __initdata = {
         * Clock-Architecture Diagram 4
         */
 
-       GATE(SCLK_SMC, "sclk_smc", "hclk_peri",
-                       RK2928_CLKGATE_CON(2), 4, 0, GFLAGS),
+       GATE(SCLK_SMC, "sclk_smc", "hclk_peri", 0,
+                       RK2928_CLKGATE_CON(2), 4, GFLAGS),
 
        COMPOSITE_NOMUX(SCLK_SPI0, "sclk_spi0", "pclk_peri", 0,
                        RK2928_CLKSEL_CON(25), 0, 7, DFLAGS,
@@ -757,7 +757,8 @@ static const char *const rk3188_critical_clocks[] __initconst = {
        "hclk_peri",
        "pclk_cpu",
        "pclk_peri",
-       "hclk_cpubus"
+       "hclk_cpubus",
+       "hclk_vio_bus",
 };
 
 static struct rockchip_clk_provider *__init rk3188_common_clk_init(struct device_node *np)

diff --git a/drivers/clk/rockchip/clk-rk3328.c b/drivers/clk/rockchip/clk-rk3328.c
index 2c54266..1eb46aa 100644 (file)
--- a/drivers/clk/rockchip/clk-rk3328.c
+++ b/drivers/clk/rockchip/clk-rk3328.c
@@ -392,7 +392,7 @@ static struct rockchip_clk_branch rk3328_clk_branches[] __initdata = {
                        RK3328_CLKGATE_CON(1), 5, GFLAGS,
                        &rk3328_i2s1_fracmux),
        GATE(SCLK_I2S1, "clk_i2s1", "i2s1_pre", CLK_SET_RATE_PARENT,
-                       RK3328_CLKGATE_CON(0), 6, GFLAGS),
+                       RK3328_CLKGATE_CON(1), 6, GFLAGS),
        COMPOSITE_NODIV(SCLK_I2S1_OUT, "i2s1_out", mux_i2s1out_p, 0,
                        RK3328_CLKSEL_CON(8), 12, 1, MFLAGS,
                        RK3328_CLKGATE_CON(1), 7, GFLAGS),

diff --git a/include/dt-bindings/clock/rk3328-cru.h b/include/dt-bindings/clock/rk3328-cru.h
index 81a6186..bcaa455 100644 (file)
--- a/include/dt-bindings/clock/rk3328-cru.h
+++ b/include/dt-bindings/clock/rk3328-cru.h
@@ -179,7 +179,7 @@
 #define HCLK_TSP               309
 #define HCLK_GMAC              310
 #define HCLK_I2S0_8CH          311
-#define HCLK_I2S1_8CH          313
+#define HCLK_I2S1_8CH          312
 #define HCLK_I2S2_2CH          313
 #define HCLK_SPDIF_8CH         314
 #define HCLK_VOP               315