drm/amdgpu: Add compatible NPS mode info

Populate the compatible NPS modes also for providing partition
configuration details through sysfs.

Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Asad Kamal <asad.kamal@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.h
index 7ac89d7..b63f532 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.h
@@ -77,6 +77,7 @@ struct amdgpu_xcp_cfg {
        u8 num_res;
        struct amdgpu_xcp_mgr *xcp_mgr;
        struct kobject kobj;
+       u16 compatible_nps_modes;
 };
 
 struct amdgpu_xcp_ip_funcs {

diff --git a/drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c b/drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c
index 890976b..fccccea 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c
+++ b/drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c
@@ -455,6 +455,7 @@ static int aqua_vanjaram_get_xcp_res_info(struct amdgpu_xcp_mgr *xcp_mgr,
        int max_res[AMDGPU_XCP_RES_MAX] = {};
        bool res_lt_xcp;
        int num_xcp, i;
+       u16 nps_modes;
 
        if (!(xcp_mgr->supp_xcp_modes & BIT(mode)))
                return -EINVAL;
@@ -467,23 +468,33 @@ static int aqua_vanjaram_get_xcp_res_info(struct amdgpu_xcp_mgr *xcp_mgr,
        switch (mode) {
        case AMDGPU_SPX_PARTITION_MODE:
                num_xcp = 1;
+               nps_modes = BIT(AMDGPU_NPS1_PARTITION_MODE);
                break;
        case AMDGPU_DPX_PARTITION_MODE:
                num_xcp = 2;
+               nps_modes = BIT(AMDGPU_NPS1_PARTITION_MODE);
                break;
        case AMDGPU_TPX_PARTITION_MODE:
                num_xcp = 3;
+               nps_modes = BIT(AMDGPU_NPS1_PARTITION_MODE) |
+                           BIT(AMDGPU_NPS4_PARTITION_MODE);
                break;
        case AMDGPU_QPX_PARTITION_MODE:
                num_xcp = 4;
+               nps_modes = BIT(AMDGPU_NPS1_PARTITION_MODE) |
+                           BIT(AMDGPU_NPS4_PARTITION_MODE);
                break;
        case AMDGPU_CPX_PARTITION_MODE:
                num_xcp = NUM_XCC(adev->gfx.xcc_mask);
+               nps_modes = BIT(AMDGPU_NPS1_PARTITION_MODE) |
+                           BIT(AMDGPU_NPS4_PARTITION_MODE);
                break;
        default:
                return -EINVAL;
        }
 
+       xcp_cfg->compatible_nps_modes =
+               (adev->gmc.supported_nps_modes & nps_modes);
        xcp_cfg->num_res = ARRAY_SIZE(max_res);
 
        for (i = 0; i < xcp_cfg->num_res; i++) {