drm/amd/display: Optimize fast validation cases

Optimize fast validation cases to only validate the highest voltage
level. This works because during fast validation we only care if the
mode can be supported or not (at any vlevel).

Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Reviewed-by: Aric Cyr <aric.cyr@amd.com>
Acked-by: Rodrigo Siqueira <rodrigo.siqueira@amd.com>
Signed-off-by: Alvin Lee <alvin.lee2@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c b/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
index 3686f1e..63c48c2 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
@@ -3542,7 +3542,7 @@ void dml30_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l
 {
        struct vba_vars_st *v = &mode_lib->vba;
        int MinPrefetchMode, MaxPrefetchMode;
-       int i;
+       int i, start_state;
        unsigned int j, k, m;
        bool   EnoughWritebackUnits = true;
        bool   WritebackModeSupport = true;
@@ -3553,6 +3553,11 @@ void dml30_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l
 
        /*MODE SUPPORT, VOLTAGE STATE AND SOC CONFIGURATION*/
 
+       if (mode_lib->validate_max_state)
+               start_state = v->soc.num_states - 1;
+       else
+               start_state = 0;
+
        CalculateMinAndMaxPrefetchMode(
                mode_lib->vba.AllowDRAMSelfRefreshOrDRAMClockChangeInVblank,
                &MinPrefetchMode, &MaxPrefetchMode);
@@ -3851,7 +3856,7 @@ void dml30_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l
                        v->SingleDPPViewportSizeSupportPerPlane,
                        &v->ViewportSizeSupport[0][0]);
 
-       for (i = 0; i < v->soc.num_states; i++) {
+       for (i = start_state; i < v->soc.num_states; i++) {
                for (j = 0; j < 2; j++) {
                        v->MaxDispclkRoundedDownToDFSGranularity = RoundToDFSGranularityDown(v->MaxDispclk[i], v->DISPCLKDPPCLKVCOSpeed);
                        v->MaxDppclkRoundedDownToDFSGranularity = RoundToDFSGranularityDown(v->MaxDppclk[i], v->DISPCLKDPPCLKVCOSpeed);
@@ -4007,7 +4012,7 @@ void dml30_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l
 
        /*Total Available Pipes Support Check*/
 
-       for (i = 0; i < v->soc.num_states; i++) {
+       for (i = start_state; i < v->soc.num_states; i++) {
                for (j = 0; j < 2; j++) {
                        if (v->TotalNumberOfActiveDPP[i][j] <= v->MaxNumDPP) {
                                v->TotalAvailablePipesSupport[i][j] = true;
@@ -4046,7 +4051,7 @@ void dml30_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l
                }
        }
 
-       for (i = 0; i < v->soc.num_states; i++) {
+       for (i = start_state; i < v->soc.num_states; i++) {
                for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) {
                        v->RequiresDSC[i][k] = false;
                        v->RequiresFEC[i][k] = false;
@@ -4174,7 +4179,7 @@ void dml30_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l
                        }
                }
        }
-       for (i = 0; i < v->soc.num_states; i++) {
+       for (i = start_state; i < v->soc.num_states; i++) {
                v->DIOSupport[i] = true;
                for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) {
                        if (!v->skip_dio_check[k] && v->BlendingAndTiming[k] == k && (v->Output[k] == dm_dp || v->Output[k] == dm_edp || v->Output[k] == dm_hdmi)
@@ -4185,7 +4190,7 @@ void dml30_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l
                }
        }
 
-       for (i = 0; i < v->soc.num_states; ++i) {
+       for (i = start_state; i < v->soc.num_states; ++i) {
                v->ODMCombine4To1SupportCheckOK[i] = true;
                for (k = 0; k < v->NumberOfActivePlanes; ++k) {
                        if (v->BlendingAndTiming[k] == k && v->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_4to1
@@ -4197,7 +4202,7 @@ void dml30_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l
 
        /* Skip dscclk validation: as long as dispclk is supported, dscclk is also implicitly supported */
 
-       for (i = 0; i < v->soc.num_states; i++) {
+       for (i = start_state; i < v->soc.num_states; i++) {
                v->NotEnoughDSCUnits[i] = false;
                v->TotalDSCUnitsRequired = 0.0;
                for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) {
@@ -4217,7 +4222,7 @@ void dml30_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l
        }
        /*DSC Delay per state*/
 
-       for (i = 0; i < v->soc.num_states; i++) {
+       for (i = start_state; i < v->soc.num_states; i++) {
                for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) {
                        if (v->OutputBppPerState[i][k] == BPP_INVALID) {
                                v->BPP = 0.0;
@@ -4333,7 +4338,7 @@ void dml30_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l
                v->cursor_bw[k] = v->NumberOfCursors[k] * v->CursorWidth[k][0] * v->CursorBPP[k][0] / 8.0 / (v->HTotal[k] / v->PixelClock[k]) * v->VRatio[k];
        }
 
-       for (i = 0; i < v->soc.num_states; i++) {
+       for (i = start_state; i < v->soc.num_states; i++) {
                for (j = 0; j < 2; j++) {
                        for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) {
                                v->swath_width_luma_ub_this_state[k] = v->swath_width_luma_ub_all_states[i][j][k];
@@ -5075,7 +5080,7 @@ void dml30_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l
 
        /*PTE Buffer Size Check*/
 
-       for (i = 0; i < v->soc.num_states; i++) {
+       for (i = start_state; i < v->soc.num_states; i++) {
                for (j = 0; j < 2; j++) {
                        v->PTEBufferSizeNotExceeded[i][j] = true;
                        for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) {
@@ -5136,7 +5141,7 @@ void dml30_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l
        }
        /*Mode Support, Voltage State and SOC Configuration*/
 
-       for (i = v->soc.num_states - 1; i >= 0; i--) {
+       for (i = v->soc.num_states - 1; i >= start_state; i--) {
                for (j = 0; j < 2; j++) {
                        if (v->ScaleRatioAndTapsSupport == 1 && v->SourceFormatPixelAndScanSupport == 1 && v->ViewportSizeSupport[i][j] == 1
                                        && v->DIOSupport[i] == 1 && v->ODMCombine4To1SupportCheckOK[i] == 1
@@ -5158,7 +5163,7 @@ void dml30_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l
        }
        {
                unsigned int MaximumMPCCombine = 0;
-               for (i = v->soc.num_states; i >= 0; i--) {
+               for (i = v->soc.num_states; i >= start_state; i--) {
                        if (i == v->soc.num_states || v->ModeSupport[i][0] == true || v->ModeSupport[i][1] == true) {
                                v->VoltageLevel = i;
                                v->ModeIsSupported = v->ModeSupport[i][0] == true || v->ModeSupport[i][1] == true;

diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
index 2b6dcb4..37a6418 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
@@ -1682,6 +1682,7 @@ noinline bool dcn30_internal_validate_bw(
                 * We don't actually support prefetch mode 2, so require that we
                 * at least support prefetch mode 1.
                 */
+               context->bw_ctx.dml.validate_max_state = fast_validate;
                context->bw_ctx.dml.soc.allow_dram_self_refresh_or_dram_clock_change_in_vblank =
                        dm_allow_self_refresh;
 
@@ -1691,6 +1692,7 @@ noinline bool dcn30_internal_validate_bw(
                        memset(merge, 0, sizeof(merge));
                        vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, merge);
                }
+               context->bw_ctx.dml.validate_max_state = false;
        }
 
        dml_log_mode_support_params(&context->bw_ctx.dml);