CLK(NULL, "sdrc_ick", &sdrc_ick),
CLK(NULL, "des_ick", &des_ick),
CLK("omap-sham", "ick", &sha_ick),
- CLK("omap_rng", "ick", &rng_ick),
+ CLK(NULL, "sha_ick", &sha_ick),
+ CLK("omap_rng", "ick", &rng_ick),
CLK(NULL, "rng_ick", &rng_ick),
CLK("omap-aes", "ick", &aes_ick),
CLK(NULL, "pka_ick", &pka_ick),
#if defined(CONFIG_CRYPTO_DEV_OMAP_SHAM) || defined(CONFIG_CRYPTO_DEV_OMAP_SHAM_MODULE)
-#ifdef CONFIG_ARCH_OMAP2
-static struct resource omap2_sham_resources[] = {
- {
- .start = OMAP24XX_SEC_SHA1MD5_BASE,
- .end = OMAP24XX_SEC_SHA1MD5_BASE + 0x64,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = 51 + OMAP_INTC_START,
- .flags = IORESOURCE_IRQ,
- }
-};
-static int omap2_sham_resources_sz = ARRAY_SIZE(omap2_sham_resources);
-#else
-#define omap2_sham_resources NULL
-#define omap2_sham_resources_sz 0
-#endif
-
#ifdef CONFIG_ARCH_OMAP3
static struct resource omap3_sham_resources[] = {
{
static void omap_init_sham(void)
{
if (cpu_is_omap24xx()) {
- sham_device.resource = omap2_sham_resources;
- sham_device.num_resources = omap2_sham_resources_sz;
+ struct omap_hwmod *oh;
+ struct platform_device *pdev;
+
+ oh = omap_hwmod_lookup("sham");
+ if (!oh)
+ return;
+
+ pdev = omap_device_build("omap-sham", -1, oh, NULL, 0);
+ WARN(IS_ERR(pdev), "Can't build omap_device for omap-sham\n");
} else if (cpu_is_omap34xx()) {
sham_device.resource = omap3_sham_resources;
sham_device.num_resources = omap3_sham_resources_sz;
+ platform_device_register(&sham_device);
} else {
pr_err("%s: platform not supported\n", __func__);
return;
}
- platform_device_register(&sham_device);
}
#else
static inline void omap_init_sham(void) { }
&omap2420_l4_core__mcbsp2,
&omap2420_l4_core__msdi1,
&omap2xxx_l4_core__rng,
+ &omap2xxx_l4_core__sham,
&omap2420_l4_core__hdq1w,
&omap2420_l4_wkup__counter_32k,
&omap2420_l3__gpmc,
&omap2430_l4_core__mcbsp5,
&omap2430_l4_core__hdq1w,
&omap2xxx_l4_core__rng,
+ &omap2xxx_l4_core__sham,
&omap2430_l4_wkup__counter_32k,
&omap2430_l3__gpmc,
NULL,
{ }
};
+static struct omap_hwmod_addr_space omap2xxx_sham_addrs[] = {
+ {
+ .pa_start = 0x480a4000,
+ .pa_end = 0x480a4000 + 0x64 - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
/*
* Common interconnect data
*/
.addr = omap2_rng_addr_space,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
+
+/* l4 core -> sham interface */
+struct omap_hwmod_ocp_if omap2xxx_l4_core__sham = {
+ .master = &omap2xxx_l4_core_hwmod,
+ .slave = &omap2xxx_sham_hwmod,
+ .clk = "sha_ick",
+ .addr = omap2xxx_sham_addrs,
+ .user = OCP_USER_MPU,
+};
.flags = HWMOD_INIT_NO_RESET,
.class = &omap2_rng_hwmod_class,
};
+
+/* SHAM */
+
+static struct omap_hwmod_class_sysconfig omap2_sham_sysc = {
+ .rev_offs = 0x5c,
+ .sysc_offs = 0x60,
+ .syss_offs = 0x64,
+ .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
+ SYSS_HAS_RESET_STATUS),
+ .sysc_fields = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap2xxx_sham_class = {
+ .name = "sham",
+ .sysc = &omap2_sham_sysc,
+};
+
+static struct omap_hwmod_irq_info omap2_sham_mpu_irqs[] = {
+ { .irq = 51 + OMAP_INTC_START, },
+ { .irq = -1 }
+};
+
+struct omap_hwmod omap2xxx_sham_hwmod = {
+ .name = "sham",
+ .mpu_irqs = omap2_sham_mpu_irqs,
+ .main_clk = "l4_ck",
+ .prcm = {
+ .omap2 = {
+ .module_offs = CORE_MOD,
+ .prcm_reg_id = 4,
+ .module_bit = OMAP24XX_EN_SHA_SHIFT,
+ .idlest_reg_id = 4,
+ .idlest_idle_bit = OMAP24XX_ST_SHA_SHIFT,
+ },
+ },
+ .class = &omap2xxx_sham_class,
+};
extern struct omap_hwmod omap2xxx_counter_32k_hwmod;
extern struct omap_hwmod omap2xxx_gpmc_hwmod;
extern struct omap_hwmod omap2xxx_rng_hwmod;
+extern struct omap_hwmod omap2xxx_sham_hwmod;
/* Common interface data across OMAP2xxx */
extern struct omap_hwmod_ocp_if omap2xxx_l3_main__l4_core;
extern struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_rfbi;
extern struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_venc;
extern struct omap_hwmod_ocp_if omap2xxx_l4_core__rng;
+extern struct omap_hwmod_ocp_if omap2xxx_l4_core__sham;
/* Common IP block data */
extern struct omap_hwmod_dma_info omap2_uart1_sdma_reqs[];