drm/amd/display: Making hubp1_program_surface_config public
authorYue Hin Lau <Yuehin.Lau@amd.com>
Thu, 28 Sep 2017 20:09:56 +0000 (16:09 -0400)
committerAlex Deucher <alexander.deucher@amd.com>
Sat, 21 Oct 2017 20:46:34 +0000 (16:46 -0400)
Signed-off-by: Yue Hin Lau <Yuehin.Lau@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.h

index 46086be..2336da5 100644 (file)
@@ -407,7 +407,7 @@ void hubp1_dcc_control(struct mem_input *mem_input, bool enable,
                        PRIMARY_SURFACE_DCC_IND_64B_BLK, dcc_ind_64b_blk);
 }
 
-static void hubp1_program_surface_config(
+void hubp1_program_surface_config(
        struct mem_input *mem_input,
        enum surface_pixel_format format,
        union dc_tiling_info *tiling_info,
@@ -970,3 +970,4 @@ void dcn10_mem_input_construct(
        mi->base.mpcc_id = 0xf;
 }
 
+
index 6538752..5c5eed5 100644 (file)
@@ -591,6 +591,15 @@ struct dcn10_mem_input {
        const struct dcn_mi_mask *mi_mask;
 };
 
+void hubp1_program_surface_config(
+       struct mem_input *mem_input,
+       enum surface_pixel_format format,
+       union dc_tiling_info *tiling_info,
+       union plane_size *plane_size,
+       enum dc_rotation_angle rotation,
+       struct dc_plane_dcc_param *dcc,
+       bool horizontal_mirror);
+
 void hubp1_program_deadline(
                struct mem_input *mem_input,
                struct _vcs_dpi_display_dlg_regs_st *dlg_attr,