dt-bindings: clock: Introduce QCOM Graphics clock bindings

Add device tree bindings for graphics clock controller for
Qualcomm Technology Inc's SDM845 SoCs.

Signed-off-by: Amit Nischal <anischal@codeaurora.org>
Reviewed-by: Rob Herring <robh@kernel.org>
[sboyd@kernel.org: Add input clocks property]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

diff --git a/Documentation/devicetree/bindings/clock/qcom,gpucc.txt b/Documentation/devicetree/bindings/clock/qcom,gpucc.txt
new file mode 100644 (file)
index 0000000..9d0358c
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/qcom,gpucc.txt
@@ -0,0 +1,22 @@
+Qualcomm Graphics Clock & Reset Controller Binding
+--------------------------------------------------
+
+Required properties :
+- compatible : shall contain "qcom,sdm845-gpucc"
+- reg : shall contain base register location and length
+- #clock-cells : from common clock binding, shall contain 1
+- #reset-cells : from common reset binding, shall contain 1
+- #power-domain-cells : from generic power domain binding, shall contain 1
+- clocks : shall contain the XO clock
+- clock-names : shall be "xo"
+
+Example:
+       gpucc: clock-controller@5090000 {
+               compatible = "qcom,sdm845-gpucc";
+               reg = <0x5090000 0x9000>;
+               #clock-cells = <1>;
+               #reset-cells = <1>;
+               #power-domain-cells = <1>;
+               clocks = <&xo_board>;
+               clock-names = "xo";
+       };

diff --git a/include/dt-bindings/clock/qcom,gpucc-sdm845.h b/include/dt-bindings/clock/qcom,gpucc-sdm845.h
new file mode 100644 (file)
index 0000000..9690d90
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,gpucc-sdm845.h
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2018, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_CLK_SDM_GPU_CC_SDM845_H
+#define _DT_BINDINGS_CLK_SDM_GPU_CC_SDM845_H
+
+/* GPU_CC clock registers */
+#define GPU_CC_CX_GMU_CLK                      0
+#define GPU_CC_CXO_CLK                         1
+#define GPU_CC_GMU_CLK_SRC                     2
+#define GPU_CC_PLL1                            3
+
+/* GPU_CC Resets */
+#define GPUCC_GPU_CC_CX_BCR                    0
+#define GPUCC_GPU_CC_GMU_BCR                   1
+#define GPUCC_GPU_CC_XO_BCR                    2
+
+/* GPU_CC GDSCRs */
+#define GPU_CX_GDSC                            0
+#define GPU_GX_GDSC                            1
+
+#endif