drm/xe/xe2hpg: Introduce performance tuning changes for Xe2_HPG.

Introduces performance tuning guide changes for Xe_HPG.

v2: Switched to open upper bound for "Tuning: L3 Cache" setting.

BSpec: 72161
Signed-off-by: Shekhar Chauhan <shekhar.chauhan@intel.com>
Signed-off-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240408170545.3769566-11-balasubramani.vivekanandan@intel.com

diff --git a/drivers/gpu/drm/xe/xe_tuning.c b/drivers/gpu/drm/xe/xe_tuning.c
index bb6db28..d4e6fa9 100644 (file)
--- a/drivers/gpu/drm/xe/xe_tuning.c
+++ b/drivers/gpu/drm/xe/xe_tuning.c
@@ -28,7 +28,7 @@ static const struct xe_rtp_entry_sr gt_tunings[] = {
        /* Xe2 */
 
        { XE_RTP_NAME("Tuning: L3 cache"),
-         XE_RTP_RULES(GRAPHICS_VERSION(2004)),
+         XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, XE_RTP_END_VERSION_UNDEFINED)),
          XE_RTP_ACTIONS(FIELD_SET(XEHP_L3SQCREG5, L3_PWM_TIMER_INIT_VAL_MASK,
                                   REG_FIELD_PREP(L3_PWM_TIMER_INIT_VAL_MASK, 0x7f)))
        },
@@ -38,11 +38,11 @@ static const struct xe_rtp_entry_sr gt_tunings[] = {
                                   REG_FIELD_PREP(L3_PWM_TIMER_INIT_VAL_MASK, 0x7f)))
        },
        { XE_RTP_NAME("Tuning: Compression Overfetch"),
-         XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2004, XE_RTP_END_VERSION_UNDEFINED)),
+         XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, XE_RTP_END_VERSION_UNDEFINED)),
          XE_RTP_ACTIONS(CLR(CCCHKNREG1, ENCOMPPERFFIX)),
        },
        { XE_RTP_NAME("Tuning: Enable compressible partial write overfetch in L3"),
-         XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2004, XE_RTP_END_VERSION_UNDEFINED)),
+         XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, XE_RTP_END_VERSION_UNDEFINED)),
          XE_RTP_ACTIONS(SET(L3SQCREG3, COMPPWOVERFETCHEN))
        },
        {}