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ARM: tegra: apalis-tk1: reorder cpu dfll clock properties
authorMarcel Ziswiler <marcel.ziswiler@toradex.com>
Sat, 1 Sep 2018 13:04:57 +0000 (15:04 +0200)
committerThierry Reding <treding@nvidia.com>
Wed, 26 Sep 2018 14:50:38 +0000 (16:50 +0200)
Reorder CPU DFLL clock properties.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi patch | blob | history
arch/arm/boot/dts/tegra124-apalis.dtsi patch | blob | history

diff --git a/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi b/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi
index 37e443e..07dd208 100644 (file)
--- a/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi
+++ b/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi
@@ -1925,8 +1925,8 @@
        /* CPU DFLL clock */
        clock@70110000 {
                status = "okay";
-               vdd-cpu-supply = <&reg_vdd_cpu>;
                nvidia,i2c-fs-rate = <400000>;
+               vdd-cpu-supply = <&reg_vdd_cpu>;
        };
 
        ahub@70300000 {
diff --git a/arch/arm/boot/dts/tegra124-apalis.dtsi b/arch/arm/boot/dts/tegra124-apalis.dtsi
index f76580f..fe10c51 100644 (file)
--- a/arch/arm/boot/dts/tegra124-apalis.dtsi
+++ b/arch/arm/boot/dts/tegra124-apalis.dtsi
@@ -1954,8 +1954,8 @@
        /* CPU DFLL clock */
        clock@70110000 {
                status = "okay";
-               vdd-cpu-supply = <&reg_vdd_cpu>;
                nvidia,i2c-fs-rate = <400000>;
+               vdd-cpu-supply = <&reg_vdd_cpu>;
        };
 
        ahub@70300000 {
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