drm/amd/display: Update to correct min FCLK when construction BB

[Description]
- For min FCLK, choose the min of 300Mhz and PMFW requirement
- Also only apply min DET check in DML for non-UR cases

Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
index e47828e..077674b 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
@@ -2315,6 +2315,9 @@ static int build_synthetic_soc_states(struct clk_bw_params *bw_params,
                        num_dcfclk_dpms++;
        }
 
+       if (num_dcfclk_dpms > 0 && bw_params->clk_table.entries[0].fclk_mhz > min_fclk_mhz)
+               min_fclk_mhz = bw_params->clk_table.entries[0].fclk_mhz;
+
        if (!max_dcfclk_mhz || !max_dispclk_mhz || !max_dtbclk_mhz)
                return -1;
 
@@ -2423,7 +2426,6 @@ static int build_synthetic_soc_states(struct clk_bw_params *bw_params,
                for (i = *num_entries - 1; i >= 0 ; i--) {
                        if (table[i].fabricclk_mhz < min_fclk_mhz) {
                                table[i].fabricclk_mhz = min_fclk_mhz;
-                               break;
                        }
                }
        }
@@ -2432,7 +2434,6 @@ static int build_synthetic_soc_states(struct clk_bw_params *bw_params,
        for (i = *num_entries - 1; i >= 0 ; i--) {
                if (table[i].dcfclk_mhz < min_dcfclk_mhz) {
                        table[i].dcfclk_mhz = min_dcfclk_mhz;
-                       break;
                }
        }
 

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
index f249981..f74730c 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
@@ -689,7 +689,8 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman
                                                mode_lib->vba.PixelClock,
                                                mode_lib->vba.VRatio,
                                                mode_lib->vba.VRatioChroma,
-                                               mode_lib->vba.UsesMALLForPStateChange);
+                                               mode_lib->vba.UsesMALLForPStateChange,
+                                               mode_lib->vba.UseUnboundedRequesting);
 
        for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
                v->MaxVStartupLines[k] = ((mode_lib->vba.Interlace[k] &&
@@ -3215,7 +3216,8 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l
                                        mode_lib->vba.PixelClock,
                                        mode_lib->vba.VRatio,
                                        mode_lib->vba.VRatioChroma,
-                                       mode_lib->vba.UsesMALLForPStateChange);
+                                       mode_lib->vba.UsesMALLForPStateChange,
+                                       mode_lib->vba.UseUnboundedRequesting);
 
                        v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.VMDataOnlyReturnBWPerState = dml32_get_return_bw_mbps_vm_only(&mode_lib->vba.soc, i,
                                        mode_lib->vba.DCFCLKState[i][j], mode_lib->vba.FabricClockPerState[i],

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
index d1000aa..61cc490 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
@@ -6271,7 +6271,8 @@ bool dml32_CalculateDETSwathFillLatencyHiding(unsigned int NumberOfActiveSurface
                double  PixelClock[],
                double  VRatioY[],
                double  VRatioC[],
-               enum dm_use_mall_for_pstate_change_mode UsesMALLForPStateChange[])
+               enum dm_use_mall_for_pstate_change_mode UsesMALLForPStateChange[],
+               enum unbounded_requesting_policy UseUnboundedRequesting)
 {
        int k;
        double SwathSizeAllSurfaces = 0;
@@ -6283,6 +6284,9 @@ bool dml32_CalculateDETSwathFillLatencyHiding(unsigned int NumberOfActiveSurface
        double SwathSizePerSurfaceC[DC__NUM_DPP__MAX];
        bool NotEnoughDETSwathFillLatencyHiding = false;
 
+       if (UseUnboundedRequesting == dm_unbounded_requesting)
+               return false;
+
        /* calculate sum of single swath size for all pipes in bytes */
        for (k = 0; k < NumberOfActiveSurfaces; k++) {
                SwathSizePerSurfaceY[k] = SwathHeightY[k] * SwathWidthY[k] * BytePerPixelInDETY[k] * NumOfDPP[k];

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h
index 9ba792c..592d174 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h
@@ -1163,6 +1163,7 @@ bool dml32_CalculateDETSwathFillLatencyHiding(unsigned int NumberOfActiveSurface
                double  PixelClock[],
                double  VRatioY[],
                double  VRatioC[],
-               enum dm_use_mall_for_pstate_change_mode UsesMALLForPStateChange[]);
+               enum dm_use_mall_for_pstate_change_mode UsesMALLForPStateChange[],
+               enum unbounded_requesting_policy UseUnboundedRequesting);
 
 #endif

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c
index b80cef7..57b9bd8 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c
@@ -294,6 +294,9 @@ static int build_synthetic_soc_states(struct clk_bw_params *bw_params,
                        num_dcfclk_dpms++;
        }
 
+       if (num_dcfclk_dpms > 0 && bw_params->clk_table.entries[0].fclk_mhz > min_fclk_mhz)
+               min_fclk_mhz = bw_params->clk_table.entries[0].fclk_mhz;
+
        if (!max_dcfclk_mhz || !max_dispclk_mhz || !max_dtbclk_mhz)
                return -1;
 
@@ -402,7 +405,6 @@ static int build_synthetic_soc_states(struct clk_bw_params *bw_params,
                for (i = *num_entries - 1; i >= 0 ; i--) {
                        if (table[i].fabricclk_mhz < min_fclk_mhz) {
                                table[i].fabricclk_mhz = min_fclk_mhz;
-                               break;
                        }
                }
        }
@@ -411,7 +413,6 @@ static int build_synthetic_soc_states(struct clk_bw_params *bw_params,
        for (i = *num_entries - 1; i >= 0 ; i--) {
                if (table[i].dcfclk_mhz < min_dcfclk_mhz) {
                        table[i].dcfclk_mhz = min_dcfclk_mhz;
-                       break;
                }
        }