drm/msm/dpu: get rid of DPU_DSC_HW_REV_1_2
authorDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Thu, 22 May 2025 19:03:42 +0000 (22:03 +0300)
committerDmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Fri, 4 Jul 2025 13:35:17 +0000 (16:35 +0300)
Continue migration to the MDSS-revision based checks and replace
DPU_DSC_HW_REV_1_2 feature bit with the core_major_ver >= 7 check.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/655403/
Link: https://lore.kernel.org/r/20250522-dpu-drop-features-v5-23-3b2085a07884@oss.qualcomm.com
12 files changed:
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c

index 9a8f604..013314b 100644 (file)
@@ -286,32 +286,30 @@ static const struct dpu_dsc_cfg sm8650_dsc[] = {
        {
                .name = "dce_0_0", .id = DSC_0,
                .base = 0x80000, .len = 0x6,
-               .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
+               .features = BIT(DPU_DSC_NATIVE_42x_EN),
                .sblk = &dsc_sblk_0,
        }, {
                .name = "dce_0_1", .id = DSC_1,
                .base = 0x80000, .len = 0x6,
-               .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
+               .features = BIT(DPU_DSC_NATIVE_42x_EN),
                .sblk = &dsc_sblk_1,
        }, {
                .name = "dce_1_0", .id = DSC_2,
                .base = 0x81000, .len = 0x6,
-               .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
+               .features = BIT(DPU_DSC_NATIVE_42x_EN),
                .sblk = &dsc_sblk_0,
        }, {
                .name = "dce_1_1", .id = DSC_3,
                .base = 0x81000, .len = 0x6,
-               .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
+               .features = BIT(DPU_DSC_NATIVE_42x_EN),
                .sblk = &dsc_sblk_1,
        }, {
                .name = "dce_2_0", .id = DSC_4,
                .base = 0x82000, .len = 0x6,
-               .features = BIT(DPU_DSC_HW_REV_1_2),
                .sblk = &dsc_sblk_0,
        }, {
                .name = "dce_2_1", .id = DSC_5,
                .base = 0x82000, .len = 0x6,
-               .features = BIT(DPU_DSC_HW_REV_1_2),
                .sblk = &dsc_sblk_1,
        },
 };
index e81a2a0..b4d41e2 100644 (file)
@@ -263,22 +263,20 @@ static const struct dpu_dsc_cfg sm8350_dsc[] = {
        {
                .name = "dce_0_0", .id = DSC_0,
                .base = 0x80000, .len = 0x4,
-               .features = BIT(DPU_DSC_HW_REV_1_2),
                .sblk = &dsc_sblk_0,
        }, {
                .name = "dce_0_1", .id = DSC_1,
                .base = 0x80000, .len = 0x4,
-               .features = BIT(DPU_DSC_HW_REV_1_2),
                .sblk = &dsc_sblk_1,
        }, {
                .name = "dce_1_0", .id = DSC_2,
                .base = 0x81000, .len = 0x4,
-               .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
+               .features = BIT(DPU_DSC_NATIVE_42x_EN),
                .sblk = &dsc_sblk_0,
        }, {
                .name = "dce_1_1", .id = DSC_3,
                .base = 0x81000, .len = 0x4,
-               .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
+               .features = BIT(DPU_DSC_NATIVE_42x_EN),
                .sblk = &dsc_sblk_1,
        },
 };
index b0e94cc..5d88f02 100644 (file)
@@ -150,7 +150,7 @@ static const struct dpu_dsc_cfg sc7280_dsc[] = {
        {
                .name = "dce_0_0", .id = DSC_0,
                .base = 0x80000, .len = 0x4,
-               .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
+               .features = BIT(DPU_DSC_NATIVE_42x_EN),
                .sblk = &dsc_sblk_0,
        },
 };
index 2cf3023..303d33d 100644 (file)
@@ -262,32 +262,28 @@ static const struct dpu_dsc_cfg sc8280xp_dsc[] = {
        {
                .name = "dce_0_0", .id = DSC_0,
                .base = 0x80000, .len = 0x4,
-               .features = BIT(DPU_DSC_HW_REV_1_2),
                .sblk = &dsc_sblk_0,
        }, {
                .name = "dce_0_1", .id = DSC_1,
                .base = 0x80000, .len = 0x4,
-               .features = BIT(DPU_DSC_HW_REV_1_2),
                .sblk = &dsc_sblk_1,
        }, {
                .name = "dce_1_0", .id = DSC_2,
                .base = 0x81000, .len = 0x4,
-               .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
+               .features = BIT(DPU_DSC_NATIVE_42x_EN),
                .sblk = &dsc_sblk_0,
        }, {
                .name = "dce_1_1", .id = DSC_3,
                .base = 0x81000, .len = 0x4,
-               .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
+               .features = BIT(DPU_DSC_NATIVE_42x_EN),
                .sblk = &dsc_sblk_1,
        }, {
                .name = "dce_2_0", .id = DSC_4,
                .base = 0x82000, .len = 0x4,
-               .features = BIT(DPU_DSC_HW_REV_1_2),
                .sblk = &dsc_sblk_0,
        }, {
                .name = "dce_2_1", .id = DSC_5,
                .base = 0x82000, .len = 0x4,
-               .features = BIT(DPU_DSC_HW_REV_1_2),
                .sblk = &dsc_sblk_1,
        },
 };
index dcef566..3c0728a 100644 (file)
@@ -276,22 +276,20 @@ static const struct dpu_dsc_cfg sm8450_dsc[] = {
        {
                .name = "dce_0_0", .id = DSC_0,
                .base = 0x80000, .len = 0x4,
-               .features = BIT(DPU_DSC_HW_REV_1_2),
                .sblk = &dsc_sblk_0,
        }, {
                .name = "dce_0_1", .id = DSC_1,
                .base = 0x80000, .len = 0x4,
-               .features = BIT(DPU_DSC_HW_REV_1_2),
                .sblk = &dsc_sblk_1,
        }, {
                .name = "dce_1_0", .id = DSC_2,
                .base = 0x81000, .len = 0x4,
-               .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
+               .features = BIT(DPU_DSC_NATIVE_42x_EN),
                .sblk = &dsc_sblk_0,
        }, {
                .name = "dce_1_1", .id = DSC_3,
                .base = 0x81000, .len = 0x4,
-               .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
+               .features = BIT(DPU_DSC_NATIVE_42x_EN),
                .sblk = &dsc_sblk_1,
        },
 };
index 5f5987d..b8a1646 100644 (file)
@@ -275,32 +275,28 @@ static const struct dpu_dsc_cfg sa8775p_dsc[] = {
        {
                .name = "dce_0_0", .id = DSC_0,
                .base = 0x80000, .len = 0x4,
-               .features = BIT(DPU_DSC_HW_REV_1_2),
                .sblk = &dsc_sblk_0,
        }, {
                .name = "dce_0_1", .id = DSC_1,
                .base = 0x80000, .len = 0x4,
-               .features = BIT(DPU_DSC_HW_REV_1_2),
                .sblk = &dsc_sblk_1,
        }, {
                .name = "dce_1_0", .id = DSC_2,
                .base = 0x81000, .len = 0x4,
-               .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
+               .features = BIT(DPU_DSC_NATIVE_42x_EN),
                .sblk = &dsc_sblk_0,
        }, {
                .name = "dce_1_1", .id = DSC_3,
                .base = 0x81000, .len = 0x4,
-               .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
+               .features = BIT(DPU_DSC_NATIVE_42x_EN),
                .sblk = &dsc_sblk_1,
        }, {
                .name = "dce_2_0", .id = DSC_4,
                .base = 0x82000, .len = 0x4,
-               .features = BIT(DPU_DSC_HW_REV_1_2),
                .sblk = &dsc_sblk_0,
        }, {
                .name = "dce_2_1", .id = DSC_5,
                .base = 0x82000, .len = 0x4,
-               .features = BIT(DPU_DSC_HW_REV_1_2),
                .sblk = &dsc_sblk_1,
        },
 };
index 6f31021..ef22a9a 100644 (file)
@@ -272,22 +272,20 @@ static const struct dpu_dsc_cfg sm8550_dsc[] = {
        {
                .name = "dce_0_0", .id = DSC_0,
                .base = 0x80000, .len = 0x4,
-               .features = BIT(DPU_DSC_HW_REV_1_2),
                .sblk = &dsc_sblk_0,
        }, {
                .name = "dce_0_1", .id = DSC_1,
                .base = 0x80000, .len = 0x4,
-               .features = BIT(DPU_DSC_HW_REV_1_2),
                .sblk = &dsc_sblk_1,
        }, {
                .name = "dce_1_0", .id = DSC_2,
                .base = 0x81000, .len = 0x4,
-               .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
+               .features = BIT(DPU_DSC_NATIVE_42x_EN),
                .sblk = &dsc_sblk_0,
        }, {
                .name = "dce_1_1", .id = DSC_3,
                .base = 0x81000, .len = 0x4,
-               .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
+               .features = BIT(DPU_DSC_NATIVE_42x_EN),
                .sblk = &dsc_sblk_1,
        },
 };
index ba8a2c5..2e7d440 100644 (file)
@@ -272,22 +272,20 @@ static const struct dpu_dsc_cfg sar2130p_dsc[] = {
        {
                .name = "dce_0_0", .id = DSC_0,
                .base = 0x80000, .len = 0x4,
-               .features = BIT(DPU_DSC_HW_REV_1_2),
                .sblk = &dsc_sblk_0,
        }, {
                .name = "dce_0_1", .id = DSC_1,
                .base = 0x80000, .len = 0x4,
-               .features = BIT(DPU_DSC_HW_REV_1_2),
                .sblk = &dsc_sblk_1,
        }, {
                .name = "dce_1_0", .id = DSC_2,
                .base = 0x81000, .len = 0x4,
-               .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
+               .features = BIT(DPU_DSC_NATIVE_42x_EN),
                .sblk = &dsc_sblk_0,
        }, {
                .name = "dce_1_1", .id = DSC_3,
                .base = 0x81000, .len = 0x4,
-               .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
+               .features = BIT(DPU_DSC_NATIVE_42x_EN),
                .sblk = &dsc_sblk_1,
        },
 };
index 77986a7..ac95d46 100644 (file)
@@ -272,22 +272,20 @@ static const struct dpu_dsc_cfg x1e80100_dsc[] = {
        {
                .name = "dce_0_0", .id = DSC_0,
                .base = 0x80000, .len = 0x4,
-               .features = BIT(DPU_DSC_HW_REV_1_2),
                .sblk = &dsc_sblk_0,
        }, {
                .name = "dce_0_1", .id = DSC_1,
                .base = 0x80000, .len = 0x4,
-               .features = BIT(DPU_DSC_HW_REV_1_2),
                .sblk = &dsc_sblk_1,
        }, {
                .name = "dce_1_0", .id = DSC_2,
                .base = 0x81000, .len = 0x4,
-               .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
+               .features = BIT(DPU_DSC_NATIVE_42x_EN),
                .sblk = &dsc_sblk_0,
        }, {
                .name = "dce_1_1", .id = DSC_3,
                .base = 0x81000, .len = 0x4,
-               .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
+               .features = BIT(DPU_DSC_NATIVE_42x_EN),
                .sblk = &dsc_sblk_1,
        },
 };
index cc17b20..01430ff 100644 (file)
@@ -176,13 +176,11 @@ enum {
  * DSC sub-blocks/features
  * @DPU_DSC_OUTPUT_CTRL       Configure which PINGPONG block gets
  *                            the pixel output from this DSC.
- * @DPU_DSC_HW_REV_1_2        DSC block supports DSC 1.1 and 1.2
  * @DPU_DSC_NATIVE_42x_EN     Supports NATIVE_422_EN and NATIVE_420_EN encoding
  * @DPU_DSC_MAX
  */
 enum {
        DPU_DSC_OUTPUT_CTRL = 0x1,
-       DPU_DSC_HW_REV_1_2,
        DPU_DSC_NATIVE_42x_EN,
        DPU_DSC_MAX
 };
index 80ffd46..d478a7b 100644 (file)
@@ -1043,7 +1043,7 @@ static void dpu_kms_mdp_snapshot(struct msm_disp_state *disp_state, struct msm_k
                msm_disp_snapshot_add_block(disp_state, cat->dsc[i].len, base,
                                            "%s", cat->dsc[i].name);
 
-               if (cat->dsc[i].features & BIT(DPU_DSC_HW_REV_1_2)) {
+               if (cat->mdss_ver->core_major_ver >= 7) {
                        struct dpu_dsc_blk enc = cat->dsc[i].sblk->enc;
                        struct dpu_dsc_blk ctl = cat->dsc[i].sblk->ctl;
 
index 7bcb1e0..c2a6595 100644 (file)
@@ -168,7 +168,7 @@ int dpu_rm_init(struct drm_device *dev,
                struct dpu_hw_dsc *hw;
                const struct dpu_dsc_cfg *dsc = &cat->dsc[i];
 
-               if (test_bit(DPU_DSC_HW_REV_1_2, &dsc->features))
+               if (cat->mdss_ver->core_major_ver >= 7)
                        hw = dpu_hw_dsc_init_1_2(dev, dsc, mmio);
                else
                        hw = dpu_hw_dsc_init(dev, dsc, mmio);