Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net

drivers/net/phy/bcm7xxx.c
  d88fd1b546ff ("net: phy: bcm7xxx: Fixed indirect MMD operations")
  f68d08c437f9 ("net: phy: bcm7xxx: Add EPHY entry for 72165")

net/sched/sch_api.c
  b193e15ac69d ("net: prevent user from passing illegal stab size")
  69508d43334e ("net_sched: Use struct_size() and flex_array_size() helpers")

Both cases trivial - adjacent code additions.

Signed-off-by: Jakub Kicinski <kuba@kernel.org>

diff --cc arch/x86/net/bpf_jit_comp.c
Simple merge

diff --cc drivers/net/ethernet/freescale/enetc/enetc_pf.c
Simple merge

diff --cc drivers/net/ethernet/hisilicon/hns3/hnae3.h
Simple merge

diff --cc drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_debugfs.c
Simple merge

diff --cc drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
Simple merge

diff --cc drivers/net/ethernet/ibm/ibmvnic.c
Simple merge

diff --cc drivers/net/ethernet/intel/ixgbe/ixgbe_main.c
Simple merge

diff --cc drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
Simple merge

diff --cc drivers/net/phy/bcm7xxx.c
index 3a29a14,27b6a3f..6ceadd2
--- 1/drivers/net/phy/bcm7xxx.c
--- 2/drivers/net/phy/bcm7xxx.c
+++ b/drivers/net/phy/bcm7xxx.c
@@@ -398,190 -415,93 +415,277 @@@ static int bcm7xxx_28nm_ephy_config_ini
        return bcm7xxx_28nm_ephy_apd_enable(phydev);
  }
  
 +static int bcm7xxx_16nm_ephy_afe_config(struct phy_device *phydev)
 +{
 +      int tmp, rcalcode, rcalnewcodelp, rcalnewcode11, rcalnewcode11d2;
 +
 +      /* Reset PHY */
 +      tmp = genphy_soft_reset(phydev);
 +      if (tmp)
 +              return tmp;
 +
 +      /* Reset AFE and PLL */
 +      bcm_phy_write_exp_sel(phydev, 0x0003, 0x0006);
 +      /* Clear reset */
 +      bcm_phy_write_exp_sel(phydev, 0x0003, 0x0000);
 +
 +      /* Write PLL/AFE control register to select 54MHz crystal */
 +      bcm_phy_write_misc(phydev, 0x0030, 0x0001, 0x0000);
 +      bcm_phy_write_misc(phydev, 0x0031, 0x0000, 0x044a);
 +
 +      /* Change Ka,Kp,Ki to pdiv=1 */
 +      bcm_phy_write_misc(phydev, 0x0033, 0x0002, 0x71a1);
 +      /* Configuration override */
 +      bcm_phy_write_misc(phydev, 0x0033, 0x0001, 0x8000);
 +
 +      /* Change PLL_NDIV and PLL_NUDGE */
 +      bcm_phy_write_misc(phydev, 0x0031, 0x0001, 0x2f68);
 +      bcm_phy_write_misc(phydev, 0x0031, 0x0002, 0x0000);
 +
 +      /* Reference frequency is 54Mhz, config_mode[15:14] = 3 (low
 +       * phase)
 +       */
 +      bcm_phy_write_misc(phydev, 0x0030, 0x0003, 0xc036);
 +
 +      /* Initialize bypass mode */
 +      bcm_phy_write_misc(phydev, 0x0032, 0x0003, 0x0000);
 +      /* Bypass code, default: VCOCLK enabled */
 +      bcm_phy_write_misc(phydev, 0x0033, 0x0000, 0x0002);
 +      /* LDOs at default setting */
 +      bcm_phy_write_misc(phydev, 0x0030, 0x0002, 0x01c0);
 +      /* Release PLL reset */
 +      bcm_phy_write_misc(phydev, 0x0030, 0x0001, 0x0001);
 +
 +      /* Bandgap curvature correction to correct default */
 +      bcm_phy_write_misc(phydev, 0x0038, 0x0000, 0x0010);
 +
 +      /* Run RCAL */
 +      bcm_phy_write_misc(phydev, 0x0039, 0x0003, 0x0038);
 +      bcm_phy_write_misc(phydev, 0x0039, 0x0003, 0x003b);
 +      udelay(2);
 +      bcm_phy_write_misc(phydev, 0x0039, 0x0003, 0x003f);
 +      mdelay(5);
 +
 +      /* AFE_CAL_CONFIG_0, Vref=1000, Target=10, averaging enabled */
 +      bcm_phy_write_misc(phydev, 0x0039, 0x0001, 0x1c82);
 +      /* AFE_CAL_CONFIG_0, no reset and analog powerup */
 +      bcm_phy_write_misc(phydev, 0x0039, 0x0001, 0x9e82);
 +      udelay(2);
 +      /* AFE_CAL_CONFIG_0, start calibration */
 +      bcm_phy_write_misc(phydev, 0x0039, 0x0001, 0x9f82);
 +      udelay(100);
 +      /* AFE_CAL_CONFIG_0, clear start calibration, set HiBW */
 +      bcm_phy_write_misc(phydev, 0x0039, 0x0001, 0x9e86);
 +      udelay(2);
 +      /* AFE_CAL_CONFIG_0, start calibration with hi BW mode set */
 +      bcm_phy_write_misc(phydev, 0x0039, 0x0001, 0x9f86);
 +      udelay(100);
 +
 +      /* Adjust 10BT amplitude additional +7% and 100BT +2% */
 +      bcm_phy_write_misc(phydev, 0x0038, 0x0001, 0xe7ea);
 +      /* Adjust 1G mode amplitude and 1G testmode1 */
 +      bcm_phy_write_misc(phydev, 0x0038, 0x0002, 0xede0);
 +
 +      /* Read CORE_EXPA9 */
 +      tmp = bcm_phy_read_exp(phydev, 0x00a9);
 +      /* CORE_EXPA9[6:1] is rcalcode[5:0] */
 +      rcalcode = (tmp & 0x7e) / 2;
 +      /* Correct RCAL code + 1 is -1% rprogr, LP: +16 */
 +      rcalnewcodelp = rcalcode + 16;
 +      /* Correct RCAL code + 1 is -15 rprogr, 11: +10 */
 +      rcalnewcode11 = rcalcode + 10;
 +      /* Saturate if necessary */
 +      if (rcalnewcodelp > 0x3f)
 +              rcalnewcodelp = 0x3f;
 +      if (rcalnewcode11 > 0x3f)
 +              rcalnewcode11 = 0x3f;
 +      /* REXT=1 BYP=1 RCAL_st1<5:0>=new rcal code */
 +      tmp = 0x00f8 + rcalnewcodelp * 256;
 +      /* Program into AFE_CAL_CONFIG_2 */
 +      bcm_phy_write_misc(phydev, 0x0039, 0x0003, tmp);
 +      /* AFE_BIAS_CONFIG_0 10BT bias code (Bias: E4) */
 +      bcm_phy_write_misc(phydev, 0x0038, 0x0001, 0xe7e4);
 +      /* invert adc clock output and 'adc refp ldo current To correct
 +       * default
 +       */
 +      bcm_phy_write_misc(phydev, 0x003b, 0x0000, 0x8002);
 +      /* 100BT stair case, high BW, 1G stair case, alternate encode */
 +      bcm_phy_write_misc(phydev, 0x003c, 0x0003, 0xf882);
 +      /* 1000BT DAC transition method per Erol, bits[32], DAC Shuffle
 +       * sequence 1 + 10BT imp adjust bits
 +       */
 +      bcm_phy_write_misc(phydev, 0x003d, 0x0000, 0x3201);
 +      /* Non-overlap fix */
 +      bcm_phy_write_misc(phydev, 0x003a, 0x0002, 0x0c00);
 +
 +      /* pwdb override (rxconfig<5>) to turn on RX LDO indpendent of
 +       * pwdb controls from DSP_TAP10
 +       */
 +      bcm_phy_write_misc(phydev, 0x003a, 0x0001, 0x0020);
 +
 +      /* Remove references to channel 2 and 3 */
 +      bcm_phy_write_misc(phydev, 0x003b, 0x0002, 0x0000);
 +      bcm_phy_write_misc(phydev, 0x003b, 0x0003, 0x0000);
 +
 +      /* Set cal_bypassb bit rxconfig<43> */
 +      bcm_phy_write_misc(phydev, 0x003a, 0x0003, 0x0800);
 +      udelay(2);
 +
 +      /* Revert pwdb_override (rxconfig<5>) to 0 so that the RX pwr
 +       * is controlled by DSP.
 +       */
 +      bcm_phy_write_misc(phydev, 0x003a, 0x0001, 0x0000);
 +
 +      /* Drop LSB */
 +      rcalnewcode11d2 = (rcalnewcode11 & 0xfffe) / 2;
 +      tmp = bcm_phy_read_misc(phydev, 0x003d, 0x0001);
 +      /* Clear bits [11:5] */
 +      tmp &= ~0xfe0;
 +      /* set txcfg_ch0<5>=1 (enable + set local rcal) */
 +      tmp |= 0x0020 | (rcalnewcode11d2 * 64);
 +      bcm_phy_write_misc(phydev, 0x003d, 0x0001, tmp);
 +      bcm_phy_write_misc(phydev, 0x003d, 0x0002, tmp);
 +
 +      tmp = bcm_phy_read_misc(phydev, 0x003d, 0x0000);
 +      /* set txcfg<45:44>=11 (enable Rextra + invert fullscaledetect)
 +       */
 +      tmp &= ~0x3000;
 +      tmp |= 0x3000;
 +      bcm_phy_write_misc(phydev, 0x003d, 0x0000, tmp);
 +
 +      return 0;
 +}
 +
 +static int bcm7xxx_16nm_ephy_config_init(struct phy_device *phydev)
 +{
 +      int ret, val;
 +
 +      ret = bcm7xxx_16nm_ephy_afe_config(phydev);
 +      if (ret)
 +              return ret;
 +
 +      ret = bcm_phy_set_eee(phydev, true);
 +      if (ret)
 +              return ret;
 +
 +      ret = bcm_phy_read_shadow(phydev, BCM54XX_SHD_SCR3);
 +      if (ret < 0)
 +              return ret;
 +
 +      val = ret;
 +
 +      /* Auto power down of DLL enabled,
 +       * TXC/RXC disabled during auto power down.
 +       */
 +      val &= ~BCM54XX_SHD_SCR3_DLLAPD_DIS;
 +      val |= BIT(8);
 +
 +      ret = bcm_phy_write_shadow(phydev, BCM54XX_SHD_SCR3, val);
 +      if (ret < 0)
 +              return ret;
 +
 +      return bcm_phy_enable_apd(phydev, true);
 +}
 +
 +static int bcm7xxx_16nm_ephy_resume(struct phy_device *phydev)
 +{
 +      int ret;
 +
 +      /* Re-apply workarounds coming out suspend/resume */
 +      ret = bcm7xxx_16nm_ephy_config_init(phydev);
 +      if (ret)
 +              return ret;
 +
 +      return genphy_config_aneg(phydev);
 +}
 +
+ #define MII_BCM7XXX_REG_INVALID       0xff
+ 
+ static u8 bcm7xxx_28nm_ephy_regnum_to_shd(u16 regnum)
+ {
+       switch (regnum) {
+       case MDIO_CTRL1:
+               return MII_BCM7XXX_SHD_3_PCS_CTRL;
+       case MDIO_STAT1:
+               return MII_BCM7XXX_SHD_3_PCS_STATUS;
+       case MDIO_PCS_EEE_ABLE:
+               return MII_BCM7XXX_SHD_3_EEE_CAP;
+       case MDIO_AN_EEE_ADV:
+               return MII_BCM7XXX_SHD_3_AN_EEE_ADV;
+       case MDIO_AN_EEE_LPABLE:
+               return MII_BCM7XXX_SHD_3_EEE_LP;
+       case MDIO_PCS_EEE_WK_ERR:
+               return MII_BCM7XXX_SHD_3_EEE_WK_ERR;
+       default:
+               return MII_BCM7XXX_REG_INVALID;
+       }
+ }
+ 
+ static bool bcm7xxx_28nm_ephy_dev_valid(int devnum)
+ {
+       return devnum == MDIO_MMD_AN || devnum == MDIO_MMD_PCS;
+ }
+ 
+ static int bcm7xxx_28nm_ephy_read_mmd(struct phy_device *phydev,
+                                     int devnum, u16 regnum)
+ {
+       u8 shd = bcm7xxx_28nm_ephy_regnum_to_shd(regnum);
+       int ret;
+ 
+       if (!bcm7xxx_28nm_ephy_dev_valid(devnum) ||
+           shd == MII_BCM7XXX_REG_INVALID)
+               return -EOPNOTSUPP;
+ 
+       /* set shadow mode 2 */
+       ret = __phy_set_clr_bits(phydev, MII_BCM7XXX_TEST,
+                                MII_BCM7XXX_SHD_MODE_2, 0);
+       if (ret < 0)
+               return ret;
+ 
+       /* Access the desired shadow register address */
+       ret = __phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL, shd);
+       if (ret < 0)
+               goto reset_shadow_mode;
+ 
+       ret = __phy_read(phydev, MII_BCM7XXX_SHD_2_CTRL_STAT);
+ 
+ reset_shadow_mode:
+       /* reset shadow mode 2 */
+       __phy_set_clr_bits(phydev, MII_BCM7XXX_TEST, 0,
+                          MII_BCM7XXX_SHD_MODE_2);
+       return ret;
+ }
+ 
+ static int bcm7xxx_28nm_ephy_write_mmd(struct phy_device *phydev,
+                                      int devnum, u16 regnum, u16 val)
+ {
+       u8 shd = bcm7xxx_28nm_ephy_regnum_to_shd(regnum);
+       int ret;
+ 
+       if (!bcm7xxx_28nm_ephy_dev_valid(devnum) ||
+           shd == MII_BCM7XXX_REG_INVALID)
+               return -EOPNOTSUPP;
+ 
+       /* set shadow mode 2 */
+       ret = __phy_set_clr_bits(phydev, MII_BCM7XXX_TEST,
+                                MII_BCM7XXX_SHD_MODE_2, 0);
+       if (ret < 0)
+               return ret;
+ 
+       /* Access the desired shadow register address */
+       ret = __phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL, shd);
+       if (ret < 0)
+               goto reset_shadow_mode;
+ 
+       /* Write the desired value in the shadow register */
+       __phy_write(phydev, MII_BCM7XXX_SHD_2_CTRL_STAT, val);
+ 
+ reset_shadow_mode:
+       /* reset shadow mode 2 */
+       return __phy_set_clr_bits(phydev, MII_BCM7XXX_TEST, 0,
+                                 MII_BCM7XXX_SHD_MODE_2);
+ }
+ 
  static int bcm7xxx_28nm_ephy_resume(struct phy_device *phydev)
  {
        int ret;

diff --cc include/net/sock.h
Simple merge

diff --cc net/bpf/test_run.c
index fcb2f49,b5f4ef3..bf1cb62
--- 1/net/bpf/test_run.c
--- 2/net/bpf/test_run.c
+++ b/net/bpf/test_run.c
@@@ -555,9 -550,14 +555,15 @@@ static void convert_skb_to___skb(struc
        memcpy(__skb->cb, &cb->data, QDISC_CB_PRIV_LEN);
        __skb->wire_len = cb->pkt_len;
        __skb->gso_segs = skb_shinfo(skb)->gso_segs;
 +      __skb->hwtstamp = skb_shinfo(skb)->hwtstamps.hwtstamp;
  }
  
+ static struct proto bpf_dummy_proto = {
+       .name   = "bpf_dummy",
+       .owner  = THIS_MODULE,
+       .obj_size = sizeof(struct sock),
+ };
+ 
  int bpf_prog_test_run_skb(struct bpf_prog *prog, const union bpf_attr *kattr,
                          union bpf_attr __user *uattr)
  {

diff --cc net/core/sock.c
Simple merge

diff --cc net/mptcp/mptcp_diag.c
Simple merge

diff --cc net/mptcp/protocol.c
Simple merge

diff --cc net/mptcp/protocol.h
Simple merge

diff --cc net/sched/sch_api.c
index e1a40d3,12f39a2..91820f6
--- 1/net/sched/sch_api.c
--- 2/net/sched/sch_api.c
+++ b/net/sched/sch_api.c
@@@ -514,7 -513,13 +514,13 @@@ static struct qdisc_size_table *qdisc_g
                return stab;
        }
  
 -      stab = kmalloc(sizeof(*stab) + tsize * sizeof(u16), GFP_KERNEL);
+       if (s->size_log > STAB_SIZE_LOG_MAX ||
+           s->cell_log > STAB_SIZE_LOG_MAX) {
+               NL_SET_ERR_MSG(extack, "Invalid logarithmic size of size table");
+               return ERR_PTR(-EINVAL);
+       }
+ 
 +      stab = kmalloc(struct_size(stab, data, tsize), GFP_KERNEL);
        if (!stab)
                return ERR_PTR(-ENOMEM);
  

diff --cc tools/testing/selftests/bpf/Makefile
Simple merge