drm/i915: stop using dev->agp->base
authorDaniel Vetter <daniel.vetter@ffwll.ch>
Thu, 7 Jun 2012 13:55:57 +0000 (15:55 +0200)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Tue, 12 Jun 2012 20:18:06 +0000 (22:18 +0200)
For that to work we need to export the base address of the gtt
mmio window from intel-gtt. Also replace all other uses of
dev->agp by values we already have at hand.

Reviewed-by: Jani Nikula <jani.nikula@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/char/agp/intel-gtt.c
drivers/gpu/drm/i915/i915_dma.c
drivers/gpu/drm/i915/i915_drv.h
drivers/gpu/drm/i915/i915_gem.c
drivers/gpu/drm/i915/i915_gem_debug.c
drivers/gpu/drm/i915/intel_display.c
drivers/gpu/drm/i915/intel_fb.c
drivers/gpu/drm/i915/intel_ringbuffer.c
include/drm/intel-gtt.h

index 53c4c7f..2aab0a0 100644 (file)
@@ -66,7 +66,6 @@ static struct _intel_private {
        struct pci_dev *bridge_dev;
        u8 __iomem *registers;
        phys_addr_t gtt_bus_addr;
-       phys_addr_t gma_bus_addr;
        u32 PGETBL_save;
        u32 __iomem *gtt;               /* I915G */
        bool clear_fake_agp; /* on first access via agp, fill with scratch */
@@ -779,7 +778,7 @@ static bool intel_enable_gtt(void)
                pci_read_config_dword(intel_private.pcidev, I915_GMADDR,
                                      &gma_addr);
 
-       intel_private.gma_bus_addr = (gma_addr & PCI_BASE_ADDRESS_MEM_MASK);
+       intel_private.base.gma_bus_addr = (gma_addr & PCI_BASE_ADDRESS_MEM_MASK);
 
        if (INTEL_GTT_GEN >= 6)
            return true;
@@ -860,7 +859,7 @@ static int intel_fake_agp_configure(void)
            return -EIO;
 
        intel_private.clear_fake_agp = true;
-       agp_bridge->gart_bus_addr = intel_private.gma_bus_addr;
+       agp_bridge->gart_bus_addr = intel_private.base.gma_bus_addr;
 
        return 0;
 }
index 97a5a58..c639d43 100644 (file)
@@ -1085,8 +1085,8 @@ static int i915_set_status_page(struct drm_device *dev, void *data,
 
        ring->status_page.gfx_addr = hws->addr & (0x1ffff<<12);
 
-       dev_priv->dri1.gfx_hws_cpu_addr = ioremap_wc(dev->agp->base + hws->addr,
-                                                    4096);
+       dev_priv->dri1.gfx_hws_cpu_addr =
+               ioremap_wc(dev_priv->mm.gtt_base_addr + hws->addr, 4096);
        if (dev_priv->dri1.gfx_hws_cpu_addr == NULL) {
                i915_dma_cleanup(dev);
                ring->status_page.gfx_addr = 0;
@@ -1482,15 +1482,18 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
        }
 
        aperture_size = dev_priv->mm.gtt->gtt_mappable_entries << PAGE_SHIFT;
+       dev_priv->mm.gtt_base_addr = dev_priv->mm.gtt->gma_bus_addr;
 
        dev_priv->mm.gtt_mapping =
-               io_mapping_create_wc(dev->agp->base, aperture_size);
+               io_mapping_create_wc(dev_priv->mm.gtt_base_addr,
+                                    aperture_size);
        if (dev_priv->mm.gtt_mapping == NULL) {
                ret = -EIO;
                goto out_rmmap;
        }
 
-       i915_mtrr_setup(dev_priv, dev->agp->base, aperture_size);
+       i915_mtrr_setup(dev_priv, dev_priv->mm.gtt_base_addr,
+                       aperture_size);
 
        /* The i915 workqueue is primarily used for batched retirement of
         * requests (and thus managing bo) once the task has been completed
@@ -1602,8 +1605,9 @@ out_gem_unload:
        destroy_workqueue(dev_priv->wq);
 out_mtrrfree:
        if (dev_priv->mm.gtt_mtrr >= 0) {
-               mtrr_del(dev_priv->mm.gtt_mtrr, dev->agp->base,
-                        dev->agp->agp_info.aper_size * 1024 * 1024);
+               mtrr_del(dev_priv->mm.gtt_mtrr,
+                        dev_priv->mm.gtt_base_addr,
+                        aperture_size);
                dev_priv->mm.gtt_mtrr = -1;
        }
        io_mapping_free(dev_priv->mm.gtt_mapping);
@@ -1640,8 +1644,9 @@ int i915_driver_unload(struct drm_device *dev)
 
        io_mapping_free(dev_priv->mm.gtt_mapping);
        if (dev_priv->mm.gtt_mtrr >= 0) {
-               mtrr_del(dev_priv->mm.gtt_mtrr, dev->agp->base,
-                        dev->agp->agp_info.aper_size * 1024 * 1024);
+               mtrr_del(dev_priv->mm.gtt_mtrr,
+                        dev_priv->mm.gtt_base_addr,
+                        dev_priv->mm.gtt->gtt_mappable_entries * PAGE_SIZE);
                dev_priv->mm.gtt_mtrr = -1;
        }
 
index ccabadd..ae4129b 100644 (file)
@@ -651,6 +651,7 @@ typedef struct drm_i915_private {
                unsigned long gtt_end;
 
                struct io_mapping *gtt_mapping;
+               phys_addr_t gtt_base_addr;
                int gtt_mtrr;
 
                /** PPGTT used for aliasing the PPGTT with the GTT */
index deaa0d4..108e4c2 100644 (file)
@@ -1122,7 +1122,7 @@ int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
 
        obj->fault_mappable = true;
 
-       pfn = ((dev->agp->base + obj->gtt_offset) >> PAGE_SHIFT) +
+       pfn = ((dev_priv->mm.gtt_base_addr + obj->gtt_offset) >> PAGE_SHIFT) +
                page_offset;
 
        /* Finally, remap it using the new GTT offset */
index a4f6aaa..bddf7be 100644 (file)
@@ -132,7 +132,8 @@ i915_gem_object_check_coherency(struct drm_i915_gem_object *obj, int handle)
                 __func__, obj, obj->gtt_offset, handle,
                 obj->size / 1024);
 
-       gtt_mapping = ioremap(dev->agp->base + obj->gtt_offset, obj->base.size);
+       gtt_mapping = ioremap(dev_priv->mm.gtt_base_addr + obj->gtt_offset,
+                             obj->base.size);
        if (gtt_mapping == NULL) {
                DRM_ERROR("failed to map GTT space\n");
                return;
index bad36e0..174549d 100644 (file)
@@ -6954,7 +6954,7 @@ void intel_modeset_init(struct drm_device *dev)
                dev->mode_config.max_width = 8192;
                dev->mode_config.max_height = 8192;
        }
-       dev->mode_config.fb_base = dev->agp->base;
+       dev->mode_config.fb_base = dev_priv->mm.gtt_base_addr;
 
        DRM_DEBUG_KMS("%d display pipe%s available.\n",
                      dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
index bf86907..e9f8338 100644 (file)
@@ -140,7 +140,9 @@ static int intelfb_create(struct intel_fbdev *ifbdev,
        info->fix.smem_start = dev->mode_config.fb_base + obj->gtt_offset;
        info->fix.smem_len = size;
 
-       info->screen_base = ioremap_wc(dev->agp->base + obj->gtt_offset, size);
+       info->screen_base =
+               ioremap_wc(dev_priv->mm.gtt_base_addr + obj->gtt_offset,
+                          size);
        if (!info->screen_base) {
                ret = -ENOSPC;
                goto out_unpin;
index 89a5e7f..14025ab 100644 (file)
@@ -968,6 +968,7 @@ static int intel_init_ring_buffer(struct drm_device *dev,
                                  struct intel_ring_buffer *ring)
 {
        struct drm_i915_gem_object *obj;
+       struct drm_i915_private *dev_priv = dev->dev_private;
        int ret;
 
        ring->dev = dev;
@@ -997,8 +998,9 @@ static int intel_init_ring_buffer(struct drm_device *dev,
        if (ret)
                goto err_unref;
 
-       ring->virtual_start = ioremap_wc(dev->agp->base + obj->gtt_offset,
-                                        ring->size);
+       ring->virtual_start =
+               ioremap_wc(dev_priv->mm.gtt->gma_bus_addr + obj->gtt_offset,
+                          ring->size);
        if (ring->virtual_start == NULL) {
                DRM_ERROR("Failed to map ringbuffer.\n");
                ret = -EINVAL;
index 923afb5..8048c00 100644 (file)
@@ -19,6 +19,8 @@ const struct intel_gtt {
        dma_addr_t scratch_page_dma;
        /* for ppgtt PDE access */
        u32 __iomem *gtt;
+       /* needed for ioremap in drm/i915 */
+       phys_addr_t gma_bus_addr;
 } *intel_gtt_get(void);
 
 void intel_gtt_chipset_flush(void);