dt-bindings: clock: add SM8250 QCOM video clock bindings

Add device tree bindings for video clock controller for SM8250 SoCs.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20200923160635.28370-4-jonathan@marek.ca
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

diff --git a/Documentation/devicetree/bindings/clock/qcom,videocc.yaml b/Documentation/devicetree/bindings/clock/qcom,videocc.yaml
index bb1c1a8..5672029 100644 (file)
--- a/Documentation/devicetree/bindings/clock/qcom,videocc.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,videocc.yaml
@@ -11,12 +11,13 @@ maintainers:
 
 description: |
   Qualcomm video clock control module which supports the clocks, resets and
-  power domains on SDM845/SC7180/SM8150.
+  power domains on SDM845/SC7180/SM8150/SM8250.
 
   See also:
     dt-bindings/clock/qcom,videocc-sc7180.h
     dt-bindings/clock/qcom,videocc-sdm845.h
     dt-bindings/clock/qcom,videocc-sm8150.h
+    dt-bindings/clock/qcom,videocc-sm8250.h
 
 properties:
   compatible:
@@ -24,6 +25,7 @@ properties:
       - qcom,sc7180-videocc
       - qcom,sdm845-videocc
       - qcom,sm8150-videocc
+      - qcom,sm8250-videocc
 
   clocks:
     items:

diff --git a/include/dt-bindings/clock/qcom,videocc-sm8250.h b/include/dt-bindings/clock/qcom,videocc-sm8250.h
new file mode 100644 (file)
index 0000000..2b2b386
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,videocc-sm8250.h
@@ -0,0 +1,34 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SM8250_H
+#define _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SM8250_H
+
+/* VIDEO_CC clocks */
+#define VIDEO_CC_MVS0_CLK_SRC          0
+#define VIDEO_CC_MVS0C_CLK             1
+#define VIDEO_CC_MVS0C_DIV2_DIV_CLK_SRC        2
+#define VIDEO_CC_MVS1_CLK_SRC          3
+#define VIDEO_CC_MVS1_DIV2_CLK         4
+#define VIDEO_CC_MVS1C_CLK             5
+#define VIDEO_CC_MVS1C_DIV2_DIV_CLK_SRC        6
+#define VIDEO_CC_PLL0                  7
+#define VIDEO_CC_PLL1                  8
+
+/* VIDEO_CC resets */
+#define VIDEO_CC_CVP_INTERFACE_BCR     0
+#define VIDEO_CC_CVP_MVS0_BCR          1
+#define VIDEO_CC_MVS0C_CLK_ARES                2
+#define VIDEO_CC_CVP_MVS0C_BCR         3
+#define VIDEO_CC_CVP_MVS1_BCR          4
+#define VIDEO_CC_MVS1C_CLK_ARES                5
+#define VIDEO_CC_CVP_MVS1C_BCR         6
+
+#define MVS0C_GDSC                     0
+#define MVS1C_GDSC                     1
+#define MVS0_GDSC                      2
+#define MVS1_GDSC                      3
+
+#endif