remoteproc: imx_rproc: correct firmware reload

ENABLE_M4 should be set to 1 when loading code to TCM, otherwise
you will not able to replace the firmware after you stop m4.

Besides ENABLE_M4, we still need set SW_M4C_RST, because this bit
will be automatically set with SW_M4C_NON_SCLR_RST set.

Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20210602064206.27004-1-peng.fan@oss.nxp.com

diff --git a/drivers/remoteproc/imx_rproc.c b/drivers/remoteproc/imx_rproc.c
index 0a45bc0..7a096f1 100644 (file)
--- a/drivers/remoteproc/imx_rproc.c
+++ b/drivers/remoteproc/imx_rproc.c
@@ -34,7 +34,8 @@
 
 #define IMX7D_M4_START                 (IMX7D_ENABLE_M4 | IMX7D_SW_M4P_RST \
                                         | IMX7D_SW_M4C_RST)
-#define IMX7D_M4_STOP                  IMX7D_SW_M4C_NON_SCLR_RST
+#define IMX7D_M4_STOP                  (IMX7D_ENABLE_M4 | IMX7D_SW_M4C_RST | \
+                                        IMX7D_SW_M4C_NON_SCLR_RST)
 
 /* Address: 0x020D8000 */
 #define IMX6SX_SRC_SCR                 0x00
@@ -45,7 +46,8 @@
 
 #define IMX6SX_M4_START                        (IMX6SX_ENABLE_M4 | IMX6SX_SW_M4P_RST \
                                         | IMX6SX_SW_M4C_RST)
-#define IMX6SX_M4_STOP                 IMX6SX_SW_M4C_NON_SCLR_RST
+#define IMX6SX_M4_STOP                 (IMX6SX_ENABLE_M4 | IMX6SX_SW_M4C_RST | \
+                                        IMX6SX_SW_M4C_NON_SCLR_RST)
 #define IMX6SX_M4_RST_MASK             (IMX6SX_ENABLE_M4 | IMX6SX_SW_M4P_RST \
                                         | IMX6SX_SW_M4C_NON_SCLR_RST \
                                         | IMX6SX_SW_M4C_RST)
@@ -684,7 +686,7 @@ static int imx_rproc_detect_mode(struct imx_rproc *priv)
                return ret;
        }
 
-       if (!(val & dcfg->src_stop))
+       if ((val & dcfg->src_mask) != dcfg->src_stop)
                priv->rproc->state = RPROC_DETACHED;
 
        return 0;