xtensa: xtfpga: fix ethernet controller endianness

Ethernet controller is attached to XTFPGA boards as native endian device,
mark it as such in DTS and pass correct endianness in platform data.
This makes network functional on big-endian CPUs.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>

diff --git a/arch/xtensa/boot/dts/xtfpga.dtsi b/arch/xtensa/boot/dts/xtfpga.dtsi
index be3fd76..de133ba 100644 (file)
--- a/arch/xtensa/boot/dts/xtfpga.dtsi
+++ b/arch/xtensa/boot/dts/xtfpga.dtsi
@@ -69,6 +69,7 @@
                enet0: ethoc@0d030000 {
                        compatible = "opencores,ethoc";
                        reg = <0x0d030000 0x4000 0x0d800000 0x4000>;
+                       native-endian;
                        interrupts = <1 1>; /* external irq 1 */
                        local-mac-address = [00 50 c2 13 6f 00];
                        clocks = <&osc>;

diff --git a/arch/xtensa/platforms/xtfpga/setup.c b/arch/xtensa/platforms/xtfpga/setup.c
index b7f468a..b509d1f 100644 (file)
--- a/arch/xtensa/platforms/xtfpga/setup.c
+++ b/arch/xtensa/platforms/xtfpga/setup.c
@@ -223,6 +223,7 @@ static struct ethoc_platform_data ethoc_pdata = {
         */
        .hwaddr = { 0x00, 0x50, 0xc2, 0x13, 0x6f, 0 },
        .phy_id = -1,
+       .big_endian = XCHAL_HAVE_BE,
 };
 
 static struct platform_device ethoc_device = {