drm/i915/gmbus: use intel_de_*() functions for register access

The implicit "dev_priv" local variable use has been a long-standing pain
point in the register access macros I915_READ(), I915_WRITE(),
POSTING_READ(), I915_READ_FW(), and I915_WRITE_FW().

Replace them with the corresponding new display engine register
accessors intel_de_read(), intel_de_write(), intel_de_posting_read(),
intel_de_read_fw(), and intel_de_write_fw().

No functional changes.

Generated using the following semantic patch:

@@
expression REG, OFFSET;
@@
- I915_READ(REG)
+ intel_de_read(dev_priv, REG)

@@
expression REG, OFFSET;
@@
- POSTING_READ(REG)
+ intel_de_posting_read(dev_priv, REG)

@@
expression REG, OFFSET;
@@
- I915_WRITE(REG, OFFSET)
+ intel_de_write(dev_priv, REG, OFFSET)

@@
expression REG;
@@
- I915_READ_FW(REG)
+ intel_de_read_fw(dev_priv, REG)

@@
expression REG, OFFSET;
@@
- I915_WRITE_FW(REG, OFFSET)
+ intel_de_write_fw(dev_priv, REG, OFFSET)

Acked-by: Chris Wilson <chris@chris-wilson.co.uk>
Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Acked-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/1fca6f7e201fb2c75fcfff213ebd982a988eb40d.1579871655.git.jani.nikula@intel.com

diff --git a/drivers/gpu/drm/i915/display/intel_gmbus.c b/drivers/gpu/drm/i915/display/intel_gmbus.c
index 3d4d19a..5083085 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_gmbus.c
+++ b/drivers/gpu/drm/i915/display/intel_gmbus.c
@@ -143,8 +143,8 @@ to_intel_gmbus(struct i2c_adapter *i2c)
 void
 intel_gmbus_reset(struct drm_i915_private *dev_priv)
 {
-       I915_WRITE(GMBUS0, 0);
-       I915_WRITE(GMBUS4, 0);
+       intel_de_write(dev_priv, GMBUS0, 0);
+       intel_de_write(dev_priv, GMBUS4, 0);
 }
 
 static void pnv_gmbus_clock_gating(struct drm_i915_private *dev_priv,
@@ -153,12 +153,12 @@ static void pnv_gmbus_clock_gating(struct drm_i915_private *dev_priv,
        u32 val;
 
        /* When using bit bashing for I2C, this bit needs to be set to 1 */
-       val = I915_READ(DSPCLK_GATE_D);
+       val = intel_de_read(dev_priv, DSPCLK_GATE_D);
        if (!enable)
                val |= PNV_GMBUSUNIT_CLOCK_GATE_DISABLE;
        else
                val &= ~PNV_GMBUSUNIT_CLOCK_GATE_DISABLE;
-       I915_WRITE(DSPCLK_GATE_D, val);
+       intel_de_write(dev_priv, DSPCLK_GATE_D, val);
 }
 
 static void pch_gmbus_clock_gating(struct drm_i915_private *dev_priv,
@@ -166,12 +166,12 @@ static void pch_gmbus_clock_gating(struct drm_i915_private *dev_priv,
 {
        u32 val;
 
-       val = I915_READ(SOUTH_DSPCLK_GATE_D);
+       val = intel_de_read(dev_priv, SOUTH_DSPCLK_GATE_D);
        if (!enable)
                val |= PCH_GMBUSUNIT_CLOCK_GATE_DISABLE;
        else
                val &= ~PCH_GMBUSUNIT_CLOCK_GATE_DISABLE;
-       I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
+       intel_de_write(dev_priv, SOUTH_DSPCLK_GATE_D, val);
 }
 
 static void bxt_gmbus_clock_gating(struct drm_i915_private *dev_priv,
@@ -179,12 +179,12 @@ static void bxt_gmbus_clock_gating(struct drm_i915_private *dev_priv,
 {
        u32 val;
 
-       val = I915_READ(GEN9_CLKGATE_DIS_4);
+       val = intel_de_read(dev_priv, GEN9_CLKGATE_DIS_4);
        if (!enable)
                val |= BXT_GMBUS_GATING_DIS;
        else
                val &= ~BXT_GMBUS_GATING_DIS;
-       I915_WRITE(GEN9_CLKGATE_DIS_4, val);
+       intel_de_write(dev_priv, GEN9_CLKGATE_DIS_4, val);
 }
 
 static u32 get_reserved(struct intel_gmbus *bus)
@@ -337,14 +337,16 @@ static int gmbus_wait(struct drm_i915_private *dev_priv, u32 status, u32 irq_en)
                irq_en = 0;
 
        add_wait_queue(&dev_priv->gmbus_wait_queue, &wait);
-       I915_WRITE_FW(GMBUS4, irq_en);
+       intel_de_write_fw(dev_priv, GMBUS4, irq_en);
 
        status |= GMBUS_SATOER;
-       ret = wait_for_us((gmbus2 = I915_READ_FW(GMBUS2)) & status, 2);
+       ret = wait_for_us((gmbus2 = intel_de_read_fw(dev_priv, GMBUS2)) & status,
+                         2);
        if (ret)
-               ret = wait_for((gmbus2 = I915_READ_FW(GMBUS2)) & status, 50);
+               ret = wait_for((gmbus2 = intel_de_read_fw(dev_priv, GMBUS2)) & status,
+                              50);
 
-       I915_WRITE_FW(GMBUS4, 0);
+       intel_de_write_fw(dev_priv, GMBUS4, 0);
        remove_wait_queue(&dev_priv->gmbus_wait_queue, &wait);
 
        if (gmbus2 & GMBUS_SATOER)
@@ -366,13 +368,13 @@ gmbus_wait_idle(struct drm_i915_private *dev_priv)
                irq_enable = GMBUS_IDLE_EN;
 
        add_wait_queue(&dev_priv->gmbus_wait_queue, &wait);
-       I915_WRITE_FW(GMBUS4, irq_enable);
+       intel_de_write_fw(dev_priv, GMBUS4, irq_enable);
 
        ret = intel_wait_for_register_fw(&dev_priv->uncore,
                                         GMBUS2, GMBUS_ACTIVE, 0,
                                         10);
 
-       I915_WRITE_FW(GMBUS4, 0);
+       intel_de_write_fw(dev_priv, GMBUS4, 0);
        remove_wait_queue(&dev_priv->gmbus_wait_queue, &wait);
 
        return ret;
@@ -404,15 +406,12 @@ gmbus_xfer_read_chunk(struct drm_i915_private *dev_priv,
                        len++;
                }
                size = len % 256 + 256;
-               I915_WRITE_FW(GMBUS0, gmbus0_reg | GMBUS_BYTE_CNT_OVERRIDE);
+               intel_de_write_fw(dev_priv, GMBUS0,
+                                 gmbus0_reg | GMBUS_BYTE_CNT_OVERRIDE);
        }
 
-       I915_WRITE_FW(GMBUS1,
-                     gmbus1_index |
-                     GMBUS_CYCLE_WAIT |
-                     (size << GMBUS_BYTE_COUNT_SHIFT) |
-                     (addr << GMBUS_SLAVE_ADDR_SHIFT) |
-                     GMBUS_SLAVE_READ | GMBUS_SW_RDY);
+       intel_de_write_fw(dev_priv, GMBUS1,
+                         gmbus1_index | GMBUS_CYCLE_WAIT | (size << GMBUS_BYTE_COUNT_SHIFT) | (addr << GMBUS_SLAVE_ADDR_SHIFT) | GMBUS_SLAVE_READ | GMBUS_SW_RDY);
        while (len) {
                int ret;
                u32 val, loop = 0;
@@ -421,7 +420,7 @@ gmbus_xfer_read_chunk(struct drm_i915_private *dev_priv,
                if (ret)
                        return ret;
 
-               val = I915_READ_FW(GMBUS3);
+               val = intel_de_read_fw(dev_priv, GMBUS3);
                do {
                        if (extra_byte_added && len == 1)
                                break;
@@ -432,7 +431,7 @@ gmbus_xfer_read_chunk(struct drm_i915_private *dev_priv,
 
                if (burst_read && len == size - 4)
                        /* Reset the override bit */
-                       I915_WRITE_FW(GMBUS0, gmbus0_reg);
+                       intel_de_write_fw(dev_priv, GMBUS0, gmbus0_reg);
        }
 
        return 0;
@@ -489,12 +488,9 @@ gmbus_xfer_write_chunk(struct drm_i915_private *dev_priv,
                len -= 1;
        }
 
-       I915_WRITE_FW(GMBUS3, val);
-       I915_WRITE_FW(GMBUS1,
-                     gmbus1_index | GMBUS_CYCLE_WAIT |
-                     (chunk_size << GMBUS_BYTE_COUNT_SHIFT) |
-                     (addr << GMBUS_SLAVE_ADDR_SHIFT) |
-                     GMBUS_SLAVE_WRITE | GMBUS_SW_RDY);
+       intel_de_write_fw(dev_priv, GMBUS3, val);
+       intel_de_write_fw(dev_priv, GMBUS1,
+                         gmbus1_index | GMBUS_CYCLE_WAIT | (chunk_size << GMBUS_BYTE_COUNT_SHIFT) | (addr << GMBUS_SLAVE_ADDR_SHIFT) | GMBUS_SLAVE_WRITE | GMBUS_SW_RDY);
        while (len) {
                int ret;
 
@@ -503,7 +499,7 @@ gmbus_xfer_write_chunk(struct drm_i915_private *dev_priv,
                        val |= *buf++ << (8 * loop);
                } while (--len && ++loop < 4);
 
-               I915_WRITE_FW(GMBUS3, val);
+               intel_de_write_fw(dev_priv, GMBUS3, val);
 
                ret = gmbus_wait(dev_priv, GMBUS_HW_RDY, GMBUS_HW_RDY_EN);
                if (ret)
@@ -568,7 +564,7 @@ gmbus_index_xfer(struct drm_i915_private *dev_priv, struct i2c_msg *msgs,
 
        /* GMBUS5 holds 16-bit index */
        if (gmbus5)
-               I915_WRITE_FW(GMBUS5, gmbus5);
+               intel_de_write_fw(dev_priv, GMBUS5, gmbus5);
 
        if (msgs[1].flags & I2C_M_RD)
                ret = gmbus_xfer_read(dev_priv, &msgs[1], gmbus0_reg,
@@ -578,7 +574,7 @@ gmbus_index_xfer(struct drm_i915_private *dev_priv, struct i2c_msg *msgs,
 
        /* Clear GMBUS5 after each index transfer */
        if (gmbus5)
-               I915_WRITE_FW(GMBUS5, 0);
+               intel_de_write_fw(dev_priv, GMBUS5, 0);
 
        return ret;
 }
@@ -601,7 +597,7 @@ do_gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num,
                pch_gmbus_clock_gating(dev_priv, false);
 
 retry:
-       I915_WRITE_FW(GMBUS0, gmbus0_source | bus->reg0);
+       intel_de_write_fw(dev_priv, GMBUS0, gmbus0_source | bus->reg0);
 
        for (; i < num; i += inc) {
                inc = 1;
@@ -629,7 +625,7 @@ retry:
         * a STOP on the very first cycle. To simplify the code we
         * unconditionally generate the STOP condition with an additional gmbus
         * cycle. */
-       I915_WRITE_FW(GMBUS1, GMBUS_CYCLE_STOP | GMBUS_SW_RDY);
+       intel_de_write_fw(dev_priv, GMBUS1, GMBUS_CYCLE_STOP | GMBUS_SW_RDY);
 
        /* Mark the GMBUS interface as disabled after waiting for idle.
         * We will re-enable it at the start of the next xfer,
@@ -640,7 +636,7 @@ retry:
                         adapter->name);
                ret = -ETIMEDOUT;
        }
-       I915_WRITE_FW(GMBUS0, 0);
+       intel_de_write_fw(dev_priv, GMBUS0, 0);
        ret = ret ?: i;
        goto out;
 
@@ -669,9 +665,9 @@ clear_err:
         * of resetting the GMBUS controller and so clearing the
         * BUS_ERROR raised by the slave's NAK.
         */
-       I915_WRITE_FW(GMBUS1, GMBUS_SW_CLR_INT);
-       I915_WRITE_FW(GMBUS1, 0);
-       I915_WRITE_FW(GMBUS0, 0);
+       intel_de_write_fw(dev_priv, GMBUS1, GMBUS_SW_CLR_INT);
+       intel_de_write_fw(dev_priv, GMBUS1, 0);
+       intel_de_write_fw(dev_priv, GMBUS0, 0);
 
        DRM_DEBUG_KMS("GMBUS [%s] NAK for addr: %04x %c(%d)\n",
                         adapter->name, msgs[i].addr,
@@ -694,7 +690,7 @@ clear_err:
 timeout:
        DRM_DEBUG_KMS("GMBUS [%s] timed out, falling back to bit banging on pin %d\n",
                      bus->adapter.name, bus->reg0 & 0xff);
-       I915_WRITE_FW(GMBUS0, 0);
+       intel_de_write_fw(dev_priv, GMBUS0, 0);
 
        /*
         * Hardware may not support GMBUS over these pins? Try GPIO bitbanging