net: pcs: xpcs: move register bit descriptions to a header file

Vendors which integrate the Designware XPCS might modify a few things
here and there, and to support those, it's best to create separate C
files in order to not clutter up the main pcs-xpcs.c.

Because the vendor files might want to access the common xpcs registers
too, let's move them in a header file which is local to this driver and
can be included by vendor files as appropriate.

Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

diff --git a/MAINTAINERS b/MAINTAINERS
index 2172f59..c821423 100644 (file)
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -17676,6 +17676,7 @@ M:      Jose Abreu <Jose.Abreu@synopsys.com>
 L:     netdev@vger.kernel.org
 S:     Supported
 F:     drivers/net/pcs/pcs-xpcs.c
+F:     drivers/net/pcs/pcs-xpcs.h
 F:     include/linux/pcs/pcs-xpcs.h
 
 SYNOPSYS DESIGNWARE I2C DRIVER

diff --git a/drivers/net/pcs/pcs-xpcs.c b/drivers/net/pcs/pcs-xpcs.c
index a2cbb2d..8ca7592 100644 (file)
--- a/drivers/net/pcs/pcs-xpcs.c
+++ b/drivers/net/pcs/pcs-xpcs.c
@@ -11,102 +11,7 @@
 #include <linux/mdio.h>
 #include <linux/phylink.h>
 #include <linux/workqueue.h>
-
-#define SYNOPSYS_XPCS_ID               0x7996ced0
-#define SYNOPSYS_XPCS_MASK             0xffffffff
-
-/* Vendor regs access */
-#define DW_VENDOR                      BIT(15)
-
-/* VR_XS_PCS */
-#define DW_USXGMII_RST                 BIT(10)
-#define DW_USXGMII_EN                  BIT(9)
-#define DW_VR_XS_PCS_DIG_STS           0x0010
-#define DW_RXFIFO_ERR                  GENMASK(6, 5)
-
-/* SR_MII */
-#define DW_USXGMII_FULL                        BIT(8)
-#define DW_USXGMII_SS_MASK             (BIT(13) | BIT(6) | BIT(5))
-#define DW_USXGMII_10000               (BIT(13) | BIT(6))
-#define DW_USXGMII_5000                        (BIT(13) | BIT(5))
-#define DW_USXGMII_2500                        (BIT(5))
-#define DW_USXGMII_1000                        (BIT(6))
-#define DW_USXGMII_100                 (BIT(13))
-#define DW_USXGMII_10                  (0)
-
-/* SR_AN */
-#define DW_SR_AN_ADV1                  0x10
-#define DW_SR_AN_ADV2                  0x11
-#define DW_SR_AN_ADV3                  0x12
-#define DW_SR_AN_LP_ABL1               0x13
-#define DW_SR_AN_LP_ABL2               0x14
-#define DW_SR_AN_LP_ABL3               0x15
-
-/* Clause 73 Defines */
-/* AN_LP_ABL1 */
-#define DW_C73_PAUSE                   BIT(10)
-#define DW_C73_ASYM_PAUSE              BIT(11)
-#define DW_C73_AN_ADV_SF               0x1
-/* AN_LP_ABL2 */
-#define DW_C73_1000KX                  BIT(5)
-#define DW_C73_10000KX4                        BIT(6)
-#define DW_C73_10000KR                 BIT(7)
-/* AN_LP_ABL3 */
-#define DW_C73_2500KX                  BIT(0)
-#define DW_C73_5000KR                  BIT(1)
-
-/* Clause 37 Defines */
-/* VR MII MMD registers offsets */
-#define DW_VR_MII_MMD_CTRL             0x0000
-#define DW_VR_MII_DIG_CTRL1            0x8000
-#define DW_VR_MII_AN_CTRL              0x8001
-#define DW_VR_MII_AN_INTR_STS          0x8002
-/* Enable 2.5G Mode */
-#define DW_VR_MII_DIG_CTRL1_2G5_EN     BIT(2)
-/* EEE Mode Control Register */
-#define DW_VR_MII_EEE_MCTRL0           0x8006
-#define DW_VR_MII_EEE_MCTRL1           0x800b
-
-/* VR_MII_DIG_CTRL1 */
-#define DW_VR_MII_DIG_CTRL1_MAC_AUTO_SW                BIT(9)
-
-/* VR_MII_AN_CTRL */
-#define DW_VR_MII_AN_CTRL_TX_CONFIG_SHIFT      3
-#define DW_VR_MII_TX_CONFIG_MASK               BIT(3)
-#define DW_VR_MII_TX_CONFIG_PHY_SIDE_SGMII     0x1
-#define DW_VR_MII_TX_CONFIG_MAC_SIDE_SGMII     0x0
-#define DW_VR_MII_AN_CTRL_PCS_MODE_SHIFT       1
-#define DW_VR_MII_PCS_MODE_MASK                        GENMASK(2, 1)
-#define DW_VR_MII_PCS_MODE_C37_1000BASEX       0x0
-#define DW_VR_MII_PCS_MODE_C37_SGMII           0x2
-
-/* VR_MII_AN_INTR_STS */
-#define DW_VR_MII_AN_STS_C37_ANSGM_FD          BIT(1)
-#define DW_VR_MII_AN_STS_C37_ANSGM_SP_SHIFT    2
-#define DW_VR_MII_AN_STS_C37_ANSGM_SP          GENMASK(3, 2)
-#define DW_VR_MII_C37_ANSGM_SP_10              0x0
-#define DW_VR_MII_C37_ANSGM_SP_100             0x1
-#define DW_VR_MII_C37_ANSGM_SP_1000            0x2
-#define DW_VR_MII_C37_ANSGM_SP_LNKSTS          BIT(4)
-
-/* SR MII MMD Control defines */
-#define AN_CL37_EN             BIT(12) /* Enable Clause 37 auto-nego */
-#define SGMII_SPEED_SS13       BIT(13) /* SGMII speed along with SS6 */
-#define SGMII_SPEED_SS6                BIT(6)  /* SGMII speed along with SS13 */
-
-/* VR MII EEE Control 0 defines */
-#define DW_VR_MII_EEE_LTX_EN           BIT(0)  /* LPI Tx Enable */
-#define DW_VR_MII_EEE_LRX_EN           BIT(1)  /* LPI Rx Enable */
-#define DW_VR_MII_EEE_TX_QUIET_EN              BIT(2)  /* Tx Quiet Enable */
-#define DW_VR_MII_EEE_RX_QUIET_EN              BIT(3)  /* Rx Quiet Enable */
-#define DW_VR_MII_EEE_TX_EN_CTRL               BIT(4)  /* Tx Control Enable */
-#define DW_VR_MII_EEE_RX_EN_CTRL               BIT(7)  /* Rx Control Enable */
-
-#define DW_VR_MII_EEE_MULT_FACT_100NS_SHIFT    8
-#define DW_VR_MII_EEE_MULT_FACT_100NS          GENMASK(11, 8)
-
-/* VR MII EEE Control 1 defines */
-#define DW_VR_MII_EEE_TRN_LPI          BIT(0)  /* Transparent Mode Enable */
+#include "pcs-xpcs.h"
 
 #define phylink_pcs_to_xpcs(pl_pcs) \
        container_of((pl_pcs), struct dw_xpcs, pcs)

diff --git a/drivers/net/pcs/pcs-xpcs.h b/drivers/net/pcs/pcs-xpcs.h
new file mode 100644 (file)
index 0000000..867537a
--- /dev/null
+++ b/drivers/net/pcs/pcs-xpcs.h
@@ -0,0 +1,103 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2020 Synopsys, Inc. and/or its affiliates.
+ * Synopsys DesignWare XPCS helpers
+ *
+ * Author: Jose Abreu <Jose.Abreu@synopsys.com>
+ */
+
+#define SYNOPSYS_XPCS_ID               0x7996ced0
+#define SYNOPSYS_XPCS_MASK             0xffffffff
+
+/* Vendor regs access */
+#define DW_VENDOR                      BIT(15)
+
+/* VR_XS_PCS */
+#define DW_USXGMII_RST                 BIT(10)
+#define DW_USXGMII_EN                  BIT(9)
+#define DW_VR_XS_PCS_DIG_STS           0x0010
+#define DW_RXFIFO_ERR                  GENMASK(6, 5)
+
+/* SR_MII */
+#define DW_USXGMII_FULL                        BIT(8)
+#define DW_USXGMII_SS_MASK             (BIT(13) | BIT(6) | BIT(5))
+#define DW_USXGMII_10000               (BIT(13) | BIT(6))
+#define DW_USXGMII_5000                        (BIT(13) | BIT(5))
+#define DW_USXGMII_2500                        (BIT(5))
+#define DW_USXGMII_1000                        (BIT(6))
+#define DW_USXGMII_100                 (BIT(13))
+#define DW_USXGMII_10                  (0)
+
+/* SR_AN */
+#define DW_SR_AN_ADV1                  0x10
+#define DW_SR_AN_ADV2                  0x11
+#define DW_SR_AN_ADV3                  0x12
+#define DW_SR_AN_LP_ABL1               0x13
+#define DW_SR_AN_LP_ABL2               0x14
+#define DW_SR_AN_LP_ABL3               0x15
+
+/* Clause 73 Defines */
+/* AN_LP_ABL1 */
+#define DW_C73_PAUSE                   BIT(10)
+#define DW_C73_ASYM_PAUSE              BIT(11)
+#define DW_C73_AN_ADV_SF               0x1
+/* AN_LP_ABL2 */
+#define DW_C73_1000KX                  BIT(5)
+#define DW_C73_10000KX4                        BIT(6)
+#define DW_C73_10000KR                 BIT(7)
+/* AN_LP_ABL3 */
+#define DW_C73_2500KX                  BIT(0)
+#define DW_C73_5000KR                  BIT(1)
+
+/* Clause 37 Defines */
+/* VR MII MMD registers offsets */
+#define DW_VR_MII_MMD_CTRL             0x0000
+#define DW_VR_MII_DIG_CTRL1            0x8000
+#define DW_VR_MII_AN_CTRL              0x8001
+#define DW_VR_MII_AN_INTR_STS          0x8002
+/* Enable 2.5G Mode */
+#define DW_VR_MII_DIG_CTRL1_2G5_EN     BIT(2)
+/* EEE Mode Control Register */
+#define DW_VR_MII_EEE_MCTRL0           0x8006
+#define DW_VR_MII_EEE_MCTRL1           0x800b
+
+/* VR_MII_DIG_CTRL1 */
+#define DW_VR_MII_DIG_CTRL1_MAC_AUTO_SW                BIT(9)
+
+/* VR_MII_AN_CTRL */
+#define DW_VR_MII_AN_CTRL_TX_CONFIG_SHIFT      3
+#define DW_VR_MII_TX_CONFIG_MASK               BIT(3)
+#define DW_VR_MII_TX_CONFIG_PHY_SIDE_SGMII     0x1
+#define DW_VR_MII_TX_CONFIG_MAC_SIDE_SGMII     0x0
+#define DW_VR_MII_AN_CTRL_PCS_MODE_SHIFT       1
+#define DW_VR_MII_PCS_MODE_MASK                        GENMASK(2, 1)
+#define DW_VR_MII_PCS_MODE_C37_1000BASEX       0x0
+#define DW_VR_MII_PCS_MODE_C37_SGMII           0x2
+
+/* VR_MII_AN_INTR_STS */
+#define DW_VR_MII_AN_STS_C37_ANSGM_FD          BIT(1)
+#define DW_VR_MII_AN_STS_C37_ANSGM_SP_SHIFT    2
+#define DW_VR_MII_AN_STS_C37_ANSGM_SP          GENMASK(3, 2)
+#define DW_VR_MII_C37_ANSGM_SP_10              0x0
+#define DW_VR_MII_C37_ANSGM_SP_100             0x1
+#define DW_VR_MII_C37_ANSGM_SP_1000            0x2
+#define DW_VR_MII_C37_ANSGM_SP_LNKSTS          BIT(4)
+
+/* SR MII MMD Control defines */
+#define AN_CL37_EN                     BIT(12) /* Enable Clause 37 auto-nego */
+#define SGMII_SPEED_SS13               BIT(13) /* SGMII speed along with SS6 */
+#define SGMII_SPEED_SS6                        BIT(6)  /* SGMII speed along with SS13 */
+
+/* VR MII EEE Control 0 defines */
+#define DW_VR_MII_EEE_LTX_EN                   BIT(0)  /* LPI Tx Enable */
+#define DW_VR_MII_EEE_LRX_EN                   BIT(1)  /* LPI Rx Enable */
+#define DW_VR_MII_EEE_TX_QUIET_EN              BIT(2)  /* Tx Quiet Enable */
+#define DW_VR_MII_EEE_RX_QUIET_EN              BIT(3)  /* Rx Quiet Enable */
+#define DW_VR_MII_EEE_TX_EN_CTRL               BIT(4)  /* Tx Control Enable */
+#define DW_VR_MII_EEE_RX_EN_CTRL               BIT(7)  /* Rx Control Enable */
+
+#define DW_VR_MII_EEE_MULT_FACT_100NS_SHIFT    8
+#define DW_VR_MII_EEE_MULT_FACT_100NS          GENMASK(11, 8)
+
+/* VR MII EEE Control 1 defines */
+#define DW_VR_MII_EEE_TRN_LPI          BIT(0)  /* Transparent Mode Enable */