RDMA/hns: Eanble SRQ capacity for hip08
authorLijun Ou <oulijun@huawei.com>
Sat, 24 Nov 2018 08:49:19 +0000 (16:49 +0800)
committerJason Gunthorpe <jgg@mellanox.com>
Wed, 5 Dec 2018 14:59:13 +0000 (07:59 -0700)
This patch configures the flags for enabling the
SRQ(Share Receive Queue) capacity as well as update the
verb of querying device for setting srq specifications.

Signed-off-by: Lijun Ou <oulijun@huawei.com>
Signed-off-by: Jason Gunthorpe <jgg@mellanox.com>
drivers/infiniband/hw/hns/hns_roce_device.h
drivers/infiniband/hw/hns/hns_roce_hw_v2.c
drivers/infiniband/hw/hns/hns_roce_hw_v2.h
drivers/infiniband/hw/hns/hns_roce_main.c

index d39bdfd..42ff400 100644 (file)
@@ -196,6 +196,7 @@ enum {
        HNS_ROCE_CAP_FLAG_RQ_INLINE             = BIT(2),
        HNS_ROCE_CAP_FLAG_RECORD_DB             = BIT(3),
        HNS_ROCE_CAP_FLAG_SQ_RECORD_DB          = BIT(4),
+       HNS_ROCE_CAP_FLAG_SRQ                   = BIT(5),
        HNS_ROCE_CAP_FLAG_MW                    = BIT(7),
        HNS_ROCE_CAP_FLAG_FRMR                  = BIT(8),
        HNS_ROCE_CAP_FLAG_ATOMIC                = BIT(10),
@@ -680,6 +681,9 @@ struct hns_roce_caps {
        int             num_qps;        /* 256k */
        int             reserved_qps;
        u32             max_wqes;       /* 16k */
+       u32             max_srqs;
+       u32             max_srq_wrs;
+       u32             max_srq_sges;
        u32             max_sq_desc_sz; /* 64 */
        u32             max_rq_desc_sz; /* 64 */
        u32             max_srq_desc_sz;
index d4609e7..2fec1f2 100644 (file)
@@ -1354,8 +1354,13 @@ static int hns_roce_v2_profile(struct hns_roce_dev *hr_dev)
        caps->local_ca_ack_delay = 0;
        caps->max_mtu = IB_MTU_4096;
 
+       caps->max_srqs          = HNS_ROCE_V2_MAX_SRQ;
+       caps->max_srq_wrs       = HNS_ROCE_V2_MAX_SRQ_WR;
+       caps->max_srq_sges      = HNS_ROCE_V2_MAX_SRQ_SGE;
+
        if (hr_dev->pci_dev->revision == 0x21)
-               caps->flags |= HNS_ROCE_CAP_FLAG_ATOMIC;
+               caps->flags |= HNS_ROCE_CAP_FLAG_ATOMIC |
+                              HNS_ROCE_CAP_FLAG_SRQ;
 
        ret = hns_roce_v2_set_bt(hr_dev);
        if (ret)
index 8bc8206..24a4851 100644 (file)
@@ -46,6 +46,9 @@
 
 #define HNS_ROCE_V2_MAX_QP_NUM                 0x2000
 #define HNS_ROCE_V2_MAX_WQE_NUM                        0x8000
+#define        HNS_ROCE_V2_MAX_SRQ                     0x100000
+#define HNS_ROCE_V2_MAX_SRQ_WR                 0x8000
+#define HNS_ROCE_V2_MAX_SRQ_SGE                        0x100
 #define HNS_ROCE_V2_MAX_CQ_NUM                 0x8000
 #define HNS_ROCE_V2_MAX_CQE_NUM                        0x10000
 #define HNS_ROCE_V2_MAX_RQ_SGE_NUM             0x100
index 1b3ee51..f6f288f 100644 (file)
@@ -220,6 +220,11 @@ static int hns_roce_query_device(struct ib_device *ib_dev,
                            IB_ATOMIC_HCA : IB_ATOMIC_NONE;
        props->max_pkeys = 1;
        props->local_ca_ack_delay = hr_dev->caps.local_ca_ack_delay;
+       if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_SRQ) {
+               props->max_srq = hr_dev->caps.max_srqs;
+               props->max_srq_wr = hr_dev->caps.max_srq_wrs;
+               props->max_srq_sge = hr_dev->caps.max_srq_sges;
+       }
 
        return 0;
 }