drm/msm: add MSM_BO_CACHED_COHERENT

Add a new cache mode for creating coherent host-cached BOs.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Jordan Crouse <jcrouse@codeaurora.org>
Link: https://lore.kernel.org/r/20210423190833.25319-5-jonathan@marek.ca
Signed-off-by: Rob Clark <robdclark@chromium.org>

diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c
index 600d445..b3337b9 100644 (file)
--- a/drivers/gpu/drm/msm/adreno/adreno_device.c
+++ b/drivers/gpu/drm/msm/adreno/adreno_device.c
@@ -466,6 +466,7 @@ static int adreno_bind(struct device *dev, struct device *master, void *data)
                config.rev.minor, config.rev.patchid);
 
        priv->is_a2xx = config.rev.core == 2;
+       priv->has_cached_coherent = config.rev.core >= 6;
 
        gpu = info->init(drm);
        if (IS_ERR(gpu)) {

diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c
index 3ecf617..917856b 100644 (file)
--- a/drivers/gpu/drm/msm/msm_drv.c
+++ b/drivers/gpu/drm/msm/msm_drv.c
@@ -41,9 +41,10 @@
  * - 1.5.0 - Add SUBMITQUERY_QUERY ioctl
  * - 1.6.0 - Syncobj support
  * - 1.7.0 - Add MSM_PARAM_SUSPENDS to access suspend count
+ * - 1.8.0 - Add MSM_BO_CACHED_COHERENT for supported GPUs (a6xx)
  */
 #define MSM_VERSION_MAJOR      1
-#define MSM_VERSION_MINOR      7
+#define MSM_VERSION_MINOR      8
 #define MSM_VERSION_PATCHLEVEL 0
 
 static const struct drm_mode_config_funcs mode_config_funcs = {

diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h
index c33fc12..2f72eab 100644 (file)
--- a/drivers/gpu/drm/msm/msm_drv.h
+++ b/drivers/gpu/drm/msm/msm_drv.h
@@ -167,6 +167,7 @@ struct msm_drm_private {
        struct msm_file_private *lastctx;
        /* gpu is only set on open(), but we need this info earlier */
        bool is_a2xx;
+       bool has_cached_coherent;
 
        struct drm_fb_helper *fbdev;
 

diff --git a/drivers/gpu/drm/msm/msm_gem.c b/drivers/gpu/drm/msm/msm_gem.c
index ffe94bd..8d19a0f 100644 (file)
--- a/drivers/gpu/drm/msm/msm_gem.c
+++ b/drivers/gpu/drm/msm/msm_gem.c
@@ -445,6 +445,9 @@ static int msm_gem_pin_iova(struct drm_gem_object *obj,
        if (msm_obj->flags & MSM_BO_MAP_PRIV)
                prot |= IOMMU_PRIV;
 
+       if (msm_obj->flags & MSM_BO_CACHED_COHERENT)
+               prot |= IOMMU_CACHE;
+
        GEM_WARN_ON(!msm_gem_is_locked(obj));
 
        if (GEM_WARN_ON(msm_obj->madv != MSM_MADV_WILLNEED))
@@ -1158,6 +1161,7 @@ static int msm_gem_new_impl(struct drm_device *dev,
                uint32_t size, uint32_t flags,
                struct drm_gem_object **obj)
 {
+       struct msm_drm_private *priv = dev->dev_private;
        struct msm_gem_object *msm_obj;
 
        switch (flags & MSM_BO_CACHE_MASK) {
@@ -1165,6 +1169,10 @@ static int msm_gem_new_impl(struct drm_device *dev,
        case MSM_BO_CACHED:
        case MSM_BO_WC:
                break;
+       case MSM_BO_CACHED_COHERENT:
+               if (priv->has_cached_coherent)
+                       break;
+               /* fallthrough */
        default:
                DRM_DEV_ERROR(dev->dev, "invalid cache flag: %x\n",
                                (flags & MSM_BO_CACHE_MASK));

diff --git a/include/uapi/drm/msm_drm.h b/include/uapi/drm/msm_drm.h
index 5596d7c..a92d90a 100644 (file)
--- a/include/uapi/drm/msm_drm.h
+++ b/include/uapi/drm/msm_drm.h
@@ -95,12 +95,11 @@ struct drm_msm_param {
 #define MSM_BO_CACHED        0x00010000
 #define MSM_BO_WC            0x00020000
 #define MSM_BO_UNCACHED      0x00040000
+#define MSM_BO_CACHED_COHERENT 0x080000
 
 #define MSM_BO_FLAGS         (MSM_BO_SCANOUT | \
                               MSM_BO_GPU_READONLY | \
-                              MSM_BO_CACHED | \
-                              MSM_BO_WC | \
-                              MSM_BO_UNCACHED)
+                              MSM_BO_CACHE_MASK)
 
 struct drm_msm_gem_new {
        __u64 size;           /* in */