ARM: tegra: Modify reshift divider during LP1

The reshift hardware module implements the RAM re-repair process. This
module uses PLLP as an input clock during LP1 resume. The input divider
for this clock is typically set for PLLP's normal rate. During LP1
resume, PLLP is bypassed and so runs at the crystal rate, which is much
slower. Consequently, decrease the divider so that the reshift module
runs at a reasonable rate during LP1 resume.

NVIDIA's downstream kernel code only does this if not compiled for
Tegra30, so the added code is made conditional upon the chip ID.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

diff --git a/arch/arm/mach-tegra/sleep-tegra30.S b/arch/arm/mach-tegra/sleep-tegra30.S
index c796a97..f01ea3b 100644 (file)
--- a/arch/arm/mach-tegra/sleep-tegra30.S
+++ b/arch/arm/mach-tegra/sleep-tegra30.S
@@ -59,6 +59,9 @@
 #define CLK_RESET_PLLX_MISC3_IDDQ      3
 #define CLK_RESET_PLLM_MISC_IDDQ       5
 #define CLK_RESET_PLLC_MISC_IDDQ       26
+#define CLK_RESET_PLLP_RESHIFT         0x528
+#define CLK_RESET_PLLP_RESHIFT_DEFAULT 0x3b
+#define CLK_RESET_PLLP_RESHIFT_ENABLE  0x3
 
 #define CLK_RESET_CLK_SOURCE_MSELECT   0x3b4
 
@@ -373,9 +376,13 @@ _pll_m_c_x_done:
        tegra_get_soc_id TEGRA_APB_MISC_BASE, r1
        cmp     r1, #TEGRA30
        beq     1f
+
        ldr     r1, [r0, #CLK_RESET_PLLP_BASE]
        bic     r1, r1, #(1<<31)        @ disable PllP bypass
        str     r1, [r0, #CLK_RESET_PLLP_BASE]
+
+       mov     r1, #CLK_RESET_PLLP_RESHIFT_DEFAULT
+       str     r1, [r0, #CLK_RESET_PLLP_RESHIFT]
 1:
 
        mov32   r7, TEGRA_TMRUS_BASE
@@ -644,6 +651,10 @@ tegra30_switch_cpu_to_clk32k:
        orrne   r0, r0, #(1 << 31)      @ enable PllP bypass on fast cluster
        bic     r0, r0, #(1 << 30)
        str     r0, [r5, #CLK_RESET_PLLP_BASE]
+       beq     1f
+       mov     r0, #CLK_RESET_PLLP_RESHIFT_ENABLE
+       str     r0, [r5, #CLK_RESET_PLLP_RESHIFT]
+1:
        ldr     r0, [r5, #CLK_RESET_PLLA_BASE]
        bic     r0, r0, #(1 << 30)
        str     r0, [r5, #CLK_RESET_PLLA_BASE]