drm/amd/powerplay: enable APCC DFLL for sienna_cichlid

Enable APCC DFLL for sienna_cichlid.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
index e006792..2db4b3f 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
@@ -162,6 +162,7 @@ static struct smu_11_0_cmn2aisc_mapping sienna_cichlid_feature_mask_map[SMU_FEAT
        FEA_MAP(TEMP_DEPENDENT_VMIN),
        FEA_MAP(MMHUB_PG),
        FEA_MAP(ATHUB_PG),
+       FEA_MAP(APCC_DFLL),
 };
 
 static struct smu_11_0_cmn2aisc_mapping sienna_cichlid_table_map[SMU_TABLE_COUNT] = {
@@ -306,6 +307,7 @@ sienna_cichlid_get_allowed_feature_mask(struct smu_context *smu,
                                | FEATURE_MASK(FEATURE_PPT_BIT)
                                | FEATURE_MASK(FEATURE_TDC_BIT)
                                | FEATURE_MASK(FEATURE_BACO_BIT)
+                               | FEATURE_MASK(FEATURE_APCC_DFLL_BIT)
                                | FEATURE_MASK(FEATURE_FAN_CONTROL_BIT)
                                | FEATURE_MASK(FEATURE_THERMAL_BIT);