dt-bindings: clock: exynosautov9: add dpum clock

Add dpum clock definitions and compatibles.

Also used clock name 'bus' instead of full clock name
dout_clkcmu_dpum_bus like other board cmu schema (GS101).

Signed-off-by: Kwanghoon Son <k.son@samsung.com>
Link: https://lore.kernel.org/r/20240809-clk_dpum-v3-1-359decc30fe2@samsung.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

diff --git a/Documentation/devicetree/bindings/clock/samsung,exynosautov9-clock.yaml b/Documentation/devicetree/bindings/clock/samsung,exynosautov9-clock.yaml
index 55c4f94..32f39e5 100644 (file)
--- a/Documentation/devicetree/bindings/clock/samsung,exynosautov9-clock.yaml
+++ b/Documentation/devicetree/bindings/clock/samsung,exynosautov9-clock.yaml
@@ -35,6 +35,7 @@ properties:
       - samsung,exynosautov9-cmu-top
       - samsung,exynosautov9-cmu-busmc
       - samsung,exynosautov9-cmu-core
+      - samsung,exynosautov9-cmu-dpum
       - samsung,exynosautov9-cmu-fsys0
       - samsung,exynosautov9-cmu-fsys1
       - samsung,exynosautov9-cmu-fsys2
@@ -109,6 +110,24 @@ allOf:
             - const: oscclk
             - const: dout_clkcmu_core_bus
 
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: samsung,exynosautov9-cmu-dpum
+
+    then:
+      properties:
+        clocks:
+          items:
+            - description: External reference clock (26 MHz)
+            - description: DPU Main bus clock (from CMU_TOP)
+
+        clock-names:
+          items:
+            - const: oscclk
+            - const: bus
+
   - if:
       properties:
         compatible:

diff --git a/include/dt-bindings/clock/samsung,exynosautov9.h b/include/dt-bindings/clock/samsung,exynosautov9.h
index 3065375..ce8fb8f 100644 (file)
--- a/include/dt-bindings/clock/samsung,exynosautov9.h
+++ b/include/dt-bindings/clock/samsung,exynosautov9.h
@@ -179,6 +179,17 @@
 #define CLK_GOUT_CORE_CCI_PCLK         4
 #define CLK_GOUT_CORE_CMU_CORE_PCLK    5
 
+/* CMU_DPUM */
+#define CLK_MOUT_DPUM_BUS_USER         1
+#define CLK_DOUT_DPUM_BUSP             2
+#define CLK_GOUT_DPUM_ACLK_DECON       3
+#define CLK_GOUT_DPUM_ACLK_DMA         4
+#define CLK_GOUT_DPUM_ACLK_DPP         5
+#define CLK_GOUT_DPUM_SYSMMU_D0_CLK    6
+#define CLK_GOUT_DPUM_SYSMMU_D1_CLK    7
+#define CLK_GOUT_DPUM_SYSMMU_D2_CLK    8
+#define CLK_GOUT_DPUM_SYSMMU_D3_CLK    9
+
 /* CMU_FSYS0 */
 #define CLK_MOUT_FSYS0_BUS_USER                1
 #define CLK_MOUT_FSYS0_PCIE_USER       2