{
        switch (format) {
        case DRM_FORMAT_ARGB8888:
-               *mode = SUN8I_MIXER_CHAN_UI_LAYER_ATTR_FBFMT_ARGB8888;
+               *mode = SUN8I_MIXER_FBFMT_ARGB8888;
                break;
 
        case DRM_FORMAT_XRGB8888:
-               *mode = SUN8I_MIXER_CHAN_UI_LAYER_ATTR_FBFMT_XRGB8888;
+               *mode = SUN8I_MIXER_FBFMT_XRGB8888;
                break;
 
        case DRM_FORMAT_RGB888:
-               *mode = SUN8I_MIXER_CHAN_UI_LAYER_ATTR_FBFMT_RGB888;
+               *mode = SUN8I_MIXER_FBFMT_RGB888;
                break;
 
        default:
                return ret;
        }
 
+       val <<= SUN8I_MIXER_CHAN_UI_LAYER_ATTR_FBFMT_OFFSET;
        regmap_update_bits(mixer->engine.regs,
                           SUN8I_MIXER_CHAN_UI_LAYER_ATTR(chan, layer),
                           SUN8I_MIXER_CHAN_UI_LAYER_ATTR_FBFMT_MASK, val);
 
 #define SUN8I_MIXER_CHAN_UI_LAYER_ATTR_EN              BIT(0)
 #define SUN8I_MIXER_CHAN_UI_LAYER_ATTR_ALPHA_MODE_MASK GENMASK(2, 1)
 #define SUN8I_MIXER_CHAN_UI_LAYER_ATTR_FBFMT_MASK      GENMASK(12, 8)
+#define SUN8I_MIXER_CHAN_UI_LAYER_ATTR_FBFMT_OFFSET    8
 #define SUN8I_MIXER_CHAN_UI_LAYER_ATTR_ALPHA_MASK      GENMASK(31, 24)
 #define SUN8I_MIXER_CHAN_UI_LAYER_ATTR_ALPHA_MODE_DEF  (1 << 1)
-#define SUN8I_MIXER_CHAN_UI_LAYER_ATTR_FBFMT_ARGB8888  (0 << 8)
-#define SUN8I_MIXER_CHAN_UI_LAYER_ATTR_FBFMT_XRGB8888  (4 << 8)
-#define SUN8I_MIXER_CHAN_UI_LAYER_ATTR_FBFMT_RGB888    (8 << 8)
 #define SUN8I_MIXER_CHAN_UI_LAYER_ATTR_ALPHA_DEF       (0xff << 24)
 
+#define SUN8I_MIXER_FBFMT_ARGB8888     0
+#define SUN8I_MIXER_FBFMT_XRGB8888     4
+#define SUN8I_MIXER_FBFMT_RGB888       8
+
 /*
  * These sub-engines are still unknown now, the EN registers are here only to
  * be used to disable these sub-engines.