drm/amd/display: Add pixel rate div calcs and programming

[WHY/HOW]
Need to calculate and set some pixel rate divisors on correct otg_inst

Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Acked-by: Alex Hung <alex.hung@amd.com>
Signed-off-by: Michael Strauss <michael.strauss@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_dccg.c b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_dccg.c
index ea78da9..3852a6d 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_dccg.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_dccg.c
@@ -219,6 +219,21 @@ void dccg314_set_dpstreamclk(
        }
 }
 
+void dccg314_set_valid_pixel_rate(
+               struct dccg *dccg,
+               int ref_dtbclk_khz,
+               int otg_inst,
+               int pixclk_khz)
+{
+       struct dtbclk_dto_params dto_params = {0};
+
+       dto_params.ref_dtbclk_khz = ref_dtbclk_khz;
+       dto_params.otg_inst = otg_inst;
+       dto_params.pixclk_khz = pixclk_khz;
+
+       dccg314_set_dtbclk_dto(dccg, &dto_params);
+}
+
 static const struct dccg_funcs dccg314_funcs = {
        .update_dpp_dto = dccg31_update_dpp_dto,
        .get_dccg_ref_freq = dccg31_get_dccg_ref_freq,
@@ -237,6 +252,8 @@ static const struct dccg_funcs dccg314_funcs = {
        .set_dispclk_change_mode = dccg31_set_dispclk_change_mode,
        .disable_dsc = dccg31_disable_dscclk,
        .enable_dsc = dccg31_enable_dscclk,
+       .set_pixel_rate_div = dccg314_set_pixel_rate_div,
+       .set_valid_pixel_rate = dccg314_set_valid_pixel_rate,
 };
 
 struct dccg *dccg314_create(

diff --git a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_hwseq.c
index 90ec764..755c715 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_hwseq.c
@@ -338,3 +338,39 @@ void dcn314_enable_power_gating_plane(struct dce_hwseq *hws, bool enable)
        if (org_ip_request_cntl == 0)
                REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0);
 }
+
+unsigned int dcn314_calculate_dccg_k1_k2_values(struct pipe_ctx *pipe_ctx, unsigned int *k1_div, unsigned int *k2_div)
+{
+       struct dc_stream_state *stream = pipe_ctx->stream;
+       unsigned int odm_combine_factor = 0;
+
+       odm_combine_factor = get_odm_config(pipe_ctx, NULL);
+
+       if (is_dp_128b_132b_signal(pipe_ctx)) {
+               *k2_div = PIXEL_RATE_DIV_BY_1;
+       } else if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal) || dc_is_dvi_signal(pipe_ctx->stream->signal)) {
+               *k1_div = PIXEL_RATE_DIV_BY_1;
+               if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420)
+                       *k2_div = PIXEL_RATE_DIV_BY_2;
+               else
+                       *k2_div = PIXEL_RATE_DIV_BY_4;
+       } else if (dc_is_dp_signal(pipe_ctx->stream->signal)) {
+               if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) {
+                       *k1_div = PIXEL_RATE_DIV_BY_1;
+                       *k2_div = PIXEL_RATE_DIV_BY_2;
+               } else if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422) {
+                       *k1_div = PIXEL_RATE_DIV_BY_2;
+                       *k2_div = PIXEL_RATE_DIV_BY_2;
+               } else {
+                       if (odm_combine_factor == 1)
+                               *k2_div = PIXEL_RATE_DIV_BY_4;
+                       else if (odm_combine_factor == 2)
+                               *k2_div = PIXEL_RATE_DIV_BY_2;
+               }
+       }
+
+       if ((*k1_div == PIXEL_RATE_DIV_NA) && (*k2_div == PIXEL_RATE_DIV_NA))
+               ASSERT(false);
+
+       return odm_combine_factor;
+}

diff --git a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_hwseq.h b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_hwseq.h
index dfdd0b7..be0f5e4 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_hwseq.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_hwseq.h
@@ -37,4 +37,6 @@ void dcn314_dsc_pg_control(struct dce_hwseq *hws, unsigned int dsc_inst, bool po
 
 void dcn314_enable_power_gating_plane(struct dce_hwseq *hws, bool enable);
 
+unsigned int dcn314_calculate_dccg_k1_k2_values(struct pipe_ctx *pipe_ctx, unsigned int *k1_div, unsigned int *k2_div);
+
 #endif /* __DC_HWSS_DCN314_H__ */

diff --git a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_init.c b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_init.c
index c87b197..b9debeb 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_init.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_init.c
@@ -144,6 +144,7 @@ static const struct hwseq_private_funcs dcn314_private_funcs = {
        .set_blend_lut = dcn30_set_blend_lut,
        .set_shaper_3dlut = dcn20_set_shaper_3dlut,
        .setup_hpo_hw_control = dcn31_setup_hpo_hw_control,
+       .calculate_dccg_k1_k2_values = dcn314_calculate_dccg_k1_k2_values,
 };
 
 void dcn314_hw_sequencer_construct(struct dc *dc)