[AT91_SHDW_WKMODE0_ANYLEVEL] = "any",
};
-static void __iomem *at91_shdwc_base;
-static struct clk *sclk;
-static void __iomem *mpddrc_base;
+static struct shdwc {
+ struct clk *sclk;
+ void __iomem *shdwc_base;
+ void __iomem *mpddrc_base;
+} at91_shdwc;
static void __init at91_wakeup_status(struct platform_device *pdev)
{
const char *reason;
- u32 reg = readl(at91_shdwc_base + AT91_SHDW_SR);
+ u32 reg = readl(at91_shdwc.shdwc_base + AT91_SHDW_SR);
/* Simple power-on, just bail out */
if (!reg)
" b .\n\t"
:
- : "r" (mpddrc_base),
+ : "r" (at91_shdwc.mpddrc_base),
"r" cpu_to_le32(AT91_DDRSDRC_LPDDR2_PWOFF),
- "r" (at91_shdwc_base),
+ "r" (at91_shdwc.shdwc_base),
"r" cpu_to_le32(AT91_SHDW_KEY | AT91_SHDW_SHDW)
: "r6");
}
if (of_property_read_bool(np, "atmel,wakeup-rtt-timer"))
mode |= AT91_SHDW_RTTWKEN;
- writel(wakeup_mode | mode, at91_shdwc_base + AT91_SHDW_MR);
+ writel(wakeup_mode | mode, at91_shdwc.shdwc_base + AT91_SHDW_MR);
}
static int __init at91_poweroff_probe(struct platform_device *pdev)
int ret;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- at91_shdwc_base = devm_ioremap_resource(&pdev->dev, res);
- if (IS_ERR(at91_shdwc_base))
- return PTR_ERR(at91_shdwc_base);
+ at91_shdwc.shdwc_base = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(at91_shdwc.shdwc_base))
+ return PTR_ERR(at91_shdwc.shdwc_base);
- sclk = devm_clk_get(&pdev->dev, NULL);
- if (IS_ERR(sclk))
- return PTR_ERR(sclk);
+ at91_shdwc.sclk = devm_clk_get(&pdev->dev, NULL);
+ if (IS_ERR(at91_shdwc.sclk))
+ return PTR_ERR(at91_shdwc.sclk);
- ret = clk_prepare_enable(sclk);
+ ret = clk_prepare_enable(at91_shdwc.sclk);
if (ret) {
dev_err(&pdev->dev, "Could not enable slow clock\n");
return ret;
np = of_find_compatible_node(NULL, NULL, "atmel,sama5d3-ddramc");
if (np) {
- mpddrc_base = of_iomap(np, 0);
+ at91_shdwc.mpddrc_base = of_iomap(np, 0);
of_node_put(np);
- if (!mpddrc_base) {
+ if (!at91_shdwc.mpddrc_base) {
ret = -ENOMEM;
goto clk_disable;
}
- ddr_type = readl(mpddrc_base + AT91_DDRSDRC_MDR) &
+ ddr_type = readl(at91_shdwc.mpddrc_base + AT91_DDRSDRC_MDR) &
AT91_DDRSDRC_MD;
if (ddr_type != AT91_DDRSDRC_MD_LPDDR2 &&
ddr_type != AT91_DDRSDRC_MD_LPDDR3) {
- iounmap(mpddrc_base);
- mpddrc_base = NULL;
+ iounmap(at91_shdwc.mpddrc_base);
+ at91_shdwc.mpddrc_base = NULL;
}
}
return 0;
clk_disable:
- clk_disable_unprepare(sclk);
+ clk_disable_unprepare(at91_shdwc.sclk);
return ret;
}
if (pm_power_off == at91_poweroff)
pm_power_off = NULL;
- if (mpddrc_base)
- iounmap(mpddrc_base);
+ if (at91_shdwc.mpddrc_base)
+ iounmap(at91_shdwc.mpddrc_base);
- clk_disable_unprepare(sclk);
+ clk_disable_unprepare(at91_shdwc.sclk);
return 0;
}