drm/msm: Use nvmem_cell_read_variable_le_u32() to read speed bin

Let's use the newly-added nvmem_cell_read_variable_le_u32() to future
proof ourselves a little bit.

Signed-off-by: Douglas Anderson <dianders@chromium.org>
Link: https://lore.kernel.org/r/20210521134516.v2.1.Id496c6fea0cb92ff6ea8ef1faf5d468eb09465e3@changeid
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Rob Clark <robdclark@chromium.org>

diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index c19d2ae..fc12804 100644 (file)
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
@@ -1724,10 +1724,10 @@ static u32 fuse_to_supp_hw(struct device *dev, struct adreno_rev rev, u32 fuse)
 static int a6xx_set_supported_hw(struct device *dev, struct adreno_rev rev)
 {
        u32 supp_hw = UINT_MAX;
-       u16 speedbin;
+       u32 speedbin;
        int ret;
 
-       ret = nvmem_cell_read_u16(dev, "speed_bin", &speedbin);
+       ret = nvmem_cell_read_variable_le_u32(dev, "speed_bin", &speedbin);
        /*
         * -ENOENT means that the platform doesn't support speedbin which is
         * fine
@@ -1740,7 +1740,6 @@ static int a6xx_set_supported_hw(struct device *dev, struct adreno_rev rev)
                              ret);
                goto done;
        }
-       speedbin = le16_to_cpu(speedbin);
 
        supp_hw = fuse_to_supp_hw(dev, rev, speedbin);