drm/i915/power: move enum skl_power_gate under display
authorJani Nikula <jani.nikula@intel.com>
Wed, 25 Jun 2025 12:39:36 +0000 (15:39 +0300)
committerJani Nikula <jani.nikula@intel.com>
Thu, 26 Jun 2025 18:50:23 +0000 (21:50 +0300)
When the display registers were split off from i915_reg.h, enum
skl_power_gate was left behind. Move it to intel_display_regs.h.

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://lore.kernel.org/r/495054983b74163ca7dcbf5a1b6a24099047bc64.1750855148.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
drivers/gpu/drm/i915/display/intel_display_regs.h
drivers/gpu/drm/i915/i915_reg.h

index e101105..fdac72f 100644 (file)
 #define   HSW_PWR_WELL_FORCE_ON                        (1 << 19)
 #define HSW_PWR_WELL_CTL6                      _MMIO(0x45414)
 
+/* SKL Fuse Status */
+enum skl_power_gate {
+       SKL_PG0,
+       SKL_PG1,
+       SKL_PG2,
+       ICL_PG3,
+       ICL_PG4,
+};
+
 #define SKL_FUSE_STATUS                                _MMIO(0x42000)
 #define  SKL_FUSE_DOWNLOAD_STATUS              (1 << 31)
 /*
index 8d56b3c..03b8958 100644 (file)
  */
 #define GEN7_SO_WRITE_OFFSET(n)                _MMIO(0x5280 + (n) * 4)
 
-/* SKL Fuse Status */
-enum skl_power_gate {
-       SKL_PG0,
-       SKL_PG1,
-       SKL_PG2,
-       ICL_PG3,
-       ICL_PG4,
-};
-
-
 #define GEN9_TIMESTAMP_OVERRIDE                                _MMIO(0x44074)
 #define  GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_SHIFT      0
 #define  GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_MASK       0x3ff