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cxl/region: fix x9 interleave typo
author
Jim Harris
<jim.harris@samsung.com>
Fri, 3 Nov 2023 20:18:34 +0000
(20:18 +0000)
committer
Dan Williams
<dan.j.williams@intel.com>
Thu, 4 Jan 2024 01:55:20 +0000
(17:55 -0800)
CXL supports x3, x6 and x12 - not x9.
Fixes:
80d10a6cee050
("cxl/region: Add interleave geometry attributes")
Signed-off-by: Jim Harris <jim.harris@samsung.com>
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
Reviewed-by: Fan Ni <fan.ni@samsung.com>
Link:
https://lore.kernel.org/r/169904271254.204936.8580772404462743630.stgit@ubuntu
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
drivers/cxl/core/region.c
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diff --git
a/drivers/cxl/core/region.c
b/drivers/cxl/core/region.c
index
3e817a6
..
76fec47
100644
(file)
--- a/
drivers/cxl/core/region.c
+++ b/
drivers/cxl/core/region.c
@@
-397,7
+397,7
@@
static ssize_t interleave_ways_store(struct device *dev,
return rc;
/*
- * Even for x3, x
9
, and x12 interleaves the region interleave must be a
+ * Even for x3, x
6
, and x12 interleaves the region interleave must be a
* power of 2 multiple of the host bridge interleave.
*/
if (!is_power_of_2(val / cxld->interleave_ways) ||