drm/i915/dg2: Add DG2-specific shadow register table

We thought the DG2 table of shadowed registers would be the same as the
gen12/xehp table, but it turns out that there are a few minor
differences that require us to define a new DG2-specific table:
 * One register is removed (0xC4D4)
 * One register is added (0xC4E0)

Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210910201030.3436066-7-matthew.d.roper@intel.com

diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index 2547a9e..c8e7c71 100644 (file)
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -1016,6 +1016,45 @@ static const struct i915_range gen12_shadowed_regs[] = {
        { .start = 0x1F8510, .end = 0x1F8550 },
 };
 
+static const struct i915_range dg2_shadowed_regs[] = {
+       { .start =   0x2030, .end =   0x2030 },
+       { .start =   0x2510, .end =   0x2550 },
+       { .start =   0xA008, .end =   0xA00C },
+       { .start =   0xA188, .end =   0xA188 },
+       { .start =   0xA278, .end =   0xA278 },
+       { .start =   0xA540, .end =   0xA56C },
+       { .start =   0xC4C8, .end =   0xC4C8 },
+       { .start =   0xC4E0, .end =   0xC4E0 },
+       { .start =   0xC600, .end =   0xC600 },
+       { .start =   0xC658, .end =   0xC658 },
+       { .start =  0x22030, .end =  0x22030 },
+       { .start =  0x22510, .end =  0x22550 },
+       { .start = 0x1C0030, .end = 0x1C0030 },
+       { .start = 0x1C0510, .end = 0x1C0550 },
+       { .start = 0x1C4030, .end = 0x1C4030 },
+       { .start = 0x1C4510, .end = 0x1C4550 },
+       { .start = 0x1C8030, .end = 0x1C8030 },
+       { .start = 0x1C8510, .end = 0x1C8550 },
+       { .start = 0x1D0030, .end = 0x1D0030 },
+       { .start = 0x1D0510, .end = 0x1D0550 },
+       { .start = 0x1D4030, .end = 0x1D4030 },
+       { .start = 0x1D4510, .end = 0x1D4550 },
+       { .start = 0x1D8030, .end = 0x1D8030 },
+       { .start = 0x1D8510, .end = 0x1D8550 },
+       { .start = 0x1E0030, .end = 0x1E0030 },
+       { .start = 0x1E0510, .end = 0x1E0550 },
+       { .start = 0x1E4030, .end = 0x1E4030 },
+       { .start = 0x1E4510, .end = 0x1E4550 },
+       { .start = 0x1E8030, .end = 0x1E8030 },
+       { .start = 0x1E8510, .end = 0x1E8550 },
+       { .start = 0x1F0030, .end = 0x1F0030 },
+       { .start = 0x1F0510, .end = 0x1F0550 },
+       { .start = 0x1F4030, .end = 0x1F4030 },
+       { .start = 0x1F4510, .end = 0x1F4550 },
+       { .start = 0x1F8030, .end = 0x1F8030 },
+       { .start = 0x1F8510, .end = 0x1F8550 },
+};
+
 static int mmio_range_cmp(u32 key, const struct i915_range *range)
 {
        if (key < range->start)
@@ -2051,7 +2090,7 @@ static int uncore_forcewake_init(struct intel_uncore *uncore)
 
        if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 55)) {
                ASSIGN_FW_DOMAINS_TABLE(uncore, __dg2_fw_ranges);
-               ASSIGN_SHADOW_TABLE(uncore, gen12_shadowed_regs);
+               ASSIGN_SHADOW_TABLE(uncore, dg2_shadowed_regs);
                ASSIGN_WRITE_MMIO_VFUNCS(uncore, fwtable);
                ASSIGN_READ_MMIO_VFUNCS(uncore, fwtable);
        } else if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) {

diff --git a/drivers/gpu/drm/i915/selftests/intel_uncore.c b/drivers/gpu/drm/i915/selftests/intel_uncore.c
index 22ef2c8..bc81281 100644 (file)
--- a/drivers/gpu/drm/i915/selftests/intel_uncore.c
+++ b/drivers/gpu/drm/i915/selftests/intel_uncore.c
@@ -68,6 +68,7 @@ static int intel_shadow_table_check(void)
                { gen8_shadowed_regs, ARRAY_SIZE(gen8_shadowed_regs) },
                { gen11_shadowed_regs, ARRAY_SIZE(gen11_shadowed_regs) },
                { gen12_shadowed_regs, ARRAY_SIZE(gen12_shadowed_regs) },
+               { dg2_shadowed_regs, ARRAY_SIZE(dg2_shadowed_regs) },
        };
        const struct i915_range *range;
        unsigned int i, j;