memory: tegra: Pre-configure debug register on Tegra20

The driver expects certain debug features to be disabled in order to
work properly. Let's disable them explicitly for consistency and to not
rely on a boot state.

Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

diff --git a/drivers/memory/tegra/tegra20-emc.c b/drivers/memory/tegra/tegra20-emc.c
index 1ce351d..85c24f2 100644 (file)
--- a/drivers/memory/tegra/tegra20-emc.c
+++ b/drivers/memory/tegra/tegra20-emc.c
@@ -22,6 +22,7 @@
 
 #define EMC_INTSTATUS                          0x000
 #define EMC_INTMASK                            0x004
+#define EMC_DBG                                        0x008
 #define EMC_TIMING_CONTROL                     0x028
 #define EMC_RC                                 0x02c
 #define EMC_RFC                                        0x030
@@ -80,6 +81,12 @@
 #define EMC_REFRESH_OVERFLOW_INT               BIT(3)
 #define EMC_CLKCHANGE_COMPLETE_INT             BIT(4)
 
+#define EMC_DBG_READ_MUX_ASSEMBLY              BIT(0)
+#define EMC_DBG_WRITE_MUX_ACTIVE               BIT(1)
+#define EMC_DBG_FORCE_UPDATE                   BIT(2)
+#define EMC_DBG_READ_DQM_CTRL                  BIT(9)
+#define EMC_DBG_CFG_PRIORITY                   BIT(24)
+
 static const u16 emc_timing_registers[] = {
        EMC_RC,
        EMC_RFC,
@@ -396,7 +403,7 @@ tegra_emc_find_node_by_ram_code(struct device *dev)
 static int emc_setup_hw(struct tegra_emc *emc)
 {
        u32 intmask = EMC_REFRESH_OVERFLOW_INT | EMC_CLKCHANGE_COMPLETE_INT;
-       u32 emc_cfg;
+       u32 emc_cfg, emc_dbg;
 
        emc_cfg = readl_relaxed(emc->regs + EMC_CFG_2);
 
@@ -419,6 +426,14 @@ static int emc_setup_hw(struct tegra_emc *emc)
        writel_relaxed(intmask, emc->regs + EMC_INTMASK);
        writel_relaxed(intmask, emc->regs + EMC_INTSTATUS);
 
+       /* ensure that unwanted debug features are disabled */
+       emc_dbg = readl_relaxed(emc->regs + EMC_DBG);
+       emc_dbg |= EMC_DBG_CFG_PRIORITY;
+       emc_dbg &= ~EMC_DBG_READ_MUX_ASSEMBLY;
+       emc_dbg &= ~EMC_DBG_WRITE_MUX_ACTIVE;
+       emc_dbg &= ~EMC_DBG_FORCE_UPDATE;
+       writel_relaxed(emc_dbg, emc->regs + EMC_DBG);
+
        return 0;
 }