arm64: dts: qcom: sdm845: switch PCIe QMP PHY to new style of bindings

Change the PCIe QMP PHY to use newer style of QMP PHY bindings (single
resource region, no per-PHY subnodes).

Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20230820142035.89903-14-dmitry.baryshkov@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index 8b56156..bf5e6eb 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
@@ -1198,8 +1198,8 @@
                        clocks = <&rpmhcc RPMH_CXO_CLK>,
                                 <&rpmhcc RPMH_CXO_CLK_A>,
                                 <&sleep_clk>,
-                                <&pcie0_lane>,
-                                <&pcie1_lane>;
+                                <&pcie0_phy>,
+                                <&pcie1_phy>;
                        clock-names = "bi_tcxo",
                                      "bi_tcxo_ao",
                                      "sleep_clk",
@@ -2371,7 +2371,7 @@
 
                        power-domains = <&gcc PCIE_0_GDSC>;
 
-                       phys = <&pcie0_lane>;
+                       phys = <&pcie0_phy>;
                        phy-names = "pciephy";
 
                        status = "disabled";
@@ -2379,15 +2379,22 @@
 
                pcie0_phy: phy@1c06000 {
                        compatible = "qcom,sdm845-qmp-pcie-phy";
-                       reg = <0 0x01c06000 0 0x18c>;
-                       #address-cells = <2>;
-                       #size-cells = <2>;
-                       ranges;
+                       reg = <0 0x01c06000 0 0x1000>;
                        clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
                                 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
                                 <&gcc GCC_PCIE_0_CLKREF_CLK>,
-                                <&gcc GCC_PCIE_PHY_REFGEN_CLK>;
-                       clock-names = "aux", "cfg_ahb", "ref", "refgen";
+                                <&gcc GCC_PCIE_PHY_REFGEN_CLK>,
+                                <&gcc GCC_PCIE_0_PIPE_CLK>;
+                       clock-names = "aux",
+                                     "cfg_ahb",
+                                     "ref",
+                                     "refgen",
+                                     "pipe";
+
+                       clock-output-names = "pcie_0_pipe_clk";
+                       #clock-cells = <0>;
+
+                       #phy-cells = <0>;
 
                        resets = <&gcc GCC_PCIE_0_PHY_BCR>;
                        reset-names = "phy";
@@ -2396,19 +2403,6 @@
                        assigned-clock-rates = <100000000>;
 
                        status = "disabled";
-
-                       pcie0_lane: phy@1c06200 {
-                               reg = <0 0x01c06200 0 0x128>,
-                                     <0 0x01c06400 0 0x1fc>,
-                                     <0 0x01c06800 0 0x218>,
-                                     <0 0x01c06600 0 0x70>;
-                               clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
-                               clock-names = "pipe0";
-
-                               #clock-cells = <0>;
-                               #phy-cells = <0>;
-                               clock-output-names = "pcie_0_pipe_clk";
-                       };
                };
 
                pcie1: pci@1c08000 {
@@ -2481,7 +2475,7 @@
 
                        power-domains = <&gcc PCIE_1_GDSC>;
 
-                       phys = <&pcie1_lane>;
+                       phys = <&pcie1_phy>;
                        phy-names = "pciephy";
 
                        status = "disabled";
@@ -2489,15 +2483,22 @@
 
                pcie1_phy: phy@1c0a000 {
                        compatible = "qcom,sdm845-qhp-pcie-phy";
-                       reg = <0 0x01c0a000 0 0x800>;
-                       #address-cells = <2>;
-                       #size-cells = <2>;
-                       ranges;
+                       reg = <0 0x01c0a000 0 0x2000>;
                        clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
                                 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
                                 <&gcc GCC_PCIE_1_CLKREF_CLK>,
-                                <&gcc GCC_PCIE_PHY_REFGEN_CLK>;
-                       clock-names = "aux", "cfg_ahb", "ref", "refgen";
+                                <&gcc GCC_PCIE_PHY_REFGEN_CLK>,
+                                <&gcc GCC_PCIE_1_PIPE_CLK>;
+                       clock-names = "aux",
+                                     "cfg_ahb",
+                                     "ref",
+                                     "refgen",
+                                     "pipe";
+
+                       clock-output-names = "pcie_1_pipe_clk";
+                       #clock-cells = <0>;
+
+                       #phy-cells = <0>;
 
                        resets = <&gcc GCC_PCIE_1_PHY_BCR>;
                        reset-names = "phy";
@@ -2506,18 +2507,6 @@
                        assigned-clock-rates = <100000000>;
 
                        status = "disabled";
-
-                       pcie1_lane: phy@1c06200 {
-                               reg = <0 0x01c0a800 0 0x800>,
-                                     <0 0x01c0a800 0 0x800>,
-                                     <0 0x01c0b800 0 0x400>;
-                               clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
-                               clock-names = "pipe0";
-
-                               #clock-cells = <0>;
-                               #phy-cells = <0>;
-                               clock-output-names = "pcie_1_pipe_clk";
-                       };
                };
 
                mem_noc: interconnect@1380000 {