clk: renesas: rzg2l: Fix typo in function name
authorLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Wed, 21 Sep 2022 08:00:51 +0000 (09:00 +0100)
committerGeert Uytterhoeven <geert+renesas@glider.be>
Mon, 17 Oct 2022 08:03:59 +0000 (10:03 +0200)
Fix typo, rzg2l_mod_clock__get_sibling -> rzg2l_mod_clock_get_sibling

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20220921080051.5604-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
drivers/clk/renesas/rzg2l-cpg.c

index 5dfe362..be4868f 100644 (file)
@@ -1014,8 +1014,8 @@ static const struct clk_ops rzg2l_mod_clock_ops = {
 };
 
 static struct mstp_clock
-*rzg2l_mod_clock__get_sibling(struct mstp_clock *clock,
-                             struct rzg2l_cpg_priv *priv)
+*rzg2l_mod_clock_get_sibling(struct mstp_clock *clock,
+                            struct rzg2l_cpg_priv *priv)
 {
        struct clk_hw *hw;
        unsigned int i;
@@ -1101,7 +1101,7 @@ rzg2l_cpg_register_mod_clk(const struct rzg2l_mod_clk *mod,
                struct mstp_clock *sibling;
 
                clock->enabled = rzg2l_mod_clock_is_enabled(&clock->hw);
-               sibling = rzg2l_mod_clock__get_sibling(clock, priv);
+               sibling = rzg2l_mod_clock_get_sibling(clock, priv);
                if (sibling) {
                        clock->sibling = sibling;
                        sibling->sibling = clock;