F: arch/arc/
F: Documentation/devicetree/bindings/arc/*
F: Documentation/devicetree/bindings/interrupt-controller/snps,arc*
+F: drivers/clocksource/arc_timer.c
F: drivers/tty/serial/arc_uart.c
T: git git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc.git
config ARC
def_bool y
+ select ARC_TIMERS
select ARCH_SUPPORTS_ATOMIC_RMW if ARC_HAS_LLSC
select BUILDTIME_EXTABLE_SORT
- select CLKSRC_OF
select CLONE_BACKWARDS
select COMMON_CLK
select GENERIC_ATOMIC64 if !ISA_ARCV2 || !(ARC_HAS_LL64 && ARC_HAS_LLSC)
config ISA_ARCV2
bool "ARC ISA v2"
+ select ARC_TIMERS_64BIT
help
ISA for the Next Generation ARC-HS cores
bool "Insn: div, divu, rem, remu"
default y
-config ARC_TIMERS_64BIT
- bool "64-bit r/o cycle counters RTC (up) and GFRC (smp)"
- default y
-
config ARC_NUMBER_OF_INTERRUPTS
int "Number of interrupts"
range 8 240
# Pass UTS_MACHINE for user_regset definition
CFLAGS_ptrace.o += -DUTS_MACHINE='"$(UTS_MACHINE)"'
-obj-y := arcksyms.o setup.o irq.o time.o reset.o ptrace.o process.o devtree.o
+obj-y := arcksyms.o setup.o irq.o reset.o ptrace.o process.o devtree.o
obj-y += signal.o traps.o sys.o troubleshoot.o stacktrace.o disasm.o
obj-$(CONFIG_ISA_ARCOMPACT) += entry-compact.o intc-compact.o
obj-$(CONFIG_ISA_ARCV2) += entry-arcv2.o intc-arcv2.o
+++ /dev/null
-/*
- * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * vineetg: Jan 1011
- * -sched_clock( ) no longer jiffies based. Uses the same clocksource
- * as gtod
- *
- * Rajeshwarr/Vineetg: Mar 2008
- * -Implemented CONFIG_GENERIC_TIME (rather deleted arch specific code)
- * for arch independent gettimeofday()
- * -Implemented CONFIG_GENERIC_CLOCKEVENTS as base for hrtimers
- *
- * Vineetg: Mar 2008: Forked off from time.c which now is time-jiff.c
- */
-
-/* ARC700 has two 32bit independent prog Timers: TIMER0 and TIMER1
- * Each can programmed to go from @count to @limit and optionally
- * interrupt when that happens.
- * A write to Control Register clears the Interrupt
- *
- * We've designated TIMER0 for events (clockevents)
- * while TIMER1 for free running (clocksource)
- *
- * Newer ARC700 cores have 64bit clk fetching RTSC insn, preferred over TIMER1
- * which however is currently broken
- */
-
-#include <linux/interrupt.h>
-#include <linux/clk.h>
-#include <linux/clk-provider.h>
-#include <linux/clocksource.h>
-#include <linux/clockchips.h>
-#include <linux/cpu.h>
-#include <linux/of.h>
-#include <linux/of_irq.h>
-#include <asm/irq.h>
-
-#include <soc/arc/timers.h>
-#include <soc/arc/mcip.h>
-
-
-static unsigned long arc_timer_freq;
-
-static int noinline arc_get_timer_clk(struct device_node *node)
-{
- struct clk *clk;
- int ret;
-
- clk = of_clk_get(node, 0);
- if (IS_ERR(clk)) {
- pr_err("timer missing clk");
- return PTR_ERR(clk);
- }
-
- ret = clk_prepare_enable(clk);
- if (ret) {
- pr_err("Couldn't enable parent clk\n");
- return ret;
- }
-
- arc_timer_freq = clk_get_rate(clk);
-
- return 0;
-}
-
-/********** Clock Source Device *********/
-
-#ifdef CONFIG_ARC_TIMERS_64BIT
-
-static cycle_t arc_read_gfrc(struct clocksource *cs)
-{
- unsigned long flags;
- u32 l, h;
-
- local_irq_save(flags);
-
- __mcip_cmd(CMD_GFRC_READ_LO, 0);
- l = read_aux_reg(ARC_REG_MCIP_READBACK);
-
- __mcip_cmd(CMD_GFRC_READ_HI, 0);
- h = read_aux_reg(ARC_REG_MCIP_READBACK);
-
- local_irq_restore(flags);
-
- return (((cycle_t)h) << 32) | l;
-}
-
-static struct clocksource arc_counter_gfrc = {
- .name = "ARConnect GFRC",
- .rating = 400,
- .read = arc_read_gfrc,
- .mask = CLOCKSOURCE_MASK(64),
- .flags = CLOCK_SOURCE_IS_CONTINUOUS,
-};
-
-static int __init arc_cs_setup_gfrc(struct device_node *node)
-{
- struct mcip_bcr mp;
- int ret;
-
- READ_BCR(ARC_REG_MCIP_BCR, mp);
- if (!mp.gfrc) {
- pr_warn("Global-64-bit-Ctr clocksource not detected");
- return -ENXIO;
- }
-
- ret = arc_get_timer_clk(node);
- if (ret)
- return ret;
-
- return clocksource_register_hz(&arc_counter_gfrc, arc_timer_freq);
-}
-CLOCKSOURCE_OF_DECLARE(arc_gfrc, "snps,archs-timer-gfrc", arc_cs_setup_gfrc);
-
-#define AUX_RTC_CTRL 0x103
-#define AUX_RTC_LOW 0x104
-#define AUX_RTC_HIGH 0x105
-
-static cycle_t arc_read_rtc(struct clocksource *cs)
-{
- unsigned long status;
- u32 l, h;
-
- /*
- * hardware has an internal state machine which tracks readout of
- * low/high and updates the CTRL.status if
- * - interrupt/exception taken between the two reads
- * - high increments after low has been read
- */
- do {
- l = read_aux_reg(AUX_RTC_LOW);
- h = read_aux_reg(AUX_RTC_HIGH);
- status = read_aux_reg(AUX_RTC_CTRL);
- } while (!(status & _BITUL(31)));
-
- return (((cycle_t)h) << 32) | l;
-}
-
-static struct clocksource arc_counter_rtc = {
- .name = "ARCv2 RTC",
- .rating = 350,
- .read = arc_read_rtc,
- .mask = CLOCKSOURCE_MASK(64),
- .flags = CLOCK_SOURCE_IS_CONTINUOUS,
-};
-
-static int __init arc_cs_setup_rtc(struct device_node *node)
-{
- struct bcr_timer timer;
- int ret;
-
- READ_BCR(ARC_REG_TIMERS_BCR, timer);
- if (!timer.rtc) {
- pr_warn("Local-64-bit-Ctr clocksource not detected");
- return -ENXIO;
- }
-
- /* Local to CPU hence not usable in SMP */
- if (IS_ENABLED(CONFIG_SMP)) {
- pr_warn("Local-64-bit-Ctr not usable in SMP");
- return -EINVAL;
- }
-
- ret = arc_get_timer_clk(node);
- if (ret)
- return ret;
-
- write_aux_reg(AUX_RTC_CTRL, 1);
-
- return clocksource_register_hz(&arc_counter_rtc, arc_timer_freq);
-}
-CLOCKSOURCE_OF_DECLARE(arc_rtc, "snps,archs-timer-rtc", arc_cs_setup_rtc);
-
-#endif
-
-/*
- * 32bit TIMER1 to keep counting monotonically and wraparound
- */
-
-static cycle_t arc_read_timer1(struct clocksource *cs)
-{
- return (cycle_t) read_aux_reg(ARC_REG_TIMER1_CNT);
-}
-
-static struct clocksource arc_counter_timer1 = {
- .name = "ARC Timer1",
- .rating = 300,
- .read = arc_read_timer1,
- .mask = CLOCKSOURCE_MASK(32),
- .flags = CLOCK_SOURCE_IS_CONTINUOUS,
-};
-
-static int __init arc_cs_setup_timer1(struct device_node *node)
-{
- int ret;
-
- /* Local to CPU hence not usable in SMP */
- if (IS_ENABLED(CONFIG_SMP))
- return -EINVAL;
-
- ret = arc_get_timer_clk(node);
- if (ret)
- return ret;
-
- write_aux_reg(ARC_REG_TIMER1_LIMIT, ARC_TIMERN_MAX);
- write_aux_reg(ARC_REG_TIMER1_CNT, 0);
- write_aux_reg(ARC_REG_TIMER1_CTRL, TIMER_CTRL_NH);
-
- return clocksource_register_hz(&arc_counter_timer1, arc_timer_freq);
-}
-
-/********** Clock Event Device *********/
-
-static int arc_timer_irq;
-
-/*
- * Arm the timer to interrupt after @cycles
- * The distinction for oneshot/periodic is done in arc_event_timer_ack() below
- */
-static void arc_timer_event_setup(unsigned int cycles)
-{
- write_aux_reg(ARC_REG_TIMER0_LIMIT, cycles);
- write_aux_reg(ARC_REG_TIMER0_CNT, 0); /* start from 0 */
-
- write_aux_reg(ARC_REG_TIMER0_CTRL, TIMER_CTRL_IE | TIMER_CTRL_NH);
-}
-
-
-static int arc_clkevent_set_next_event(unsigned long delta,
- struct clock_event_device *dev)
-{
- arc_timer_event_setup(delta);
- return 0;
-}
-
-static int arc_clkevent_set_periodic(struct clock_event_device *dev)
-{
- /*
- * At X Hz, 1 sec = 1000ms -> X cycles;
- * 10ms -> X / 100 cycles
- */
- arc_timer_event_setup(arc_timer_freq / HZ);
- return 0;
-}
-
-static DEFINE_PER_CPU(struct clock_event_device, arc_clockevent_device) = {
- .name = "ARC Timer0",
- .features = CLOCK_EVT_FEAT_ONESHOT |
- CLOCK_EVT_FEAT_PERIODIC,
- .rating = 300,
- .set_next_event = arc_clkevent_set_next_event,
- .set_state_periodic = arc_clkevent_set_periodic,
-};
-
-static irqreturn_t timer_irq_handler(int irq, void *dev_id)
-{
- /*
- * Note that generic IRQ core could have passed @evt for @dev_id if
- * irq_set_chip_and_handler() asked for handle_percpu_devid_irq()
- */
- struct clock_event_device *evt = this_cpu_ptr(&arc_clockevent_device);
- int irq_reenable = clockevent_state_periodic(evt);
-
- /*
- * Any write to CTRL reg ACks the interrupt, we rewrite the
- * Count when [N]ot [H]alted bit.
- * And re-arm it if perioid by [I]nterrupt [E]nable bit
- */
- write_aux_reg(ARC_REG_TIMER0_CTRL, irq_reenable | TIMER_CTRL_NH);
-
- evt->event_handler(evt);
-
- return IRQ_HANDLED;
-}
-
-
-static int arc_timer_starting_cpu(unsigned int cpu)
-{
- struct clock_event_device *evt = this_cpu_ptr(&arc_clockevent_device);
-
- evt->cpumask = cpumask_of(smp_processor_id());
-
- clockevents_config_and_register(evt, arc_timer_freq, 0, ARC_TIMERN_MAX);
- enable_percpu_irq(arc_timer_irq, 0);
- return 0;
-}
-
-static int arc_timer_dying_cpu(unsigned int cpu)
-{
- disable_percpu_irq(arc_timer_irq);
- return 0;
-}
-
-/*
- * clockevent setup for boot CPU
- */
-static int __init arc_clockevent_setup(struct device_node *node)
-{
- struct clock_event_device *evt = this_cpu_ptr(&arc_clockevent_device);
- int ret;
-
- arc_timer_irq = irq_of_parse_and_map(node, 0);
- if (arc_timer_irq <= 0) {
- pr_err("clockevent: missing irq");
- return -EINVAL;
- }
-
- ret = arc_get_timer_clk(node);
- if (ret) {
- pr_err("clockevent: missing clk");
- return ret;
- }
-
- /* Needs apriori irq_set_percpu_devid() done in intc map function */
- ret = request_percpu_irq(arc_timer_irq, timer_irq_handler,
- "Timer0 (per-cpu-tick)", evt);
- if (ret) {
- pr_err("clockevent: unable to request irq\n");
- return ret;
- }
-
- ret = cpuhp_setup_state(CPUHP_AP_ARC_TIMER_STARTING,
- "AP_ARC_TIMER_STARTING",
- arc_timer_starting_cpu,
- arc_timer_dying_cpu);
- if (ret) {
- pr_err("Failed to setup hotplug state");
- return ret;
- }
- return 0;
-}
-
-static int __init arc_of_timer_init(struct device_node *np)
-{
- static int init_count = 0;
- int ret;
-
- if (!init_count) {
- init_count = 1;
- ret = arc_clockevent_setup(np);
- } else {
- ret = arc_cs_setup_timer1(np);
- }
-
- return ret;
-}
-CLOCKSOURCE_OF_DECLARE(arc_clkevt, "snps,arc-timer", arc_of_timer_init);
select CLKSRC_MMIO
select CLKSRC_OF
+config ARC_TIMERS
+ bool "Support for 32-bit TIMERn counters in ARC Cores" if COMPILE_TEST
+ depends on GENERIC_CLOCKEVENTS
+ select CLKSRC_OF
+ help
+ These are legacy 32-bit TIMER0 and TIMER1 counters found on all ARC cores
+ (ARC700 as well as ARC HS38).
+ TIMER0 serves as clockevent while TIMER1 provides clocksource
+
+config ARC_TIMERS_64BIT
+ bool "Support for 64-bit counters in ARC HS38 cores" if COMPILE_TEST
+ depends on GENERIC_CLOCKEVENTS
+ depends on ARC_TIMERS
+ select CLKSRC_OF
+ help
+ This enables 2 different 64-bit timers: RTC (for UP) and GFRC (for SMP)
+ RTC is implemented inside the core, while GFRC sits outside the core in
+ ARConnect IP block. Driver automatically picks one of them for clocksource
+ as appropriate.
+
config ARM_ARCH_TIMER
bool
select CLKSRC_OF if OF
obj-$(CONFIG_CLKSRC_NPS) += timer-nps.o
obj-$(CONFIG_OXNAS_RPS_TIMER) += timer-oxnas-rps.o
+obj-$(CONFIG_ARC_TIMERS) += arc_timer.o
obj-$(CONFIG_ARM_ARCH_TIMER) += arm_arch_timer.o
obj-$(CONFIG_ARM_GLOBAL_TIMER) += arm_global_timer.o
obj-$(CONFIG_ARMV7M_SYSTICK) += armv7m_systick.o
--- /dev/null
+/*
+ * Copyright (C) 2016-17 Synopsys, Inc. (www.synopsys.com)
+ * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/* ARC700 has two 32bit independent prog Timers: TIMER0 and TIMER1, Each can be
+ * programmed to go from @count to @limit and optionally interrupt.
+ * We've designated TIMER0 for clockevents and TIMER1 for clocksource
+ *
+ * ARCv2 based HS38 cores have RTC (in-core) and GFRC (inside ARConnect/MCIP)
+ * which are suitable for UP and SMP based clocksources respectively
+ */
+
+#include <linux/interrupt.h>
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/clocksource.h>
+#include <linux/clockchips.h>
+#include <linux/cpu.h>
+#include <linux/of.h>
+#include <linux/of_irq.h>
+
+#include <soc/arc/timers.h>
+#include <soc/arc/mcip.h>
+
+
+static unsigned long arc_timer_freq;
+
+static int noinline arc_get_timer_clk(struct device_node *node)
+{
+ struct clk *clk;
+ int ret;
+
+ clk = of_clk_get(node, 0);
+ if (IS_ERR(clk)) {
+ pr_err("timer missing clk");
+ return PTR_ERR(clk);
+ }
+
+ ret = clk_prepare_enable(clk);
+ if (ret) {
+ pr_err("Couldn't enable parent clk\n");
+ return ret;
+ }
+
+ arc_timer_freq = clk_get_rate(clk);
+
+ return 0;
+}
+
+/********** Clock Source Device *********/
+
+#ifdef CONFIG_ARC_TIMERS_64BIT
+
+static cycle_t arc_read_gfrc(struct clocksource *cs)
+{
+ unsigned long flags;
+ u32 l, h;
+
+ local_irq_save(flags);
+
+ __mcip_cmd(CMD_GFRC_READ_LO, 0);
+ l = read_aux_reg(ARC_REG_MCIP_READBACK);
+
+ __mcip_cmd(CMD_GFRC_READ_HI, 0);
+ h = read_aux_reg(ARC_REG_MCIP_READBACK);
+
+ local_irq_restore(flags);
+
+ return (((cycle_t)h) << 32) | l;
+}
+
+static struct clocksource arc_counter_gfrc = {
+ .name = "ARConnect GFRC",
+ .rating = 400,
+ .read = arc_read_gfrc,
+ .mask = CLOCKSOURCE_MASK(64),
+ .flags = CLOCK_SOURCE_IS_CONTINUOUS,
+};
+
+static int __init arc_cs_setup_gfrc(struct device_node *node)
+{
+ struct mcip_bcr mp;
+ int ret;
+
+ READ_BCR(ARC_REG_MCIP_BCR, mp);
+ if (!mp.gfrc) {
+ pr_warn("Global-64-bit-Ctr clocksource not detected");
+ return -ENXIO;
+ }
+
+ ret = arc_get_timer_clk(node);
+ if (ret)
+ return ret;
+
+ return clocksource_register_hz(&arc_counter_gfrc, arc_timer_freq);
+}
+CLOCKSOURCE_OF_DECLARE(arc_gfrc, "snps,archs-timer-gfrc", arc_cs_setup_gfrc);
+
+#define AUX_RTC_CTRL 0x103
+#define AUX_RTC_LOW 0x104
+#define AUX_RTC_HIGH 0x105
+
+static cycle_t arc_read_rtc(struct clocksource *cs)
+{
+ unsigned long status;
+ u32 l, h;
+
+ /*
+ * hardware has an internal state machine which tracks readout of
+ * low/high and updates the CTRL.status if
+ * - interrupt/exception taken between the two reads
+ * - high increments after low has been read
+ */
+ do {
+ l = read_aux_reg(AUX_RTC_LOW);
+ h = read_aux_reg(AUX_RTC_HIGH);
+ status = read_aux_reg(AUX_RTC_CTRL);
+ } while (!(status & _BITUL(31)));
+
+ return (((cycle_t)h) << 32) | l;
+}
+
+static struct clocksource arc_counter_rtc = {
+ .name = "ARCv2 RTC",
+ .rating = 350,
+ .read = arc_read_rtc,
+ .mask = CLOCKSOURCE_MASK(64),
+ .flags = CLOCK_SOURCE_IS_CONTINUOUS,
+};
+
+static int __init arc_cs_setup_rtc(struct device_node *node)
+{
+ struct bcr_timer timer;
+ int ret;
+
+ READ_BCR(ARC_REG_TIMERS_BCR, timer);
+ if (!timer.rtc) {
+ pr_warn("Local-64-bit-Ctr clocksource not detected");
+ return -ENXIO;
+ }
+
+ /* Local to CPU hence not usable in SMP */
+ if (IS_ENABLED(CONFIG_SMP)) {
+ pr_warn("Local-64-bit-Ctr not usable in SMP");
+ return -EINVAL;
+ }
+
+ ret = arc_get_timer_clk(node);
+ if (ret)
+ return ret;
+
+ write_aux_reg(AUX_RTC_CTRL, 1);
+
+ return clocksource_register_hz(&arc_counter_rtc, arc_timer_freq);
+}
+CLOCKSOURCE_OF_DECLARE(arc_rtc, "snps,archs-timer-rtc", arc_cs_setup_rtc);
+
+#endif
+
+/*
+ * 32bit TIMER1 to keep counting monotonically and wraparound
+ */
+
+static cycle_t arc_read_timer1(struct clocksource *cs)
+{
+ return (cycle_t) read_aux_reg(ARC_REG_TIMER1_CNT);
+}
+
+static struct clocksource arc_counter_timer1 = {
+ .name = "ARC Timer1",
+ .rating = 300,
+ .read = arc_read_timer1,
+ .mask = CLOCKSOURCE_MASK(32),
+ .flags = CLOCK_SOURCE_IS_CONTINUOUS,
+};
+
+static int __init arc_cs_setup_timer1(struct device_node *node)
+{
+ int ret;
+
+ /* Local to CPU hence not usable in SMP */
+ if (IS_ENABLED(CONFIG_SMP))
+ return -EINVAL;
+
+ ret = arc_get_timer_clk(node);
+ if (ret)
+ return ret;
+
+ write_aux_reg(ARC_REG_TIMER1_LIMIT, ARC_TIMERN_MAX);
+ write_aux_reg(ARC_REG_TIMER1_CNT, 0);
+ write_aux_reg(ARC_REG_TIMER1_CTRL, TIMER_CTRL_NH);
+
+ return clocksource_register_hz(&arc_counter_timer1, arc_timer_freq);
+}
+
+/********** Clock Event Device *********/
+
+static int arc_timer_irq;
+
+/*
+ * Arm the timer to interrupt after @cycles
+ * The distinction for oneshot/periodic is done in arc_event_timer_ack() below
+ */
+static void arc_timer_event_setup(unsigned int cycles)
+{
+ write_aux_reg(ARC_REG_TIMER0_LIMIT, cycles);
+ write_aux_reg(ARC_REG_TIMER0_CNT, 0); /* start from 0 */
+
+ write_aux_reg(ARC_REG_TIMER0_CTRL, TIMER_CTRL_IE | TIMER_CTRL_NH);
+}
+
+
+static int arc_clkevent_set_next_event(unsigned long delta,
+ struct clock_event_device *dev)
+{
+ arc_timer_event_setup(delta);
+ return 0;
+}
+
+static int arc_clkevent_set_periodic(struct clock_event_device *dev)
+{
+ /*
+ * At X Hz, 1 sec = 1000ms -> X cycles;
+ * 10ms -> X / 100 cycles
+ */
+ arc_timer_event_setup(arc_timer_freq / HZ);
+ return 0;
+}
+
+static DEFINE_PER_CPU(struct clock_event_device, arc_clockevent_device) = {
+ .name = "ARC Timer0",
+ .features = CLOCK_EVT_FEAT_ONESHOT |
+ CLOCK_EVT_FEAT_PERIODIC,
+ .rating = 300,
+ .set_next_event = arc_clkevent_set_next_event,
+ .set_state_periodic = arc_clkevent_set_periodic,
+};
+
+static irqreturn_t timer_irq_handler(int irq, void *dev_id)
+{
+ /*
+ * Note that generic IRQ core could have passed @evt for @dev_id if
+ * irq_set_chip_and_handler() asked for handle_percpu_devid_irq()
+ */
+ struct clock_event_device *evt = this_cpu_ptr(&arc_clockevent_device);
+ int irq_reenable = clockevent_state_periodic(evt);
+
+ /*
+ * Any write to CTRL reg ACks the interrupt, we rewrite the
+ * Count when [N]ot [H]alted bit.
+ * And re-arm it if perioid by [I]nterrupt [E]nable bit
+ */
+ write_aux_reg(ARC_REG_TIMER0_CTRL, irq_reenable | TIMER_CTRL_NH);
+
+ evt->event_handler(evt);
+
+ return IRQ_HANDLED;
+}
+
+
+static int arc_timer_starting_cpu(unsigned int cpu)
+{
+ struct clock_event_device *evt = this_cpu_ptr(&arc_clockevent_device);
+
+ evt->cpumask = cpumask_of(smp_processor_id());
+
+ clockevents_config_and_register(evt, arc_timer_freq, 0, ARC_TIMERN_MAX);
+ enable_percpu_irq(arc_timer_irq, 0);
+ return 0;
+}
+
+static int arc_timer_dying_cpu(unsigned int cpu)
+{
+ disable_percpu_irq(arc_timer_irq);
+ return 0;
+}
+
+/*
+ * clockevent setup for boot CPU
+ */
+static int __init arc_clockevent_setup(struct device_node *node)
+{
+ struct clock_event_device *evt = this_cpu_ptr(&arc_clockevent_device);
+ int ret;
+
+ arc_timer_irq = irq_of_parse_and_map(node, 0);
+ if (arc_timer_irq <= 0) {
+ pr_err("clockevent: missing irq");
+ return -EINVAL;
+ }
+
+ ret = arc_get_timer_clk(node);
+ if (ret) {
+ pr_err("clockevent: missing clk");
+ return ret;
+ }
+
+ /* Needs apriori irq_set_percpu_devid() done in intc map function */
+ ret = request_percpu_irq(arc_timer_irq, timer_irq_handler,
+ "Timer0 (per-cpu-tick)", evt);
+ if (ret) {
+ pr_err("clockevent: unable to request irq\n");
+ return ret;
+ }
+
+ ret = cpuhp_setup_state(CPUHP_AP_ARC_TIMER_STARTING,
+ "AP_ARC_TIMER_STARTING",
+ arc_timer_starting_cpu,
+ arc_timer_dying_cpu);
+ if (ret) {
+ pr_err("Failed to setup hotplug state");
+ return ret;
+ }
+ return 0;
+}
+
+static int __init arc_of_timer_init(struct device_node *np)
+{
+ static int init_count = 0;
+ int ret;
+
+ if (!init_count) {
+ init_count = 1;
+ ret = arc_clockevent_setup(np);
+ } else {
+ ret = arc_cs_setup_timer1(np);
+ }
+
+ return ret;
+}
+CLOCKSOURCE_OF_DECLARE(arc_clkevt, "snps,arc-timer", arc_of_timer_init);
projects / linux-2.6-microblaze.git / commitdiff