drm/i915/crt: Extract intel_crt_regs.h

Move the analog port register definitions into their
own file.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20241107161123.16269-7-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>

diff --git a/drivers/gpu/drm/i915/display/intel_crt.c b/drivers/gpu/drm/i915/display/intel_crt.c
index e21e402..4784a85 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_crt.c
+++ b/drivers/gpu/drm/i915/display/intel_crt.c
@@ -38,6 +38,7 @@
 #include "i915_reg.h"
 #include "intel_connector.h"
 #include "intel_crt.h"
+#include "intel_crt_regs.h"
 #include "intel_crtc.h"
 #include "intel_ddi.h"
 #include "intel_ddi_buf_trans.h"

diff --git a/drivers/gpu/drm/i915/display/intel_crt_regs.h b/drivers/gpu/drm/i915/display/intel_crt_regs.h
new file mode 100644 (file)
index 0000000..9a93020
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_crt_regs.h
@@ -0,0 +1,48 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2024 Intel Corporation
+ */
+
+#ifndef __INTEL_CRT_REGS_H__
+#define __INTEL_CRT_REGS_H__
+
+#include "intel_display_reg_defs.h"
+
+#define ADPA                   _MMIO(0x61100)
+#define PCH_ADPA               _MMIO(0xe1100)
+#define VLV_ADPA               _MMIO(VLV_DISPLAY_BASE + 0x61100)
+#define   ADPA_DAC_ENABLE                      REG_BIT(31)
+#define   ADPA_PIPE_SEL_MASK                   REG_BIT(30)
+#define   ADPA_PIPE_SEL(pipe)                  REG_FIELD_PREP(ADPA_PIPE_SEL_MASK, (pipe))
+#define   ADPA_PIPE_SEL_MASK_CPT               REG_GENMASK(30, 29)
+#define   ADPA_PIPE_SEL_CPT(pipe)              REG_FIELD_PREP(ADPA_PIPE_SEL_MASK_CPT, (pipe))
+#define   ADPA_CRT_HOTPLUG_MONITOR_MASK                REG_GENMASK(25, 24)
+#define   ADPA_CRT_HOTPLUG_MONITOR_NONE                REG_FIELD_PREP(ADPA_CRT_HOTPLUG_MONITOR_MASK, 0)
+#define   ADPA_CRT_HOTPLUG_MONITOR_COLOR       REG_FIELD_PREP(ADPA_CRT_HOTPLUG_MONITOR_MASK, 3)
+#define   ADPA_CRT_HOTPLUG_MONITOR_MONO                REG_FIELD_PREP(ADPA_CRT_HOTPLUG_MONITOR_MASK, 2)
+#define   ADPA_CRT_HOTPLUG_ENABLE              REG_BIT(23)
+#define   ADPA_CRT_HOTPLUG_PERIOD_MASK         REG_BIT(22)
+#define   ADPA_CRT_HOTPLUG_PERIOD_64           REG_FIELD_PREP(ADPA_CRT_HOTPLUG_PERIOD_MASK, 0)
+#define   ADPA_CRT_HOTPLUG_PERIOD_128          REG_FIELD_PREP(ADPA_CRT_HOTPLUG_PERIOD_MASK, 1)
+#define   ADPA_CRT_HOTPLUG_WARMUP_MASK         REG_BIT(21)
+#define   ADPA_CRT_HOTPLUG_WARMUP_5MS          REG_FIELD_PREP(ADPA_CRT_HOTPLUG_WARMUP_MASK, 0)
+#define   ADPA_CRT_HOTPLUG_WARMUP_10MS         REG_FIELD_PREP(ADPA_CRT_HOTPLUG_WARMUP_MASK, 1)
+#define   ADPA_CRT_HOTPLUG_SAMPLE_MASK         REG_BIT(20)
+#define   ADPA_CRT_HOTPLUG_SAMPLE_2S           REG_FIELD_PREP(ADPA_CRT_HOTPLUG_SAMPLE_MASK, 0)
+#define   ADPA_CRT_HOTPLUG_SAMPLE_4S           REG_FIELD_PREP(ADPA_CRT_HOTPLUG_SAMPLE_MASK, 1)
+#define   ADPA_CRT_HOTPLUG_VOLTAGE_MASK                REG_GENMASK(19, 18)
+#define   ADPA_CRT_HOTPLUG_VOLTAGE_40          REG_FIELD_PREP(ADPA_CRT_HOTPLUG_VOLTAGE_MASK, 0)
+#define   ADPA_CRT_HOTPLUG_VOLTAGE_50          REG_FIELD_PREP(ADPA_CRT_HOTPLUG_VOLTAGE_MASK, 1)
+#define   ADPA_CRT_HOTPLUG_VOLTAGE_60          REG_FIELD_PREP(ADPA_CRT_HOTPLUG_VOLTAGE_MASK, 2)
+#define   ADPA_CRT_HOTPLUG_VOLTAGE_70          REG_FIELD_PREP(ADPA_CRT_HOTPLUG_VOLTAGE_MASK, 3)
+#define   ADPA_CRT_HOTPLUG_VOLREF_MASK         REG_BIT(17)
+#define   ADPA_CRT_HOTPLUG_VOLREF_325MV                REG_FIELD_PREP(ADPA_CRT_HOTPLUG_VOLREF_MASK, 0)
+#define   ADPA_CRT_HOTPLUG_VOLREF_475MV                REG_FIELD_PREP(ADPA_CRT_HOTPLUG_VOLREF_MASK, 1)
+#define   ADPA_CRT_HOTPLUG_FORCE_TRIGGER       REG_BIT(16)
+#define   ADPA_USE_VGA_HVPOLARITY              REG_BIT(15)
+#define   ADPA_HSYNC_CNTL_DISABLE              REG_BIT(11)
+#define   ADPA_VSYNC_CNTL_DISABLE              REG_BIT(10)
+#define   ADPA_VSYNC_ACTIVE_HIGH               REG_BIT(4)
+#define   ADPA_HSYNC_ACTIVE_HIGH               REG_BIT(3)
+
+#endif /* __INTEL_CRT_REGS_H__ */

diff --git a/drivers/gpu/drm/i915/display/intel_pch_display.c b/drivers/gpu/drm/i915/display/intel_pch_display.c
index 4210de8..cd48d3e 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_pch_display.c
+++ b/drivers/gpu/drm/i915/display/intel_pch_display.c
@@ -6,6 +6,7 @@
 #include "g4x_dp.h"
 #include "i915_reg.h"
 #include "intel_crt.h"
+#include "intel_crt_regs.h"
 #include "intel_de.h"
 #include "intel_display_types.h"
 #include "intel_dpll.h"

diff --git a/drivers/gpu/drm/i915/gvt/display.c b/drivers/gpu/drm/i915/gvt/display.c
index 17f74cb..b613682 100644 (file)
--- a/drivers/gpu/drm/i915/gvt/display.c
+++ b/drivers/gpu/drm/i915/gvt/display.c
@@ -40,6 +40,7 @@
 
 #include "display/bxt_dpio_phy_regs.h"
 #include "display/i9xx_plane_regs.h"
+#include "display/intel_crt_regs.h"
 #include "display/intel_cursor_regs.h"
 #include "display/intel_display.h"
 #include "display/intel_dpio_phy.h"

diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
index 9494d81..25acb9d 100644 (file)
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -45,6 +45,7 @@
 #include "intel_mchbar_regs.h"
 #include "display/bxt_dpio_phy_regs.h"
 #include "display/i9xx_plane_regs.h"
+#include "display/intel_crt_regs.h"
 #include "display/intel_cursor_regs.h"
 #include "display/intel_display_types.h"
 #include "display/intel_dmc_regs.h"

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index b670dc2..261f388 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1147,44 +1147,6 @@
 #define _TRANS_MULT_B          0x6102c
 #define TRANS_MULT(dev_priv, trans)    _MMIO_TRANS2(dev_priv, (trans), _TRANS_MULT_A)
 
-/* VGA port control */
-#define ADPA                   _MMIO(0x61100)
-#define PCH_ADPA                _MMIO(0xe1100)
-#define VLV_ADPA               _MMIO(VLV_DISPLAY_BASE + 0x61100)
-#define   ADPA_DAC_ENABLE                      REG_BIT(31)
-#define   ADPA_PIPE_SEL_MASK                   REG_BIT(30)
-#define   ADPA_PIPE_SEL(pipe)                  REG_FIELD_PREP(ADPA_PIPE_SEL_MASK, (pipe))
-#define   ADPA_PIPE_SEL_MASK_CPT               REG_GENMASK(30, 29)
-#define   ADPA_PIPE_SEL_CPT(pipe)              REG_FIELD_PREP(ADPA_PIPE_SEL_MASK_CPT, (pipe))
-#define   ADPA_CRT_HOTPLUG_MONITOR_MASK                REG_GENMASK(25, 24)
-#define   ADPA_CRT_HOTPLUG_MONITOR_NONE                REG_FIELD_PREP(ADPA_CRT_HOTPLUG_MONITOR_MASK, 0)
-#define   ADPA_CRT_HOTPLUG_MONITOR_COLOR       REG_FIELD_PREP(ADPA_CRT_HOTPLUG_MONITOR_MASK, 3)
-#define   ADPA_CRT_HOTPLUG_MONITOR_MONO                REG_FIELD_PREP(ADPA_CRT_HOTPLUG_MONITOR_MASK, 2)
-#define   ADPA_CRT_HOTPLUG_ENABLE              REG_BIT(23)
-#define   ADPA_CRT_HOTPLUG_PERIOD_MASK         REG_BIT(22)
-#define   ADPA_CRT_HOTPLUG_PERIOD_64           REG_FIELD_PREP(ADPA_CRT_HOTPLUG_PERIOD_MASK, 0)
-#define   ADPA_CRT_HOTPLUG_PERIOD_128          REG_FIELD_PREP(ADPA_CRT_HOTPLUG_PERIOD_MASK, 1)
-#define   ADPA_CRT_HOTPLUG_WARMUP_MASK         REG_BIT(21)
-#define   ADPA_CRT_HOTPLUG_WARMUP_5MS          REG_FIELD_PREP(ADPA_CRT_HOTPLUG_WARMUP_MASK, 0)
-#define   ADPA_CRT_HOTPLUG_WARMUP_10MS         REG_FIELD_PREP(ADPA_CRT_HOTPLUG_WARMUP_MASK, 1)
-#define   ADPA_CRT_HOTPLUG_SAMPLE_MASK         REG_BIT(20)
-#define   ADPA_CRT_HOTPLUG_SAMPLE_2S           REG_FIELD_PREP(ADPA_CRT_HOTPLUG_SAMPLE_MASK, 0)
-#define   ADPA_CRT_HOTPLUG_SAMPLE_4S           REG_FIELD_PREP(ADPA_CRT_HOTPLUG_SAMPLE_MASK, 1)
-#define   ADPA_CRT_HOTPLUG_VOLTAGE_MASK                REG_GENMASK(19, 18)
-#define   ADPA_CRT_HOTPLUG_VOLTAGE_40          REG_FIELD_PREP(ADPA_CRT_HOTPLUG_VOLTAGE_MASK, 0)
-#define   ADPA_CRT_HOTPLUG_VOLTAGE_50          REG_FIELD_PREP(ADPA_CRT_HOTPLUG_VOLTAGE_MASK, 1)
-#define   ADPA_CRT_HOTPLUG_VOLTAGE_60          REG_FIELD_PREP(ADPA_CRT_HOTPLUG_VOLTAGE_MASK, 2)
-#define   ADPA_CRT_HOTPLUG_VOLTAGE_70          REG_FIELD_PREP(ADPA_CRT_HOTPLUG_VOLTAGE_MASK, 3)
-#define   ADPA_CRT_HOTPLUG_VOLREF_MASK         REG_BIT(17)
-#define   ADPA_CRT_HOTPLUG_VOLREF_325MV                REG_FIELD_PREP(ADPA_CRT_HOTPLUG_VOLREF_MASK, 0)
-#define   ADPA_CRT_HOTPLUG_VOLREF_475MV                REG_FIELD_PREP(ADPA_CRT_HOTPLUG_VOLREF_MASK, 1)
-#define   ADPA_CRT_HOTPLUG_FORCE_TRIGGER       REG_BIT(16)
-#define   ADPA_USE_VGA_HVPOLARITY              REG_BIT(15)
-#define   ADPA_HSYNC_CNTL_DISABLE              REG_BIT(11)
-#define   ADPA_VSYNC_CNTL_DISABLE              REG_BIT(10)
-#define   ADPA_VSYNC_ACTIVE_HIGH               REG_BIT(4)
-#define   ADPA_HSYNC_ACTIVE_HIGH               REG_BIT(3)
-
 /* Hotplug control (945+ only) */
 #define PORT_HOTPLUG_EN(dev_priv)              _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61110)
 #define   PORTB_HOTPLUG_INT_EN                 (1 << 29)

diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
index 955c9a3..6384938 100644 (file)
--- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
+++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
@@ -8,6 +8,7 @@
 #include "display/intel_audio_regs.h"
 #include "display/intel_backlight_regs.h"
 #include "display/intel_color_regs.h"
+#include "display/intel_crt_regs.h"
 #include "display/intel_cursor_regs.h"
 #include "display/intel_display_types.h"
 #include "display/intel_dmc_regs.h"