ACPICA: Clear PM register write-only bits on reading

Affects PM1 Control register only. When reading the register, zero
the write-only bits as per the ACPI spec.  ACPICA BZ 443. Lin Ming.

http://www.acpica.org/bugzilla/show_bug.cgi?id=443

Signed-off-by: Lin Ming <ming.m.lin@intel.com>
Signed-off-by: Bob Moore <robert.moore@intel.com>
Signed-off-by: Len Brown <len.brown@intel.com>

diff --git a/drivers/acpi/acpica/aclocal.h b/drivers/acpi/acpica/aclocal.h
index 42ef0cb..772ee5c 100644 (file)
--- a/drivers/acpi/acpica/aclocal.h
+++ b/drivers/acpi/acpica/aclocal.h
@@ -781,6 +781,10 @@ struct acpi_bit_register_info {
  */
 #define ACPI_PM1_STATUS_PRESERVED_BITS          0x0800 /* Bit 11 */
 
+/* Write-only bits must be zeroed by software */
+
+#define ACPI_PM1_CONTROL_WRITEONLY_BITS         0x2004 /* Bits 13, 2 */
+
 /* For control registers, both ignored and reserved bits must be preserved */
 
 #define ACPI_PM1_CONTROL_IGNORED_BITS           0x0201 /* Bits 9, 0(SCI_EN) */

diff --git a/drivers/acpi/acpica/hwregs.c b/drivers/acpi/acpica/hwregs.c
index f8ee0a7..7b2fb60 100644 (file)
--- a/drivers/acpi/acpica/hwregs.c
+++ b/drivers/acpi/acpica/hwregs.c
@@ -207,6 +207,13 @@ acpi_hw_register_read(u32 register_id, u32 * return_value)
                                               xpm1a_control_block,
                                               &acpi_gbl_FADT.
                                               xpm1b_control_block);
+
+               /*
+                * Zero the write-only bits. From the ACPI specification, "Hardware
+                * Write-Only Bits": "Upon reads to registers with write-only bits,
+                * software masks out all write-only bits."
+                */
+               value &= ~ACPI_PM1_CONTROL_WRITEONLY_BITS;
                break;
 
        case ACPI_REGISTER_PM2_CONTROL: /* 8-bit access */