Merge branches 'clk-cleanup', 'clk-renesas', 'clk-socfpga', 'clk-allwinner' and ...

 - Use clk_hw pointers in socfpga driver
 - Cleanup parent data in qcom clk drivers

* clk-cleanup:
  clk: Drop double "if" in clk_core_determine_round_nolock() comment
  clk: at91: Trivial typo fixes in the file sama7g5.c
  clk: use clk_core_enable_lock() a bit more

* clk-renesas:
  clk: renesas: Zero init clk_init_data
  clk: renesas: Couple of spelling fixes
  clk: renesas: r8a779a0: Add CMT clocks
  clk: renesas: r8a7795: Add TMU clocks
  clk: renesas: r8a779a0: Add TSC clock
  clk: renesas: r8a779a0: Add TMU clocks
  clk: renesas: r8a77965: Add DAB clock
  clk: renesas: r8a77990: Add DAB clock

* clk-socfpga:
  clk: socfpga: remove redundant initialization of variable div
  clk: socfpga: arria10: Fix memory leak of socfpga_clk on error return
  clk: socfpga: Fix code formatting
  clk: socfpga: Convert to s10/agilex/n5x to use clk_hw
  clk: socfpga: arria10: convert to use clk_hw
  clk: socfpga: use clk_hw_register for a5/c5

* clk-allwinner:
  clk: sunxi: Demote non-conformant kernel-doc headers
  clk: sunxi-ng: v3s: use sigma-delta modulation for audio-pll

* clk-qcom: (45 commits)
  clk: qcom: rpmh: add support for SDX55 rpmh IPA clock
  clk: qcom: gcc-sdm845: get rid of the test clock
  clk: qcom: convert SDM845 Global Clock Controller to parent_data
  dt-bindings: clock: separate SDM845 GCC clock bindings
  clk: qcom: apss-ipq-pll: Add missing MODULE_DEVICE_TABLE
  clk: qcom: a53-pll: Add missing MODULE_DEVICE_TABLE
  clk: qcom: a7-pll: Add missing MODULE_DEVICE_TABLE
  clk: qcom: gcc-sm8350: use ARRAY_SIZE instead of specifying num_parents
  clk: qcom: gcc-sm8250: use ARRAY_SIZE instead of specifying num_parents
  clk: qcom: gcc-sm8150: use ARRAY_SIZE instead of specifying num_parents
  clk: qcom: gcc-sc8180x: use ARRAY_SIZE instead of specifying num_parents
  clk: qcom: gcc-sc7180: use ARRAY_SIZE instead of specifying num_parents
  clk: qcom: videocc-sm8250: use parent_hws where possible
  clk: qcom: videocc-sm8150: use parent_hws where possible
  clk: qcom: gpucc-sm8250: use parent_hws where possible
  clk: qcom: gpucc-sm8150: use parent_hws where possible
  clk: qcom: gcc-sm8350: use parent_hws where possible
  clk: qcom: gcc-sm8250: use parent_hws where possible
  clk: qcom: gcc-sm8150: use parent_hws where possible
  clk: qcom: gcc-sdx55: use parent_hws where possible
  ...

diff --git a/drivers/clk/at91/sama7g5.c b/drivers/clk/at91/sama7g5.c
index a6e20b3..9e1ec48 100644 (file)
--- a/drivers/clk/at91/sama7g5.c
+++ b/drivers/clk/at91/sama7g5.c
@@ -166,7 +166,7 @@ static const struct {
                  .c = &pll_characteristics,
                  .t = PLL_TYPE_FRAC,
                   /*
-                   * This feeds syspll_divpmcck which may feed critial parts
+                   * This feeds syspll_divpmcck which may feed critical parts
                    * of the systems like timers. Therefore it should not be
                    * disabled.
                    */
@@ -178,7 +178,7 @@ static const struct {
                  .c = &pll_characteristics,
                  .t = PLL_TYPE_DIV,
                   /*
-                   * This may feed critial parts of the systems like timers.
+                   * This may feed critical parts of the systems like timers.
                    * Therefore it should not be disabled.
                    */
                  .f = CLK_IS_CRITICAL | CLK_SET_RATE_GATE,
@@ -455,7 +455,7 @@ static const struct {
  * @pp:                        PLL parents
  * @pp_mux_table:      PLL parents mux table
  * @r:                 clock output range
- * @pp_chg_id:         id in parrent array of changeable PLL parent
+ * @pp_chg_id:         id in parent array of changeable PLL parent
  * @pp_count:          PLL parents count
  * @id:                        clock id
  */

diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
index 5052541..d181c6d 100644 (file)
--- a/drivers/clk/clk.c
+++ b/drivers/clk/clk.c
@@ -1330,7 +1330,7 @@ static int clk_core_determine_round_nolock(struct clk_core *core,
                return 0;
 
        /*
-        * At this point, core protection will be disabled if
+        * At this point, core protection will be disabled
         * - if the provider is not protected at all
         * - if the calling consumer is the only one which has exclusivity
         *   over the provider
@@ -2078,12 +2078,8 @@ static void clk_change_rate(struct clk_core *core)
                return;
 
        if (core->flags & CLK_SET_RATE_UNGATE) {
-               unsigned long flags;
-
                clk_core_prepare(core);
-               flags = clk_enable_lock();
-               clk_core_enable(core);
-               clk_enable_unlock(flags);
+               clk_core_enable_lock(core);
        }
 
        if (core->new_parent && core->new_parent != core->parent) {
@@ -2116,11 +2112,7 @@ static void clk_change_rate(struct clk_core *core)
        core->rate = clk_recalc(core, best_parent_rate);
 
        if (core->flags & CLK_SET_RATE_UNGATE) {
-               unsigned long flags;
-
-               flags = clk_enable_lock();
-               clk_core_disable(core);
-               clk_enable_unlock(flags);
+               clk_core_disable_lock(core);
                clk_core_unprepare(core);
        }
 
@@ -3564,8 +3556,6 @@ static int __clk_core_init(struct clk_core *core)
         * reparenting clocks
         */
        if (core->flags & CLK_IS_CRITICAL) {
-               unsigned long flags;
-
                ret = clk_core_prepare(core);
                if (ret) {
                        pr_warn("%s: critical clk '%s' failed to prepare\n",
@@ -3573,9 +3563,7 @@ static int __clk_core_init(struct clk_core *core)
                        goto out;
                }
 
-               flags = clk_enable_lock();
-               ret = clk_core_enable(core);
-               clk_enable_unlock(flags);
+               ret = clk_core_enable_lock(core);
                if (ret) {
                        pr_warn("%s: critical clk '%s' failed to enable\n",
                               __func__, core->name);

diff --git a/drivers/clk/renesas/clk-div6.c b/drivers/clk/renesas/clk-div6.c
index 5ca183e..8fb68e7 100644 (file)
--- a/drivers/clk/renesas/clk-div6.c
+++ b/drivers/clk/renesas/clk-div6.c
@@ -216,7 +216,7 @@ struct clk * __init cpg_div6_register(const char *name,
                                      struct raw_notifier_head *notifiers)
 {
        unsigned int valid_parents;
-       struct clk_init_data init;
+       struct clk_init_data init = {};
        struct div6_clock *clock;
        struct clk *clk;
        unsigned int i;
@@ -267,7 +267,6 @@ struct clk * __init cpg_div6_register(const char *name,
        /* Register the clock. */
        init.name = name;
        init.ops = &cpg_div6_clock_ops;
-       init.flags = 0;
        init.parent_names = parent_names;
        init.num_parents = valid_parents;
 

diff --git a/drivers/clk/renesas/clk-mstp.c b/drivers/clk/renesas/clk-mstp.c
index 003e9ce..90804ac 100644 (file)
--- a/drivers/clk/renesas/clk-mstp.c
+++ b/drivers/clk/renesas/clk-mstp.c
@@ -150,7 +150,7 @@ static struct clk * __init cpg_mstp_clock_register(const char *name,
        const char *parent_name, unsigned int index,
        struct mstp_clock_group *group)
 {
-       struct clk_init_data init;
+       struct clk_init_data init = {};
        struct mstp_clock *clock;
        struct clk *clk;
 

diff --git a/drivers/clk/renesas/r8a7795-cpg-mssr.c b/drivers/clk/renesas/r8a7795-cpg-mssr.c
index 068018a..c32d2c6 100644 (file)
--- a/drivers/clk/renesas/r8a7795-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7795-cpg-mssr.c
@@ -128,6 +128,11 @@ static struct mssr_mod_clk r8a7795_mod_clks[] __initdata = {
        DEF_MOD("fdp1-2",                117,   R8A7795_CLK_S2D1), /* ES1.x */
        DEF_MOD("fdp1-1",                118,   R8A7795_CLK_S0D1),
        DEF_MOD("fdp1-0",                119,   R8A7795_CLK_S0D1),
+       DEF_MOD("tmu4",                  121,   R8A7795_CLK_S0D6),
+       DEF_MOD("tmu3",                  122,   R8A7795_CLK_S3D2),
+       DEF_MOD("tmu2",                  123,   R8A7795_CLK_S3D2),
+       DEF_MOD("tmu1",                  124,   R8A7795_CLK_S3D2),
+       DEF_MOD("tmu0",                  125,   R8A7795_CLK_CP),
        DEF_MOD("scif5",                 202,   R8A7795_CLK_S3D4),
        DEF_MOD("scif4",                 203,   R8A7795_CLK_S3D4),
        DEF_MOD("scif3",                 204,   R8A7795_CLK_S3D4),
@@ -362,6 +367,7 @@ static const unsigned int r8a7795es1_mod_nullify[] __initconst = {
 static const struct mssr_mod_reparent r8a7795es1_mod_reparent[] __initconst = {
        { MOD_CLK_ID(118), R8A7795_CLK_S2D1 },  /* FDP1-1 */
        { MOD_CLK_ID(119), R8A7795_CLK_S2D1 },  /* FDP1-0 */
+       { MOD_CLK_ID(121), R8A7795_CLK_S3D2 },  /* TMU4 */
        { MOD_CLK_ID(217), R8A7795_CLK_S3D1 },  /* SYS-DMAC2 */
        { MOD_CLK_ID(218), R8A7795_CLK_S3D1 },  /* SYS-DMAC1 */
        { MOD_CLK_ID(219), R8A7795_CLK_S3D1 },  /* SYS-DMAC0 */

diff --git a/drivers/clk/renesas/r8a77965-cpg-mssr.c b/drivers/clk/renesas/r8a77965-cpg-mssr.c
index 46a1577..bc1be8b 100644 (file)
--- a/drivers/clk/renesas/r8a77965-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a77965-cpg-mssr.c
@@ -250,6 +250,7 @@ static const struct mssr_mod_clk r8a77965_mod_clks[] __initconst = {
        DEF_MOD("ssi2",                 1013,   MOD_CLK_ID(1005)),
        DEF_MOD("ssi1",                 1014,   MOD_CLK_ID(1005)),
        DEF_MOD("ssi0",                 1015,   MOD_CLK_ID(1005)),
+       DEF_MOD("dab",                  1016,   R8A77965_CLK_S0D6),
        DEF_MOD("scu-all",              1017,   R8A77965_CLK_S3D4),
        DEF_MOD("scu-dvc1",             1018,   MOD_CLK_ID(1017)),
        DEF_MOD("scu-dvc0",             1019,   MOD_CLK_ID(1017)),

diff --git a/drivers/clk/renesas/r8a77990-cpg-mssr.c b/drivers/clk/renesas/r8a77990-cpg-mssr.c
index 2d172f8..a582f2e 100644 (file)
--- a/drivers/clk/renesas/r8a77990-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a77990-cpg-mssr.c
@@ -232,6 +232,7 @@ static const struct mssr_mod_clk r8a77990_mod_clks[] __initconst = {
        DEF_MOD("ssi2",                 1013,   MOD_CLK_ID(1005)),
        DEF_MOD("ssi1",                 1014,   MOD_CLK_ID(1005)),
        DEF_MOD("ssi0",                 1015,   MOD_CLK_ID(1005)),
+       DEF_MOD("dab",                  1016,   R8A77990_CLK_S3D1),
        DEF_MOD("scu-all",              1017,   R8A77990_CLK_S3D4),
        DEF_MOD("scu-dvc1",             1018,   MOD_CLK_ID(1017)),
        DEF_MOD("scu-dvc0",             1019,   MOD_CLK_ID(1017)),

diff --git a/drivers/clk/renesas/r8a779a0-cpg-mssr.c b/drivers/clk/renesas/r8a779a0-cpg-mssr.c
index f23fe9d..867c565 100644 (file)
--- a/drivers/clk/renesas/r8a779a0-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a779a0-cpg-mssr.c
@@ -144,6 +144,7 @@ static const struct cpg_core_clk r8a779a0_core_clks[] __initconst = {
        DEF_FIXED("vcbus",      R8A779A0_CLK_VCBUS,     CLK_PLL5_DIV4,  1, 1),
        DEF_FIXED("cbfusa",     R8A779A0_CLK_CBFUSA,    CLK_EXTAL,      2, 1),
        DEF_FIXED("cp",         R8A779A0_CLK_CP,        CLK_EXTAL,      2, 1),
+       DEF_FIXED("cl16mck",    R8A779A0_CLK_CL16MCK,   CLK_PLL1_DIV2,  64, 1),
 
        DEF_SD("sd0",           R8A779A0_CLK_SD0,       CLK_SDSRC,      0x870),
 
@@ -192,6 +193,11 @@ static const struct mssr_mod_clk r8a779a0_mod_clks[] __initconst = {
        DEF_MOD("sdhi0",        706,    R8A779A0_CLK_SD0),
        DEF_MOD("sydm1",        709,    R8A779A0_CLK_S1D2),
        DEF_MOD("sydm2",        710,    R8A779A0_CLK_S1D2),
+       DEF_MOD("tmu0",         713,    R8A779A0_CLK_CL16MCK),
+       DEF_MOD("tmu1",         714,    R8A779A0_CLK_S1D4),
+       DEF_MOD("tmu2",         715,    R8A779A0_CLK_S1D4),
+       DEF_MOD("tmu3",         716,    R8A779A0_CLK_S1D4),
+       DEF_MOD("tmu4",         717,    R8A779A0_CLK_S1D4),
        DEF_MOD("vin00",        730,    R8A779A0_CLK_S1D1),
        DEF_MOD("vin01",        731,    R8A779A0_CLK_S1D1),
        DEF_MOD("vin02",        800,    R8A779A0_CLK_S1D1),
@@ -227,10 +233,15 @@ static const struct mssr_mod_clk r8a779a0_mod_clks[] __initconst = {
        DEF_MOD("vspd0",        830,    R8A779A0_CLK_S3D1),
        DEF_MOD("vspd1",        831,    R8A779A0_CLK_S3D1),
        DEF_MOD("rwdt",         907,    R8A779A0_CLK_R),
+       DEF_MOD("cmt0",         910,    R8A779A0_CLK_R),
+       DEF_MOD("cmt1",         911,    R8A779A0_CLK_R),
+       DEF_MOD("cmt2",         912,    R8A779A0_CLK_R),
+       DEF_MOD("cmt3",         913,    R8A779A0_CLK_R),
        DEF_MOD("pfc0",         915,    R8A779A0_CLK_CP),
        DEF_MOD("pfc1",         916,    R8A779A0_CLK_CP),
        DEF_MOD("pfc2",         917,    R8A779A0_CLK_CP),
        DEF_MOD("pfc3",         918,    R8A779A0_CLK_CP),
+       DEF_MOD("tsc",          919,    R8A779A0_CLK_CL16MCK),
        DEF_MOD("vspx0",        1028,   R8A779A0_CLK_S1D1),
        DEF_MOD("vspx1",        1029,   R8A779A0_CLK_S1D1),
        DEF_MOD("vspx2",        1030,   R8A779A0_CLK_S1D1),

diff --git a/drivers/clk/renesas/r9a06g032-clocks.c b/drivers/clk/renesas/r9a06g032-clocks.c
index 892e91b..71b1144 100644 (file)
--- a/drivers/clk/renesas/r9a06g032-clocks.c
+++ b/drivers/clk/renesas/r9a06g032-clocks.c
@@ -279,7 +279,7 @@ static const struct r9a06g032_clkdesc r9a06g032_clocks[] = {
        /*
         * These are not hardware clocks, but are needed to handle the special
         * case where we have a 'selector bit' that doesn't just change the
-        * parent for a clock, but also the gate it's suposed to use.
+        * parent for a clock, but also the gate it's supposed to use.
         */
        {
                .index = R9A06G032_UART_GROUP_012,
@@ -311,7 +311,7 @@ static const struct r9a06g032_clkdesc r9a06g032_clocks[] = {
 
 struct r9a06g032_priv {
        struct clk_onecell_data data;
-       spinlock_t lock; /* protects concurent access to gates */
+       spinlock_t lock; /* protects concurrent access to gates */
        void __iomem *reg;
 };
 
@@ -504,7 +504,7 @@ r9a06g032_register_gate(struct r9a06g032_priv *clocks,
 {
        struct clk *clk;
        struct r9a06g032_clk_gate *g;
-       struct clk_init_data init;
+       struct clk_init_data init = {};
 
        g = kzalloc(sizeof(*g), GFP_KERNEL);
        if (!g)
@@ -674,7 +674,7 @@ r9a06g032_register_div(struct r9a06g032_priv *clocks,
 {
        struct r9a06g032_clk_div *div;
        struct clk *clk;
-       struct clk_init_data init;
+       struct clk_init_data init = {};
        unsigned int i;
 
        div = kzalloc(sizeof(*div), GFP_KERNEL);
@@ -758,7 +758,7 @@ r9a06g032_register_bitsel(struct r9a06g032_priv *clocks,
 {
        struct clk *clk;
        struct r9a06g032_clk_bitsel *g;
-       struct clk_init_data init;
+       struct clk_init_data init = {};
        const char *names[2];
 
        /* allocate the gate */
@@ -849,7 +849,7 @@ r9a06g032_register_dualgate(struct r9a06g032_priv *clocks,
 {
        struct r9a06g032_clk_dualgate *g;
        struct clk *clk;
-       struct clk_init_data init;
+       struct clk_init_data init = {};
 
        /* allocate the gate */
        g = kzalloc(sizeof(*g), GFP_KERNEL);

diff --git a/drivers/clk/renesas/rcar-cpg-lib.c b/drivers/clk/renesas/rcar-cpg-lib.c
index 7e7e5d1..5678768 100644 (file)
--- a/drivers/clk/renesas/rcar-cpg-lib.c
+++ b/drivers/clk/renesas/rcar-cpg-lib.c
@@ -226,7 +226,7 @@ struct clk * __init cpg_sd_clk_register(const char *name,
        void __iomem *base, unsigned int offset, const char *parent_name,
        struct raw_notifier_head *notifiers, bool skip_first)
 {
-       struct clk_init_data init;
+       struct clk_init_data init = {};
        struct sd_clock *clock;
        struct clk *clk;
        u32 val;

diff --git a/drivers/clk/renesas/rcar-gen2-cpg.c b/drivers/clk/renesas/rcar-gen2-cpg.c
index d4fa3dc..edae874 100644 (file)
--- a/drivers/clk/renesas/rcar-gen2-cpg.c
+++ b/drivers/clk/renesas/rcar-gen2-cpg.c
@@ -137,7 +137,7 @@ static struct clk * __init cpg_z_clk_register(const char *name,
                                              const char *parent_name,
                                              void __iomem *base)
 {
-       struct clk_init_data init;
+       struct clk_init_data init = {};
        struct cpg_z_clk *zclk;
        struct clk *clk;
 
@@ -147,7 +147,6 @@ static struct clk * __init cpg_z_clk_register(const char *name,
 
        init.name = name;
        init.ops = &cpg_z_clk_ops;
-       init.flags = 0;
        init.parent_names = &parent_name;
        init.num_parents = 1;
 

diff --git a/drivers/clk/renesas/rcar-gen3-cpg.c b/drivers/clk/renesas/rcar-gen3-cpg.c
index 1782659..caa0f94 100644 (file)
--- a/drivers/clk/renesas/rcar-gen3-cpg.c
+++ b/drivers/clk/renesas/rcar-gen3-cpg.c
@@ -143,7 +143,7 @@ static struct clk * __init cpg_z_clk_register(const char *name,
                                              unsigned int div,
                                              unsigned int offset)
 {
-       struct clk_init_data init;
+       struct clk_init_data init = {};
        struct cpg_z_clk *zclk;
        struct clk *clk;
 

diff --git a/drivers/clk/renesas/rcar-usb2-clock-sel.c b/drivers/clk/renesas/rcar-usb2-clock-sel.c
index 3abafd7..34a85dc 100644 (file)
--- a/drivers/clk/renesas/rcar-usb2-clock-sel.c
+++ b/drivers/clk/renesas/rcar-usb2-clock-sel.c
@@ -144,7 +144,7 @@ static int rcar_usb2_clock_sel_probe(struct platform_device *pdev)
        struct device_node *np = dev->of_node;
        struct usb2_clock_sel_priv *priv;
        struct clk *clk;
-       struct clk_init_data init;
+       struct clk_init_data init = {};
        int ret;
 
        priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
@@ -188,9 +188,6 @@ static int rcar_usb2_clock_sel_probe(struct platform_device *pdev)
 
        init.name = "rcar_usb2_clock_sel";
        init.ops = &usb2_clock_sel_clock_ops;
-       init.flags = 0;
-       init.parent_names = NULL;
-       init.num_parents = 0;
        priv->hw.init = &init;
 
        clk = clk_register(NULL, &priv->hw);

diff --git a/drivers/clk/renesas/renesas-cpg-mssr.c b/drivers/clk/renesas/renesas-cpg-mssr.c
index bffbc3d..fc531d3 100644 (file)
--- a/drivers/clk/renesas/renesas-cpg-mssr.c
+++ b/drivers/clk/renesas/renesas-cpg-mssr.c
@@ -408,7 +408,7 @@ static void __init cpg_mssr_register_mod_clk(const struct mssr_mod_clk *mod,
        struct mstp_clock *clock = NULL;
        struct device *dev = priv->dev;
        unsigned int id = mod->id;
-       struct clk_init_data init;
+       struct clk_init_data init = {};
        struct clk *parent, *clk;
        const char *parent_name;
        unsigned int i;

diff --git a/drivers/clk/socfpga/clk-agilex.c b/drivers/clk/socfpga/clk-agilex.c
index 7689bdd..92a6d74 100644 (file)
--- a/drivers/clk/socfpga/clk-agilex.c
+++ b/drivers/clk/socfpga/clk-agilex.c
@@ -303,18 +303,18 @@ static const struct stratix10_gate_clock agilex_gate_clks[] = {
 static int n5x_clk_register_c_perip(const struct n5x_perip_c_clock *clks,
                                       int nums, struct stratix10_clock_data *data)
 {
-       struct clk *clk;
+       struct clk_hw *hw_clk;
        void __iomem *base = data->base;
        int i;
 
        for (i = 0; i < nums; i++) {
-               clk = n5x_register_periph(&clks[i], base);
-               if (IS_ERR(clk)) {
+               hw_clk = n5x_register_periph(&clks[i], base);
+               if (IS_ERR(hw_clk)) {
                        pr_err("%s: failed to register clock %s\n",
                               __func__, clks[i].name);
                        continue;
                }
-               data->clk_data.clks[clks[i].id] = clk;
+               data->clk_data.hws[clks[i].id] = hw_clk;
        }
        return 0;
 }
@@ -322,18 +322,18 @@ static int n5x_clk_register_c_perip(const struct n5x_perip_c_clock *clks,
 static int agilex_clk_register_c_perip(const struct stratix10_perip_c_clock *clks,
                                       int nums, struct stratix10_clock_data *data)
 {
-       struct clk *clk;
+       struct clk_hw *hw_clk;
        void __iomem *base = data->base;
        int i;
 
        for (i = 0; i < nums; i++) {
-               clk = s10_register_periph(&clks[i], base);
-               if (IS_ERR(clk)) {
+               hw_clk = s10_register_periph(&clks[i], base);
+               if (IS_ERR(hw_clk)) {
                        pr_err("%s: failed to register clock %s\n",
                               __func__, clks[i].name);
                        continue;
                }
-               data->clk_data.clks[clks[i].id] = clk;
+               data->clk_data.hws[clks[i].id] = hw_clk;
        }
        return 0;
 }
@@ -341,37 +341,38 @@ static int agilex_clk_register_c_perip(const struct stratix10_perip_c_clock *clk
 static int agilex_clk_register_cnt_perip(const struct stratix10_perip_cnt_clock *clks,
                                         int nums, struct stratix10_clock_data *data)
 {
-       struct clk *clk;
+       struct clk_hw *hw_clk;
        void __iomem *base = data->base;
        int i;
 
        for (i = 0; i < nums; i++) {
-               clk = s10_register_cnt_periph(&clks[i], base);
-               if (IS_ERR(clk)) {
+               hw_clk = s10_register_cnt_periph(&clks[i], base);
+               if (IS_ERR(hw_clk)) {
                        pr_err("%s: failed to register clock %s\n",
                               __func__, clks[i].name);
                        continue;
                }
-               data->clk_data.clks[clks[i].id] = clk;
+               data->clk_data.hws[clks[i].id] = hw_clk;
        }
 
        return 0;
 }
 
-static int agilex_clk_register_gate(const struct stratix10_gate_clock *clks,                                       int nums, struct stratix10_clock_data *data)
+static int agilex_clk_register_gate(const struct stratix10_gate_clock *clks,
+                                   int nums, struct stratix10_clock_data *data)
 {
-       struct clk *clk;
+       struct clk_hw *hw_clk;
        void __iomem *base = data->base;
        int i;
 
        for (i = 0; i < nums; i++) {
-               clk = s10_register_gate(&clks[i], base);
-               if (IS_ERR(clk)) {
+               hw_clk = s10_register_gate(&clks[i], base);
+               if (IS_ERR(hw_clk)) {
                        pr_err("%s: failed to register clock %s\n",
                               __func__, clks[i].name);
                        continue;
                }
-               data->clk_data.clks[clks[i].id] = clk;
+               data->clk_data.hws[clks[i].id] = hw_clk;
        }
 
        return 0;
@@ -380,18 +381,18 @@ static int agilex_clk_register_gate(const struct stratix10_gate_clock *clks,
 static int agilex_clk_register_pll(const struct stratix10_pll_clock *clks,
                                 int nums, struct stratix10_clock_data *data)
 {
-       struct clk *clk;
+       struct clk_hw *hw_clk;
        void __iomem *base = data->base;
        int i;
 
        for (i = 0; i < nums; i++) {
-               clk = agilex_register_pll(&clks[i], base);
-               if (IS_ERR(clk)) {
+               hw_clk = agilex_register_pll(&clks[i], base);
+               if (IS_ERR(hw_clk)) {
                        pr_err("%s: failed to register clock %s\n",
                               __func__, clks[i].name);
                        continue;
                }
-               data->clk_data.clks[clks[i].id] = clk;
+               data->clk_data.hws[clks[i].id] = hw_clk;
        }
 
        return 0;
@@ -400,64 +401,49 @@ static int agilex_clk_register_pll(const struct stratix10_pll_clock *clks,
 static int n5x_clk_register_pll(const struct stratix10_pll_clock *clks,
                                 int nums, struct stratix10_clock_data *data)
 {
-       struct clk *clk;
+       struct clk_hw *hw_clk;
        void __iomem *base = data->base;
        int i;
 
        for (i = 0; i < nums; i++) {
-               clk = n5x_register_pll(&clks[i], base);
-               if (IS_ERR(clk)) {
+               hw_clk = n5x_register_pll(&clks[i], base);
+               if (IS_ERR(hw_clk)) {
                        pr_err("%s: failed to register clock %s\n",
                               __func__, clks[i].name);
                        continue;
                }
-               data->clk_data.clks[clks[i].id] = clk;
+               data->clk_data.hws[clks[i].id] = hw_clk;
        }
 
        return 0;
 }
 
-static struct stratix10_clock_data *__socfpga_agilex_clk_init(struct platform_device *pdev,
-                                                   int nr_clks)
+static int agilex_clkmgr_init(struct platform_device *pdev)
 {
        struct device_node *np = pdev->dev.of_node;
        struct device *dev = &pdev->dev;
        struct stratix10_clock_data *clk_data;
-       struct clk **clk_table;
        struct resource *res;
        void __iomem *base;
-       int ret;
+       int i, num_clks;
 
        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
        base = devm_ioremap_resource(dev, res);
        if (IS_ERR(base))
-               return ERR_CAST(base);
-
-       clk_data = devm_kzalloc(dev, sizeof(*clk_data), GFP_KERNEL);
-       if (!clk_data)
-               return ERR_PTR(-ENOMEM);
+               return PTR_ERR(base);
 
-       clk_data->base = base;
-       clk_table = devm_kcalloc(dev, nr_clks, sizeof(*clk_table), GFP_KERNEL);
-       if (!clk_table)
-               return ERR_PTR(-ENOMEM);
-
-       clk_data->clk_data.clks = clk_table;
-       clk_data->clk_data.clk_num = nr_clks;
-       ret = of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data->clk_data);
-       if (ret)
-               return ERR_PTR(ret);
+       num_clks = AGILEX_NUM_CLKS;
 
-       return clk_data;
-}
+       clk_data = devm_kzalloc(dev, struct_size(clk_data, clk_data.hws,
+                               num_clks), GFP_KERNEL);
+       if (!clk_data)
+               return -ENOMEM;
 
-static int agilex_clkmgr_init(struct platform_device *pdev)
-{
-       struct stratix10_clock_data *clk_data;
+       for (i = 0; i < num_clks; i++)
+               clk_data->clk_data.hws[i] = ERR_PTR(-ENOENT);
 
-       clk_data = __socfpga_agilex_clk_init(pdev, AGILEX_NUM_CLKS);
-       if (IS_ERR(clk_data))
-               return PTR_ERR(clk_data);
+       clk_data->base = base;
+       clk_data->clk_data.num = num_clks;
 
        agilex_clk_register_pll(agilex_pll_clks, ARRAY_SIZE(agilex_pll_clks), clk_data);
 
@@ -470,16 +456,36 @@ static int agilex_clkmgr_init(struct platform_device *pdev)
 
        agilex_clk_register_gate(agilex_gate_clks, ARRAY_SIZE(agilex_gate_clks),
                              clk_data);
+       of_clk_add_hw_provider(np, of_clk_hw_onecell_get, &clk_data->clk_data);
        return 0;
 }
 
 static int n5x_clkmgr_init(struct platform_device *pdev)
 {
+       struct device_node *np = pdev->dev.of_node;
+       struct device *dev = &pdev->dev;
        struct stratix10_clock_data *clk_data;
+       struct resource *res;
+       void __iomem *base;
+       int i, num_clks;
+
+       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+       base = devm_ioremap_resource(dev, res);
+       if (IS_ERR(base))
+               return PTR_ERR(base);
+
+       num_clks = AGILEX_NUM_CLKS;
+
+       clk_data = devm_kzalloc(dev, struct_size(clk_data, clk_data.hws,
+                               num_clks), GFP_KERNEL);
+       if (!clk_data)
+               return -ENOMEM;
+
+       for (i = 0; i < num_clks; i++)
+               clk_data->clk_data.hws[i] = ERR_PTR(-ENOENT);
 
-       clk_data = __socfpga_agilex_clk_init(pdev, AGILEX_NUM_CLKS);
-       if (IS_ERR(clk_data))
-               return PTR_ERR(clk_data);
+       clk_data->base = base;
+       clk_data->clk_data.num = num_clks;
 
        n5x_clk_register_pll(agilex_pll_clks, ARRAY_SIZE(agilex_pll_clks), clk_data);
 
@@ -492,6 +498,7 @@ static int n5x_clkmgr_init(struct platform_device *pdev)
 
        agilex_clk_register_gate(agilex_gate_clks, ARRAY_SIZE(agilex_gate_clks),
                              clk_data);
+       of_clk_add_hw_provider(np, of_clk_hw_onecell_get, &clk_data->clk_data);
        return 0;
 }
 

diff --git a/drivers/clk/socfpga/clk-gate-a10.c b/drivers/clk/socfpga/clk-gate-a10.c
index cd5df91..738c533 100644 (file)
--- a/drivers/clk/socfpga/clk-gate-a10.c
+++ b/drivers/clk/socfpga/clk-gate-a10.c
@@ -98,7 +98,7 @@ static void __init __socfpga_gate_init(struct device_node *node,
        u32 div_reg[3];
        u32 clk_phase[2];
        u32 fixed_div;
-       struct clk *clk;
+       struct clk_hw *hw_clk;
        struct socfpga_gate_clk *socfpga_clk;
        const char *clk_name = node->name;
        const char *parent_name[SOCFPGA_MAX_PARENTS];
@@ -146,6 +146,7 @@ static void __init __socfpga_gate_init(struct device_node *node,
                if (IS_ERR(socfpga_clk->sys_mgr_base_addr)) {
                        pr_err("%s: failed to find altr,sys-mgr regmap!\n",
                                        __func__);
+                       kfree(socfpga_clk);
                        return;
                }
        }
@@ -159,13 +160,13 @@ static void __init __socfpga_gate_init(struct device_node *node,
        init.num_parents = of_clk_parent_fill(node, parent_name, SOCFPGA_MAX_PARENTS);
        init.parent_names = parent_name;
        socfpga_clk->hw.hw.init = &init;
+       hw_clk = &socfpga_clk->hw.hw;
 
-       clk = clk_register(NULL, &socfpga_clk->hw.hw);
-       if (WARN_ON(IS_ERR(clk))) {
+       if (clk_hw_register(NULL, hw_clk)) {
                kfree(socfpga_clk);
                return;
        }
-       rc = of_clk_add_provider(node, of_clk_src_simple_get, clk);
+       rc = of_clk_add_provider(node, of_clk_src_simple_get, hw_clk);
        if (WARN_ON(rc))
                return;
 }

diff --git a/drivers/clk/socfpga/clk-gate-s10.c b/drivers/clk/socfpga/clk-gate-s10.c
index 083b2ec..b84f262 100644 (file)
--- a/drivers/clk/socfpga/clk-gate-s10.c
+++ b/drivers/clk/socfpga/clk-gate-s10.c
@@ -31,7 +31,7 @@ static unsigned long socfpga_dbg_clk_recalc_rate(struct clk_hw *hwclk,
                                                  unsigned long parent_rate)
 {
        struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk);
-       u32 div = 1, val;
+       u32 div, val;
 
        val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift;
        val &= GENMASK(socfpgaclk->width - 1, 0);
@@ -65,12 +65,13 @@ static const struct clk_ops dbgclk_ops = {
        .get_parent = socfpga_gate_get_parent,
 };
 
-struct clk *s10_register_gate(const struct stratix10_gate_clock *clks, void __iomem *regbase)
+struct clk_hw *s10_register_gate(const struct stratix10_gate_clock *clks, void __iomem *regbase)
 {
-       struct clk *clk;
+       struct clk_hw *hw_clk;
        struct socfpga_gate_clk *socfpga_clk;
        struct clk_init_data init;
        const char *parent_name = clks->parent_name;
+       int ret;
 
        socfpga_clk = kzalloc(sizeof(*socfpga_clk), GFP_KERNEL);
        if (!socfpga_clk)
@@ -112,10 +113,12 @@ struct clk *s10_register_gate(const struct stratix10_gate_clock *clks, void __io
                init.parent_data = clks->parent_data;
        socfpga_clk->hw.hw.init = &init;
 
-       clk = clk_register(NULL, &socfpga_clk->hw.hw);
-       if (WARN_ON(IS_ERR(clk))) {
+       hw_clk = &socfpga_clk->hw.hw;
+
+       ret = clk_hw_register(NULL, &socfpga_clk->hw.hw);
+       if (ret) {
                kfree(socfpga_clk);
-               return NULL;
+               return ERR_PTR(ret);
        }
-       return clk;
+       return hw_clk;
 }

diff --git a/drivers/clk/socfpga/clk-gate.c b/drivers/clk/socfpga/clk-gate.c
index cf94a12..1ec9678 100644 (file)
--- a/drivers/clk/socfpga/clk-gate.c
+++ b/drivers/clk/socfpga/clk-gate.c
@@ -174,13 +174,14 @@ void __init socfpga_gate_init(struct device_node *node)
        u32 div_reg[3];
        u32 clk_phase[2];
        u32 fixed_div;
-       struct clk *clk;
+       struct clk_hw *hw_clk;
        struct socfpga_gate_clk *socfpga_clk;
        const char *clk_name = node->name;
        const char *parent_name[SOCFPGA_MAX_PARENTS];
        struct clk_init_data init;
        struct clk_ops *ops;
        int rc;
+       int err;
 
        socfpga_clk = kzalloc(sizeof(*socfpga_clk), GFP_KERNEL);
        if (WARN_ON(!socfpga_clk))
@@ -238,12 +239,14 @@ void __init socfpga_gate_init(struct device_node *node)
        init.parent_names = parent_name;
        socfpga_clk->hw.hw.init = &init;
 
-       clk = clk_register(NULL, &socfpga_clk->hw.hw);
-       if (WARN_ON(IS_ERR(clk))) {
+       hw_clk = &socfpga_clk->hw.hw;
+
+       err = clk_hw_register(NULL, hw_clk);
+       if (err) {
                kfree(socfpga_clk);
                return;
        }
-       rc = of_clk_add_provider(node, of_clk_src_simple_get, clk);
+       rc = of_clk_add_provider(node, of_clk_src_simple_get, hw_clk);
        if (WARN_ON(rc))
                return;
 }

diff --git a/drivers/clk/socfpga/clk-periph-a10.c b/drivers/clk/socfpga/clk-periph-a10.c
index 3e0c557..b9cdde4 100644 (file)
--- a/drivers/clk/socfpga/clk-periph-a10.c
+++ b/drivers/clk/socfpga/clk-periph-a10.c
@@ -61,7 +61,7 @@ static __init void __socfpga_periph_init(struct device_node *node,
        const struct clk_ops *ops)
 {
        u32 reg;
-       struct clk *clk;
+       struct clk_hw *hw_clk;
        struct socfpga_periph_clk *periph_clk;
        const char *clk_name = node->name;
        const char *parent_name[SOCFPGA_MAX_PARENTS];
@@ -104,12 +104,13 @@ static __init void __socfpga_periph_init(struct device_node *node,
 
        periph_clk->hw.hw.init = &init;
 
-       clk = clk_register(NULL, &periph_clk->hw.hw);
-       if (WARN_ON(IS_ERR(clk))) {
+       hw_clk = &periph_clk->hw.hw;
+
+       if (clk_hw_register(NULL, hw_clk)) {
                kfree(periph_clk);
                return;
        }
-       rc = of_clk_add_provider(node, of_clk_src_simple_get, clk);
+       rc = of_clk_add_provider(node, of_clk_src_simple_get, hw_clk);
        if (rc < 0) {
                pr_err("Could not register clock provider for node:%s\n",
                       clk_name);
@@ -119,7 +120,7 @@ static __init void __socfpga_periph_init(struct device_node *node,
        return;
 
 err_clk:
-       clk_unregister(clk);
+       clk_hw_unregister(hw_clk);
 }
 
 void __init socfpga_a10_periph_init(struct device_node *node)

diff --git a/drivers/clk/socfpga/clk-periph-s10.c b/drivers/clk/socfpga/clk-periph-s10.c
index 0ff2b9d..e5a5fef 100644 (file)
--- a/drivers/clk/socfpga/clk-periph-s10.c
+++ b/drivers/clk/socfpga/clk-periph-s10.c
@@ -93,14 +93,15 @@ static const struct clk_ops peri_cnt_clk_ops = {
        .get_parent = clk_periclk_get_parent,
 };
 
-struct clk *s10_register_periph(const struct stratix10_perip_c_clock *clks,
+struct clk_hw *s10_register_periph(const struct stratix10_perip_c_clock *clks,
                                void __iomem *reg)
 {
-       struct clk *clk;
+       struct clk_hw *hw_clk;
        struct socfpga_periph_clk *periph_clk;
        struct clk_init_data init;
        const char *name = clks->name;
        const char *parent_name = clks->parent_name;
+       int ret;
 
        periph_clk = kzalloc(sizeof(*periph_clk), GFP_KERNEL);
        if (WARN_ON(!periph_clk))
@@ -118,23 +119,25 @@ struct clk *s10_register_periph(const struct stratix10_perip_c_clock *clks,
                init.parent_data = clks->parent_data;
 
        periph_clk->hw.hw.init = &init;
+       hw_clk = &periph_clk->hw.hw;
 
-       clk = clk_register(NULL, &periph_clk->hw.hw);
-       if (WARN_ON(IS_ERR(clk))) {
+       ret = clk_hw_register(NULL, hw_clk);
+       if (ret) {
                kfree(periph_clk);
-               return NULL;
+               return ERR_PTR(ret);
        }
-       return clk;
+       return hw_clk;
 }
 
-struct clk *n5x_register_periph(const struct n5x_perip_c_clock *clks,
+struct clk_hw *n5x_register_periph(const struct n5x_perip_c_clock *clks,
                                void __iomem *regbase)
 {
-       struct clk *clk;
+       struct clk_hw *hw_clk;
        struct socfpga_periph_clk *periph_clk;
        struct clk_init_data init;
        const char *name = clks->name;
        const char *parent_name = clks->parent_name;
+       int ret;
 
        periph_clk = kzalloc(sizeof(*periph_clk), GFP_KERNEL);
        if (WARN_ON(!periph_clk))
@@ -151,23 +154,25 @@ struct clk *n5x_register_periph(const struct n5x_perip_c_clock *clks,
        init.parent_names = parent_name ? &parent_name : NULL;
 
        periph_clk->hw.hw.init = &init;
+       hw_clk = &periph_clk->hw.hw;
 
-       clk = clk_register(NULL, &periph_clk->hw.hw);
-       if (WARN_ON(IS_ERR(clk))) {
+       ret = clk_hw_register(NULL, hw_clk);
+       if (ret) {
                kfree(periph_clk);
-               return NULL;
+               return ERR_PTR(ret);
        }
-       return clk;
+       return hw_clk;
 }
 
-struct clk *s10_register_cnt_periph(const struct stratix10_perip_cnt_clock *clks,
+struct clk_hw *s10_register_cnt_periph(const struct stratix10_perip_cnt_clock *clks,
                                    void __iomem *regbase)
 {
-       struct clk *clk;
+       struct clk_hw *hw_clk;
        struct socfpga_periph_clk *periph_clk;
        struct clk_init_data init;
        const char *name = clks->name;
        const char *parent_name = clks->parent_name;
+       int ret;
 
        periph_clk = kzalloc(sizeof(*periph_clk), GFP_KERNEL);
        if (WARN_ON(!periph_clk))
@@ -195,11 +200,12 @@ struct clk *s10_register_cnt_periph(const struct stratix10_perip_cnt_clock *clks
                init.parent_data = clks->parent_data;
 
        periph_clk->hw.hw.init = &init;
+       hw_clk = &periph_clk->hw.hw;
 
-       clk = clk_register(NULL, &periph_clk->hw.hw);
-       if (WARN_ON(IS_ERR(clk))) {
+       ret = clk_hw_register(NULL, hw_clk);
+       if (ret) {
                kfree(periph_clk);
-               return NULL;
+               return ERR_PTR(ret);
        }
-       return clk;
+       return hw_clk;
 }

diff --git a/drivers/clk/socfpga/clk-periph.c b/drivers/clk/socfpga/clk-periph.c
index 5e0c4b4..43707e2 100644 (file)
--- a/drivers/clk/socfpga/clk-periph.c
+++ b/drivers/clk/socfpga/clk-periph.c
@@ -51,7 +51,7 @@ static __init void __socfpga_periph_init(struct device_node *node,
        const struct clk_ops *ops)
 {
        u32 reg;
-       struct clk *clk;
+       struct clk_hw *hw_clk;
        struct socfpga_periph_clk *periph_clk;
        const char *clk_name = node->name;
        const char *parent_name[SOCFPGA_MAX_PARENTS];
@@ -94,13 +94,13 @@ static __init void __socfpga_periph_init(struct device_node *node,
        init.parent_names = parent_name;
 
        periph_clk->hw.hw.init = &init;
+       hw_clk = &periph_clk->hw.hw;
 
-       clk = clk_register(NULL, &periph_clk->hw.hw);
-       if (WARN_ON(IS_ERR(clk))) {
+       if (clk_hw_register(NULL, hw_clk)) {
                kfree(periph_clk);
                return;
        }
-       rc = of_clk_add_provider(node, of_clk_src_simple_get, clk);
+       rc = of_clk_add_provider(node, of_clk_src_simple_get, hw_clk);
 }
 
 void __init socfpga_periph_init(struct device_node *node)

diff --git a/drivers/clk/socfpga/clk-pll-a10.c b/drivers/clk/socfpga/clk-pll-a10.c
index 3338f05..bee0f7d 100644 (file)
--- a/drivers/clk/socfpga/clk-pll-a10.c
+++ b/drivers/clk/socfpga/clk-pll-a10.c
@@ -63,11 +63,11 @@ static const struct clk_ops clk_pll_ops = {
        .get_parent = clk_pll_get_parent,
 };
 
-static struct clk * __init __socfpga_pll_init(struct device_node *node,
+static struct clk_hw * __init __socfpga_pll_init(struct device_node *node,
        const struct clk_ops *ops)
 {
        u32 reg;
-       struct clk *clk;
+       struct clk_hw *hw_clk;
        struct socfpga_pll *pll_clk;
        const char *clk_name = node->name;
        const char *parent_name[SOCFGPA_MAX_PARENTS];
@@ -101,14 +101,14 @@ static struct clk * __init __socfpga_pll_init(struct device_node *node,
        pll_clk->hw.hw.init = &init;
 
        pll_clk->hw.bit_idx = SOCFPGA_PLL_EXT_ENA;
+       hw_clk = &pll_clk->hw.hw;
 
-       clk = clk_register(NULL, &pll_clk->hw.hw);
-       if (WARN_ON(IS_ERR(clk))) {
+       if (clk_hw_register(NULL, hw_clk)) {
                kfree(pll_clk);
                return NULL;
        }
-       of_clk_add_provider(node, of_clk_src_simple_get, clk);
-       return clk;
+       of_clk_add_provider(node, of_clk_src_simple_get, hw_clk);
+       return hw_clk;
 }
 
 void __init socfpga_a10_pll_init(struct device_node *node)

diff --git a/drivers/clk/socfpga/clk-pll-s10.c b/drivers/clk/socfpga/clk-pll-s10.c
index f6f66e0..70076a8 100644 (file)
--- a/drivers/clk/socfpga/clk-pll-s10.c
+++ b/drivers/clk/socfpga/clk-pll-s10.c
@@ -107,7 +107,7 @@ static unsigned long clk_boot_clk_recalc_rate(struct clk_hw *hwclk,
                                         unsigned long parent_rate)
 {
        struct socfpga_pll *socfpgaclk = to_socfpga_clk(hwclk);
-       u32 div = 1;
+       u32 div;
 
        div = ((readl(socfpgaclk->hw.reg) &
                SWCTRLBTCLKSEL_MASK) >>
@@ -187,13 +187,14 @@ static const struct clk_ops clk_boot_ops = {
        .prepare = clk_pll_prepare,
 };
 
-struct clk *s10_register_pll(const struct stratix10_pll_clock *clks,
+struct clk_hw *s10_register_pll(const struct stratix10_pll_clock *clks,
                             void __iomem *reg)
 {
-       struct clk *clk;
+       struct clk_hw *hw_clk;
        struct socfpga_pll *pll_clk;
        struct clk_init_data init;
        const char *name = clks->name;
+       int ret;
 
        pll_clk = kzalloc(sizeof(*pll_clk), GFP_KERNEL);
        if (WARN_ON(!pll_clk))
@@ -216,21 +217,24 @@ struct clk *s10_register_pll(const struct stratix10_pll_clock *clks,
 
        pll_clk->hw.bit_idx = SOCFPGA_PLL_POWER;
 
-       clk = clk_register(NULL, &pll_clk->hw.hw);
-       if (WARN_ON(IS_ERR(clk))) {
+       hw_clk = &pll_clk->hw.hw;
+
+       ret = clk_hw_register(NULL, hw_clk);
+       if (ret) {
                kfree(pll_clk);
-               return NULL;
+               return ERR_PTR(ret);
        }
-       return clk;
+       return hw_clk;
 }
 
-struct clk *agilex_register_pll(const struct stratix10_pll_clock *clks,
+struct clk_hw *agilex_register_pll(const struct stratix10_pll_clock *clks,
                                void __iomem *reg)
 {
-       struct clk *clk;
+       struct clk_hw *hw_clk;
        struct socfpga_pll *pll_clk;
        struct clk_init_data init;
        const char *name = clks->name;
+       int ret;
 
        pll_clk = kzalloc(sizeof(*pll_clk), GFP_KERNEL);
        if (WARN_ON(!pll_clk))
@@ -252,22 +256,24 @@ struct clk *agilex_register_pll(const struct stratix10_pll_clock *clks,
        pll_clk->hw.hw.init = &init;
 
        pll_clk->hw.bit_idx = SOCFPGA_PLL_POWER;
+       hw_clk = &pll_clk->hw.hw;
 
-       clk = clk_register(NULL, &pll_clk->hw.hw);
-       if (WARN_ON(IS_ERR(clk))) {
+       ret = clk_hw_register(NULL, hw_clk);
+       if (ret) {
                kfree(pll_clk);
-               return NULL;
+               return ERR_PTR(ret);
        }
-       return clk;
+       return hw_clk;
 }
 
-struct clk *n5x_register_pll(const struct stratix10_pll_clock *clks,
+struct clk_hw *n5x_register_pll(const struct stratix10_pll_clock *clks,
                             void __iomem *reg)
 {
-       struct clk *clk;
+       struct clk_hw *hw_clk;
        struct socfpga_pll *pll_clk;
        struct clk_init_data init;
        const char *name = clks->name;
+       int ret;
 
        pll_clk = kzalloc(sizeof(*pll_clk), GFP_KERNEL);
        if (WARN_ON(!pll_clk))
@@ -289,11 +295,12 @@ struct clk *n5x_register_pll(const struct stratix10_pll_clock *clks,
        pll_clk->hw.hw.init = &init;
 
        pll_clk->hw.bit_idx = SOCFPGA_PLL_POWER;
+       hw_clk = &pll_clk->hw.hw;
 
-       clk = clk_register(NULL, &pll_clk->hw.hw);
-       if (WARN_ON(IS_ERR(clk))) {
+       ret = clk_hw_register(NULL, hw_clk);
+       if (ret) {
                kfree(pll_clk);
-               return NULL;
+               return ERR_PTR(ret);
        }
-       return clk;
+       return hw_clk;
 }

diff --git a/drivers/clk/socfpga/clk-pll.c b/drivers/clk/socfpga/clk-pll.c
index 3cf99df..dcb573d 100644 (file)
--- a/drivers/clk/socfpga/clk-pll.c
+++ b/drivers/clk/socfpga/clk-pll.c
@@ -70,16 +70,18 @@ static const struct clk_ops clk_pll_ops = {
        .get_parent = clk_pll_get_parent,
 };
 
-static __init struct clk *__socfpga_pll_init(struct device_node *node,
+static __init struct clk_hw *__socfpga_pll_init(struct device_node *node,
        const struct clk_ops *ops)
 {
        u32 reg;
-       struct clk *clk;
+       struct clk_hw *hw_clk;
        struct socfpga_pll *pll_clk;
        const char *clk_name = node->name;
        const char *parent_name[SOCFPGA_MAX_PARENTS];
        struct clk_init_data init;
        struct device_node *clkmgr_np;
+       int rc;
+       int err;
 
        of_property_read_u32(node, "reg", &reg);
 
@@ -105,13 +107,15 @@ static __init struct clk *__socfpga_pll_init(struct device_node *node,
 
        pll_clk->hw.bit_idx = SOCFPGA_PLL_EXT_ENA;
 
-       clk = clk_register(NULL, &pll_clk->hw.hw);
-       if (WARN_ON(IS_ERR(clk))) {
+       hw_clk = &pll_clk->hw.hw;
+
+       err = clk_hw_register(NULL, hw_clk);
+       if (err) {
                kfree(pll_clk);
-               return NULL;
+               return ERR_PTR(err);
        }
-       of_clk_add_provider(node, of_clk_src_simple_get, clk);
-       return clk;
+       rc = of_clk_add_provider(node, of_clk_src_simple_get, hw_clk);
+       return hw_clk;
 }
 
 void __init socfpga_pll_init(struct device_node *node)

diff --git a/drivers/clk/socfpga/clk-s10.c b/drivers/clk/socfpga/clk-s10.c
index 661a8e9..f0bd771 100644 (file)
--- a/drivers/clk/socfpga/clk-s10.c
+++ b/drivers/clk/socfpga/clk-s10.c
@@ -274,18 +274,18 @@ static const struct stratix10_gate_clock s10_gate_clks[] = {
 static int s10_clk_register_c_perip(const struct stratix10_perip_c_clock *clks,
                                    int nums, struct stratix10_clock_data *data)
 {
-       struct clk *clk;
+       struct clk_hw *hw_clk;
        void __iomem *base = data->base;
        int i;
 
        for (i = 0; i < nums; i++) {
-               clk = s10_register_periph(&clks[i], base);
-               if (IS_ERR(clk)) {
+               hw_clk = s10_register_periph(&clks[i], base);
+               if (IS_ERR(hw_clk)) {
                        pr_err("%s: failed to register clock %s\n",
                               __func__, clks[i].name);
                        continue;
                }
-               data->clk_data.clks[clks[i].id] = clk;
+               data->clk_data.hws[clks[i].id] = hw_clk;
        }
        return 0;
 }
@@ -293,18 +293,18 @@ static int s10_clk_register_c_perip(const struct stratix10_perip_c_clock *clks,
 static int s10_clk_register_cnt_perip(const struct stratix10_perip_cnt_clock *clks,
                                      int nums, struct stratix10_clock_data *data)
 {
-       struct clk *clk;
+       struct clk_hw *hw_clk;
        void __iomem *base = data->base;
        int i;
 
        for (i = 0; i < nums; i++) {
-               clk = s10_register_cnt_periph(&clks[i], base);
-               if (IS_ERR(clk)) {
+               hw_clk = s10_register_cnt_periph(&clks[i], base);
+               if (IS_ERR(hw_clk)) {
                        pr_err("%s: failed to register clock %s\n",
                               __func__, clks[i].name);
                        continue;
                }
-               data->clk_data.clks[clks[i].id] = clk;
+               data->clk_data.hws[clks[i].id] = hw_clk;
        }
 
        return 0;
@@ -313,18 +313,18 @@ static int s10_clk_register_cnt_perip(const struct stratix10_perip_cnt_clock *cl
 static int s10_clk_register_gate(const struct stratix10_gate_clock *clks,
                                 int nums, struct stratix10_clock_data *data)
 {
-       struct clk *clk;
+       struct clk_hw *hw_clk;
        void __iomem *base = data->base;
        int i;
 
        for (i = 0; i < nums; i++) {
-               clk = s10_register_gate(&clks[i], base);
-               if (IS_ERR(clk)) {
+               hw_clk = s10_register_gate(&clks[i], base);
+               if (IS_ERR(hw_clk)) {
                        pr_err("%s: failed to register clock %s\n",
                               __func__, clks[i].name);
                        continue;
                }
-               data->clk_data.clks[clks[i].id] = clk;
+               data->clk_data.hws[clks[i].id] = hw_clk;
        }
 
        return 0;
@@ -333,62 +333,50 @@ static int s10_clk_register_gate(const struct stratix10_gate_clock *clks,
 static int s10_clk_register_pll(const struct stratix10_pll_clock *clks,
                                 int nums, struct stratix10_clock_data *data)
 {
-       struct clk *clk;
+       struct clk_hw *hw_clk;
        void __iomem *base = data->base;
        int i;
 
        for (i = 0; i < nums; i++) {
-               clk = s10_register_pll(&clks[i], base);
-               if (IS_ERR(clk)) {
+               hw_clk = s10_register_pll(&clks[i], base);
+               if (IS_ERR(hw_clk)) {
                        pr_err("%s: failed to register clock %s\n",
                               __func__, clks[i].name);
                        continue;
                }
-               data->clk_data.clks[clks[i].id] = clk;
+               data->clk_data.hws[clks[i].id] = hw_clk;
        }
 
        return 0;
 }
 
-static struct stratix10_clock_data *__socfpga_s10_clk_init(struct platform_device *pdev,
-                                                   int nr_clks)
+static int s10_clkmgr_init(struct platform_device *pdev)
 {
        struct device_node *np = pdev->dev.of_node;
        struct device *dev = &pdev->dev;
        struct stratix10_clock_data *clk_data;
-       struct clk **clk_table;
        struct resource *res;
        void __iomem *base;
+       int i, num_clks;
 
        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
        base = devm_ioremap_resource(dev, res);
        if (IS_ERR(base)) {
                pr_err("%s: failed to map clock registers\n", __func__);
-               return ERR_CAST(base);
+               return PTR_ERR(base);
        }
 
-       clk_data = devm_kzalloc(dev, sizeof(*clk_data), GFP_KERNEL);
+       num_clks = STRATIX10_NUM_CLKS;
+       clk_data = devm_kzalloc(dev, struct_size(clk_data, clk_data.hws,
+                                                num_clks), GFP_KERNEL);
        if (!clk_data)
-               return ERR_PTR(-ENOMEM);
+               return -ENOMEM;
 
-       clk_data->base = base;
-       clk_table = devm_kcalloc(dev, nr_clks, sizeof(*clk_table), GFP_KERNEL);
-       if (!clk_table)
-               return ERR_PTR(-ENOMEM);
-
-       clk_data->clk_data.clks = clk_table;
-       clk_data->clk_data.clk_num = nr_clks;
-       of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data->clk_data);
-       return clk_data;
-}
+       for (i = 0; i < num_clks; i++)
+               clk_data->clk_data.hws[i] = ERR_PTR(-ENOENT);
 
-static int s10_clkmgr_init(struct platform_device *pdev)
-{
-       struct stratix10_clock_data *clk_data;
-
-       clk_data = __socfpga_s10_clk_init(pdev, STRATIX10_NUM_CLKS);
-       if (IS_ERR(clk_data))
-               return PTR_ERR(clk_data);
+       clk_data->base = base;
+       clk_data->clk_data.num = num_clks;
 
        s10_clk_register_pll(s10_pll_clks, ARRAY_SIZE(s10_pll_clks), clk_data);
 
@@ -401,6 +389,8 @@ static int s10_clkmgr_init(struct platform_device *pdev)
 
        s10_clk_register_gate(s10_gate_clks, ARRAY_SIZE(s10_gate_clks),
                              clk_data);
+
+       of_clk_add_hw_provider(np, of_clk_hw_onecell_get, &clk_data->clk_data);
        return 0;
 }
 

diff --git a/drivers/clk/socfpga/stratix10-clk.h b/drivers/clk/socfpga/stratix10-clk.h
index 420deed..61eaf3a 100644 (file)
--- a/drivers/clk/socfpga/stratix10-clk.h
+++ b/drivers/clk/socfpga/stratix10-clk.h
@@ -7,7 +7,7 @@
 #define        __STRATIX10_CLK_H
 
 struct stratix10_clock_data {
-       struct clk_onecell_data clk_data;
+       struct clk_hw_onecell_data      clk_data;
        void __iomem            *base;
 };
 
@@ -71,18 +71,18 @@ struct stratix10_gate_clock {
        u8                      fixed_div;
 };
 
-struct clk *s10_register_pll(const struct stratix10_pll_clock *,
-                            void __iomem *);
-struct clk *agilex_register_pll(const struct stratix10_pll_clock *,
-                               void __iomem *);
-struct clk *n5x_register_pll(const struct stratix10_pll_clock *clks,
+struct clk_hw *s10_register_pll(const struct stratix10_pll_clock *clks,
                             void __iomem *reg);
-struct clk *s10_register_periph(const struct stratix10_perip_c_clock *,
+struct clk_hw *agilex_register_pll(const struct stratix10_pll_clock *clks,
                                void __iomem *reg);
-struct clk *n5x_register_periph(const struct n5x_perip_c_clock *clks,
+struct clk_hw *n5x_register_pll(const struct stratix10_pll_clock *clks,
+                            void __iomem *reg);
+struct clk_hw *s10_register_periph(const struct stratix10_perip_c_clock *clks,
+                               void __iomem *reg);
+struct clk_hw *n5x_register_periph(const struct n5x_perip_c_clock *clks,
                                void __iomem *reg);
-struct clk *s10_register_cnt_periph(const struct stratix10_perip_cnt_clock *,
-                                   void __iomem *);
-struct clk *s10_register_gate(const struct stratix10_gate_clock *,
-                             void __iomem *);
+struct clk_hw *s10_register_cnt_periph(const struct stratix10_perip_cnt_clock *clks,
+                                   void __iomem *reg);
+struct clk_hw *s10_register_gate(const struct stratix10_gate_clock *clks,
+                             void __iomem *reg);
 #endif /* __STRATIX10_CLK_H */

diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c b/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c
index 0e36ca3..a774942 100644 (file)
--- a/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c
@@ -40,18 +40,29 @@ static SUNXI_CCU_NKMP_WITH_GATE_LOCK(pll_cpu_clk, "pll-cpu",
  * the base (2x, 4x and 8x), and one variable divider (the one true
  * pll audio).
  *
- * We don't have any need for the variable divider for now, so we just
- * hardcode it to match with the clock names
+ * With sigma-delta modulation for fractional-N on the audio PLL,
+ * we have to use specific dividers. This means the variable divider
+ * can no longer be used, as the audio codec requests the exact clock
+ * rates we support through this mechanism. So we now hard code the
+ * variable divider to 1. This means the clock rates will no longer
+ * match the clock names.
  */
 #define SUN8I_V3S_PLL_AUDIO_REG        0x008
 
-static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
-                                  "osc24M", 0x008,
-                                  8, 7,        /* N */
-                                  0, 5,        /* M */
-                                  BIT(31),     /* gate */
-                                  BIT(28),     /* lock */
-                                  0);
+static struct ccu_sdm_setting pll_audio_sdm_table[] = {
+       { .rate = 22579200, .pattern = 0xc0010d84, .m = 8, .n = 7 },
+       { .rate = 24576000, .pattern = 0xc000ac02, .m = 14, .n = 14 },
+};
+
+static SUNXI_CCU_NM_WITH_SDM_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
+                                      "osc24M", 0x008,
+                                      8, 7,    /* N */
+                                      0, 5,    /* M */
+                                      pll_audio_sdm_table, BIT(24),
+                                      0x284, BIT(31),
+                                      BIT(31), /* gate */
+                                      BIT(28), /* lock */
+                                      CLK_SET_RATE_UNGATE);
 
 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video_clk, "pll-video",
                                        "osc24M", 0x0010,
@@ -524,10 +535,10 @@ static struct ccu_common *sun8i_v3_ccu_clks[] = {
        &mipi_csi_clk.common,
 };
 
-/* We hardcode the divider to 4 for now */
+/* We hardcode the divider to 1 for SDM support */
 static CLK_FIXED_FACTOR_HWS(pll_audio_clk, "pll-audio",
                            clk_parent_pll_audio,
-                           4, 1, CLK_SET_RATE_PARENT);
+                           1, 1, CLK_SET_RATE_PARENT);
 static CLK_FIXED_FACTOR_HWS(pll_audio_2x_clk, "pll-audio-2x",
                            clk_parent_pll_audio,
                            2, 1, CLK_SET_RATE_PARENT);

diff --git a/drivers/clk/sunxi/clk-sun6i-ar100.c b/drivers/clk/sunxi/clk-sun6i-ar100.c
index e1b7d09..54babc2 100644 (file)
--- a/drivers/clk/sunxi/clk-sun6i-ar100.c
+++ b/drivers/clk/sunxi/clk-sun6i-ar100.c
@@ -16,7 +16,7 @@
 
 #include "clk-factors.h"
 
-/**
+/*
  * sun6i_get_ar100_factors - Calculates factors p, m for AR100
  *
  * AR100 rate is calculated as follows

diff --git a/drivers/clk/sunxi/clk-sun9i-core.c b/drivers/clk/sunxi/clk-sun9i-core.c
index 305ad78..d93c7a5 100644 (file)
--- a/drivers/clk/sunxi/clk-sun9i-core.c
+++ b/drivers/clk/sunxi/clk-sun9i-core.c
@@ -14,7 +14,7 @@
 #include "clk-factors.h"
 
 
-/**
+/*
  * sun9i_a80_get_pll4_factors() - calculates n, p, m factors for PLL4
  * PLL4 rate is calculated as follows
  * rate = (parent_rate * n >> p) / (m + 1);
@@ -90,7 +90,7 @@ static void __init sun9i_a80_pll4_setup(struct device_node *node)
 CLK_OF_DECLARE(sun9i_a80_pll4, "allwinner,sun9i-a80-pll4-clk", sun9i_a80_pll4_setup);
 
 
-/**
+/*
  * sun9i_a80_get_gt_factors() - calculates m factor for GT
  * GT rate is calculated as follows
  * rate = parent_rate / (m + 1);
@@ -145,7 +145,7 @@ static void __init sun9i_a80_gt_setup(struct device_node *node)
 CLK_OF_DECLARE(sun9i_a80_gt, "allwinner,sun9i-a80-gt-clk", sun9i_a80_gt_setup);
 
 
-/**
+/*
  * sun9i_a80_get_ahb_factors() - calculates p factor for AHB0/1/2
  * AHB rate is calculated as follows
  * rate = parent_rate >> p;
@@ -225,7 +225,7 @@ static void __init sun9i_a80_apb0_setup(struct device_node *node)
 CLK_OF_DECLARE(sun9i_a80_apb0, "allwinner,sun9i-a80-apb0-clk", sun9i_a80_apb0_setup);
 
 
-/**
+/*
  * sun9i_a80_get_apb1_factors() - calculates m, p factors for APB1
  * APB1 rate is calculated as follows
  * rate = (parent_rate >> p) / (m + 1);

diff --git a/drivers/clk/sunxi/clk-usb.c b/drivers/clk/sunxi/clk-usb.c
index d78a784..5460218 100644 (file)
--- a/drivers/clk/sunxi/clk-usb.c
+++ b/drivers/clk/sunxi/clk-usb.c
@@ -15,7 +15,7 @@
 #include <linux/spinlock.h>
 
 
-/**
+/*
  * sunxi_usb_reset... - reset bits in usb clk registers handling
  */