clk: en7523: remove REG_PCIE*_{MEM,MEM_MASK} configuration

REG_PCIE*_MEM and REG_PCIE*_MEM_MASK regs (PBUS_CSR memory region) are not
part of the scu block on the EN7581 SoC and they are used to select the
PCIE ports on the PBUS, so remove this configuration from the clock driver
and set these registers in the PCIE host driver instead.
This patch does not introduce any backward incompatibility since the dts
for EN7581 SoC is not upstream yet.

Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
Link: https://lore.kernel.org/r/20241112-clk-en7581-syscon-v2-2-8ada5e394ae4@kernel.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

diff --git a/drivers/clk/clk-en7523.c b/drivers/clk/clk-en7523.c
index 22fbea6..ec67168 100644 (file)
--- a/drivers/clk/clk-en7523.c
+++ b/drivers/clk/clk-en7523.c
@@ -31,12 +31,6 @@
 #define   REG_RESET_CONTROL_PCIE1      BIT(27)
 #define   REG_RESET_CONTROL_PCIE2      BIT(26)
 /* EN7581 */
-#define REG_PCIE0_MEM                  0x00
-#define REG_PCIE0_MEM_MASK             0x04
-#define REG_PCIE1_MEM                  0x08
-#define REG_PCIE1_MEM_MASK             0x0c
-#define REG_PCIE2_MEM                  0x10
-#define REG_PCIE2_MEM_MASK             0x14
 #define REG_NP_SCU_PCIC                        0x88
 #define REG_NP_SCU_SSTR                        0x9c
 #define REG_PCIE_XSI0_SEL_MASK         GENMASK(14, 13)
@@ -415,26 +409,14 @@ static void en7581_pci_disable(struct clk_hw *hw)
 static int en7581_clk_hw_init(struct platform_device *pdev,
                              void __iomem *np_base)
 {
-       void __iomem *pb_base;
        u32 val;
 
-       pb_base = devm_platform_ioremap_resource(pdev, 3);
-       if (IS_ERR(pb_base))
-               return PTR_ERR(pb_base);
-
        val = readl(np_base + REG_NP_SCU_SSTR);
        val &= ~(REG_PCIE_XSI0_SEL_MASK | REG_PCIE_XSI1_SEL_MASK);
        writel(val, np_base + REG_NP_SCU_SSTR);
        val = readl(np_base + REG_NP_SCU_PCIC);
        writel(val | 3, np_base + REG_NP_SCU_PCIC);
 
-       writel(0x20000000, pb_base + REG_PCIE0_MEM);
-       writel(0xfc000000, pb_base + REG_PCIE0_MEM_MASK);
-       writel(0x24000000, pb_base + REG_PCIE1_MEM);
-       writel(0xfc000000, pb_base + REG_PCIE1_MEM_MASK);
-       writel(0x28000000, pb_base + REG_PCIE2_MEM);
-       writel(0xfc000000, pb_base + REG_PCIE2_MEM_MASK);
-
        return 0;
 }