pmdomain: mediatek: Add support for MT6735

Add support for SCPSYS power domains of MT6735. All non-CPU power domains
are added except for MD2 (C2K modem), which is left out due to issues
with powering it on.

Signed-off-by: Yassine Oudjana <y.oudjana@protonmail.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20241017085136.68053-3-y.oudjana@protonmail.com
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>

diff --git a/drivers/pmdomain/mediatek/mt6735-pm-domains.h b/drivers/pmdomain/mediatek/mt6735-pm-domains.h
new file mode 100644 (file)
index 0000000..71896be
--- /dev/null
+++ b/drivers/pmdomain/mediatek/mt6735-pm-domains.h
@@ -0,0 +1,96 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __SOC_MEDIATEK_MT6735_PM_DOMAINS_H
+#define __SOC_MEDIATEK_MT6735_PM_DOMAINS_H
+
+#include "mtk-pm-domains.h"
+#include <dt-bindings/power/mediatek,mt6735-power-controller.h>
+
+/*
+ * MT6735 power domain support
+ */
+
+static const struct scpsys_domain_data scpsys_domain_data_mt6735[] = {
+       [MT6735_POWER_DOMAIN_MD1] = {
+               .name = "md1",
+               .sta_mask = PWR_STATUS_MD1,
+               .ctl_offs = SPM_MD1_PWR_CON,
+               .pwr_sta_offs = SPM_PWR_STATUS,
+               .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,
+               .sram_pdn_bits = GENMASK(8, 8),
+               .sram_pdn_ack_bits = 0,
+               .bp_cfg = {
+                       BUS_PROT_INFRA_UPDATE_TOPAXI(MT6735_TOP_AXI_PROT_EN_MD1),
+               },
+       },
+       [MT6735_POWER_DOMAIN_CONN] = {
+               .name = "conn",
+               .sta_mask = PWR_STATUS_CONN,
+               .ctl_offs = SPM_CONN_PWR_CON,
+               .pwr_sta_offs = SPM_PWR_STATUS,
+               .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,
+               .sram_pdn_bits = GENMASK(8, 8),
+               .sram_pdn_ack_bits = 0,
+               .bp_cfg = {
+                       BUS_PROT_INFRA_UPDATE_TOPAXI(MT6735_TOP_AXI_PROT_EN_CONN),
+               },
+       },
+       [MT6735_POWER_DOMAIN_DIS] = {
+               .name = "dis",
+               .sta_mask = PWR_STATUS_DISP,
+               .ctl_offs = SPM_DIS_PWR_CON,
+               .pwr_sta_offs = SPM_PWR_STATUS,
+               .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,
+               .sram_pdn_bits = GENMASK(11, 8),
+               .sram_pdn_ack_bits = GENMASK(12, 12),
+               .bp_cfg = {
+                       BUS_PROT_INFRA_UPDATE_TOPAXI(MT8173_TOP_AXI_PROT_EN_MM_M0),
+               },
+       },
+       [MT6735_POWER_DOMAIN_MFG] = {
+               .name = "mfg",
+               .sta_mask = PWR_STATUS_MFG,
+               .ctl_offs = SPM_MFG_PWR_CON,
+               .pwr_sta_offs = SPM_PWR_STATUS,
+               .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,
+               .sram_pdn_bits = GENMASK(11, 8),
+               .sram_pdn_ack_bits = GENMASK(12, 12),
+               .bp_cfg = {
+                       BUS_PROT_INFRA_UPDATE_TOPAXI(MT8173_TOP_AXI_PROT_EN_MFG_S),
+               },
+       },
+       [MT6735_POWER_DOMAIN_ISP] = {
+               .name = "isp",
+               .sta_mask = PWR_STATUS_ISP,
+               .ctl_offs = SPM_ISP_PWR_CON,
+               .pwr_sta_offs = SPM_PWR_STATUS,
+               .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,
+               .sram_pdn_bits = GENMASK(11, 8),
+               .sram_pdn_ack_bits = GENMASK(13, 12),
+       },
+       [MT6735_POWER_DOMAIN_VDE] = {
+               .name = "vde",
+               .sta_mask = PWR_STATUS_VDEC,
+               .ctl_offs = SPM_VDE_PWR_CON,
+               .pwr_sta_offs = SPM_PWR_STATUS,
+               .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,
+               .sram_pdn_bits = GENMASK(11, 8),
+               .sram_pdn_ack_bits = GENMASK(12, 12),
+       },
+       [MT6735_POWER_DOMAIN_VEN] = {
+               .name = "ven",
+               .sta_mask = BIT(8),
+               .ctl_offs = SPM_VEN_PWR_CON,
+               .pwr_sta_offs = SPM_PWR_STATUS,
+               .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,
+               .sram_pdn_bits = GENMASK(11, 8),
+               .sram_pdn_ack_bits = GENMASK(15, 12),
+       },
+};
+
+static const struct scpsys_soc_data mt6735_scpsys_data = {
+       .domains_data = scpsys_domain_data_mt6735,
+       .num_domains = ARRAY_SIZE(scpsys_domain_data_mt6735),
+};
+
+#endif /* __SOC_MEDIATEK_MT6735_PM_DOMAINS_H */

diff --git a/drivers/pmdomain/mediatek/mtk-pm-domains.c b/drivers/pmdomain/mediatek/mtk-pm-domains.c
index 3580913..b866b00 100644 (file)
--- a/drivers/pmdomain/mediatek/mtk-pm-domains.c
+++ b/drivers/pmdomain/mediatek/mtk-pm-domains.c
@@ -16,6 +16,7 @@
 #include <linux/regulator/consumer.h>
 #include <linux/soc/mediatek/infracfg.h>
 
+#include "mt6735-pm-domains.h"
 #include "mt6795-pm-domains.h"
 #include "mt8167-pm-domains.h"
 #include "mt8173-pm-domains.h"
@@ -608,6 +609,10 @@ static void scpsys_domain_cleanup(struct scpsys *scpsys)
 }
 
 static const struct of_device_id scpsys_of_match[] = {
+       {
+               .compatible = "mediatek,mt6735-power-controller",
+               .data = &mt6735_scpsys_data,
+       },
        {
                .compatible = "mediatek,mt6795-power-controller",
                .data = &mt6795_scpsys_data,

diff --git a/drivers/pmdomain/mediatek/mtk-pm-domains.h b/drivers/pmdomain/mediatek/mtk-pm-domains.h
index aaba5e6..2ac9680 100644 (file)
--- a/drivers/pmdomain/mediatek/mtk-pm-domains.h
+++ b/drivers/pmdomain/mediatek/mtk-pm-domains.h
@@ -21,6 +21,7 @@
 #define SPM_ISP_PWR_CON                        0x0238
 #define SPM_DIS_PWR_CON                        0x023c
 #define SPM_CONN_PWR_CON               0x0280
+#define SPM_MD1_PWR_CON                        0x0284
 #define SPM_VEN2_PWR_CON               0x0298
 #define SPM_AUDIO_PWR_CON              0x029c
 #define SPM_MFG_2D_PWR_CON             0x02c0
@@ -30,6 +31,7 @@
 #define SPM_PWR_STATUS                 0x060c
 #define SPM_PWR_STATUS_2ND             0x0610
 
+#define PWR_STATUS_MD1                 BIT(0)
 #define PWR_STATUS_CONN                        BIT(1)
 #define PWR_STATUS_DISP                        BIT(3)
 #define PWR_STATUS_MFG                 BIT(4)

diff --git a/include/linux/soc/mediatek/infracfg.h b/include/linux/soc/mediatek/infracfg.h
index 6c6cccc..9956e18 100644 (file)
--- a/include/linux/soc/mediatek/infracfg.h
+++ b/include/linux/soc/mediatek/infracfg.h
@@ -434,6 +434,11 @@
 #define MT7622_TOP_AXI_PROT_EN_WB              (BIT(2) | BIT(6) | \
                                                 BIT(7) | BIT(8))
 
+#define MT6735_TOP_AXI_PROT_EN_CONN            (BIT(2) | BIT(8))
+#define MT6735_TOP_AXI_PROT_EN_MD1             (BIT(24) | BIT(25) | \
+                                                BIT(26) | BIT(27) | \
+                                                BIT(28))
+
 #define INFRA_TOPAXI_PROTECTEN                 0x0220
 #define INFRA_TOPAXI_PROTECTSTA1               0x0228
 #define INFRA_TOPAXI_PROTECTEN_SET             0x0260