drm/amd/display: Add renoir hw_seq
authorBhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Wed, 2 Oct 2019 15:54:56 +0000 (11:54 -0400)
committerAlex Deucher <alexander.deucher@amd.com>
Thu, 17 Oct 2019 20:27:34 +0000 (16:27 -0400)
This change adds renoir hw_seq, needed to do renoir
specific hw programing

Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Reviewed-by: Roman Li <Roman.Li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
drivers/gpu/drm/amd/display/dc/dcn21/Makefile
drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hwseq.c [new file with mode: 0644]
drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hwseq.h [new file with mode: 0644]
drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h

index ac04d77..32d145a 100644 (file)
@@ -679,6 +679,7 @@ struct dce_hwseq_registers {
        HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN17_PGFSM_PWR_STATUS, mask_sh), \
        HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN18_PGFSM_PWR_STATUS, mask_sh), \
        HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \
+       HWSEQ_LVTMA_MASK_SH_LIST(mask_sh), \
        HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh), \
        HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh)
 #endif
index 32bf6cf..df1be8a 100644 (file)
@@ -670,6 +670,10 @@ static void dcn10_bios_golden_init(struct dc *dc)
        int i;
        bool allow_self_fresh_force_enable = true;
 
+#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
+       if (dc->hwss.s0i3_golden_init_wa && dc->hwss.s0i3_golden_init_wa(dc))
+               return;
+#endif
        if (dc->res_pool->hubbub->funcs->is_allow_self_refresh_enabled)
                allow_self_fresh_force_enable =
                                dc->res_pool->hubbub->funcs->is_allow_self_refresh_enabled(dc->res_pool->hubbub);
index b2b3909..5b8f42a 100644 (file)
@@ -1,7 +1,7 @@
 #
 # Makefile for DCN21.
 
-DCN21 = dcn21_hubp.o dcn21_hubbub.o dcn21_resource.o
+DCN21 = dcn21_hubp.o dcn21_hubbub.o dcn21_resource.o dcn21_hwseq.o
 
 CFLAGS_dcn21_resource.o := -mhard-float -msse -mpreferred-stack-boundary=4
 
diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hwseq.c
new file mode 100644 (file)
index 0000000..b25215c
--- /dev/null
@@ -0,0 +1,122 @@
+/*
+ * Copyright 2016 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "dm_services.h"
+#include "dm_helpers.h"
+#include "core_types.h"
+#include "resource.h"
+#include "dce/dce_hwseq.h"
+#include "dcn20/dcn20_hwseq.h"
+#include "vmid.h"
+#include "reg_helper.h"
+#include "hw/clk_mgr.h"
+
+
+#define DC_LOGGER_INIT(logger)
+
+#define CTX \
+       hws->ctx
+#define REG(reg)\
+       hws->regs->reg
+
+#undef FN
+#define FN(reg_name, field_name) \
+       hws->shifts->field_name, hws->masks->field_name
+
+/* Temporary read settings, future will get values from kmd directly */
+static void mmhub_update_page_table_config(struct dcn_hubbub_phys_addr_config *config,
+               struct dce_hwseq *hws)
+{
+       uint32_t page_table_base_hi;
+       uint32_t page_table_base_lo;
+
+       REG_GET(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,
+                       PAGE_DIRECTORY_ENTRY_HI32, &page_table_base_hi);
+       REG_GET(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
+                       PAGE_DIRECTORY_ENTRY_LO32, &page_table_base_lo);
+
+       config->gart_config.page_table_base_addr = ((uint64_t)page_table_base_hi << 32) | page_table_base_lo;
+
+}
+
+static int dcn21_init_sys_ctx(struct dce_hwseq *hws, struct dc *dc, struct dc_phy_addr_space_config *pa_config)
+{
+       struct dcn_hubbub_phys_addr_config config;
+
+       config.system_aperture.fb_top = pa_config->system_aperture.fb_top;
+       config.system_aperture.fb_offset = pa_config->system_aperture.fb_offset;
+       config.system_aperture.fb_base = pa_config->system_aperture.fb_base;
+       config.system_aperture.agp_top = pa_config->system_aperture.agp_top;
+       config.system_aperture.agp_bot = pa_config->system_aperture.agp_bot;
+       config.system_aperture.agp_base = pa_config->system_aperture.agp_base;
+       config.gart_config.page_table_start_addr = pa_config->gart_config.page_table_start_addr;
+       config.gart_config.page_table_end_addr = pa_config->gart_config.page_table_end_addr;
+       config.gart_config.page_table_base_addr = pa_config->gart_config.page_table_base_addr;
+
+       mmhub_update_page_table_config(&config, hws);
+
+       return dc->res_pool->hubbub->funcs->init_dchub_sys_ctx(dc->res_pool->hubbub, &config);
+}
+
+// work around for Renoir s0i3, if register is programmed, bypass golden init.
+
+static bool dcn21_s0i3_golden_init_wa(struct dc *dc)
+{
+       struct dce_hwseq *hws = dc->hwseq;
+       uint32_t value = 0;
+
+       value = REG_READ(MICROSECOND_TIME_BASE_DIV);
+
+       return value != 0x00120464;
+}
+
+void dcn21_exit_optimized_pwr_state(
+               const struct dc *dc,
+               struct dc_state *context)
+{
+       dc->clk_mgr->funcs->update_clocks(
+                       dc->clk_mgr,
+                       context,
+                       false);
+}
+
+void dcn21_optimize_pwr_state(
+               const struct dc *dc,
+               struct dc_state *context)
+{
+       dc->clk_mgr->funcs->update_clocks(
+                       dc->clk_mgr,
+                       context,
+                       true);
+}
+
+void dcn21_hw_sequencer_construct(struct dc *dc)
+{
+       dcn20_hw_sequencer_construct(dc);
+       dc->hwss.init_sys_ctx = dcn21_init_sys_ctx;
+       dc->hwss.s0i3_golden_init_wa = dcn21_s0i3_golden_init_wa;
+       dc->hwss.optimize_pwr_state = dcn21_optimize_pwr_state;
+       dc->hwss.exit_optimized_pwr_state = dcn21_exit_optimized_pwr_state;
+}
diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hwseq.h b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hwseq.h
new file mode 100644 (file)
index 0000000..be67b62
--- /dev/null
@@ -0,0 +1,33 @@
+/*
+* Copyright 2016 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef __DC_HWSS_DCN21_H__
+#define __DC_HWSS_DCN21_H__
+
+struct dc;
+
+void dcn21_hw_sequencer_construct(struct dc *dc);
+
+#endif /* __DC_HWSS_DCN21_H__ */
index dfeda29..ac61163 100644 (file)
@@ -23,8 +23,6 @@
  *
  */
 
-#include <linux/slab.h>
-
 #include "dm_services.h"
 #include "dc.h"
 
@@ -42,7 +40,7 @@
 #include "irq/dcn21/irq_service_dcn21.h"
 #include "dcn20/dcn20_dpp.h"
 #include "dcn20/dcn20_optc.h"
-#include "dcn20/dcn20_hwseq.h"
+#include "dcn21/dcn21_hwseq.h"
 #include "dce110/dce110_hw_sequencer.h"
 #include "dcn20/dcn20_opp.h"
 #include "dcn20/dcn20_dsc.h"
@@ -350,6 +348,30 @@ static const struct bios_registers bios_regs = {
                NBIO_SR(BIOS_SCRATCH_6)
 };
 
+static const struct dce_dmcu_registers dmcu_regs = {
+               DMCU_DCN10_REG_LIST()
+};
+
+static const struct dce_dmcu_shift dmcu_shift = {
+               DMCU_MASK_SH_LIST_DCN10(__SHIFT)
+};
+
+static const struct dce_dmcu_mask dmcu_mask = {
+               DMCU_MASK_SH_LIST_DCN10(_MASK)
+};
+
+static const struct dce_abm_registers abm_regs = {
+               ABM_DCN20_REG_LIST()
+};
+
+static const struct dce_abm_shift abm_shift = {
+               ABM_MASK_SH_LIST_DCN20(__SHIFT)
+};
+
+static const struct dce_abm_mask abm_mask = {
+               ABM_MASK_SH_LIST_DCN20(_MASK)
+};
+
 #ifdef CONFIG_DRM_AMD_DC_DMUB
 static const struct dcn21_dmcub_registers dmcub_regs = {
                DMCUB_REG_LIST_DCN()
@@ -1441,6 +1463,19 @@ static const struct resource_create_funcs res_create_maximus_funcs = {
        .create_hwseq = dcn21_hwseq_create,
 };
 
+#define CTX ctx
+
+#define REG(reg_name) \
+       (DCN_BASE.instance[0].segment[mm ## reg_name ## _BASE_IDX] + mm ## reg_name)
+
+static uint32_t read_pipe_fuses(struct dc_context *ctx)
+{
+       uint32_t value = REG_READ(CC_DC_PIPE_DIS);
+       /* RV1 support max 4 pipes */
+       value = value & 0xf;
+       return value;
+}
+
 static struct resource_funcs dcn21_res_pool_funcs = {
        .destroy = dcn21_destroy_resource_pool,
        .link_enc_create = dcn20_link_encoder_create,
@@ -1460,9 +1495,10 @@ static bool construct(
        struct dc *dc,
        struct dcn21_resource_pool *pool)
 {
-       int i;
+       int i, j;
        struct dc_context *ctx = dc->ctx;
        struct irq_service_init_data init_data;
+       uint32_t pipe_fuses = read_pipe_fuses(ctx);
 
        ctx->dc_bios->regs = &bios_regs;
 
@@ -1480,7 +1516,9 @@ static bool construct(
         *************************************************/
        pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
 
-       pool->base.pipe_count = 4;
+       /* max pipe num for ASIC before check pipe fuses */
+       pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
+
        dc->caps.max_downscale_ratio = 200;
        dc->caps.i2c_speed_in_khz = 100;
        dc->caps.max_cursor_size = 256;
@@ -1540,6 +1578,26 @@ static bool construct(
                goto create_fail;
        }
 
+       pool->base.dmcu = dcn20_dmcu_create(ctx,
+                       &dmcu_regs,
+                       &dmcu_shift,
+                       &dmcu_mask);
+       if (pool->base.dmcu == NULL) {
+               dm_error("DC: failed to create dmcu!\n");
+               BREAK_TO_DEBUGGER();
+               goto create_fail;
+       }
+
+       pool->base.abm = dce_abm_create(ctx,
+                       &abm_regs,
+                       &abm_shift,
+                       &abm_mask);
+       if (pool->base.abm == NULL) {
+               dm_error("DC: failed to create abm!\n");
+               BREAK_TO_DEBUGGER();
+               goto create_fail;
+       }
+
 #ifdef CONFIG_DRM_AMD_DC_DMUB
        pool->base.dmcub = dcn21_dmcub_create(ctx,
                        &dmcub_regs,
@@ -1561,8 +1619,15 @@ static bool construct(
        if (!pool->base.irqs)
                goto create_fail;
 
+       j = 0;
        /* mem input -> ipp -> dpp -> opp -> TG */
        for (i = 0; i < pool->base.pipe_count; i++) {
+               /* if pipe is disabled, skip instance of HW pipe,
+                * i.e, skip ASIC register instance
+                */
+               if ((pipe_fuses & (1 << i)) != 0)
+                       continue;
+
                pool->base.hubps[i] = dcn21_hubp_create(ctx, i);
                if (pool->base.hubps[i] == NULL) {
                        BREAK_TO_DEBUGGER();
@@ -1586,6 +1651,23 @@ static bool construct(
                                "DC: failed to create dpps!\n");
                        goto create_fail;
                }
+
+               pool->base.opps[i] = dcn21_opp_create(ctx, i);
+               if (pool->base.opps[i] == NULL) {
+                       BREAK_TO_DEBUGGER();
+                       dm_error(
+                               "DC: failed to create output pixel processor!\n");
+                       goto create_fail;
+               }
+
+               pool->base.timing_generators[i] = dcn21_timing_generator_create(
+                               ctx, i);
+               if (pool->base.timing_generators[i] == NULL) {
+                       BREAK_TO_DEBUGGER();
+                       dm_error("DC: failed to create tg!\n");
+                       goto create_fail;
+               }
+               j++;
        }
 
        for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
@@ -1606,27 +1688,9 @@ static bool construct(
                pool->base.sw_i2cs[i] = NULL;
        }
 
-       for (i = 0; i < pool->base.res_cap->num_opp; i++) {
-               pool->base.opps[i] = dcn21_opp_create(ctx, i);
-               if (pool->base.opps[i] == NULL) {
-                       BREAK_TO_DEBUGGER();
-                       dm_error(
-                               "DC: failed to create output pixel processor!\n");
-                       goto create_fail;
-               }
-       }
-
-       for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
-               pool->base.timing_generators[i] = dcn21_timing_generator_create(
-                               ctx, i);
-               if (pool->base.timing_generators[i] == NULL) {
-                       BREAK_TO_DEBUGGER();
-                       dm_error("DC: failed to create tg!\n");
-                       goto create_fail;
-               }
-       }
-
-       pool->base.timing_generator_count = i;
+       pool->base.timing_generator_count = j;
+       pool->base.pipe_count = j;
+       pool->base.mpcc_count = j;
 
        pool->base.mpc = dcn21_mpc_create(ctx);
        if (pool->base.mpc == NULL) {
@@ -1669,7 +1733,7 @@ static bool construct(
                        &res_create_funcs : &res_create_maximus_funcs)))
                        goto create_fail;
 
-       dcn20_hw_sequencer_construct(dc);
+       dcn21_hw_sequencer_construct(dc);
 
        dc->caps.max_planes =  pool->base.pipe_count;
 
index e775d7a..d39c1e1 100644 (file)
@@ -349,6 +349,9 @@ struct hw_sequencer_funcs {
                        enum dc_clock_type clock_type,
                        struct dc_clock_config *clock_cfg);
 
+#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
+       bool (*s0i3_golden_init_wa)(struct dc *dc);
+#endif
 };
 
 void color_space_to_black_color(