drm/amdgpu/sdma5.2: add mes support for sdma ib test

Add MES support for sdma ib test.

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
index 7c9c703..83c6cca 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
@@ -1042,21 +1042,37 @@ static int sdma_v5_2_ring_test_ib(struct amdgpu_ring *ring, long timeout)
        long r;
        u32 tmp = 0;
        u64 gpu_addr;
+       volatile uint32_t *cpu_ptr = NULL;
 
-       r = amdgpu_device_wb_get(adev, &index);
-       if (r) {
-               dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r);
-               return r;
-       }
-
-       gpu_addr = adev->wb.gpu_addr + (index * 4);
        tmp = 0xCAFEDEAD;
-       adev->wb.wb[index] = cpu_to_le32(tmp);
        memset(&ib, 0, sizeof(ib));
-       r = amdgpu_ib_get(adev, NULL, 256, AMDGPU_IB_POOL_DIRECT, &ib);
-       if (r) {
-               DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
-               goto err0;
+
+       if (ring->is_mes_queue) {
+               uint32_t offset = 0;
+               offset = amdgpu_mes_ctx_get_offs(ring, AMDGPU_MES_CTX_IB_OFFS);
+               ib.gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);
+               ib.ptr = (void *)amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset);
+
+               offset = amdgpu_mes_ctx_get_offs(ring,
+                                        AMDGPU_MES_CTX_PADDING_OFFS);
+               gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);
+               cpu_ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset);
+               *cpu_ptr = tmp;
+       } else {
+               r = amdgpu_device_wb_get(adev, &index);
+               if (r) {
+                       dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r);
+                       return r;
+               }
+
+               gpu_addr = adev->wb.gpu_addr + (index * 4);
+               adev->wb.wb[index] = cpu_to_le32(tmp);
+
+               r = amdgpu_ib_get(adev, NULL, 256, AMDGPU_IB_POOL_DIRECT, &ib);
+               if (r) {
+                       DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
+                       goto err0;
+               }
        }
 
        ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
@@ -1083,7 +1099,12 @@ static int sdma_v5_2_ring_test_ib(struct amdgpu_ring *ring, long timeout)
                DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
                goto err1;
        }
-       tmp = le32_to_cpu(adev->wb.wb[index]);
+
+       if (ring->is_mes_queue)
+               tmp = le32_to_cpu(*cpu_ptr);
+       else
+               tmp = le32_to_cpu(adev->wb.wb[index]);
+
        if (tmp == 0xDEADBEEF)
                r = 0;
        else
@@ -1093,7 +1114,8 @@ err1:
        amdgpu_ib_free(adev, &ib, NULL);
        dma_fence_put(f);
 err0:
-       amdgpu_device_wb_free(adev, index);
+       if (!ring->is_mes_queue)
+               amdgpu_device_wb_free(adev, index);
        return r;
 }