drm/amd/display: Fix rn audio playback and video playback speed

[WHY]
dprefclk is improperly read due to incorrect units used.
Causes an audio clock to be improperly set, making audio
non-functional and videos play back too fast

[HOW]
Scale dprefclk value from MHz to KHz (multiply by 1000)
to ensure that dprefclk_khz is in correct units

Signed-off-by: Michael Strauss <michael.strauss@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Reviewed-by: Roman Li <Roman.Li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
index 93e46e3..fb8aa94 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
@@ -377,7 +377,7 @@ void rn_get_clk_states(struct clk_mgr *clk_mgr_base, struct clk_states *s)
 
        rn_dump_clk_registers(&sb, clk_mgr_base, &log_info);
 
-       s->dprefclk_khz = sb.dprefclk;
+       s->dprefclk_khz = sb.dprefclk * 1000;
 }
 
 void rn_enable_pme_wa(struct clk_mgr *clk_mgr_base)
@@ -633,16 +633,15 @@ void rn_clk_mgr_construct(
                        clk_mgr->dentist_vco_freq_khz = 3600000;
 
                rn_dump_clk_registers(&s, &clk_mgr->base, &log_info);
-               clk_mgr->base.dprefclk_khz = s.dprefclk;
-
-               if (clk_mgr->base.dprefclk_khz != 600000) {
-                       clk_mgr->base.dprefclk_khz = 600000;
-                       ASSERT(1); //TODO: Renoir follow up.
-               }
+               /* Convert dprefclk units from MHz to KHz */
+               /* Value already divided by 10, some resolution lost */
+               clk_mgr->base.dprefclk_khz = s.dprefclk * 1000;
 
                /* in case we don't get a value from the register, use default */
-               if (clk_mgr->base.dprefclk_khz == 0)
+               if (clk_mgr->base.dprefclk_khz == 0) {
+                       ASSERT(clk_mgr->base.dprefclk_khz == 600000);
                        clk_mgr->base.dprefclk_khz = 600000;
+               }
        }
 
        dce_clock_read_ss_info(clk_mgr);