ARM: dts: qcom: ipq4019: align clocks in I2C with DT schema

The DT schema expects clocks core-iface order.  No functional change.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220405063451.12011-5-krzysztof.kozlowski@linaro.org

diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi
index 1f6c4ab..8974421 100644 (file)
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
@@ -276,9 +276,9 @@
                        compatible = "qcom,i2c-qup-v2.2.1";
                        reg = <0x78b7000 0x600>;
                        interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
-                       clocks = <&gcc GCC_BLSP1_AHB_CLK>,
-                                <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>;
-                       clock-names = "iface", "core";
+                       clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>,
+                                <&gcc GCC_BLSP1_AHB_CLK>;
+                       clock-names = "core", "iface";
                        #address-cells = <1>;
                        #size-cells = <0>;
                        dmas = <&blsp_dma 8>, <&blsp_dma 9>;
@@ -290,9 +290,9 @@
                        compatible = "qcom,i2c-qup-v2.2.1";
                        reg = <0x78b8000 0x600>;
                        interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
-                       clocks = <&gcc GCC_BLSP1_AHB_CLK>,
-                                <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
-                       clock-names = "iface", "core";
+                       clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
+                                <&gcc GCC_BLSP1_AHB_CLK>;
+                       clock-names = "core", "iface";
                        #address-cells = <1>;
                        #size-cells = <0>;
                        dmas = <&blsp_dma 10>, <&blsp_dma 11>;