cxgb4: collect TX rate limit info in UP CIM logs
authorRahul Lakkireddy <rahul.lakkireddy@chelsio.com>
Tue, 2 Jan 2018 07:18:58 +0000 (12:48 +0530)
committerDavid S. Miller <davem@davemloft.net>
Wed, 3 Jan 2018 15:57:59 +0000 (10:57 -0500)
Collect TX rate limiting related information in UP CIM logs.

Signed-off-by: Rahul Lakkireddy <rahul.lakkireddy@chelsio.com>
Signed-off-by: Ganesh Goudar <ganeshgr@chelsio.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
drivers/net/ethernet/chelsio/cxgb4/cudbg_entity.h
drivers/net/ethernet/chelsio/cxgb4/cudbg_if.h
drivers/net/ethernet/chelsio/cxgb4/cudbg_lib.c
drivers/net/ethernet/chelsio/cxgb4/cxgb4_cudbg.c
drivers/net/ethernet/chelsio/cxgb4/t4_regs.h

index 2e71e33..b57acb8 100644 (file)
@@ -405,37 +405,55 @@ static const u32 t6_ma_ireg_array2[][IREG_NUM_ELEM] = {
        {0x78f8, 0x78fc, 0xe640, 13} /* t6_ma_regs_e640_to_e7c0 */
 };
 
-static const u32 t6_up_cim_reg_array[][IREG_NUM_ELEM] = {
-       {0x7b50, 0x7b54, 0x2000, 0x20}, /* up_cim_2000_to_207c */
-       {0x7b50, 0x7b54, 0x2080, 0x1d}, /* up_cim_2080_to_20fc */
-       {0x7b50, 0x7b54, 0x00, 0x20}, /* up_cim_00_to_7c */
-       {0x7b50, 0x7b54, 0x80, 0x20}, /* up_cim_80_to_fc */
-       {0x7b50, 0x7b54, 0x100, 0x11}, /* up_cim_100_to_14c */
-       {0x7b50, 0x7b54, 0x200, 0x10}, /* up_cim_200_to_23c */
-       {0x7b50, 0x7b54, 0x240, 0x2}, /* up_cim_240_to_244 */
-       {0x7b50, 0x7b54, 0x250, 0x2}, /* up_cim_250_to_254 */
-       {0x7b50, 0x7b54, 0x260, 0x2}, /* up_cim_260_to_264 */
-       {0x7b50, 0x7b54, 0x270, 0x2}, /* up_cim_270_to_274 */
-       {0x7b50, 0x7b54, 0x280, 0x20}, /* up_cim_280_to_2fc */
-       {0x7b50, 0x7b54, 0x300, 0x20}, /* up_cim_300_to_37c */
-       {0x7b50, 0x7b54, 0x380, 0x14}, /* up_cim_380_to_3cc */
-
-};
-
-static const u32 t5_up_cim_reg_array[][IREG_NUM_ELEM] = {
-       {0x7b50, 0x7b54, 0x2000, 0x20}, /* up_cim_2000_to_207c */
-       {0x7b50, 0x7b54, 0x2080, 0x19}, /* up_cim_2080_to_20ec */
-       {0x7b50, 0x7b54, 0x00, 0x20}, /* up_cim_00_to_7c */
-       {0x7b50, 0x7b54, 0x80, 0x20}, /* up_cim_80_to_fc */
-       {0x7b50, 0x7b54, 0x100, 0x11}, /* up_cim_100_to_14c */
-       {0x7b50, 0x7b54, 0x200, 0x10}, /* up_cim_200_to_23c */
-       {0x7b50, 0x7b54, 0x240, 0x2}, /* up_cim_240_to_244 */
-       {0x7b50, 0x7b54, 0x250, 0x2}, /* up_cim_250_to_254 */
-       {0x7b50, 0x7b54, 0x260, 0x2}, /* up_cim_260_to_264 */
-       {0x7b50, 0x7b54, 0x270, 0x2}, /* up_cim_270_to_274 */
-       {0x7b50, 0x7b54, 0x280, 0x20}, /* up_cim_280_to_2fc */
-       {0x7b50, 0x7b54, 0x300, 0x20}, /* up_cim_300_to_37c */
-       {0x7b50, 0x7b54, 0x380, 0x14}, /* up_cim_380_to_3cc */
+static const u32 t6_up_cim_reg_array[][IREG_NUM_ELEM + 1] = {
+       {0x7b50, 0x7b54, 0x2000, 0x20, 0}, /* up_cim_2000_to_207c */
+       {0x7b50, 0x7b54, 0x2080, 0x1d, 0}, /* up_cim_2080_to_20fc */
+       {0x7b50, 0x7b54, 0x00, 0x20, 0}, /* up_cim_00_to_7c */
+       {0x7b50, 0x7b54, 0x80, 0x20, 0}, /* up_cim_80_to_fc */
+       {0x7b50, 0x7b54, 0x100, 0x11, 0}, /* up_cim_100_to_14c */
+       {0x7b50, 0x7b54, 0x200, 0x10, 0}, /* up_cim_200_to_23c */
+       {0x7b50, 0x7b54, 0x240, 0x2, 0}, /* up_cim_240_to_244 */
+       {0x7b50, 0x7b54, 0x250, 0x2, 0}, /* up_cim_250_to_254 */
+       {0x7b50, 0x7b54, 0x260, 0x2, 0}, /* up_cim_260_to_264 */
+       {0x7b50, 0x7b54, 0x270, 0x2, 0}, /* up_cim_270_to_274 */
+       {0x7b50, 0x7b54, 0x280, 0x20, 0}, /* up_cim_280_to_2fc */
+       {0x7b50, 0x7b54, 0x300, 0x20, 0}, /* up_cim_300_to_37c */
+       {0x7b50, 0x7b54, 0x380, 0x14, 0}, /* up_cim_380_to_3cc */
+       {0x7b50, 0x7b54, 0x2900, 0x4, 0x4}, /* up_cim_2900_to_3d40 */
+       {0x7b50, 0x7b54, 0x2904, 0x4, 0x4}, /* up_cim_2904_to_3d44 */
+       {0x7b50, 0x7b54, 0x2908, 0x4, 0x4}, /* up_cim_2908_to_3d48 */
+       {0x7b50, 0x7b54, 0x2910, 0x4, 0x4}, /* up_cim_2910_to_3d4c */
+       {0x7b50, 0x7b54, 0x2914, 0x4, 0x4}, /* up_cim_2914_to_3d50 */
+       {0x7b50, 0x7b54, 0x2920, 0x10, 0x10}, /* up_cim_2920_to_2a10 */
+       {0x7b50, 0x7b54, 0x2924, 0x10, 0x10}, /* up_cim_2924_to_2a14 */
+       {0x7b50, 0x7b54, 0x2928, 0x10, 0x10}, /* up_cim_2928_to_2a18 */
+       {0x7b50, 0x7b54, 0x292c, 0x10, 0x10}, /* up_cim_292c_to_2a1c */
+};
+
+static const u32 t5_up_cim_reg_array[][IREG_NUM_ELEM + 1] = {
+       {0x7b50, 0x7b54, 0x2000, 0x20, 0}, /* up_cim_2000_to_207c */
+       {0x7b50, 0x7b54, 0x2080, 0x19, 0}, /* up_cim_2080_to_20ec */
+       {0x7b50, 0x7b54, 0x00, 0x20, 0}, /* up_cim_00_to_7c */
+       {0x7b50, 0x7b54, 0x80, 0x20, 0}, /* up_cim_80_to_fc */
+       {0x7b50, 0x7b54, 0x100, 0x11, 0}, /* up_cim_100_to_14c */
+       {0x7b50, 0x7b54, 0x200, 0x10, 0}, /* up_cim_200_to_23c */
+       {0x7b50, 0x7b54, 0x240, 0x2, 0}, /* up_cim_240_to_244 */
+       {0x7b50, 0x7b54, 0x250, 0x2, 0}, /* up_cim_250_to_254 */
+       {0x7b50, 0x7b54, 0x260, 0x2, 0}, /* up_cim_260_to_264 */
+       {0x7b50, 0x7b54, 0x270, 0x2, 0}, /* up_cim_270_to_274 */
+       {0x7b50, 0x7b54, 0x280, 0x20, 0}, /* up_cim_280_to_2fc */
+       {0x7b50, 0x7b54, 0x300, 0x20, 0}, /* up_cim_300_to_37c */
+       {0x7b50, 0x7b54, 0x380, 0x14, 0}, /* up_cim_380_to_3cc */
+       {0x7b50, 0x7b54, 0x2900, 0x4, 0x4}, /* up_cim_2900_to_3d40 */
+       {0x7b50, 0x7b54, 0x2904, 0x4, 0x4}, /* up_cim_2904_to_3d44 */
+       {0x7b50, 0x7b54, 0x2908, 0x4, 0x4}, /* up_cim_2908_to_3d48 */
+       {0x7b50, 0x7b54, 0x2910, 0x4, 0x4}, /* up_cim_2910_to_3d4c */
+       {0x7b50, 0x7b54, 0x2914, 0x4, 0x4}, /* up_cim_2914_to_3d50 */
+       {0x7b50, 0x7b54, 0x2918, 0x4, 0x4}, /* up_cim_2918_to_3d54 */
+       {0x7b50, 0x7b54, 0x291c, 0x4, 0x4}, /* up_cim_291c_to_3d58 */
+       {0x7b50, 0x7b54, 0x2924, 0x10, 0x10}, /* up_cim_2924_to_2914 */
+       {0x7b50, 0x7b54, 0x2928, 0x10, 0x10}, /* up_cim_2928_to_2a18 */
+       {0x7b50, 0x7b54, 0x292c, 0x10, 0x10}, /* up_cim_292c_to_2a1c */
 };
 
 static const u32 t6_hma_ireg_array[][IREG_NUM_ELEM] = {
index e8173ae..88e7400 100644 (file)
@@ -21,6 +21,7 @@
 /* Error codes */
 #define CUDBG_STATUS_NO_MEM -19
 #define CUDBG_STATUS_ENTITY_NOT_FOUND -24
+#define CUDBG_STATUS_NOT_IMPLEMENTED -28
 #define CUDBG_SYSTEM_ERROR -29
 #define CUDBG_STATUS_CCLK_NOT_DEFINED -32
 
index 336670d..0a3871f 100644 (file)
@@ -2422,11 +2422,21 @@ int cudbg_collect_up_cim_indirect(struct cudbg_init *pdbg_init,
 {
        struct adapter *padap = pdbg_init->adap;
        struct cudbg_buffer temp_buff = { 0 };
+       u32 local_offset, local_range;
        struct ireg_buf *up_cim;
+       u32 size, j, iter;
+       u32 instance = 0;
        int i, rc, n;
-       u32 size;
 
-       n = sizeof(t5_up_cim_reg_array) / (IREG_NUM_ELEM * sizeof(u32));
+       if (is_t5(padap->params.chip))
+               n = sizeof(t5_up_cim_reg_array) /
+                   ((IREG_NUM_ELEM + 1) * sizeof(u32));
+       else if (is_t6(padap->params.chip))
+               n = sizeof(t6_up_cim_reg_array) /
+                   ((IREG_NUM_ELEM + 1) * sizeof(u32));
+       else
+               return CUDBG_STATUS_NOT_IMPLEMENTED;
+
        size = sizeof(struct ireg_buf) * n;
        rc = cudbg_get_buff(dbg_buff, size, &temp_buff);
        if (rc)
@@ -2444,6 +2454,7 @@ int cudbg_collect_up_cim_indirect(struct cudbg_init *pdbg_init,
                                                t5_up_cim_reg_array[i][2];
                        up_cim_reg->ireg_offset_range =
                                                t5_up_cim_reg_array[i][3];
+                       instance = t5_up_cim_reg_array[i][4];
                } else if (is_t6(padap->params.chip)) {
                        up_cim_reg->ireg_addr = t6_up_cim_reg_array[i][0];
                        up_cim_reg->ireg_data = t6_up_cim_reg_array[i][1];
@@ -2451,13 +2462,35 @@ int cudbg_collect_up_cim_indirect(struct cudbg_init *pdbg_init,
                                                t6_up_cim_reg_array[i][2];
                        up_cim_reg->ireg_offset_range =
                                                t6_up_cim_reg_array[i][3];
+                       instance = t6_up_cim_reg_array[i][4];
                }
 
-               rc = t4_cim_read(padap, up_cim_reg->ireg_local_offset,
-                                up_cim_reg->ireg_offset_range, buff);
-               if (rc) {
-                       cudbg_put_buff(&temp_buff, dbg_buff);
-                       return rc;
+               switch (instance) {
+               case NUM_CIM_CTL_TSCH_CHANNEL_INSTANCES:
+                       iter = up_cim_reg->ireg_offset_range;
+                       local_offset = 0x120;
+                       local_range = 1;
+                       break;
+               case NUM_CIM_CTL_TSCH_CHANNEL_TSCH_CLASS_INSTANCES:
+                       iter = up_cim_reg->ireg_offset_range;
+                       local_offset = 0x10;
+                       local_range = 1;
+                       break;
+               default:
+                       iter = 1;
+                       local_offset = 0;
+                       local_range = up_cim_reg->ireg_offset_range;
+                       break;
+               }
+
+               for (j = 0; j < iter; j++, buff++) {
+                       rc = t4_cim_read(padap,
+                                        up_cim_reg->ireg_local_offset +
+                                        (j * local_offset), local_range, buff);
+                       if (rc) {
+                               cudbg_put_buff(&temp_buff, dbg_buff);
+                               return rc;
+                       }
                }
                up_cim++;
        }
index 581d628..a2d6c8a 100644 (file)
@@ -274,7 +274,13 @@ static u32 cxgb4_get_entity_length(struct adapter *adap, u32 entity)
                len = sizeof(struct cudbg_ulptx_la);
                break;
        case CUDBG_UP_CIM_INDIRECT:
-               n = sizeof(t5_up_cim_reg_array) / (IREG_NUM_ELEM * sizeof(u32));
+               n = 0;
+               if (is_t5(adap->params.chip))
+                       n = sizeof(t5_up_cim_reg_array) /
+                           ((IREG_NUM_ELEM + 1) * sizeof(u32));
+               else if (is_t6(adap->params.chip))
+                       n = sizeof(t6_up_cim_reg_array) /
+                           ((IREG_NUM_ELEM + 1) * sizeof(u32));
                len = sizeof(struct ireg_buf) * n;
                break;
        case CUDBG_PBT_TABLE:
index f6701e0..863bc29 100644 (file)
@@ -45,6 +45,9 @@
 #define PF_BASE(idx) (PF0_BASE + (idx) * PF_STRIDE)
 #define PF_REG(idx, reg) (PF_BASE(idx) + (reg))
 
+#define NUM_CIM_CTL_TSCH_CHANNEL_INSTANCES 4
+#define NUM_CIM_CTL_TSCH_CHANNEL_TSCH_CLASS_INSTANCES 16
+
 #define MYPORT_BASE 0x1c000
 #define MYPORT_REG(reg_addr) (MYPORT_BASE + (reg_addr))