Merge patch series "RISC-V: Fixes for riscv_has_extension[un]likely()'s alternative...

Conor Dooley <conor.dooley@microchip.com> says:

Here's my attempt at fixing both the use of an FPU on XIP kernels and
the issue that Jason ran into where CONFIG_FPU, which needs the
alternatives frame work for has_fpu() checks, could be enabled without
the alternatives actually being present.

For the former, a "slow" fallback that does not use alternatives is
added to riscv_has_extension_[un]likely() that can be used with XIP.
Obviously, we want to make use of Jisheng's alternatives based approach
where possible, so any users of riscv_has_extension_[un]likely() will
want to make sure that they select RISCV_ALTERNATIVE.
If they don't however, they'll hit the fallback path which (should,
sparing a silly mistake from me!) behave in the same way, thus
succeeding silently. Sounds like a

To prevent "depends on !XIP_KERNEL; select RISCV_ALTERNATIVE" spreading
like the plague through the various places that want to check for the
presence of extensions, and sidestep the potential silent "success"
mentioned above, all users RISCV_ALTERNATIVE are converted from selects
to dependencies, with the option being selected for all !XIP_KERNEL
builds.

I know that the VDSO was a key place that Jisheng wanted to use the new
helper rather than static branches, and I think the fallback path
should not cause issues there.

See the thread at [1] for the prior discussion.

1 - https://lore.kernel.org/linux-riscv/20230128172856.3814-1-jszhang@kernel.org/T/#m21390d570997145d31dd8bb95002fd61f99c6573

[Palmer: these were also merged into fixes, but there's a cleanup that
depends on the merge so I'm taking it into for-next as well.]

* b4-shazam-merge:
  RISC-V: always select RISCV_ALTERNATIVE for non-xip kernels
  RISC-V: add non-alternative fallback for riscv_has_extension_[un]likely()

Link: https://lore.kernel.org/r/20230324100538.3514663-1-conor.dooley@microchip.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
* commit '1ee7fc3f4d0a93831a20d5566f203d5ad6d44de8':
  RISC-V: always select RISCV_ALTERNATIVE for non-xip kernels
  RISC-V: add non-alternative fallback for riscv_has_extension_[un]likely()

diff --cc arch/riscv/Kconfig
Simple merge

diff --cc arch/riscv/Kconfig.errata
index 69621ae,0000000..0c8f465
mode 100644,000000..100644
--- 1/arch/riscv/Kconfig.errata
--- /dev/null
+++ b/arch/riscv/Kconfig.errata
@@@ -1,82 -1,0 +1,80 @@@
-       depends on !XIP_KERNEL
-       select RISCV_ALTERNATIVE
 +menu "CPU errata selection"
 +
 +config ERRATA_SIFIVE
 +      bool "SiFive errata"
-       depends on !XIP_KERNEL
-       select RISCV_ALTERNATIVE
++      depends on RISCV_ALTERNATIVE
 +      help
 +        All SiFive errata Kconfig depend on this Kconfig. Disabling
 +        this Kconfig will disable all SiFive errata. Please say "Y"
 +        here if your platform uses SiFive CPU cores.
 +
 +        Otherwise, please say "N" here to avoid unnecessary overhead.
 +
 +config ERRATA_SIFIVE_CIP_453
 +      bool "Apply SiFive errata CIP-453"
 +      depends on ERRATA_SIFIVE && 64BIT
 +      default y
 +      help
 +        This will apply the SiFive CIP-453 errata to add sign extension
 +        to the $badaddr when exception type is instruction page fault
 +        and instruction access fault.
 +
 +        If you don't know what to do here, say "Y".
 +
 +config ERRATA_SIFIVE_CIP_1200
 +      bool "Apply SiFive errata CIP-1200"
 +      depends on ERRATA_SIFIVE && 64BIT
 +      default y
 +      help
 +        This will apply the SiFive CIP-1200 errata to repalce all
 +        "sfence.vma addr" with "sfence.vma" to ensure that the addr
 +        has been flushed from TLB.
 +
 +        If you don't know what to do here, say "Y".
 +
 +config ERRATA_THEAD
 +      bool "T-HEAD errata"
++      depends on RISCV_ALTERNATIVE
 +      help
 +        All T-HEAD errata Kconfig depend on this Kconfig. Disabling
 +        this Kconfig will disable all T-HEAD errata. Please say "Y"
 +        here if your platform uses T-HEAD CPU cores.
 +
 +        Otherwise, please say "N" here to avoid unnecessary overhead.
 +
 +config ERRATA_THEAD_PBMT
 +      bool "Apply T-Head memory type errata"
 +      depends on ERRATA_THEAD && 64BIT && MMU
 +      select RISCV_ALTERNATIVE_EARLY
 +      default y
 +      help
 +        This will apply the memory type errata to handle the non-standard
 +        memory type bits in page-table-entries on T-Head SoCs.
 +
 +        If you don't know what to do here, say "Y".
 +
 +config ERRATA_THEAD_CMO
 +      bool "Apply T-Head cache management errata"
 +      depends on ERRATA_THEAD && MMU
 +      select RISCV_DMA_NONCOHERENT
 +      default y
 +      help
 +        This will apply the cache management errata to handle the
 +        non-standard handling on non-coherent operations on T-Head SoCs.
 +
 +        If you don't know what to do here, say "Y".
 +
 +config ERRATA_THEAD_PMU
 +      bool "Apply T-Head PMU errata"
 +      depends on ERRATA_THEAD && RISCV_PMU_SBI
 +      default y
 +      help
 +        The T-Head C9xx cores implement a PMU overflow extension very
 +        similar to the core SSCOFPMF extension.
 +
 +        This will apply the overflow errata to handle the non-standard
 +        behaviour via the regular SBI PMU driver and interface.
 +
 +        If you don't know what to do here, say "Y".
 +
 +endmenu # "CPU errata selection"

diff --cc arch/riscv/include/asm/hwcap.h
Simple merge